ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS843022I-48 is a Fibre Channel Clock ICS Generator and a member of the HiPerClocksTM famHiPerClockSTM ily of high performance devices from IDT. The ICS843022I-48 uses a 25MHz crystal to synthesize 125MHz or 75MHz. The ICS843022I-48 has excellent phase jitter performance, over the 12kHz - 20MHz integration range. The ICS843022I-48 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. * One differential 3.3V or 2.5V LVPECL output * Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal * Output frequencies: 125MHz or 75MHz (selectable) * RMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz - 20MHz): 0.72ps (typical) @ 3.3V * Full 3.3V and 2.5V operating supply * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages FUNCTION TABLE Inputs FREQ_SEL M Divide N Divide Output Frequencies (with a 25MHz crystal) 0 /20 /4 125MHz (default) 1 /2 4 /8 75MHz BLOCK DIAGRAM PIN ASSIGNMENT XTAL_IN OSC PLL XTAL_OUT DIV. N /4, /8 Q nQ 0 = /20 (default) 1 = /24 1 2 3 4 8 7 6 5 VCC Q nQ FREQ_SEL ICS843022I-48 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View FREQ_SEL Pulldown IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR VCCA VEE XTAL_OUT XTAL_IN 1 ICS843022AGI-48 REV A OCTOBER 31, 2006 ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 VCCA Power 2 Power 5 VEE XTAL_OUT, XTAL_IN FREQ_SEL 6, 7 nQ, Q Output Differential clock output. LVPECL interface levels. 8 VCC Power Core supply pin. 3, 4 Type Input Input Description Analog supply pin. Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 k IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR Test Conditions Minimum 2 Typical Maximum Units ICS843022AGI-48 REV A OCTOBER 31, 2006 ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 101.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = -40C TO 85C Symbol Parameter VCC Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3. 3 3.465 V VCC - 0.10 3.3 VCCA Analog Supply Voltage VCC V ICCA Analog Supply Current 10 mA IEE Power Supply Current 80 mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 2.5V5%, TA = -40C TO 85C Symbol Parameter VCC Core Supply Voltage Test Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V VCC - 0.10 2.5 VCCA Analog Supply Voltage VCC V ICCA Analog Supply Current 10 V IEE Power Supply Current 75 mA Maximum Units VCC + 0.3 V TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = -40C TO 85C Symbol Parameter VIH Input High Voltage Test Conditions Minimum Typical 1.3 VIL Input Low Voltage IIH Input High Current VCC = VIN = 3.465V IIL Input Low Current VCC = 3.465V, VIN = 0V -0.3 0. 7 V 15 0 A -5 A TABLE 3D. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 2.5V5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 1.1 VCC + 0.3 V VIL Input Low Voltage -0.3 0.5 V IIH Input High Current VCC = VIN = 2.625V 15 0 A IIL Input Low Current VCC = 2.625V, VIN = 0V IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR 3 -5 A ICS843022AGI-48 REV A OCTOBER 31, 2006 ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR TABLE 3E. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V5% OR 2.5V5%, TA = -40C TO 85C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCC - 1.4 Typical VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units NOTE 1: Outputs terminated with 50 to VCC - 2V. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 25 Equivalent Series Resistance (ESR) MHz 50 Shunt Capacitance Drive Level 7 pF 100 W TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = -40C TO 85C Symbol Parameter fOUT Output Frequency tjit(O) tR / tF RMS Phase Jitter ; NOTE 1 Output Rise/Fall Time Test Conditions 125MHz, Integration Range: 12kHz - 20MHz 75MHz, Integration Range: 900kHz - 7.5MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot. Minimum Typical Maximum Units 125 MHz 75 MHz 0.72 ps 0.51 ps 250 450 ps 48 52 % Maximum Units TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = 2.5V5%, TA = -40C TO 85C Symbol fOUT tjit(O) tR / tF Parameter Test Conditions Minimum Output Frequency RMS Phase Jitter; NOTE 1 Output Rise/Fall Time 125MHz, Integration Range: 12kHz - 20MHz 75MHz, Integration Range: 900kHz - 7.5MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot. IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR 4 Typical 125 MHz 75 MHz 0.66 ps 0.60 ps 25 0 450 ps 48 52 % ICS843022AGI-48 REV A OCTOBER 31, 2006 ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR TYPICAL PHASE NOISE AT 125MHZ @ 3.3V Fibre Channel Filter 125MHz NOISE POWER dBc Hz RMS Phase Noise Jitter 12kHz to 20MHz = 0.72ps (typical) Raw Phase Noise Data Phase Noise Result by adding a Fibre Channel Filter to raw data OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 75MHZ @ 3.3V 75MHz Fibre Channel Filter Raw Phase Noise Data NOISE POWER dBc Hz RMS Phase Jitter (Random) 900kHz to 7.5MHz = 0.51ps (typical) Phase Noise Result by adding Fibre Channel Filter to raw data OFFSET FREQUENCY (HZ) IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR 5 ICS843022AGI-48 REV A OCTOBER 31, 2006 ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V 2V 2V 2V VCC Qx SCOPE VCC Qx SCOPE VCCA VCCA LVPECL LVPECL nQx nQx VEE VEE -0.5V 0.125V -1.3V 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT Noise Power Phase Noise Plot 80% VSW I N G Phase Noise Mask f1 Offset Frequency 80% Clock Outputs 20% 20% tR tF f2 RMS Jitter = Area Under the Masked Phase Noise Plot OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME nQ Q t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR 6 ICS843022AGI-48 REV A OCTOBER 31, 2006 ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843022I-48 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. 3.3V or 2.5V VCC .01F VCCA .01F 10 10 F FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS843022I-48 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel XTAL_OUT C1 27p X1 18pF Parallel Crystal XTAL_IN C2 27p FIGURE 2. CRYSTAL INPUt INTERFACE IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR 7 ICS843022AGI-48 REV A OCTOBER 31, 2006 ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR LVCMOS TO XTAL INTERFACE (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver VDD VDD R1 Ro .1uf Rs Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are 3.3V Zo = 50 125 FOUT FIN 125 Zo = 50 Zo = 50 FOUT 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o FIN 50 Zo = 50 VCC - 2V RTT 84 FIGURE 4A. LVPECL OUTPUT TERMINATION IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR 84 FIGURE 4B. LVPECL OUTPUT TERMINATION 8 ICS843022AGI-48 REV A OCTOBER 31, 2006 ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR TERMINATION FOR 2.5V LVPECL OUTPUT Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. 2.5V VCC=2.5V 2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm R3 250 + Zo = 50 Ohm + Zo = 50 Ohm - Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR 9 ICS843022AGI-48 REV A OCTOBER 31, 2006 ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843022I-48. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843022I-48 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 80mA = 277.2mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 277.2mW + 30mW = 307.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.307W * 125.5C/W = 123.5C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 8-PIN TSSOP, FORCED CONVECTION JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR 10 0 1 2.5 129.5C/W 125.5C/W 123.5C/W ICS843022AGI-48 REV A OCTOBER 31, 2006 ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CC * For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (VCCO_MAX - VOH_MAX) = 0.9V * For logic low, VOUT = VOL_MAX = VCC_MAX - 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (V L CC_MAX - VOH_MAX))/R ] * (VCC_MAX - VOH_MAX) = L [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX) = [(2V - (V L CC_MAX - VOL_MAX))/R ] * (VCC_MAX - VOL_MAX) = L [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR 11 ICS843022AGI-48 REV A OCTOBER 31, 2006 ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 129.5C/W 125.5C/W 123.5C/W TRANSISTOR COUNT The transistor count for ICS843022I-48 is: 2086 IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR 12 ICS843022AGI-48 REV A OCTOBER 31, 2006 ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR 13 ICS843022AGI-48 REV A OCTOBER 31, 2006 ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843022AGI-48 2AI48 8 lead TSSOP tube -40C to 85C ICS843022AGI-48T 2AI48 8 lead TSSOP 2500 tape & reel -40C to 85C ICS843022AGI-48LF AI48L 8 lead "Lead-Free" TSSOP tube -40C to 85C ICS843022AGI-48LFT AI48L 8 lead "Lead-Free" TSSOP 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM 3.3V, 2.5V LVPECL CLOCK GENERATOR 14 ICS843022AGI-48 REV A OCTOBER 31, 2006 ICS843022I-48 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA