CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
PSoC® Mixed-Signal Array
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-12025 Rev. *M Revised April 18, 2008
Features
■Powerful Harvard Architecture Processor
❐M8C Processor Speeds to 24 MHz
❐Low power at high speed
❐2.4V to 5.25V Operating Voltage
❐Operating Voltages Down to 1.0V using On-Chip Switch
Mode Pump (SMP)
❐Industrial Temperature Range: -40°C to +85°C
■Advanced Peripherals (PSoC Blocks)
❐4 Analog Type “E” PSoC Blocks provide:
• 2 Comparators with DAC Refs
• Single or Dual 8-Bit 28 Channel ADC
❐4 Digital PSoC Blocks provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART, SPI™ Master or Slave
• Connectable to All GPIO Pins
❐Complex Peripherals by Combining Blocks
■Flexible On-Chip Memory
❐8K Flash Program Storage 50,000 Erase/Write Cycles
❐512 Bytes SRAM Data Storage
❐In-System Serial Programming (ISSP™)
❐Partial Flash Updates
❐Flexible Protection Modes
❐EEPROM Emulation in Flash
■Complete Develop me nt Tools
❐Free Development Software
(PSoC Designer™)
❐Full-Featured, In-Circuit Emu lator and Programmer
❐Full Speed Emulation
❐Complex Breakpoint S tructure
❐128K Trace Memory
■Precision, Programmable Clocking
❐Internal ±2.5% 24/48 MHz Oscillator
❐Internal Oscillator for Watchdog and Sleep
■Programmable Pi n Co n fi guration s
❐25 mA Drive on All GPIO
❐Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐Up to 8 Analog Inputs on GPIO
❐Configurable Interrupt on All GPIO
■Versatile Analog Mux
❐Common Internal Analog Bus
❐Simultaneous Connection of IO Combinations
❐Capacitive Sensing Application Capability
■Additional System Resources
❐I2C™ Master, Slave and Multi-Master to 400 kHz
❐Watchdog and Sleep Timers
❐User-Configurable Low Vol tage Detection
❐Integrated Supervisory Circuit
❐On-Chip Precision V oltage Reference
Block Diagram
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CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 2 of 43
PSoC® Functional Overview
The PSoC® family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
one low cost single-chip programmable component. A PSoC
device includes configurable blocks of analog and digital logic,
and programmable interconnect. This architecture enables the
user to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.
The PSoC architecture, shown in Figure 1, consists of four main
areas: the Core, the System Resources , the Digit al Sys tem, and
the Analog System. Configurable global bus resources allow
combining all the device resources into a complete custom
system. Each CY8C21x34 PSoC device includes four digital
blocks and four analog blocks. Depending on the PSoC
package, up to 28 general purpose IO (GPIO) are also included.
The GPIO provide access to the global digital and analog in ter-
connects.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillato r) and ILO (inter nal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard
architecture microprocessor.
System Resources provide the following additional capabilities:
■Digital clocks to increase the flexibility of the PSoC
mixed-signal arrays.
■I2C functionality to implement an I2C master and slave.
■An internal voltage reference, MultiMaster, that provides an
absolute value of 1.3V to a number of PSoC subsystems.
■A switch mode pump (SMP) that generates normal operating
voltages off a single battery cell.
■Various system resets supported by the M8C.
The Digital System consists of an array of digital PSoC blocks
that may be configured into any number of digital peripherals.
The digital blocks are connected to the GPIO through a series of
global buses that can route any signal to any pin, freeing designs
from the constraints of a fixed peripheral controller.
The Analog System consists of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to 8
bits in precision.
The Digital System
The Digital System consists of 4 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or combined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user module references. Digital peripheral configurations include
the following.
■PWMs (8 to 32 bit)
■PWMs with Dead band (8 to 32 bit)
■Counters (8 to 32 bit)
■Timers (8 to 32 bit)
■UART 8 bit with selectable parity
■SPI master and slave
■I2C slave and multi-master
■Cyclical Redundancy Checke r/Generator (8 to 32 bit)
■IrDA
■Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controlle r.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 4.
Figure 1. Digital System Block Diagram
DIGITAL SYSTEM
To System Bus
Digital
Clocks
From Core
Digital PSoC Block Array
To Analog
System
8
Row Input
Configuration
Row O utput
Configuration
88
8
Row 0
DBB00 DBB01 DCB02 DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 3
Port 2
Port 1
Port 0
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Document Number: 38-1202 5 Rev. *M Page 3 of 43
The Analog System
The Analog System consists of 4 configurable blocks that allow
the creation of complex ana log si gna l flows. Analog perip heral s
are very flexible and may be customized to support specific
application requirements. Some of the common PSoC analog
functions for this device (most available as user modules) are:
■Analog-to-digital converters (single or dual, with 8-bit
resolution)
■Pin-to-pin comparator
■Single-ended comparators (up to 2) with absolute (1.3V)
reference or 8-bit DAC reference
■1.3V reference (as a System Resource)
In most PSoC devices, analog blocks are provided in columns of
three, which includes one CT (Continuous Time) and two SC
(Switched Capacitor) blocks. The CY8C21x34 devices provide
limited functionality Type “E” analog blocks. Each column
contains one CT Type E block an d one SC Type E block. Refe r
to the PSoC Mixed-Signal Array T echnical Reference Manual for
detailed information on the CY8C21x34’ s Type E analog blocks.
Figure 2. Analog System Block Diagram
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins may
be connected to the bus individual ly or in any combination. The
bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. An additional 8 :1
analog input multiple xer provides a second path to bring Port 0
pins to the ana l og arra y.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■Track pad, finger sensing.
■Chip-wide mux that allows analog input from any IO pin.
■Crosspoint connection between any IO pin combinations.
When designing capacitive sensing applications, refer to the
signal-to-noise system level requirement found in Application
Note AN2403 on the Cypress web site at
http://www.cypress.com.
Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a switch mode pump, low
voltage detection, and power on reset. Brief statements
describing the merits of each system resource follow.
■Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master , and multi-mast er modes are all
supported.
■Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■An internal 1.3 voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
■An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
■Versatile analog multiplexer system.
AC OL 1MU X
ACE00 ACE01
Array
Ar ra y In pu t
Configuration
ASE10 ASE11
X
X
X
X
X
An al o g Mux Bus
All IO
ACI0[1:0] ACI1[1:0]
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Document Number: 38-1202 5 Rev. *M Page 4 of 43
PSoC Device Characteristics
Depending on you r PSoC device chara cteri stics, the di gital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog block s. Table 1 lists the resources available for specific
PSoC device groups. The PSoC device covered by this data
sheet is highlighted in this table.
Getting Started
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register ,
and electrical specifications. For in-depth information with
detai le d pro gram mi ng i nfo rmation , refer the PSoC Mixed-Signal
Array Technical Reference Manual available at
http://www.cypress.com/psoc.
For up-to-date Ordering, Packaging, and Electrical S pecification
information, refer the latest PSoC device data sheets at
http://www.cypress.com.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online S t ore web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page, and cl ick PSoC (Program-
mable System-on-Chip) to view a current list of available items.
Technical Training Modules
Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced analog and CapSense. Go to
http://www.cypress.com/techtrain.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located on the left side of the web page, and select
CYPros Consultants.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support.
Application Notes
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Design Resources list located in the center of the web
page. Application notes are sorted by date by default.
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Window s 2000, Windows
Millennium (Me), or Windows XP. (See Figure 3 on page 5)
PSoC Designer helps the customer to select an operating
configuration for the PSoC, write app lication code tha t uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debug ger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a hig h-leve l C lan gua ge compiler
developed specifically for the devices in the family.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
IO
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
CY8C29x66 up to
64 416 12 4 4 12 2K 32K
CY8C27x43 up to
44 2812 4 4 12 256
Bytes 16K
CY8C24x94 56 1 4 48 2 2 6 1K 16K
CY8C24x23A up to
24 1412 226256
Bytes 4K
CY8C21x34 up to
28 1428 0 2 4a
a. Limited analog functionality.
512
Bytes 8K
CY8C21x23 16 1 4 8 0 2 4a256
Bytes 4K
CY8C20x34 up to
28 0028 0 0 3b
b. Two analog blocks and one CapSense.
512
Bytes 8K
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Document Number: 38-1202 5 Rev. *M Page 5 of 43
Figure 3. PSoC Designer Subsystems
PSoC Designer Software Subsystems
Device Editor
The device editor subsystem enables the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration allows changing configurations at run time.
PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer can print out a configuration sheet for a given
project configuration for use du ring application programming in
conjunction with the Device Data Sheet. After the framework is
generated, the user can add application-specific code to flesh
out the framework. It is also possible to change the selected
components and regenerate the framework.
Design Browser
The Design Browser enables users to select and import
preconfigured designs into the user ’s project. Users can easily
browse a catalog of preconfigured designs to facilitate
time-to-design. Examples provided in the tools include a
300-baud modem, LIN Bus master and slave, fan controller , and
magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
Assembler. The macro assembler allows the seamless
merging of the assembly code with C code. The link libraries
automatically use absolute addressing or are compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Co mpiler. A C language compiler that supports
the PSoC family of devices i s ava ilable. Even i f you have neve r
worked in the C languag e before, the product qui ckly helps you
create complete C programs for the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the p rogram in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read the
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for pro cedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in gettin g started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed
(24 MHz) operation.
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Designing with User Modules
The development p rocess for the PSo C device differs from th at
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of use r-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the
hardware and software. This substantially lowers the risk of
having to select a different part to meet the final design
requirements.
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a lib rary of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains over 50 common peripherals such as ADCs, DACs
Timers, Counters, UARTs, and other uncommon peripherals,
such as DTMF Generators and Bi-Quad analog filte r sections .
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more di gital PSoC blocks, one for ea ch 8 b its
of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut yo ur develop ment time. The use r
module application programming interface (API) provides
high-level functions to control and respond to hardware events
at run time. The API also provides optional interrupt service
routines that you can adapt as needed.
The API functions are document ed in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graph ical user interface (GUI)
for configuring the hardware. Y ou can pick the user modules you
need for your project and map the m onto the PSoC blocks with
point-and-click simplicity. Next, you build sign al chains by inter-
connecting user module s to each other and the IO pins. At thi s
stage, you must also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project,
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically co nfigures
the device to your specification and provides the high-level user
module API functions.
Figure 4. User Module and Source Code Development Flows
The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open th e p roject source code files (including
all generated code files) from a hierarchal view . The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker . Synt ax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and enables you to define complex
breakpoint events that include monitoring address and data bus
values, memory locations, and external signals.
Debugger
Interface
to ICE
Application Editor
Device Editor
Project
Manager
Source
Code
Editor
Storage
Inspector
User
Module
Selection
Placement
and
Parameter
-ization
Generate
Application
Build
All
Event &
Breakpoint
Manager
Build
Manager
Source
Code
Generator
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Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 2 on page 7 lists all the abbreviations used to
measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
Table 2. Acronyms Used
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only
memory
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human body model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision power on reset
PSoC® Programmable System-on-Chip™
PWM pulse width modulator
SC switched capacitor
SLIMO slow IMO
SMP switch mode pump
SRAM static random access memory
[+] Feedback
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Document Number: 38-1202 5 Rev. *M Page 8 of 43
Pin Information
The CY8C21x34 PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with
a “P”) is capable of Digital IO and connection to the common analog bus. How ever, Vss, Vdd, SMP, and XRES are no t capable of
Digital IO.
16-Pin Part Pinout
Figure 5. CY8C21234 16-Pin PSoC Device
SOIC
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
P1[4], EXTCLK, M
P1[2], M
P1[0], I2C SDA, M
16
15
14
13
12
11
1
2
3
4
5
6
7
8
A, I, M , P0[7]
A, I, M , P0[5]
A, I, M , P0[3]
A, I, M , P0[1]
SMP
Vss
M, I2C SCL, P1[1]
Vss 10
9
Table 3. Pin Definitions - CY8C21234 16-Pin (SOIC)
Pin No. Type Name Description
Digital Analog
1IO I, M P0[7] Analog column mux input.
2IO I, M P0[5] Analog column mux input.
3IO I, M P0[3] Analog column mux input, integrating input.
4IO I, M P0[1] Analog column mux input, integrating input.
5Power SMP Switch Mode Pump (SMP) connection to required external components.
6Power Vss Ground connection.
7IO MP1[1] I2C Serial Clock (SCL), ISSP-SCLK*.
8Power Vss Ground connection.
9IO MP1[0] I2C Serial Data (SDA), ISSP-SDATA*.
10 IO MP1[2]
11 IO MP1[4] Optional External Clock Input (EXTCLK).
12 IO I, M P0[0] Analog column mux input.
13 IO I, M P0[2] Analog column mux input.
14 IO I, M P0[4] Analog column mux input.
15 IO I, M P0[6] Analog column mux input.
16 Power Vdd Supply voltage.
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
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Document Number: 38-1202 5 Rev. *M Page 9 of 43
20-Pin Part Pinout
Figure 6. CY8C21334 20-Pin PSoC Device
SSOP
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
XRES
P1[6], M
P1[4], EXTCLK, M
P1[2], M
P1[0], I2C SDA, M
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
A, I, M , P0[7]
A, I, M , P0[5]
A, I, M , P0[3]
A, I, M , P0[1]
M, I2C SCL, P1[7]
SDA, P1[5]
M, P1[3]
SCL, P1[1]
Vss
Vss
M, I2C
M, I2C
Table 4. Pin Definitions - CY8C21334 20-Pin (SSOP)
Pin No. Type Name Description
Digital Analog
1IO I, M P0[7] Analog column mux input.
2IO I, M P0[5] Analog column mux input.
3IO I, M P0[3] Analog column mux input, integrating in put.
4IO I, M P0[1] Analog column mux input, integrating input.
5Power Vss Ground connection.
6IO MP1[7] I2C Serial Clock (SCL).
7IO MP1[5] I2C Serial Data (SDA).
8IO MP1[3]
9IO MP1[1] I2C Serial Clock (SCL), ISSP-SCLK*.
10 Power Vss Ground connection.
11 IO MP1[0] I2C Serial Data (SDA), ISSP-SDATA*.
12 IO MP1[2]
13 IO MP1[4] Optional External Clock Input (EXTCLK).
14 IO MP1[6]
15 Input XRES Active high external reset with internal pull down.
16 IO I, M P0[0] Analog column mux input.
17 IO I, M P0[2] Analog column mux input.
18 IO I, M P0[4] Analog column mux input.
19 IO I, M P0[6] Analog column mux input.
20 Power Vdd Supply voltage.
LEGEND A = Analog, I = Input, O = Outp ut, and M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 10 of 43
28-Pin Part Pinout
Figure 7. CY8C21534 28-Pin PSoC Device
A, I, M , P0[7]
A, I, M , P0[5]
A, I, M , P0[3]
A, I, M , P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[ 1 ]
Vss
M, I2C SCL, P1[7]
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
Vss
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
XRES
P1[6], M
P1[4], EXTCLK, M
P1[2], M
P1[0], I2C SDA, M
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Table 5. Pin Definitions - CY8C21534 28-Pin (SSOP)
Pin No. Type Name Description
Digital Analog
1IO I, M P0[7] Analog column mux input.
2IO I, M P0[5] Analog column mux input and column output.
3IO I, M P0[3] Analog column mux input and column output, integrating input.
4IO I, M P0[1] Analog column mux input, integrating input.
5IO MP2[7]
6IO MP2[5]
7IO I, M P2[3] Direct switched capacitor block input.
8IO I, M P2[1] Direct switched capacitor block input.
9Power Vss Ground connection.
10 IO MP1[7] I2C Serial Clock (SCL).
11 IO MP1[5] I2C Serial Data (SDA).
12 IO MP1[3]
13 IO MP1[1] I2C Serial Clock (SCL), ISSP-SCLK*.
14 Power Vss Ground connection.
15 IO MP1[0] I2C Serial Data (SDA), ISSP-SDATA*.
16 IO MP1[2]
17 IO MP1[4] Optional External Clock Input (EXTCLK).
18 IO MP1[6]
19 Input XRES Active high external reset with internal pull down.
20 IO I, M P2[0] Direct switched capacitor block input.
21 IO I, M P2[2] Direct switched capacitor block input.
22 IO MP2[4]
23 IO MP2[6]
24 IO I, M P0[0] Analog column mux input.
25 IO I, M P0[2] Analog column mux input.
26 IO I, M P0[4] Analog column mux input
27 IO I, M P0[6] Analog column mux input.
28 Power Vdd Supply voltage.
LEGEND A: Analog, I: Input, O = Outpu t, and M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
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CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 11 of 43
32-Pin Part Pinout
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
SMP
QFN
(Top View)
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
Vss
P0[3], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
Vss
M, 12C SCL, P1[7]
P0[0], A, I, M
P2[6], M
P3[0], M
XRES
M, 12C SDA, P1[5]
M, P1[3]
M, 12C SCL, P1[1]
Vss
M, 12C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P0[5], A, I, M
Figure 8. CY8C21434 32-Pin PSoC Device Figure 9. CY8C21634 32-Pin PSoC Device
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
M, P3[3]
QFN
(Top View)
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
Vss
P0[3], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
M, P3[1]
M, 12C SCL, P1[7]
P0[0], A, I, M
P2[6], M
P3[0], M
XRES
M, 12C SDA, P1[5]
M, P1[3]
M, 12C SCL, P1[1]
Vss
M, 12C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P0[5], A, I, M
Figure 10. CY8C21434 32-Pin Sawn PSoC Device Figure 11. CY8C21634 32-Pin Sawn PSoC Device
[+] Feedback
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CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 12 of 43
Table 6. Pin Definitions - CY8C21434/CY8C21634 32-Pin (QFN**)
Pin
No. Type Name Description
Digital Analog
1IO I, M P0[1] Analog column mux input, integrating input.
2IO M P2[7]
3IO M P2[5]
4IO MP2[3]
5IO MP2[1]
6IO M P3[3] In CY8C21434 part.
6Power SMP Switch Mode Pump (SMP) connection to required external components in
CY8C21634 part.
7IO MP3[1] In CY8C21434 part.
7Power Vss Ground connection in CY8C21634 part.
8IO MP1[7] I2C Serial Clock (SCL).
9IO MP1[5] I2C Serial Data (SDA).
10 IO MP1[3]
11 IO MP1[1] I2C Serial Clock (SCL), ISSP-SCLK*.
12 Power Vss Ground connection.
13 IO MP1[0] I2C Serial Data (SDA), ISSP-SDATA*.
14 IO MP1[2]
15 IO MP1[4] Optional External Clock Input (EXTCLK).
16 IO MP1[6]
17 Input XRES Active high external reset with intern al pull down.
18 IO M P3[0]
19 IO M P3[2]
20 IO MP2[0]
21 IO MP2[2]
22 IO MP2[4]
23 IO MP2[6]
24 IO I, M P0[0] Analog column mux input.
25 IO I, M P0[2] Analog column mux input.
26 IO I, M P0[4] Analog column mux input.
27 IO I, M P0[6] Analog column mux input.
28 Power Vdd Supply voltage.
29 IO I, M P0[7] Analog column mux input.
30 IO I, M P0[5] Analog column mux input.
31 IO I, M P0[3] Analog column mux input, integrating input.
32 Power Vss Ground connection.
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
** The center pad on the QFN package must be conn ected to ground (Vss) for best mechanical, the rmal, and electrical performance. If not connected to gr ound, it must
be electrically floated and not connected to any other signal.
[+] Feedback
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CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 13 of 43
56-Pin Part Pinout
The 56-pin SSOP part is for the CY8C21001 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for productio n.
Figure 12. CY8C21001 56-Pin PSoC Device
Table 7. Pin Definitions - CY8C21001 56-Pin (SSOP)
Pin No. Type Pin Name Description
Digital Analog
1Power Vss Ground connection.
2IO I P0[7] Analog column mux inpu t.
3IO I P0[5] Analog column mux inpu t and column output.
4IO I P0[3] Analog column mux inpu t and column output.
5IO I P0[1] Analog column mux inpu t.
6IO P2[7]
7IO P2[5]
8IO I P2[3] Direct switched capacitor block input.
9IO I P2[1] Direct switched capacitor block input.
10 NC No connection.
11 NC No connection.
12 NC No connection.
13 NC No connection.
14 OCD OCDE OCD even data IO.
15 OCD OCDO OCD odd data output.
16 Power SMP Switch Mode Pump (SMP) connection to required external components.
17 Power Vss Ground connection.
18 Power Vss Ground connection.
19 IO P3[3]
SSOP
156 Vdd
2
AI, P0[7] 55 P0[6], AI
3
AI, P0[5] 54 P0[4], AI
4
AI, P0[3] 53 P0[2], AI
5
AI, P0[1] 52 P0[0], AI
6
P2[7] 51 P2[6]
7
P2[5] 50 P2[4]
8
P2[3] 49 P2[2]
9P2[1] 48 P2[0]
10
NC 47 NC
11
NC 46 NC
12NC 45 P3[2]
13
NC 44 P3[0]
14OCDE 43 CCLK
15
OCDO 42 HCLK
16
SMP 41 XRES
17
Vss 40 NC
18
Vss 39 NC
19
P3[3] 38 NC
20
P3[1] 37 NC
21
NC 36 NC
22
NC 35 NC
23I2C SCL, P1[7] 34 P1[6]
24
I2C SDA, P1[5] 33 P1[4], EXTCLK
25
NC 32 P1[2]
26
P1[3] 31 P1[0], I2C SDA, SDATA
27
SCLK, I2C SCL, P1[1] 30 NC
28Vss 29 NC
Vss
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CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 14 of 43
20 IO P3[1]
21 NC No connection.
22 NC No connection.
23 IO P1[7] I2C Serial Clock (SCL).
24 IO P1[5] I2C Serial Data (SDA).
25 NC No connection.
26 IO P1[3] IFMTEST.
27 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*.
28 Power Vss Ground connection.
29 NC No connection.
30 NC No connection.
31 IO P1[0] Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA*.
32 IO P1[2] VFMTEST.
33 IO P1[4] Optional External Clock Input (EXTCLK).
34 IO P1[6]
35 NC No connection.
36 NC No connection.
37 NC No connection.
38 NC No connection.
39 NC No connection.
40 NC No connection.
41 Input XRES Active high external reset with internal pull down.
42 OCD HCLK OCD high-speed clock output.
43 OCD CCLK OCD CPU clock output.
44 IO P3[0]
45 IO P3[2]
46 NC No connection.
47 NC No connection.
48 IO I P2[0]
49 IO I P2[2]
50 IO P2[4]
51 IO P2[6]
52 IO I P0[0] Analog column mux inpu t.
53 IO I P0[2] Analog column mux inpu t and column output.
54 IO I P0[4] Analog column mux inpu t and column output.
55 IO I P0[6] Analog column mux inpu t.
56 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Table 7. Pin Definitions - CY8C21001 56-Pin (SSOP) (continued)
Pin No. Type Pin Name Description
Digital Analog
[+] Feedback
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CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 15 of 43
Register Reference
This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, refer the PSoC Mixed-Signal Array
Technical Reference Manual.
Register Conventions
The register conventions spe ci fic to this section are listed in Table 8.
Register Mapping Tables
The PSoC devi ce has a total register add ress space of 512 bytes. The register space is referred to as IO space and is divided i nto
two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user
is in Bank 1.
Note In the following register mapping tables, blank fields are Reserved and must not be accessed.
Table 8. Register Conventions
Convention Description
R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific
Table 9. Register Map 0 Table: User Sp ace
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
PRT0DR 00 RW 40 ASE10CR0 80 RW C0
PRT0IE 01 RW 41 81 C1
PRT0GS 02 RW 42 82 C2
PRT0DM2 03 RW 43 83 C3
PRT1DR 04 RW 44 ASE11CR0 84 RW C4
PRT1IE 05 RW 45 85 C5
PRT1GS 06 RW 46 86 C6
PRT1DM2 07 RW 47 87 C7
PRT2DR 08 RW 48 88 C8
PRT2IE 09 RW 49 89 C9
PRT2GS 0A RW 4A 8A CA
PRT2DM2 0B RW 4B 8B CB
PRT3DR 0C RW 4C 8C CC
PRT3IE 0D RW 4D 8D CD
PRT3GS 0E RW 4E 8E CE
PRT3DM2 0F RW 4F 8F CF
10 50 90 CUR_PP D0 RW
11 51 91 STK_PP D1 RW
12 52 92 D2
13 53 93 IDX_PP D3 RW
14 54 94 MVR_PP D4 RW
15 55 95 MVW_PP D5 RW
16 56 96 I2C_CFG D6 RW
17 57 97 I2C_SCR D7 #
18 58 98 I2C_DR D8 RW
19 59 99 I2C_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C DC
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F DF
Blank fields are Reserved and must not be accessed . # Access is bit specific.
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CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 16 of 43
DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW
DBB00DR1 21 W AMUXCFG 61 RW A1 INT_MSK1 E1 RW
DBB00DR2 22 RW PWM_CR 62 RW A2 INT_VC E2 RC
DBB00CR0 23 # 63 A3 RES_WDT E3 W
DBB01DR0 24 # CMP_CR0 64 # A4 E4
DBB01DR1 25 W 65 A5 E5
DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW
DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW
DCB02DR0 28 # ADC0_CR 68 #A8 E8
DCB02DR1 29 W ADC1_CR 69 #A9 E9
DCB02DR2 2A RW 6A AA EA
DCB02CR0 2B # 6B AB EB
DCB03DR0 2C # TMP_DR0 6C RW AC EC
DCB03DR1 2D W TMP_DR1 6D RW AD ED
DCB03DR2 2E RW TMP_DR2 6E RW AE EE
DCB03CR0 2F # TMP_DR3 6F RW AF EF
30 70 RDI0RI B0 RW F0
31 71 RDI0SYN B1 RW F1
32 ACE00CR1 72 RW RDI0IS B2 RW F2
33 ACE00CR2 73 RW RDI0LT0 B3 RW F3
34 74 RDI0LT1 B4 RW F4
35 75 RDI0RO0 B5 RW F5
36 ACE01CR1 76 RW RDI0RO1 B6 RW F6
37 ACE01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD DAC_D FD RW
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Table 9. Register Map 0 Table: User Sp ace (continued)
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Blank fields are Reserved and must not be accessed . # Access is bit specific.
Table 10. Register Map 1 Table: Configuration Space
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
PRT0DM0 00 RW 40 ASE10CR0 80 RW C0
PRT0DM1 01 RW 41 81 C1
PRT0IC0 02 RW 42 82 C2
PRT0IC1 03 RW 43 83 C3
PRT1DM0 04 RW 44 ASE11CR0 84 RW C4
PRT1DM1 05 RW 45 85 C5
PRT1IC0 06 RW 46 86 C6
PRT1IC1 07 RW 47 87 C7
PRT2DM0 08 RW 48 88 C8
PRT2DM1 09 RW 49 89 C9
PRT2IC0 0A RW 4A 8A CA
PRT2IC1 0B RW 4B 8B CB
PRT3DM0 0C RW 4C 8C CC
PRT3DM1 0D RW 4D 8D CD
PRT3IC0 0E RW 4E 8E CE
PRT3IC1 0F RW 4F 8F CF
10 50 90 GDI_O_IN D0 RW
11 51 91 GDI_E_IN D1 RW
12 52 92 GDI_O_OU D2 RW
13 53 93 GDI_E_OU D3 RW
14 54 94 D4
Blank fields are Reserved and must not be accessed . # Access is bit specific.
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CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 17 of 43
15 55 95 D5
16 56 96 D6
17 57 97 D7
18 58 98 MUX_CR0 D8 RW
19 59 99 MUX_CR1 D9 RW
1A 5A 9A MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW
1C 5C 9C DC
1D 5D 9D OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW
DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW
DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW
23 AMD_CR0 63 RW A3 VLT_CR E3 RW
DBB01FN 24 RW CMP_GO_EN 64 RW A4 VLT_CMP E4 R
DBB01IN 25 RW 65 A5 ADC0_TR E5 RW
DBB01OU 26 RW AMD_CR1 66 RW A6 ADC1_TR E6 RW
27 ALT_CR0 67 RW A7 E7
DCB02FN 28 RW 68 A8 IMO_TR E8 W
DCB02IN 29 RW 69 A9 ILO_TR E9 W
DCB02OU 2A RW 6A AA BDG_TR EA RW
2B CLK_CR3 6B RW AB ECO_TR EB W
DCB03FN 2C RW TMP_DR0 6C RW AC EC
DCB03IN 2D RW TMP_DR1 6D RW AD ED
DCB03OU 2E RW TMP_DR2 6E RW AE EE
2F TMP_DR3 6F RW AF EF
30 70 RDI0RI B0 RW F0
31 71 RDI0SYN B1 RW F1
32 ACE00CR1 72 RW RDI0IS B2 RW F2
33 ACE00CR2 73 RW RDI0LT0 B3 RW F3
34 74 RDI0LT1 B4 RW F4
35 75 RDI0RO0 B5 RW F5
36 ACE01CR1 76 RW RDI0RO1 B6 RW F6
37 ACE01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FLS_PR1 FA RW
3B 7B BB FB
3C 7C BC FC
3D 7D BD DAC_CR FD RW
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Table 10. Register Map 1 Table: Configuration Space (continued)
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Blank fields are Reserved and must not be accessed . # Access is bit specific.
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 18 of 43
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For up to date electrical specifications,
visit the web site http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC as specified, except where noted.
Refer Table 25 on page 26 for the electrical specifications on the internal ma in oscillator (IMO) using SLIMO mode.
Table 11 lists the units of measure that are used in this section.
Table 11. Units of Measure
Symbol Unit of Measure Symbol Unit of Measure
oCdegree Celsius μWmicrowatts
dB decibels mA milli-ampere
fF femto farad ms milli-second
Hz hertz mV milli-volts
KB 1024 bytes nA nanoampere
Kbit 1024 bits ns nanosecond
kHz kilohertz nV nanovolts
kΩkilohm Wohm
MHz megahertz pA picoampere
MΩmegaohm pF picofarad
μAmicroampere pp peak-to-peak
μFmicrofarad ppm parts per million
μHmicrohenry ps picosecond
μsmicrosecond sps samples per second
μVmicrovolts ssigma: one standard deviation
μVrms microvolts root-mean-square Vvolts
5.25
4.75
3.00
93 kHz 12 MHz 24 MHz
CPU Frequency
Vdd Voltage
5.25
4.75
3.00
93 kHz 12 MHz 24 MHz
IMO Frequency
Vdd Voltage
3.60
6 MHz
SLIMO Mode = 0
SLIMO
Mode=0
2.40
SLIMO
Mode=1
SLIMO
Mode=1 SLIMO
Mode=1
2.40
3 MHz
Valid
Operating
Region
SLIMO
Mode=1
SLIMO
Mode=0
Figure 13. Voltage versus CPU Frequency Figure 14. IMO Frequency T rim Options
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Document Number: 38-1202 5 Rev. *M Page 19 of 43
Absolute Maximum Ratings
Operating Temperature
DC Electrical Characteristics
DC Chip-Level Specifications
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 12. Absolute Maximum Ratings
Symbol Description Min Typ Max Units Notes
TSTG Storage Temperature -55 25 +100 oCHigher storage temperatu r es
reduce dat a retention time. Recom-
mended storage temperature is
+25oC ± 25oC. Extended duration
storage temperatures above 65oC
degrade reliability.
TAAmbient Temperature with Power Applied -40 –+85 oC
Vdd Supply Voltage on Vdd Relative to Vss -0.5 –+6.0 V
VIO DC Input Voltage Vss -
0.5 –Vdd +
0.5 V
VIOZ DC Voltage Applied to Tri-state Vss -
0.5 –Vdd +
0.5 V
IMIO Maximum Current into any Port Pin -25 –+50 mA
ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD.
LU Latch-up Current – – 200 mA
Table 13. Operating Temperature
Symbol Description Min Typ Max Units Notes
TAAmbient Te mperature -40 –+85 oC
TJJunction Temperature -40 –+100 oCThe temperature rise from ambient
to junction is package specific. See
T able 40 on page 38. The user must
limit the power consumption to
comply with this requiremen t.
Table 14. DC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
Vdd Supply Voltage 2.40 –5.25 VSee Table 23 on page 24.
IDD Supply Current, IMO = 24 MHz – 3 4 mA Conditions are Vdd = 5.0V,
TA = 25oC, CPU = 3 MHz, 48 MHz
disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz.
IDD3 Supply Current, IMO = 6 MHz using SLIMO
mode. –1.2 2mA Conditions are Vdd = 3.3V,
TA = 25oC, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz.
IDD27 Supply Current, IMO = 6 MHz using SLIMO
mode. –1.1 1.5 mA Conditions are Vdd = 2.55V,
TA = 25oC, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz.
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 20 of 43
DC General Purpose IO Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T A ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85°C, respectively . Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
ISB27 Sleep (Mode) Current with POR, LVD, Sleep
T imer , WDT, and internal slow oscillator active.
Mid temperature range.
–2.6 4. μAVdd = 2.55V, 0oC ≤ TA ≤ 40oC.
ISB Sleep (Mode) Current with POR, LVD, Sleep
T imer, WDT, and internal slow oscillator active. –2.8 5μAVdd = 3.3V, -40oC ≤ TA ≤ 85oC.
VREF Reference Voltage (Bandgap) 1.28 1.30 1.32 VTrimmed for appropriate Vdd.
Vdd = 3.0V to 5.25V.
VREF27 Reference Voltage (Bandgap) 1.16 1.30 1.33 VTrimmed for appropriate Vdd. Vdd =
2.4V to 3.0V.
AGND Analog Ground VREF
- 0.003 VREF VREF
+ 0.003 V
Table 14. DC Chip-Level Specifications (continued)
Symbol Description Min Typ Max Units Notes
Table 15. 5V and 3.3V DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
RPU Pull up Resistor 4 5.6 8 kΩ
RPD Pull down Resistor 4 5.6 8 kΩ
VOH High Output Level Vdd -
1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
VOL Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
VIL Input Low Level – – 0.8 V Vdd = 3.0 to 5.25.
VIH Input High Le ve l 2.1 – V Vdd = 3.0 to 5.25.
VHInput Hysteresis –60 –mV
IIL Input Leakage (Absolute Value) –1–nA Gross tested to 1 μA.
CIN Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent.
Temp = 25oC.
COUT Capacitive Load on Pins as Output –3.5 10 pF Package and pin dependent.
Temp = 25oC.
Table 16. 2.7V DC GPIO Sp ecifications
Symbol Description Min Typ Max Units Notes
RPU Pull up Resistor 4 5.6 8 kΩ
RPD Pull down Resistor 4 5.6 8 kΩ
VOH High Output Level Vdd -
0.4 – – V IOH = 2.5 mA (6.25 Typ), Vdd = 2.4
to 3.0V (16 mA maximum, 50 mA Typ
combined IOH budget).
VOL Low Output Level – – 0.75 V IOL = 10 mA, Vdd = 2.4 to 3.0V (90
mA maximum combined IOL
budget).
VIL Input Low Level – – 0.75 V Vdd = 2.4 to 3.0.
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 21 of 43
DC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T A ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85°C, respectively . Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
VIH Input High Level 2.0 – – V Vdd = 2.4 to 3.0.
VHInput Hysteresis – 90 – mV
IIL Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA.
CIN Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent.
Temp = 25oC.
COUT Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dependent.
Temp = 25oC.
Table 16. 2.7V DC GPIO Sp ecifications (continued)
Symbol Description Min Typ Max Units Notes
Table 17. 5V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input Offset Voltage (absolute value) – 2.5 15 mV
TCVOSOA Average Input Offset Voltage Drift – 10 – μV/oC
IEBOAa
a. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.
Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.
CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent.
Temp = 25oC.
VCMOA Common Mode Voltage Range 0.0 – Vdd - 1 V
GOLOA Open Loop Gain – 80 – dB
ISOA Amplifier Supply Current – 10 30 μA
Table 18. 3.3V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input Offset Voltage (absolute value) – 2.5 15 mV
TCVOSOA Average Input Offset Voltage Drift – 10 – μV/oC
IEBOAaInput Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.
CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent.
Temp = 25oC.
VCMOA Common Mode Voltage Range 0 – Vdd - 1 V
GOLOA Open Loop Gain – 80 – dB
ISOA Amplifier Supply Current – 10 30 μA
a.Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.
Table 19. 2.7V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input Offset Voltage (absolute value) – 2.5 15 mV
TCVOSOA Average Input Offset Voltage Drift – 10 – μV/oC
IEBOAaInput Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.
CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent.
Temp = 25oC.
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 22 of 43
DC Low Power Comparator Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V at 25°C and are for design guidance only.
DC Switch Mode Pump Specifications
Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
VCMOA Common Mode Voltage Range 0 – Vdd - 1 V
GOLOA Open Loop Gain – 80 – dB
ISOA Amplifier Supply Current – 10 30 μA
a. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.
Table 19. 2.7V DC Operational Amplifier Specifications (continued)
Symbol Description Min Typ Max Units Notes
Table 20. DC Low Power Comparator Specifications
Symbol Description Min Typ Max Units Notes
VREFLPC Low power comparator (LPC) reference
voltage range 0.2 – Vdd - 1 V
ISLPC LPC supply current – 10 40 μA
VOSLPC LPC voltage offset – 2.5 30 mV
Table 21. DC Switch Mode Pump (SMP) Specifications
Symbol Description Min Typ Max Units Notes
VPUMP5V 5V Output Voltage from Pump 4.75 5.0 5.25 V Configuration of footnote.a
Average, neglecting ripple.
SMP trip voltage is set to 5.0V.
VPUMP3V 3.3V Output Voltage from Pump 3.00 3.25 3.60 V Con figuration of footnote.a
Average, neglecting ripple.
SMP trip voltage is set to 3.25V .
VPUMP2V 2.6V Output Voltage from Pump 2.45 2.55 2.80 V Con figuration of footnote.a
Average, neglecting ripple.
SMP trip voltage is set to 2.55V .
IPUMP Available Output Current
VBAT = 1.8V, VPUMP = 5.0V
VBAT = 1.5V, VPUMP = 3.25V
VBAT = 1.3V, VPUMP = 2.55V
5
8
8
–
–
–
–
–
–
mA
mA
mA
Configuration of footnote.a
SMP trip voltage is set to 5.0V.
SMP trip voltage is set to 3.25V .
SMP trip voltage is set to 2.55V .
VBAT5V Input Voltage Range from Battery 1.8 – 5.0 V Configuration of footnote.a
SMP trip voltage is set to 5.0V.
VBAT3V Input Voltage Range from Battery 1.0 – 3.3 V Configuration of footnote.a
SMP trip voltage is set to 3.25V .
VBAT2V Input Voltage Range from Battery 1.0 – 2.8 V Configuration of footnote.a
SMP trip voltage is set to 2.55V .
VBATSTA
RT Minimum Input Voltage from Battery to Start
Pump 1.2 – – V Configuration of footnote.a 0oC
≤ TA ≤ 100. 1.25V at TA = -40oC.
ΔVPUMP_
Line Line Regulation (over Vi range) – 5 – %VOConfiguration of footnote.a VO
is the “Vdd Value for PUMP
Trip” speci fied by the VM[2:0]
setting in the DC POR and LVD
Specification, T able 23 on page
24.
[+] Feedback
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CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 23 of 43
Figure 15. Basic Switch Mode Pump Circuit
ΔVPUMP_
Load Load Regulation – 5 – %VOConfiguration of footnote.a VO
is the “Vdd Value for PUMP
Trip” speci fied by the VM[2:0]
setting in the DC POR and LVD
Specification, T able 23 on page
24.
ΔVPUMP_
Ripple Output Voltage Ripple (depends on cap/load) – 100 – mVpp Configuration of footno te.a
Load is 5 mA.
E3Efficiency 35 50 – % Confi guration of footnote.a
Load is 5 mA. SMP trip voltage
is set to 3.25V.
E2Efficiency 35 80 – % For I load = 1mA, VPUMP =
2.55V, VBAT = 1.3V,
10 uH inductor , 1 uF capacitor ,
and Schottky diode.
FPUMP Switching Frequency – 1.3 – MHz
DCPUMP Sw itching Duty Cycle – 50 – %
a. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 15.
Table 21. DC Switch Mode Pump (SMP) Specifications (continued)
Symbol Description Min Typ Max Units Notes
Battery C1
D1
+PSoC
Vdd
Vss
SMP
VBAT
L1
VPUMP
[+] Feedback
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CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 24 of 43
DC Analog Mux Bus Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
DC POR and LVD Specifications
Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 22. DC Analog Mux Bus Specifications
Symbol Description Min Typ Max Units Notes
RSW Switch Resistance to Common Analog Bus – – 400
800 W
WVdd ≥ 2.7V
2.4V ≤ Vdd ≤ 2.7V
RVDD Resistance of Initialization Switch to Vdd – – 800 W
Table 23. DC POR and LVD Specifications
Symbol Description Min Typ Max Units Notes
VPPOR0
VPPOR1
VPPOR2
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b –2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
Vdd must be greater than or equal
to 2.5V during startup, reset from
the XRES pin, or reset from
Watchdog.
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Tr ip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.45
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.51a
2.99b
3.09
3.20
4.55
4.75
4.83
4.95
a. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply.
b. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply.
V
V
V
V
V
V
V
V
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
Vdd Value for PUMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.45
2.96
3.03
3.18
4.54
4.62
4.71
4.89
2.55
3.02
3.10
3.25
4.64
4.73
4.82
5.00
2.62c
3.09
3.16
3.32d
4.74
4.83
4.92
5.12
c. Always greater than 50 mV above VLVD0.
d. Always greater than 50 mV above VLVD3.
V
V
V
V
V
V
V
V
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 25 of 43
DC Programming Specifications
Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 24. DC Programming Specifications
Symbol Description Min Typ Max Units Notes
VddIWRITE Supply Voltage for Flash Write Operations 2.70 ––V
IDDP Supply Current During Programming or Verify – 5 25 mA
VILP Input Low Voltage During Programming or
Verify – – 0.8 V
VIHP Input High Voltage During Programming or
Verify 2.2 ––V
IILP Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify – – 0.2 mA Driving internal pull down resistor.
IIHP Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify – – 1.5 mA Driving internal pull down resistor.
VOLV Output Low V oltage During Programming or
Verify – – Vss +
0.75 V
VOHV Output High Voltage During Programming or
Verify Vdd -
1.0 –Vdd V
FlashENPB Flash Endurance (per block) 50,000 –––Erase/write cycles per block.
FlashENT Flash Endurance (total)a
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum
cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles
to 36x50,000 and that no single block ever sees more than 50,000 cycles).
b For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature
argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more
information.
1,800,
000 –––Erase/write cycles.
FlashDR Flash Data Retention 10 ––Years
[+] Feedback
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Document Number: 38-1202 5 Rev. *M Page 26 of 43
AC Electrical Characteristics
AC Chip-Level Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T A ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85°C, respectively . Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 25. 5V and 3.3V AC Chip-Level Specificati on s
Symbol Description Min Typ Max Units Notes
FIMO24 Internal Main Oscillator Frequency for 24 MHz 23.4 24 24.6a,b,
cMHz Trimmed for 5V or 3.3V operation
using factory trim values. See
Figure 14 on page 18. SLIMO
mode = 0.
FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 66.35a,b,
cMHz Trimmed for 5V or 3.3V operation
using factory trim values. See
Figure 14 on page 18. SLIMO
mode = 1.
FCPU1 CPU Frequency (5V Nomina l) 0.93 24 24.6a,b
a. 4.75V < Vdd < 5.25V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
MHz 24 MHz only for SLIMO mode = 0.
FCPU2 CPU Frequency (3.3V Nomina l) 0.93 12 12.3b,c
c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “ Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information
on trimming for operation at 3.3V.
MHz
FBLK5 Digital PSoC Block Frequency0(5V Nominal) 048 49.2a,b,
d
d. See the individual user module data sheets for information on maximum frequencies for user modules.
MHz Refer to the AC Digital Block
Specifications.
FBLK33 Digital PSoC Block Frequency (3.3V Nominal) 024 24.6b,d MHz
F32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHz
Jitter32k 32 kHz RMS Period Jitter –100 200 ns
Jitter32k 32 kHz Peak-to-Peak Period Jitter –1400 –
TXRST External Reset Pulse Width 10 – – μs
DC24M 24 MHz Duty Cycle 40 50 60 %
Step24M 24 MHz Trim Step Size – 50 – kHz
Fout48M 48 MHz Output Frequency 46.8 48.0 49.2a,c MHz Trimmed. Using factory trim
values.
Jitter24M1 24 MHz Peak-to-Peak Period Jitter (IMO) –600 ps
FMAX Maximum frequency of signal on row input or
row output. – – 12.3 MHz
TRAMP Supply Ramp T ime 0 – – μs
Table 26. 2.7V AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
FIMO12 Internal Main Oscillator Frequency for 12 MHz 11.5 12012.7a,b,
cMHz Trimmed for 2.7V operation using
factory trim values. See Figure 14
on page 18. SLIMO mode = 1.
FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 66.35a,b,
cMHz Trimmed for 2.7V operation using
factory trim values. See Figure 14
on page 18. SLIMO mode = 1.
FCPU1 CPU Frequency (2.7V Nomina l) 0.093 33.15a,b MHz 24 MHz only for SLIMO mode = 0.
FBLK27 Digital PSoC Block Frequency (2.7V Nominal) 012 12.5a,b,
cMHz Refer to the AC Digital Block
Specifications.
F32K1 Internal Low Speed Oscillator Frequency 832 96 kHz
[+] Feedback
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Document Number: 38-1202 5 Rev. *M Page 27 of 43
Figure 16. 24 MHz Period Jitter (IMO) Timing Diagram
Figure 17. 32 kHz Period Jitter (ILO) Timing Diagram
AC General Purpose IO Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T A ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85°C, respectively . Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Jitter32k 32 kHz RMS Period Jitter –150 200 ns
Jitter32k 32 kHz Peak-to-Peak Period Jitter –1400 –
TXRST External Reset Pulse Width 10 – – μs
FMAX Maximum frequency of signal on row input or
row output. – – 12.3 MHz
TRAMP Supply Ramp T ime 0 – – μs
a. 2.4V < Vdd < 3.0V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
c. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum
frequency for user modules.
Table 26. 2.7V AC Chip-Level Specifications (continued)
Symbol Description Min Typ Max Units Notes
Jitter24M1
F24M
Jitter32k
F32K1
Table 27. 5V and 3.3V AC GPIO Specifications
Symbol Description Min Typ Max Units Notes
FGPIO GPIO Operating Frequency 0–12 MHz Normal Strong Mode
TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.5 to 5.25V , 10% - 90%
TFallF Fall Time, Normal S trong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90%
TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 7 27 – ns Vdd = 3 to 5.25V, 10% - 90%
TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 7 22 – ns Vdd = 3 to 5.25V, 10% - 90%
Table 28. 2.7V AC GPIO Sp ecifications
Symbol Description Min Typ Max Units Notes
FGPIO GPIO Operating Frequency 0–3MHz Normal Strong Mode
TRiseF Rise T ime, Normal Strong Mode, Cload = 50 pF 6–50 ns Vdd = 2.4 to 3.0V, 10% - 90%
TFallF Fall Time, Normal S trong Mode, Cload = 50 pF 6–50 ns Vdd = 2.4 to 3.0V, 10% - 90%
TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 18 40 120 ns Vdd = 2.4 to 3.0V, 10% - 90%
TFallS Fall Time, Slow S trong Mode, Cload = 50 pF 18 40 120 ns Vdd = 2.4 to 3.0V, 10% - 90%
[+] Feedback
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Document Number: 38-1202 5 Rev. *M Page 28 of 43
Figure 18. GPIO Timing Diagram
AC Operational Amplifier Specifications
Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
AC Low Power Comparator Specifications
Table 30 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V at 25°C and are for design guidance only.
AC Analog Mux Bus Specifications
Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
TFallF
TFallS
TRiseF
TRiseS
90%
10%
GPIO
Pin
Output
Voltage
Table 29. AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
TCOMP Comparator Mode Response Time, 50 mV
Overdrive 100
200 ns
ns Vdd ≥ 3.0V.
2.4V < Vcc < 3.0V.
Table 30. AC Low Power Comparator Specifications
Symbol Description Min Typ Max Units Notes
TRLPC LPC response time – – 50 μs≥ 50 mV overdrive comparator
reference set within VREFLPC.
Table 31. AC Analog Mux Bus Specifications
Symbol Description Min Typ Max Units Notes
FSW Switch Rate – – 3.17 MHz
[+] Feedback
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Document Number: 38-1202 5 Rev. *M Page 29 of 43
AC Digital Block Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T A ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85°C, respectively . Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 32. 5V and 3.3V AC Digital Block Specifications
Function Description Min Typ Max Units Notes
All
Functions Maximum Block Clocking Frequency (> 4.75V) 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Block Clocking Frequency (< 4.75V) 24.6 MHz 3.0V < Vdd < 4.75V.
Timer Capture Pu lse Wi dth 50a
a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
– – ns
Maximum Frequency, No Capture – – 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency , With or Without Capture – – 24.6 MHz
Counter Enable Pulse Width 50 – – ns
Maximum Frequency, No Enable Input – – 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, Enable Input – – 24.6 MHz
Dead Band Kill Pulse Width:
Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 50 – – ns
Disable Mode 50 – – ns
Maximum Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.
CRCPRS
(PRS
Mode)
Maximum Input Clock Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.
CRCPRS
(CRC
Mode)
Maximum Input Clock Frequency – – 24.6 MHz
SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz
due to 2 x over clocking.
SPIS Maximum Input Clock Frequency – – 4.1 MHz
Width of SS_ Negated Between Transmissions 50 – – ns
Transmitter Maximum Input Clock Frequency
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
–
–
–
–
24.6
49.2
MHz
MHz
Maximum data rate at 3 .08 MHz
due to 8 x over clocking.
Maximum data rate at 6 .15 MHz
due to 8 x over clocking.
Receiver Maximum Input Clock Frequency
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
–
–
–
–
24.6
49.2
MHz
MHz
Maximum data rate at 3 .08 MHz
due to 8 x over clocking.
Maximum data rate at 6 .15 MHz
due to 8 x over clocking.
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 30 of 43
AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2 .7V at 25°C
and are for design guidance only.
Table 33. 2.7V AC Digital Block Specifications
Function Description Min Typ Max Units Notes
All
Functions Maximum Block Clocking Frequency 12.7 MHz 2.4V < Vdd < 3.0V.
Timer Capture Pu lse Wi dth 100a– – ns
Maximum Frequency , With or Without Capture – – 12.7 MHz
Counter Enable Pulse Width 100 – – ns
Maximum Frequency, No Enable Input – – 12.7 MHz
Maximum Frequency, Enable Input – – 12.7 MHz
Dead Band Kill Pulse Width:
Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 100 – – ns
Disable Mode 100 – – ns
Maximum Frequency – – 12.7 MHz
CRCPRS
(PRS
Mode)
Maximum Input Clock Frequency – – 12.7 MHz
CRCPRS
(CRC
Mode)
Maximum Input Clock Frequency – – 12.7 MHz
SPIM Maximum Input Clock Frequency – – 6.35 MHz M a ximum data rate at 3.1 7 MHz
due to 2 x over clocking.
SPIS Maximum Input Clock Frequency – – 4.1 MHz
Width of SS_ Negated Between Transmissions 100 – – ns
Transmitter Maximum Input Clock Frequency – – 12.7 MHz Maximum data rate at 1.59 MH z
due to 8 x over clocking.
Receiver Maximum Input Clock Frequency – – 12.7 MHz M a ximum data rate at 1.5 9 MHz
due to 8 x over clocking.
a. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Table 34. 5V AC External Clock Specifications
Symbol Description Min Typ Max Units
FOSCEXT Frequency 0.093 –24.6 MHz
– High Period 20.6 –5300 ns
– Low Period 20.6 ––ns
– Power Up IMO to Switch 150 – – μs
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 31 of 43
AC Programming Specifications
Table 37 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, or 3 .0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25 °C and are for
design guid an ce on ly.
Table 35. 3.3V AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency with CPU Clock divide by 1 0.093 – 12.3 MHz Maximum CPU frequency is 12
MHz at 3.3V. With the CPU clock
divider set to 1, the external clock
must adhere to the maximum
frequency and duty cycle
requirements.
FOSCEXT Frequency with CPU Clock divide by 2 or
greater 0.186 – 24.6 MHz If the frequency of the external clock
is greater than 12 MHz, the CPU
clock divider must be set to 2 or
greater . In this case, the CPU clock
divider ensures that the fifty percent
duty cycle requirement is met.
– High Period with CPU Clock divide by 1 41.7 –5300 ns
– Low Period with CPU Clock divide by 1 41.7 ––ns
– Power Up IMO to Switch 150 – – μs
Table 36. 2.7V AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency with CPU Clock divide by 1 0.093 –3.08
0MHz Maximum CPU frequency is 3 MHz
at 2.7V. With the CPU clock divider
set to 1, the external clock must
adhere to the maximum frequency
and duty cycle requi rements.
FOSCEXT Frequency with CPU Clock divide by 2 or
greater 0.186 – 6.35 MHz If the frequency of the external clock
is greater than 3 MHz, the CPU
clock divider must be set to 2 or
greater . In this case, the CPU clock
divider ensures that the fifty percent
duty cycle requirement is met.
– High Period with CPU Clock divide by 1 160 –5300 ns
– Low Period with CPU Clock divide by 1 160 ––ns
– Power Up IMO to Switch 150 – – μs
Table 37. AC Programming Specifications
Symbol Description Min Typ Max Units Notes
TRSCLK Rise Time of SCLK 1 – 20 ns
TFSCLK Fall Time of SCLK 1 – 20 ns
TSSCLK Data Set up Time to Falling Edge of SCLK 40 ––ns
THSCLK Data Hold Time from Falling Edge of SCLK 40 ––ns
FSCLK Frequency of SCLK 0–8MHz
TERASEB Flash Erase Time (Bl ock) –15 –ms
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 32 of 43
AC I2C Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T A ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85°C, respectively . Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
TWRITE Flash Block Write Time –30 –ms
TDSCLK Data Out Delay from Falling Edge of SCLK – – 45 ns 3.6 < Vdd
TDSCLK3 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6
TDSCLK2 Data Out Delay from Falling Edge of SCLK – – 70 ns 2.4 ≤ Vdd ≤ 3.0
Table 37. AC Programming Specifications (continued)
Symbol Description Min Typ Max Units Notes
Table 38. AC Characteristics of the I2C SDA and SCL Pins for Vdd ≥ 3.0V
Symbol Description Standard Mode Fast Mode Units
Min Max Min Max
FSCLI2C SCL Clock Frequency 0 100 0 400 kHz
THDSTAI2C Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
4.0 –0.6–μs
TLOWI2C LOW Period of the SCL Clock 4.7 –1.3–μs
THIGHI2C HIGH Period of the SCL Clock 4.0 –0.6–μs
TSUSTAI2C Set-up Time fo r a Repeated START
Condition 4.7 –0.6–μs
THDDATI2C Data Hold Time 0 –0–μs
TSUDATI2C Data Set-up Time 250 –100
a
a. A Fast-Mode I2C-bus device may be used in a S tandard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the
SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus
specification) before the SCL line is released.
–ns
TSUSTOI2C Set-up Time for STOP Condition 4.0 –0.6–μs
TBUFI2C Bus Free Time Between a STOP and ST ART
Condition 4.7 –1.3–μs
TSPI2C Pulse Width of spikes are suppressed by the
input filter. –– 0 50 ns
Table 39. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported)
Symbol Description Standard Mode Fast Mode Units
Min Max Min Max
FSCLI2C SCL Clock Frequency 0 100 – – kHz
THDSTAI2C Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
4.0 – – – μs
TLOWI2C LOW Period of the SCL Clock 4.7 – – – μs
THIGHI2C HIGH Period of the SCL Clock 4.0 – – – μs
TSUSTAI2C Set up Time for a Repeated START
Condition 4.7 – – – μs
THDDATI2C Data Hold Time 0 – – – μs
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 33 of 43
Figure 19. Definition for Timing for Fast/Standard Mode on the I2C Bus
TSUDATI2C Data Set-up Time 250 – – –ns
TSUSTOI2C Set up Time for STOP Condition 4.0 – – – μs
TBUFI2C Bus Free Time Between a STOP and ST ART
Condition 4.7 –––μs
TSPI2C Pulse Width of spikes are suppressed by the
input filter. ––––ns
Table 39. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) (continued)
Symbol Description Standard Mode Fast Mode Units
Min Max Min Max
SDA
SCL
SSr SP
TBUFI2C
TSPI2C
THDSTAI2C
TSUSTOI2C
TSUSTAI2C
TLOWI2C
THIGHI2C
THDDATI2C
THDSTAI2C
TSUDATI2C
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 34 of 43
Packaging Information
This section shows the packaging specifications for the CY8C21x34 PSoC device with the thermal impe dances for each package.
Important Note Emulation tools may re quire a larger are a on the target PCB th an th e chip’s footprint. For a de tailed descripti on of
the emulation tools’ dimensions, refer to the document titled PSoC Emu lator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 20. 16-Pin (150-Mil) SOIC
Figure 21. 20-Pin (210-MIL) SSOP
PIN 1 ID
0°~8°
18
916
SEATING PLANE
0.230[5.842]
0.244[6.197]
0.157[3.987]
0.150[3.810]
0.386[9.804]
0.393[9.982]
0.050[1.270]
BSC
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
DIMENSIONS IN INCHES[MM] MIN.
MAX.
0.016[0.406]
0.010[0.254] X 45°
0.004[0.102]
REFERENCE JEDEC MS-012
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
PACKAGE WEIGHT 0.15gms
51-85068 *B
51-85077 *C
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 36 of 43
Figure 24. 32-Pin (5x5 mm 0.60 MAX) QFN
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Figure 25. 32-Pin Sawn QFN Package
E-PAD X, Y for this product is 3.53 mm, 3.53 mm (+/-0.11 mm)
001-06392 *A
2. BASED ON REF JEDEC # MO-248
NOTES:
1. HATCH AREA IS SOLDERABLE EXPOSED PAD
BOTTOM VIEW
N
2
1
SEATING PLANE
TOP VIEW
2X
2X
0.20 DIA TYP.
N
2
1
SIDE VIEW
4.90
5.10
4.90
5.10
(0.93 MAX)
0.20 REF
(0.05 MAX)
PIN #1 I.D.
R0.20
0.23±0.05
3.50
0.50
PIN #1 CORNER
3.50
-0.20
3.50
3.50
SOLDERABLE
EXPOSED
PAD
0.45
001-30999 **
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 37 of 43
Figure 26. 32-Pin Thin Sawn QFN Package
Figure 27. 56-Pin (300-Mil) SSOP
4. DIMENSIONS ARE IN MILLIMETERS [MIN/MAX]
2. BASED ON R EF JEDEC # MO-248
NOTES:
PART NO. DESCRIPTION
6. PACKAGE CODE
LR32D STANDARD
LQ32D PB-FREE
1. HAT CH AREA IS SO LDERABLE EXPOSED PAD
BOTTOM VIEW
N
2
1
SEATING PLANE
TOP VIEW
2X
2X
0.20 DIA TYP.
N
2
1
SIDE VIEW
4.90
5.10
4.90
5.10
(0.05 MAX)
R0.30
3.55
0.50
PIN #1 CORNER
5. MAXIMUM ALLOWABLE BURRS IS 0.076mm
-0.20
IN ALL DIRECTIONS.
3. PACKAGE WEIGHT: 0.0388g
SOLDERABLE
EXPOSED
PAD
R
0.45
0.23 +/-0.05
3.5
3.5
3.55
001-42168 *A
51-85062 *C
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 38 of 43
Thermal Impedances
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 40. Thermal Impedances per Package
Package Typical θJA * Typical θJC
16 SOIC 123 oC/W 55 oC/W
20 SSOP 117 oC/W 41 oC/W
28 SSOP 96 oC/W 39 oC/W
32 QFN** 5x5 mm 0.60 MAX 27 oC/W 15 oC/W
32 QFN** 5x5 mm 0.93 MAX 22 oC/W 12 oC/W
* TJ = TA + Power x θJA
** To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.
Table 41. Solder Reflow Peak Temperature
Package Minimum Peak Temperature* Maximum Peak Temperature
16 SOIC 240oC260oC
20 SSOP 240oC260oC
28 SSOP 240oC260oC
32 QFN 240oC260oC
*Higher temperatures may be required based on the solder melting po int. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with
Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 39 of 43
Development Tool Selection
This section presents the development tools available for all
current PSoC device families including the CY8C21x34 family.
Software
PSoC Designer
™
At the core of the PSoC development software suite is PSoC
Designer. Used by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for half a decade.
PSoC Designer is available free of charge at
http://www.cypress.com under DESIGN RESOURCES >>
Software and Drivers.
PSoC Express
™
As the newest addition to the PSoC development software suite,
PSoC Express is the first visual embedded system design tool
that allows a user to create an entire PSoC project and generate
a schematic, BOM, and data sheet without writing a sin gle line
of code. Users work directly with application objects such as
LEDs, switches, sensors, and fans. PSoC Express is available
free of charge at http://www.cypress.com/psocexpress.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or operates
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free ofcharge at http://www.cypress.com/psocpro-
grammer.
CY3202-C iMAGEcraft C Compiler
CY3202 is the optio nal upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It can be purchased from the
Cypress Online Store. At http://www.cypress.com, click the
Online Store shoppin g cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a
current list of available items.
Development Kits
All development kits can be purchased from the Cypress Online
Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyp ing and deve lopment with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the content of specific memory locations. Advance
emulation features also supported through PSoC Designer. The
kit includes:
■PSoC Designer Software CD
■ICE-Cube In-Circuit Emulator
■ICE Flex-Pod for CY8C29x66 Family
■Cat-5 Adapter
■Mini-Eval Programming Board
■110 ~ 240V Power Supp ly, Euro-Plug Adapter
■iMAGEcraft C Compiler (Registration Required)
■ISSP Cable
■USB 2.0 Cable and Blue Cat-5 Cable
■2 CY8C29466-24PXI 28-PDIP Chip Samples
CY3210-ExpressDK PSoC Express Development Kit
The CY3210-ExpressDK is for advanced prototyping and
development with PSoC Express (may be used with ICE-Cube
In-Circuit Emulator). It provides access to I2C buses, voltage
reference, switches, upgradeable modules and more. The kit
includes:
■PSoC Express Software CD
■Express Development Board
■4 Fan Modules
■2 Proto Modules
■MiniProg In-System Serial Programmer
■MiniEval PCB Evaluation Board
■Jumper Wire Kit
■USB 2.0 Cable
■Serial Cable (DB9)
■110 ~ 240V Power Supp ly, Euro-Plug Adapter
■2 CY8C24423A-24PXI 28-PDIP Chip Sa mples
■2 CY8C27443-24PXI 28-PDIP Chip Samples
■2 CY8C29466-24PXI 28-PDIP Chip Samples
Evaluation Tools
All evaluation tools can be pu rchased from the Cypress Online
Store.
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices through the MiniProg1 programming unit. The MiniProg
is a small, compact prototyping programmer that connects to the
PC through a provided USB 2.0 cable. The kit includes:
■MiniProg Programming Unit
■MiniEval Socket Programming and Evaluation Board
■28-Pin CY8C29466-24PXI PDIP PSoC Device Samp le
■28-Pin CY8C27443-24PXI PDIP PSoC Device Samp le
■PSoC Designer Software CD
■Getting St arted Guide
■USB 2.0 Cable
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 40 of 43
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
■Evaluation Board with LCD Module
■MiniProg Programming Unit
■28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■PSoC Designer Software CD
■Getting Started Guide
■USB 2.0 Cable
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a
development board for the CY8C24794-24LFXI PSoC device.
Special features of the board include both USB and capacitive
sensing development and debugging support. This evaluation
board also includes an LCD module, potentiometer, LEDs, an
enunciator and plenty of bread boarding space to meet all of your
evaluation needs. The kit includes:
■PSoCEvalUSB Board
■LCD Module
■MIniProg Programming Unit
■Mini USB Cable
■PSoC Designer and Example Projects CD
■Getting Started Guide
■Wire Pack
Device Programmers
All device programmers can be purchased from the Cypress
Online Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit include s:
■Modular Programmer Base
■3 Programming Module Cards
■MiniProg Programming Unit
■PSoC Designer Software CD
■Getting St arted Guide
■USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note CY3207ISSP needs special software and is not compatible
with PSoC Programmer. The kit includes:
■CY3207 Programmer Unit
■PSoC ISSP Software CD
■110 ~ 240V Power Supp ly, Euro-Plug Adapter
■USB 2.0 Cable
Accessories (Emulation and Programming)
3rd-Party Tools
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during devel-
opment and producti on. Spe ci fic details for each of these tools
can be found at http://www.cypress.com under DESIGN
RESOURCES >> Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note AN2323 “Debugging - Build a PSoC
Emulator into Your Board”.
Table 42. Emulation and Programming Accessories
Part # Pin Package Flex-Pod Kit a
a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
Foot Kitb
b. Foot kit includes surface mount feet that can be soldered to the target PCB.
Adapter
CY8C21234-24S 16 SOIC CY3250-21X34 CY3250-16SOIC-FK Programming adapter converts
non-DIP package to DIP
footprint. Specific details and
ordering information for each of
the adapters can be found at
http://www.emulation.com.
CY8C21334-24PVXI 20 SSOP CY3250-21X34 CY3250 -20SSOP-FK
CY8C21434-24LFXI 32 QFN CY3250-21X34QFN CY3250-32QFN-FK
CY8C21534-24PVXI 28 SSOP CY3250-21X34 CY3250 -28SSOP-FK
CY8C21634-24LFXI 32 QFN CY3250-21X34QFN CY3250-32QFN-FK
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 41 of 43
Ordering Information
Package
Ordering
Code
Flash
(Bytes)
SRAM
(Bytes)
Switch Mode
Pump
Temperature
Range
Digital
Blocks
Analog
Blocks
Digital IO
Pins
Analog
Inputsa
Analog
Outputs
XRES Pin
16 Pin (150-Mil) SOIC CY8C21234-24SXI 8K 512 Yes -40°C to +85°C 4 4 12 12a0No
16 Pin (150-Mil) SOIC
(Tape and Reel) CY8C21234-24SXIT 8K 512 Yes -40°C to +85°C 4 4 12 12a0No
20 Pin (210-Mil) SSOP CY8C21334-24PVXI 8K 512 No -40°C to +85°C 4 4 16 16a0Yes
20 Pin (210-Mil) SSOP
(Tape and Reel) CY8C21334-24PVXIT 8K 512 No -40°C to +85°C 4 4 16 16a0Yes
28 Pin (210-Mil) SSOP CY8C21534-24PVXI 8K 512 No -40°C to +85°C 4 4 24 24a0Yes
28 Pin (210-Mil) SSOP
(Tape and Reel) CY8C21534-24PVXIT 8K 512 No -40°C to +85°C 4 4 24 24a0Yes
32 Pin (5x5 mm 0.93 MAX)
QFN bCY8C21434-24LFXI 8K 512 No -40°C to +85°C 4 4 28 28a0Yes
32 Pin (5x5 mm 0.93 MAX)
QFN b (Tape and Reel) CY8C21434-24LFXIT 8K 512 No -40°C to +85°C 4 4 28 28a0Yes
32 Pin (5x5 mm 0.60 MAX)
QFN bCY8C21434-24LKXI 8K 512 No -40°C to +85°C 4 4 28 28a0Yes
32 Pin (5x5 mm 0.60 MAX)
QFN b (Tape and Reel) CY8C21434-24LKXIT 8K 512 No -40°C to +85°C 4 4 28 28a0Yes
32 Pin (5x5 mm 0.93 MAX)
QFN bCY8C21634-24LFXI 8K 512 Yes -40°C to +85°C 4 4 26 26a0Yes
32 Pin (5x5 mm 0.93 MAX)
QFN b (Tape and Reel) CY8C21634-24LFXIT 8K 512 Yes -40°C to +85°C 4 4 26 26a0Yes
32 Pin (5x5 mm 0.93 MAX)
SAWN QFN CY8C21434-24LTXI 8K 512 No -40°C to +85°C 4 4 28 28a0Yes
32 Pin (5x5 mm 0.93 MAX)
SAWN QFN b (T ape and Reel) CY8C21434-24LTXIT 8K 512 No -40°C to +85°C 4 4 28 28a0Yes
32 Pin (5x5 mm 0.60 MAX)
THIN SAWN QFN CY8C21434-24LQXI 8K 512 No -40°C to +85°C 4 4 28 28a0Yes
32 Pin (5x5 mm 0.60 MAX)
THIN SAWN QFN
(Tape and Reel)
CY8C21434-24LQXIT 8K 512 No -40°C to +85°C 4 4 28 28a0Yes
32 Pin (5x5 mm 0.93 MAX)
SAWN QFN bCY8C21634-24LTXI 8K 512 Yes -40°C to +85°C 4 4 26 26a0Yes
32 Pin (5x5 mm 0.93 MAX)
SAWN QFN b (T ape and Reel) CY8C21634-24LTXIT 8K 512 Yes -40°C to +85°C 4 4 26 26a0Yes
56 Pin OCD SSOP CY8C21001-24PVXI 8K 512 Yes -40°C to +85°C 4 4 26 26a0Yes
a. All Digital IO Pins also connect to the common analog mux.
b. Refer to the section 32-Pin Part Pinout on page 11 for pin differences.
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CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-1202 5 Rev. *M Page 42 of 43
Ordering Code Definitions
CY 8 C 21 xxx-24xx Package Type: Thermal Rating:
PX = PDIP Pb-Free C = Commercial
SX = SOIC Pb-Free I = Industrial
PVX = SSOP Pb-Free E = Extended
LFX/LKX = QFN Pb-Free
AX = TQFP Pb-Free
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
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Document Number: 38-12025 Rev. *M Revised April 18, 2008 Page 43 of 43
All products and company names mentioned in this document may be the tr ademarks of their respective holders.
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
© Cypress Semicondu ctor Corpor ation, 2004-2008. The informatio n contai ned herei n is subject to chan ge without no tice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypres s pro d ucts are n ot war ran ted no r int end ed to be us ed for
medical, life supp or t, l if e savin g, cr it ical control or safety applicatio ns, unl ess pu r suan t to a n exp re ss wri tte n ag reement with Cypress. Furthermore, Cyp ress doe s not auth ori ze i t s pr o ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product s in life-support syst ems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwid e patent prot ection (Uni ted States and foreign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product t o be used only in conjuncti on with a Cypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written perm ission of Cypres s.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY A ND FITNESS FOR A PARTICULAR PURPOSE. C ypress reserves the right to make changes without further notice to the materials des cribed herein. Cypress does not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and i n doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
Document Title: CY8C21234/CY8C21334/CY8C21434/CY8C21534/CY8C21634 PSoC® Mixed-Sign al Array
Document Number: 38-12025
Revision ECN Orig. of
Change Description of Change
** 227340 HMT New silicon and document (Revision **).
*A 235992 SFV Updated Overview and Electrical S pec. chapters, along with revisions to the 24-pin pinout part.
Revised the register mapping tables. Added a SSOP 28-pin part.
*B 248572 SFV Changed title to include all part #s. Changed 28-pin SSOP from CY8C21434 to CY8C21534.
Changed pin 9 on the 28-pin SSOP from SMP pin to Vss pin. Added SMP block to architecture
diagram. Update Electrical Specifications. Added another 32-pin MLF part: CY8C21634.
*C 277832 HMT Verify data sheet standards from SFV memo. Add Analog Input Mux to applicable pin outs.
Update PSoC Characteristics table. Update diagrams and specs. Final.
*D 285293 HMT Update 2.7V DC GPIO spec. Add Reflow Peak Temp. table.
*E 301739 HMT DC Chip-Level Sp ecification changes. Update links to new CY.com Portal.
*F 329104 HMT Re-add pinout ISSP notation. Fix TMP register names. Clarify ADC feature. Update Electrical
S pecifications. Update Reflow Peak Temp. table. Add 32 MLF E-PAD dimensions. Add ThetaJC
to Thermal Impedance table. Fix 20-pin package order number. Add CY logo. Update CY
copyright.
*G 352736 HMT Add new color and logo. Add URL to preferred dimensions for mounting MLF packages. Update
Transmitter and Receiver AC Digital Block Electrical S p ecifications.
*H 390152 HMT Clarify MLF thermal pad connection info. Replace 16 -pin 300-MIL SOIC with correct 150-MIL.
*I 413404 HMT Update 32-pin QFN E-Pa d dimensions and rev. *A. Update CY branding and QFN convention.
*J 430185 HMT Add new 32-pin 5x5 mm 0.60 thickness QFN package and diagram, CY8C21434-24LKXI.
Update thermal resistance data. Add 56-pin SSOP on-chip debug non-production part,
CY8C21001-24PVXI. Update typical and recomm ended Storage Temperature per industrial
specs. Update copyright and tradema rks.
*K 677717 HMT Add CapSense SNR requirement reference. Add new Dev. Tool section. Add CY8C20x34 to
PSoC Device Characteristics table. Add Low Power Comparator (LPC) AC/DC electrical spec.
tables. Update rev. of 32-Lead (5x5 mm 0.60 MAX) QFN package diagram.
*L 2147847 UVS/PYRS Added 32-Pin QFN Sawn pin diagram, package diagram, and ordering information.
*M 2273246 UVS/AESA Add ed 32 pin thin sawn package diagram.
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