IR3505
Page 1 of 19 Mar 04th, 2008
DATA SHEET
XPHASE3TM PHASE IC
DESCRIPTION
The IR3505 Phase IC combined with an IR XPhase3TM Control IC provides a full featured and flexible way to
implement power solutions for the latest high performance CPUs and ASICs. The “Control” IC provides
overall system control and interfaces with any number of “Phase” ICs which each drive and monitor a single
phase of a multiphase converter. The XPhase3TM architecture results in a power supply that is smaller, less
expensive, and easier to design while providing higher efficiency than conventional approaches.
FEATURES
• 7V/2A gate drivers (4A GATEL sink current)
• Support converter output voltage up to 5.1 V (Limited to VCCL-1.4V)
• Support loss-less inductor current sensing
• Feed-forward voltage mode control
• Integrated boot-strap synchronous PFET
• Only four IC related external components per phase
• 3 wire analog bus connects Control and Phase ICs (VDAC, Error Amp, ISHARE)
• 3 wire digital bus for accurate daisy-chain phase timing control without external components
• Debugging function isolates phase IC from the converter
• Self-calibration of PWM ramp, current sense amplifier, and current share amplifier
• Single-wire bidirectional average current sharing
• Small thermally enhanced 16L 3 x 3mm MLPQ package
• RoHS compliant
APPLICATION CIRCUIT
CCS
CSIN- 15
VCC 13
EAIN 16
ISHARE
1SW 12
GATEH 11
BOOST 10
CSIN+ 14
DACIN
2
CLKIN
6
PHSIN
4
PHSOUT
5
GATEL
8
PGND
7
VCCL 9
LGND
3
IR3505
PHASE
IC
CVCCL
CBST
RCS
CIN
L
VOUT+
VOUT-
VCCL
12V
COUT
6 Wire
Bus to
Control
IC
IR3505
Page 2 of 19 Mar 04th, 2008
ORDERING INFORMATION
Part Number Package Order Quantity
IR3505MTRPBF 16 Lead MLPQ
(3 x 3 mm body)
3000 per reel
* IR3505MPBF 16 Lead MLPQ
(3 x 3 mm body)
100 piece strips
* Samples only
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specifications are not implied.
Operating Junction Temperature…………….. 0oC to 150oC
Storage Temperature Range………………….-65oC to 150oC
MSL Rating………………………………………2
Reflow Temperature…………………………….260oC
Note:
1. Maximum GATEH – SW = 8V
2. Maximum BOOST – GATEH = 8V
PIN # PIN NAME VMAX VMIN ISOURCE ISINK
1 ISHARE 8V -0.3V 1mA 1mA
2 DACIN 3.3V -0.3V 1mA 1mA
3 LGND n/a n/a n/a n/a
4 PHSIN 8V -0.3V 1mA 1mA
5 PHSOUT 8V -0.3V 2mA 2mA
6 CLKIN 8V -0.3V 1mA 1mA
7 PGND 0.3V -0.3V 5A for 100ns,
200mA DC
n/a
8 GATEL 8V -0.3V DC, -5V for
100ns
5A for 100ns,
200mA DC
5A for 100ns,
200mA DC
9 VCCL 8V -0.3V n/a 5A for 100ns,
200mA DC
10 BOOST 34V -0.3V 1A for 100ns,
100mA DC
3A for 100ns,
100mA DC
11 GATEH 34V -0.3V DC, -5V for
100ns
3A for 100ns,
100mA DC
3A for 100ns,
100mA DC
12 SW 34V -0.3V DC, -5V for
100ns
3A for 100ns,
100mA DC
n/a
13 VCC 18V -0.3V n/a 10mA
14 CSIN+ 8V -0.3V 1mA 1mA
15 CSIN- 8V -0.3V 1mA 1mA
16 EAIN 8V -0.3V 1mA 1mA
IR3505
Page 3 of 19 Mar 04th, 2008
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
8.0V ≤ VCC ≤ 16V, 4.75V ≤ VCCL ≤ 7.5V, 0.5V ≤ V(DACIN) ≤ 1.6V, 250kHz ≤ CLKIN ≤ 9MHz, 250kHz ≤ PHSIN
≤1.5MHz, 0 oC ≤ TJ ≤ 125 oC
ELECTRICAL CHARACTERISTICS
The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions.
Typical values represent the median values, which are related to 25°C. CGATEH = 3.3nF, CGATEL = 6.8nF (unless
otherwise specified).
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Gate Drivers
GATEH Source Resistance BOOST – SW = 7V. Note 1 1.0 2.5 Ω
GATEH Sink Resistance BOOST – SW = 7V. Note 1 1.0 2.5 Ω
GATEL Source Resistance VCCL – PGND = 7V. Note 1 1.0 2.5 Ω
GATEL Sink Resistance VCCL – PGND = 7V. Note 1 0.4 1.0 Ω
GATEH Source Current
BOOST=7V, GATEH=2.5V, SW=0V. 2.0 A
GATEH Sink Current
BOOST=7V, GATEH=2.5V, SW=0V. 2.0 A
GATEL Source Current
VCCL=7V, GATEL=2.5V, PGND=0V. 2.0 A
GATEL Sink Current
VCCL=7V, GATEL=2.5V, PGND=0V. 4.0 A
GATEH Rise Time BOOST – SW = 7V, measure 1V to 4V
transition time
5 10 ns
GATEH Fall Time BOOST - SW = 7V, measure 4V to 1V
transition time
5 10 ns
GATEL Rise Time VCCL – PGND = 7V, Measure 1V to 4V
transition time
10 20 ns
GATEL Fall Time VCCL – PGND = 7V, Measure 4V to 1V
transition time
5 10 ns
GATEL low to GATEH high
delay
BOOST = VCCL = 7V, SW = PGND = 0V,
measure time from GATEL falling to 1V to
GATEH rising to 1V
10 20 40 ns
GATEH low to GATEL high
delay
BOOST = VCCL = 7V, SW = PGND = 0V,
measure time from GATEH falling to 1V to
GATEL rising to 1V
10 20 40 ns
Disable Pull-Down
Resistance
Note 1 30 80 130 kΩ
Clock
CLKIN Threshold Compare to V(VCCL) 40 45 57 %
CLKIN Bias Current CLKIN = V(VCCL) -0.5 0.0 0.5 µA
CLKIN Phase Delay Measure time from CLKIN<1V to
GATEH>1V
40 75 125 ns
PHSIN Threshold Compare to V(VCCL) 35 50 55 %
PHSOUT Propagation
Delay
Measure time from CLKIN > (VCCL * 50% )
to PHSOUT > (VCCL *50%). 10pF @125 oC
4 15 35 ns
PHSIN Pull-Down
Resistance
30 100 170 kΩ
PHSOUT High Voltage I(PHSOUT) = -10mA, measure VCCL –
PHSOUT
1 0.6 V
PHSOUT Low Voltage I(PHSOUT) = 10mA 0.4 1 V
IR3505
Page 4 of 19 Mar 04th, 2008
PARAMETER TEST CONDITION MIN TYP MAX UNIT
PWM Comparator
PWM Ramp Slope Vin=12V
42
52.5
57
mV/
%DC
Input Offset Voltage Note 1 -5 0 5 mV
EAIN Bias Current 0 ≤ EAIN ≤ 3V -5 -0.3 5 µA
Minimum Pulse Width Note 1 65 75 ns
Minimum GATEH Turn-off
Time 20 80 160 nS
Current Sense Amplifier
CSIN+/- Bias Current -200 0 200 nA
CSIN+/- Bias Current
Mismatch
Note 1 -50 0 50 nA
Input Offset Voltage CSIN+ = CSIN- = DACIN. Measure
input referred offset from DACIN
-1 1 mV
Gain 0.5V ≤ V(DACIN) < 1.6V 30 32.5 35 V/V
Unity Gain Bandwidth C(ISHARE)=10pF. Measure at ISHARE.
Note 1
4.8 6.8 8.8 MHz
Slew Rate 6 V/µs
Differential Input Range 0.8V ≤ V(DACIN) ≤ 1.6V, Note 1 -10 50 mV
Differential Input Range 0.5V ≤ V(DACIN) < 0.8V, Note 1 -5 50 mV
Common Mode Input Range Note 1 0 Note2 V
Rout at TJ = 25 oC Note 1 2.3 3.0 3.7 kΩ
Rout at TJ = 125 oC 3.6 4.7 5.4 kΩ
ISHARE Source Current 0.500 1.6 2.9 mA
ISHARE Sink Current 0.500 1.4 2.9 mA
Share Adjust Amplifier
Input Offset Voltage Note 1 -3 0 3 mV
Differential Input Range Note 1 -1 1 V
Gain CSIN+ = CSIN- = DACIN. Note 1 4 5.0 6 V/V
Unity Gain Bandwidth Note 1 4 8.5 17 kHz
PWM Ramp Floor Voltage ISHARE unconnected
Measured Relative to DACIN
-116 0 +116 mV
Maximum PWM Ramp Floor
Voltage
ISHARE = DACIN - 200mV
Measured relative to FLOOR with
ISHARE unconnected
120
180
240
mV
Minimum PWM Ramp Floor
Voltage
ISHARE = DACIN + 200mV
Measured relative to FLOOR with
ISHARE unconnected
-220
-160
-100
mV
Body Brake Comparator
Threshold Voltage with EAIN
falling.
Measured relative to PWM Ramp Floor
Voltage -300 -200 -110 mV
Threshold Voltage with EAIN
rising.
Measured relative to PWM Ramp Floor
Voltage -200 -100 -10 mV
Hysteresis 70 105 130 mV
Propagation Delay VCCL = 5V. Measure time from EAIN <
V(DACIN) (200mV overdrive) to GATEL
transition to < 4V.
40 65 90 ns
IR3505
Page 5 of 19 Sept 26th, 2007
Note 1: Guaranteed by design, but not tested in production
Note 2: VCCL-0.5V or VCC – 2.5V, whichever is lower
PARAMETER TEST CONDITION MIN TYP MAX UNIT
OVP Comparator
OVP Threshold Step V(ISHARE) up until GATEL drives
high. Compare to V(VCCL)
-1.0 -0.8 -0.4 V
Propagation Delay V(VCCL)=5V, Step V(ISHARE) up from
V(DACIN) to V(VCCL). Measure time to
V(GATEL)>4V.
15 40 70 nS
Synchronous Rectification Disable Comparator
Threshold Voltage The ratio of V(CSIN-) / V(DACIN), below
which V(GATEL) is always low.
66 75 86 %
Negative Current Comparator
Input Offset Voltage Note 1 -16 0 16 mV
Propagation Delay Time Apply step voltage to V(CSIN+) –
V(CSIN-). Measure time to V(GATEL)<
1V.
100 200 400 nS
Bootstrap Diode
Forward Voltage I(BOOST) = 30mA, VCCL=6.5V 180 260 480 mV
Debug Comparator
Threshold Voltage Compare to V(VCCL) -250 -150 -50 mV
General
VCC Supply Current 1.1 3.0 6.1 mA
VCCL Supply Current 3.1 6.7 12.1 mA
BOOST Supply Current 4.75V ≤ V(BOOST)-V(SW) ≤ 8V 1.2 3.5 5.8 mA
DACIN Bias Current
-1.5
-0.75 1 µA
SW Bias Current -0.5 -1.8 -2.9 mA
IR3505
Page 6 of 19 Sept 26th, 2007
PIN DESCRIPTION
PIN# PIN SYMBOL PIN DESCRIPTION
1 ISHARE Output of the Current Sense Amplifier is connected to this pin through a 3kΩ
resistor. Voltage on this pin is equal to V(DACIN) + 32.5 [V(CSIN+) – V(CSIN-)].
Connecting all ISHARE pins together creates a share bus which provides an
indication of the average current being supplied by all the phases. The signal is used
by the Control IC for voltage positioning and over-current protection. OVP mode is
initiated if the voltage on this pin rises above V(VCCL)- 0.8V.
2 DACIN Reference voltage input from the Control IC. The Current Sense signal and PWM
ramp is referenced to the voltage on this pin.
3 LGND Ground for internal IC circuits. IC substrate is connected to this pin.
4 PHSIN Phase clock input.
5 PHSOUT Phase clock output.
6 CLKIN Clock input.
7 PGND Return for low side driver and reference for GATEH non-overlap comparator.
8 GATEL Low-side driver output and input to GATEH non-overlap comparator.
9 VCCL Supply for low-side driver. Internal bootstrap synchronous PFET is connected from
this pin to the BOOST pin.
10 BOOST Supply for high-side driver. Internal bootstrap synchronous PFET is connected
between this pin and the VCCL pin.
11 GATEH High-side driver output and input to GATEL non-overlap comparator.
12 SW Return for high-side driver and reference for GATEL non-overlap comparator.
13 VCC Supply for internal IC circuits.
14 CSIN+ Non-Inverting input to the current sense amplifier, and input to debug comparator.
15 CSIN- Inverting input to the current sense amplifier, and input to synchronous rectification
disable comparator.
16 EAIN PWM comparator input from the error amplifier output of Control IC. Body Braking
mode is initiated if the voltage on this pin is less than V(DACIN).
IR3505
Page 7 of 19 Sept 26th, 2007
SYSTEM THEORY OF OPERATION
PWM Control Method
The PWM block diagram of the XPhaseTM architecture is shown in Figure 1. Feed-forward voltage mode control with
trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used
for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The PWM
ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The
input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage
drop related to changes in load current.
PWM
COMPARATOR
RDRP1
VSETPT
CLKIN
RCSCCS
PHSIN
DACIN
VCC
GATEH
ISHARE
CSIN+
GATEL
EAIN
CSIN-
CCOMP1
VCCH
CBST
VCCL
PGND
SW
VID6
PHSOUT
VID6
CLK
D
Q
PHSIN
CCOMP
RFB
+
-
+
-
+
-
+
-
+
-
CLKIN
RCS
CDRP
+
-
CCS
+
-
RDRP
+
-
3K
GND
VOUT
VDAC
VO
DACIN
VCC
PHSIN
VOSNS-
VOSNS+
LGND
ISHARE
IIN
VDRP
EAIN
GATEH
CSIN-
CSIN+
GATEL
EAOUT
CLKOUT
VIN
FB
IROSC
VID6
REMOTE SENSE
AMPLIFIER
VCCH
RCOMP
CBST
CLK
2
R
3
D
1Q4
Q5
VCCL
GATE DRIVE
VOLTAGE
PHSOUT
PWM
COMPARATOR
VID6
VID6
VID6
CLK
D
Q
+
-
+
-
+
-
+
-
+
-
3K
VID6
CLK
2
R
3
D
1Q4
Q5
VID6
-
+
VID6
+
+
RAMP
DISCHARGE
CLAMP
ENABLE
BODY
BRAKING
COMPARATOR
RVSETPT
PWM LATCH
CURRENT
SENSE
AMPLIFIER
SHARE ADJUST
ERROR AMPLIFIER
RESET
DOMINANT
1 2
PHASE IC
PGND
-
+
SW
VID6
+
+
-
+
LDO AMPLIFIER
RAMP
DISCHARGE
CLAMP
ENABLE
BODY
BRAKING
COMPARATOR
VDRP
AMP
VDAC
IVSETPT
CLOCK GENERATOR
CURRENT
SENSE
AMPLIFIER
RESET
DOMINANT
PWM LATCH
SHARE ADJUST
ERROR AMPLIFIER
ERROR
AMPLIFIER
RFB1
COUT
CONTROL IC
CFB
1 2
PHSOUT
PHASE IC
Figure 1 PWM Block Diagram
Frequency and Phase Timing Control
The oscillator is located in the Control IC and the system clock frequency is programmable from 250kHz to 9MHZ
by an external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs.
The phase timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output
(PHSOUT) is connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is
connected to PHSIN of the second phase IC, etc. and PHSOUT of the last phase IC is connected back to PHSIN of
the control IC. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and
detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop.
Figure 2 shows the phase timing for a four phase converter. The switching frequency is set by the resistor ROSC as
shown in Figure 9. The clock frequency equals the number of phase times the switching frequency.
IR3505
Page 8 of 19 Sept 26th, 2007
Phase IC1
PWM Latch SET
Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT
(Phase IC1 PHSIN)
Phase IC 1 PHSOUT
(Phase IC2 PHSIN)
Phase IC 2 PHSOUT
(Phase IC3 PHSIN)
Phase IC 3 PHSOUT
(Phase IC4 PHSIN)
Phase IC4 PHSOUT
(Control IC PHSIN)
Figure 2 Four Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is
set; the PWM ramp voltage begins to increase; the low side driver is turned off, and the high side driver is turned on
after the non-overlap time. When the PWM ramp voltage exceeds the error amplifier’s output voltage the PWM latch
is reset. This turns off the high side driver, turns on the low side driver after the non-overlap time, and activates the
ramp discharge clamp. The clamp drives the PWM ramp voltage to the level set by the share adjust amplifier until
the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode
input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required.
It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
An additional advantage of this PWM modulator is that differences in ground or input voltage at the phases have no
effect on operation since the PWM ramps are referenced to VDAC.
Figure 3 depicts PWM operating waveforms under various conditions.
IR3505
Page 9 of 19 Sept 26th, 2007
PHASE IC
CLOCK
PULSE
EAIN
VDAC
PWMRMP
GATEH
GATEL
STEADY-STATE
OPERATION
DUTY CYCLE DECREASE
DUE TO VIN INCREASE
(FEED-FORWARD)
DUTY CYCLE INCREASE
DUE TO LOAD
INCREASE
STEADY-STATE
OPERATION
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OR FAULT
(VCCLUV, OCP, VID=11111X)
Figure 3 PWM Operating Waveforms
Body BrakingTM
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in
response to a load step decrease is;
O
MINMAX
SLEW V
IIL
T)(* −
=
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in
response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the
synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout +
VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient
decrease is now;
BODYDIODEO
MINMAX
SLEW VV
IIL
T
+
−
=)(*
Since the voltage drop in the body diode is often comparable to the output voltage, the inductor current slew rate
can be increased significantly. This patented technique is referred to as “body braking” and is accomplished through
the “body braking comparator” located in the phase IC. If the error amplifier’s output voltage drops below the output
voltage of the share adjust amplifier in the phase IC, this comparator turns off the low side gate driver.
Lossless Average Inductor Current Sensing
Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor
and measuring the voltage across the capacitor, as shown in Figure 4. The equation of the sensing network is,
CSCS
L
L
CSCS
LC CsR
sLR
si
CsR
svsv
+
+
=
+
=1
)(
1
1
)()(
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time
constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the
voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of
inductor DC current, but affects the AC component of the inductor current.
IR3505
Page 10 of 19 Sept 26th, 2007
Figure 4 Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being
delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage
can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the
inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no
information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from
peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the
frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance
of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay,
any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 5. Its gain is nominally
32.5 and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop feedback path.
The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before clipping.
The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and other phases
through an on-chip 3KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are tied together and
the voltage on the share bus represents the average current through all the inductors and is used by the control IC for
voltage positioning and current limit protection. The input offset of this amplifier is calibrated to +/- 1mV in order to
reduce the current sense error.
The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input
offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This
calibration algorithm creates ripple on ISHARE bus with a frequency of fsw/(32*28) in a multiphase architecture.
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each phase IC. The
output of the current sense amplifier is compared with the average current at the share bus. If current in a phase is
smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM
ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current, the
share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty cycle and
output current. The current share amplifier is internally compensated so that the crossover frequency of the current
share loop is much slower than that of the voltage loop and the two loops do not interact.
CO
L
R
L
R
CS
CCS
V
O
Current
Sense Amp
CSOUT
iL
v
L
vCS
c
IR3505
Page 11 of 19 Sept 26th, 2007
IR3505 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3505 is shown in Figure 5, and specific features are discussed in the following sections.
PWM_CLKPWM_CLK
100% DUTY LATCH
(CLKIN IF 1-PHASE)
RESET
DOMINANT
+
NEGATIVE
CURRENT
LATCH
S
RQ
PWMQ
PHSIN
VCCL
3K
CLK
R
D Q
Q
+
-
S
R
Q
+
-
+
-
+
-
+
-
CLK
D
Q
+
-
+
-
+
-
S
R
Q
+
-
+
-
VCC
LGND
ISHARE
EAIN
GATEL
PGND
BOOST
VCCL
CSIN-
SW
GATEH
CSIN+
CLKIN
DACIN
PHSOUT
PHSIN
CALIBRATION
RMPOUT PWM RESET
VCC
CALIBRATION
CSAOUT
CALIBRATION
DACIN
PHSIN
DACIN
DEBUG OFF
SHARE_ADJ
IROSC
IROSC
DACIN-SHARE_ADJ
VCCL
PWM LATCH
SHARE
ADJUST
AMPLIFIER
BODY BRAKING
COMPARATOR
PWM COMPARATOR
1V
X33
CURRENT SENSE
AMPLIFIER
-
SYNCHRONOUS RECTIFICATION
DISABLE COMPARATOR
+
GATEL NON-
OVERLAP
COMPARATOR
1V
PWM RAMP
GENERATOR
OVP
COMPARATOR
+
GATEL NON-
OVERLAP
LATCH
GATEH NON-
OVERLAP
LATCH
GATEH
DRIVER
GATEL
DRIVER
SET
DOMINANT
SET
DOMINANT
X
0.75
DEBUG
COMPARATOR
(LOW=OPEN)
RESET
DOMINANT
GATEH NON-
OVERLAP
COMPARATOR
NEGATIVE CURRENT
COMPARATOR
0.8V
100mV
0.2V
200mV
CLK
D
Q
PWMQ
PWM_CLKPWM_CLK
Figure 5 Block diagram
Tri-State Gate Drivers
The gate drivers can deliver up to 2A peak current (4A sink current for bottom driver). An adaptive non-overlap
circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shoot-through current while
minimizing body diode conduction. The non-overlap latch is added to eliminate the error triggering caused by the
switching noise. An enable signal is provided by the control IC to the phase IC without the addition of a dedicated
signal line. The error amplifier output of the control IC drives low in response to any fault condition such as VCCL
under voltage or output overload. The IR3505 Body BrakingTM comparator detects this and drives bottom gate
output low. This tri-state operation prevents negative inductor current and negative output voltage during power-
down.
A synchronous rectification disable comparator is used to detect converter CSIN- pin voltage, which represents
local converter output voltage. If the voltage is below 75% of VDAC and negative current is detected, GATEL drives
low, which disables synchronous rectification and eliminates negative current during power-up.
The gate drivers pull low if the supply voltages are below the normal operating range. An 80kΩ resistor is connected
across the GATEH/GATEL and PGND pins to prevent the GATEH/GATEL voltage from rising due to leakage or
other causes under these conditions.
IR3505
Page 12 of 19 Sept 26th, 2007
Over Voltage Protection (OVP)
The IR3505 includes over-voltage protection that turns on the low side MOSFET to protect the load in the event
of a shorted high-side MOSFET, converter out of regulation, or connection of the converter output to an
excessive output voltage. As shown in Figure 6, if ISHARE pin voltage is above V(VCCL) – 0.8V, which
represents over-voltage condition detected by control IC, the over-voltage latch is set. GATEL drives high and
GATEH drives low. The OVP circuit overrides the normal PWM operation and within approximately 150ns will
fully turn-on the low side MOSFET, which remains ON until ISHARE drops below V(VCCL) – 0.8V when over
voltage ends. The over voltage fault is latched in control IC and can only be reset by cycling the power to
control IC. The error amplifier output (EAIN) is pulled down by control IC and will remain low. The lower
MOSFETs alone can not clamp the output voltage however an SCR or N-MOSFET could be triggered with the
OVP output to prevent processor damage.
AFTER
OVP
OUTPUT
VOLTAGE
(VO)
OVP
THRESHOLD
ISHARE(IIN)
VCCL-800 mV
OVP CONDITIONNORMAL OPERATION
GATEH
GATEL
ERROR
AMPLIFIER
INPUT
(EAIN)
VDAC
FAULT LATCH
(CONTROL IC)
Figure 6 - Over-voltage protection waveforms
PWM Ramp
Every time the phase IC is powered up PWM ramp magnitude is calibrated to generate a 50 mV/% ramp for a
VCC=12V. For example, for a 15% duty ratio the ramp amplitude is 750mV for VCC=12V. Feed-forward
control is achieved because the PWM ramp varies with VCC voltage proportionally after calibration.
Debugging Mode
If CSIN+ pin is pulled up to VCCL voltage, IR3505 enters into debugging mode. Both drivers are pulled low
and ISHARE output is disconnected from the current share bus, which isolates this phase IC from other
phases. However, the phase timing from PHSIN to PHSOUT does not change.
IR3505
Page 13 of 19 Sept 26th, 2007
Emulated Bootstrap Diode
IR3505 integrates a PFET to emulate the bootstrap diode. An external bootstrap diode connected from VCCL
pin to BOOST pin can be added to reduce the drop across the PFET but is not needed in most applications.
APPLICATIONS INFORMATION
IR3505 EXTERNAL COMPONENTS
Inductor Current Sensing Capacitor CCS and Resistor RCS
The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS and capacitor
CCS in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage
across the capacitor CCS represents the inductor current. If the two time constants are not the same, the AC
component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch
does not affect the average current sharing among the multiple phases, but does effect the current signal ISHARE
as well as the output voltage during the load current transient if adaptive voltage positioning is adopted.
Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCS as
follows.
CS
L
CS C
RL
R= (1)
Bootstrap Capacitor CBST
Depending on the duty cycle and gate drive current of the phase IC, a capacitor in the range of 0.1uF to 1uF is
needed for the bootstrap circuit.
Decoupling Capacitors for Phase IC
A 0.1uF-1uF decoupling capacitor is required at the VCCL pin.
CURRENT SHARE LOOP COMPENSATION
The internal compensation of current share loop ensures that crossover frequency of the current share loop is at
least one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated.
The crossover frequency of current share loop is approximately 8 kHz.
Output Voltage Bleed Resistor
The floating high side driver draws bias current from the BOOST pin (3.5mA typical). This current flows out of
the IR3505 through the SW pin and will charge up the output capacitor when the control IC is disabled. A
bleed resistor connected from the converter output voltage to ground is required to prevent the output voltage
from exceeding the control IC Over-Voltage protection threshold. The bleed resistor can be selected using the
following equation.
RBLEED = VBLEED / (5.8mA x N) (2)
Where VBLEED is the maximum desired output voltage pre-bias and N is the number of IR3505 used in the
converter.
Optional phases
A converter can be designed to support more or less phases. This can be quite useful in situations where the final
load current is unknown or where increased load current may be required at some time in the future.
IR3505
Page 14 of 19 Sept 26th, 2007
Figure 7 provides an application circuit that allows adjustment to the number of phases. By populating zero ohm
jumpers, or not; the number of phases can be adjusted by diverting the daisy chain timing from a 3505 to the next
one in sequence. The effect of more or less phases on converter performance can be tested without actually
removing a 3505 or it’s MOSFETs from the printed circuit board through use of a pull-up resistor from VCCL to
the CSIN+ pin to enable de-bug mode.
Figure 7 – Optional Phase application circuit
CSIN- 15
VCC 13
EAIN 16
ISHARE
1SW 12
GATEH 11
BOOST 10
CSIN+ 14
DACIN
2
CLKIN
6
PHSIN
4
PHSOUT
5
GATEL
8
PGND
7
VCCL 9
LGND
3
IR3505
PHASE
IC
U1
CSIN- 15
VCC 13
EAIN 16
ISHARE
1SW 12
GATEH 11
BOOST 10
CSIN+ 14
DACIN
2
CLKIN
6
PHSIN
4
PHSOUT
5
GATEL
8
PGND
7
VCCL 9
LGND
3
IR3505
PHASE
IC
U2
CSIN- 15
VCC 13
EAIN 16
ISHARE
1SW 12
GATEH 11
BOOST 10
CSIN+ 14
DACIN
2
CLKIN
6
PHSIN
4
PHSOUT
5
GATEL
8
PGND
7
VCCL 9
LGND
3
IR3505
PHASE
IC
U3
R11
0 ohm
R13
Open
R23
Open
R33
Open
R21
0 ohm
R31
0 ohm
CLKOUT
25
PHSOUT
26
PHSIN
27
IR3500
CONTROL
IC
U0
R12
open
R22
open
R32
open
CSIN- 15
VCC 13
EAIN 16
ISHARE
1SW 12
GATEH 11
BOOST 10
CSIN+ 14
DACIN
2
CLKIN
6
PHSIN
4
PHSOUT
5
GATEL
8
PGND
7
VCCL 9
LGND
3
IR3505
PHASE
IC
U1
CSIN- 15
VCC 13
EAIN 16
ISHARE
1SW 12
GATEH 11
BOOST 10
CSIN+ 14
DACIN
2
CLKIN
6
PHSIN
4
PHSOUT
5
GATEL
8
PGND
7
VCCL 9
LGND
3
IR3505
PHASE
IC
U2
R11
0 ohm
CSIN- 15
VCC 13
EAIN 16
ISHARE
1SW 12
GATEH 11
BOOST 10
CSIN+ 14
DACIN
2
CLKIN
6
PHSIN
4
PHSOUT
5
GATEL
8
PGND
7
VCCL 9
LGND
3
IR3505
PHASE
IC
U3
R13
Open
R23
Open
R33
0 ohm
R21
0 ohm
R31
open
CLKOUT
25
PHSOUT
26
PHSIN
27
IR3500
CONTROL
IC
U0
R12
open
R22
0 ohm
R32
open
Three
Phase
Two
Phase
IR3505
Page 15 of 19 Sept 26th, 2007
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the
PCB layout, therefore minimizing the noise coupled to the IC.
• Dedicate at least one middle layer for a ground plane, which is then split into signal ground plane (LGND)
and power ground plane (PGND).
• Separate analog bus (EAIN, DACIN, and ISHARE) from digital bus (CLKIN, PHSIN, and PHSOUT) to
reduce the noise coupling.
• Connect PGND to LGND pins to their respective ground planes through vias.
• Place current sense resistors and capacitors (RCS and CCS) close to phase IC. Use Kelvin connection for
the inductor current sense wires, but separate the two wires by ground polygon. The wire from the inductor
terminal to CSIN- should not cross over the fast transition nodes, i.e. switching nodes, gate drive outputs
and bootstrap nodes.
• Place the decoupling capacitor CVCCL as close as possible to the VCCL pin.
• Place the phase IC as close as possible to the MOSFETs to reduce the parasitic resistance and
inductance of the gate drive paths.
• Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET.
Use combination of different packages of ceramic capacitors.
• There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor,
output capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and
the load. Route the switching power paths using wide and short traces or polygons; use multiple vias for
connections between layers.
PGND
GATEL
VCCL
GATEH
BOOST
VCC
EAIN
To Digital Bus
To Inductor
To LGND
Plane
C
VCCL
To VIN
D
BST
SW
C
BST
To Gate
Drive
Voltage
PHSIN
LGND
DACIN
ISHARE
CSIN
-
PHSOUT
CLKIN
To Top
MOSFET
PGND
PLANE
LGND
PLANE
Ground
Polygon
C
VCC
R
CS
C
CS
To Bottom
MOSFET
To Analog Bus
To Switching
Node
R
PGND
GATEL
VCCL
GATEH
BOOST
VCC
EAIN
To Digital Bus
To Inductor
To LGND
Plane
C
VCCL
To VIN
D
BST
SW
C
BST
To Gate
Drive
Voltage
PHSIN
LGND
DACIN
ISHARE
PHSOUT
CLKIN
To Top
MOSFET
PGND
PLANE
LGND
PLANE
Ground
Polygon
C
VCC
R
CS
C
CS
To Bottom
MOSFET
To Analog Bus
To Switching
Node
CSIN+
CSIN -
IR3505
Page 16 of 19 Sept 26th, 2007
PCB Metal and Component Placement
• Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should
be ≥ 0.2mm to minimize shorting.
• Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm
inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard
extension will accommodate any part misalignment and ensure a fillet.
• Center pad land length and width should be equal to maximum part pad length and width. However, the
minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥
0.23mm for 3 oz. Copper)
• Four 0.3mm diameter vias shall be placed in the pad land spaced at 0.85mm, and connected to ground
to minimize the noise effect on the IC, and to transfer heat to the PCB
IR3505
Page 17 of 19 Sept 26th, 2007
Solder Resist
• The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The
solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all
Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads.
• The minimum solder resist width is 0.13mm.
• At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide
a fillet so a solder resist width of ≥ 0.17mm remains.
• The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto
the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is
allowable to have the solder resist opening for the land pad to be smaller than the part pad.
• Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high
aspect ratio of the solder resist strip separating the lead lands from the pad land.
• The four vias in the land pad should be tented or plugged from bottom board side with solder resist.
IR3505
Page 18 of 19 Sept 26th, 2007
Stencil Design
• The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands.
Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm
pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower;
openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release.
• The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead
land.
• The land pad aperture should be approximately 70% area of solder on the center pad. If too much
solder is deposited on the center pad the part will float and the lead lands will be open.
• The maximum length and width of the land pad stencil aperture should be equal to the solder resist
opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the
lead lands when the part is pushed into the solder paste.
IR3505
Page 19 of 19 Sept 26th, 2007
PACKAGE INFORMATION
16L MLPQ (3 x 3 mm Body) – θJA = 38oC/W, θJC = 3oC/W
Data and specifications subject to change without notice.
This product will be designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
www.irf.com
