AOZ8001 Ultra-Low Capacitance TVS Diode Array General Description Features The AOZ8001 is a transient voltage suppressor array designed to protect high speed data lines from ESD and lightning. This device incorporates four surge rated, low capacitance steering diodes and a TVS in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. They may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4. The TVS diodes provide effective suppression of ESD voltages: 15kV (air discharge) and 8kV (contact discharge). The AOZ8001 comes in RoHS compliant, SOT-143 and SC-89 package and is rated over a -40C to +85C ambient temperature range. They are compatible with both lead free and SnPb assembly techniques. ESD protection for high-speed data lines: - IEC 61000-4-2, level 4 (ESD) immunity test - 15kV (air discharge) and 8kV (contact discharge) - IEC 61000-4-5 (Lightning) 5A (8/20s) - Human Body Model (HBM) 15kV Small package saves board space Low insertion loss Protects four I/O lines Low capacitance between I/O lines: 0.9pF Low clamping voltage Low operating voltage: 5.0V Applications The very small 1.7 x 1.7 x 0.6mm SC-89 package makes it ideal for applications where PCB space is a premium. The SC-89 has a flow through package design for an optimal and user friendly PCB layout design. The small size, low capacitance and high ESD protection makes it ideal for protecting high speed video and data communication interfaces. USB 2.0 power and data line protection Video graphics cards Monitors and flat panel displays Digital Video Interface (DVI) 10/100/1000 Ethernet Notebook computers Typical Application USB Controller USB Controller +5V +5V D+ D+ D- D- GND GND 1 6 2 5 3 4 AOZ8001 Figure 1. USB 2.0 High Speed Port Rev. 1.6 July 2007 www.aosmd.com Page 1 of 11 AOZ8001 Ordering Information Part Number Ambient Temperature Range Package Environmental AOZ8001KI -40C to +85C SC-89 RoHS Compliant AOZ8001JI S nt RoH plia Com SOT-143 All AOS Products are offering in packaging with Pb-free plating and compliant to RoHS standards. Please visit wwww.aosmd.com/web/rohs_compliant.jsp for additional information. Pin Configuration VN CH1 4 1 2 3 VP CH2 CH1 1 6 NC VN 2 5 VP NC 3 4 CH2 SOT-143 SC-89 (Top View) (Top View) Absolute Maximum Ratings Exceeding the Absolute Maximum ratings may damage the device. Parameter Rating VP - VN 6V Peak Pulse Current (IPP), tP = 8/20s 5A Peak Power Dissipation (TBD @ 25C) SOT-143 SC-89 TBD TBD Storage Temperature (TS) -65C to +150C ESD Rating per IEC61000-4-2, Contact(1) 8kV ESD Rating per IEC61000-4-2, Air(1) 15kV Model(2) 15kV ESD Rating per Human Body Notes: 1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330. 2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5k. Maximum Operating Ratings Parameter Rating Junction Temperature (TJ) Rev. 1.6 July 2007 -40C to +85C www.aosmd.com Page 2 of 11 AOZ8001 Electrical Characteristics TA = 25C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40C to +85C. Symbol VRWM VBR Parameter Reverse Working Voltage Conditions Min. 2(4) IT = 1mA, between pins 5 and IR Reverse Leakage Current VRWM = 5V, between pins 5 and 2 VF Diode Forward Voltage IF = 15mA Cj 5.5 V IPP = 1A, tp = 100ns, any I/O pin to Channel Clamp Voltage Positive Transients Negative Transient IPP = 5A, tp = 100ns, any I/O pin to Ground(5)(7) Channel Clamp Voltage Positive Transients Negative Transient IPP = 12A, tp = 100ns, any I/O pin to Ground(5)(7) Junction Capacitance VR = 0V, f = 1MHz, any I/O pin to Ground(5) pins(5) VR = 0V, f = 1MHz, any I/O pin to VR = 0V, f = 1MHz, between I/O V 0.1 A 1 V 9.75 -1.52 V V 10.42 -2.94 V V 13 -5.75 V V 1.85 1.94 pF 0.9 0.94 pF 1.0 1.17 pF 0.03 pF 0.85 Ground(5)(7) Channel Clamp Voltage Positive Transients Negative Transient Channel Input Capacitance Matching Units 6.6 0.70 VR = 0V, f = 1MHz, between I/O Cj Max. Between pin 5 and 2(3) Reverse Breakdown Voltage VCL Typ. Ground(6) pins(5) Notes: 3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level. 4. VBR is measured at the pulse test current IT. 5. Measurements performed with no external capacitor on VP (pin 5 floating). 6. Measurements performed with VP biased to 3.3 Volts (pin 5 @ 3.3V). 7. Measurements performed using a 100ns Transmission Line Pulse (TLP) system. Rev. 1.6 July 2007 www.aosmd.com Page 3 of 11 AOZ8001 Typical Performance Characteristics Typical Variation of CIN vs VR Clamping Voltage vs. Peak Pulse Current (tperiod = 100ns, tr = 1ns) (f = 1MHz, T = 25C) 14 Vp (Pin 5) = Float 1.75 1.50 1.25 1.00 Vp (Pin 5) = 3.3V 0.75 0.50 0.25 0.00 0.00 13 Clamping Voltage, VCL (V) Input Capacitance (pF) 2.00 12 11 10 9 8 7 6 1.00 2.00 3.00 4.00 5.00 0 Input Voltage (V) 2 4 Forward Voltage vs. Forward Current Insertion Loss (dB) Forward Voltage (V) 6 5 4 3 2 1 0 4 6 12 8 10 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 12 1 Forward Current (A) 10 100 1000 Frequency (MHz) I/O - I/O Insertion Loss (S21) vs. Frequency Analog Crosstalk (I/O-I/O) vs. Frequency (Vp = Float) 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 20 Insertion Loss (dB) Insertion Loss (dB) 10 (Vp = 3.3V) 7 2 8 I/O - Gnd Insertion Loss (S21) vs. Frequency (tperiod = 100ns, tr = 1ns) 0 6 Peak Pulse Current, IPP (A) 0 -20 -40 -60 -80 1 10 100 1000 10 Frequency (MHz) Rev. 1.6 July 2007 100 1000 Frequency (MHz) www.aosmd.com Page 4 of 11 AOZ8001 Application Information The AOZ8001 TVS is design to protect two data lines from fast damaging transient over-voltage by clamping it to a reference. When the transient on a protected data line exceed the reference voltage the steering diode is forward bias thus, conducting the harmful ESD transient away from the sensitive circuitry under protection. PCB Layout Guidelines Printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines. The location of the protection devices on the PCB is the simplest and most important design rule to follow. The AOZ8001 devices should be located as close as possible to the noise source. The placement of the AOZ8001 devices should be used on all data and power lines that enter or exit the PCB at the I/O connector. In most systems, surge pulses occur on data and power lines that enter the PCB through the I/O connector. Placing the AOZ8001 devices as close as possible to the noise source ensures that a surge voltage will be clamped before the pulse can be coupled into adjacent PCB traces. In addition, the PCB should use the shortest possible traces. A short trace length equates to low impedance, which ensures that the surge energy will be dissipated by the AOZ8001 device. Long signal traces will act as antennas to receive energy from fields that are produced by the ESD pulse. By keeping line lengths as short as possible, the efficiency of the line to act as an antenna for ESD related fields is reduced. Minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible. The protection circuits should shunt the surge voltage to either the reference or chassis ground. Shunting the surge voltage directly to the IC's signal ground can cause ground bounce. The clamping performance of TVS diodes on a single ground PCB can be improved by minimizing the impedance with relatively short and wide ground traces. The PCB layout and IC package parasitic inductances can cause significant overshoot to the TVS's clamping voltage. The inductance of the PCB can be reduced by using short trace lengths and multiple layers with separate ground and power planes. One effective method to minimize loop problems is to incorporate a ground plane in the PCB design. The AOZ8001 ultra-low capacitance TVS is designed to protect four high speed data transmission lines from transient over-voltages by clamping them to a fixed reference. The low inductance and construction minimizes voltage overshoot during high current surges. When the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: 1. Place the TVS near the IO terminals or connectors to restrict transient coupling. 2. Fill unused portions of the PCB with ground plane. 3. Minimize the path length between the TVS and the protected line. 4. Minimize all conductive loops including power and ground loops. 5. The ESD transient return path to ground should be kept as short as possible. 6. Never run critical signals near board edges. 7. Use ground planes whenever possible. 8. Avoid running critical signal traces (clocks, resets, etc.) near PCB edges. 9. Separate chassis ground traces from components and signal traces by at least 4mm. 10. Keep the chassis ground trace length-to-width ratio <5:1 to minimize inductance. 11. Protect all external connections with TVS diodes. Connector Protected IC D+ D+ D- DFlow Through Layout Rev. 1.6 July 2007 www.aosmd.com Page 5 of 11 AOZ8001 AOZ8001 VCC 4 1 3 2 VCC Reset Clock SIM I/O GND 3 2 VCC 1 4 AOZ8001 SIM Card Port Connection AOZ8001 TPBIASx 4 3 TPAx+ TPAx- IEEE 1394 PHY 1 4 2 IEEE 1394 Connector 3 TPBx+ TPBx- GND 1 2 AOZ8001 IEEE1394 Port Connection Rev. 1.6 July 2007 www.aosmd.com Page 6 of 11 AOZ8001 AOZ8001 4 3 TRD0+ TRD0- 1 2 AOZ8001 4 3 TRD1+ TRD1- 1 Ethernet Controller 2 RJ45 Connector AOZ8001 4 3 TRD2+ TRD2- 1 2 AOZ8001 4 3 TRD3+ TRD3- 1 2 10/100 Ethernet Port Connection Rev. 1.6 July 2007 www.aosmd.com Page 7 of 11 AOZ8001 Package Dimensions, SOT143-4L D e c S L1 E E1 e1 b2 b A A1 RECOMMENDED LAND PATTERN 1.92 0.70 0.60 1.90 0.70 1.05 0.76 UNIT: mm Dimensions in millimeters Symbols A A1 Min. 0.890 0.013 b b2 c D E E1 e e1 L1 S 0.370 0.760 0.085 2.800 2.100 1.200 Nom. -- -- Max. 1.120 0.100 -- 0.510 -- 0.940 -- 0.180 -- 3.040 ---- 2.640 -- 1.400 1.920 BSC 0.200 BSC 0.550 REF 0.450 -- 0.600 0 -- 8 Dimensions in inches Symbols A A1 Min. 0.035 0.001 b b2 c D E E1 e e1 L1 S 0.015 0.030 0.003 0.110 0.083 0.047 Nom. -- -- Max. 0.044 0.004 -- 0.020 -- 0.037 -- 0.007 -- 0.120 ---- 0.104 -- 0.055 0.076 BSC 0.008 BSC 0.022 REF 0.018 -- 0.024 0 -- 8 Notes: 1. All dimensions are in millimeters. 2. Tolerances are 0.10mm unless otherwise specified. 3. Package body sizes exclude mold flash and gate burrs. 4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact. Rev. 1.6 July 2007 www.aosmd.com Page 8 of 11 AOZ8001 Package Dimensions, SC-89 D E1 E c e b A1 L1 L A RECOMMENDED LAND PATTERN 0.50 1.25 0.45 0.30 UNIT: mm Dimensions in millimeters Symbols A A1 b Min. 0.53 0.00 0.15 c D E E1 e L 0.10 1.50 1.50 1.10 L1 Nom. 0.58 -- 0.20 Dimensions in inches Max. 0.62 0.10 0.30 Symbols A A1 b Min. 0.021 0.000 0.006 0.11 1.60 1.60 1.20 0.50 BSC 0.25 0.35 0.18 1.70 1.70 1.30 0.004 0.059 0.059 0.043 0.45 c D E E1 e L 0.13 0.27 L1 0.005 0.20 Nom. 0.023 -- 0.008 Max. 0.024 0.004 0.012 0.004 0.007 0.063 0.067 0.063 0.067 0.047 0.051 0.020 BSC 0.010 0.014 0.018 0.008 0.011 Notes: 1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per end. Dimension E1 does not include interlead flash or protrusion. 2. Dimensions D and E1 are determinded at the outmost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact. 4. All dimensions are in millimeters. Rev. 1.6 July 2007 www.aosmd.com Page 9 of 11 AOZ8001 Part Marking AOZ8001KI AOZ8001JI (SC-89) (SOT-143) Top Marking PWL PNOA Part Number Code Assembly Lot and Location Code Week & Year Code Part Number Code Assembly Location Code Option Code Bottom Marking YWLT Year & Week Code Rev. 1.6 July 2007 www.aosmd.com Assembly Lot Code Page 10 of 11 AOZ8001 This datasheet contains preliminary data; supplementary data may be published at a later date. Alpha & Omega Semiconductor reserves the right to make changes at any time without notice. LIFE SUPPORT POLICY ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 1.6 July 2007 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 11 of 11