Rev. 1.6 July 2007
www.aosmd.com
Page 1 of 11
AOZ8001
Ultra-Low Capacitance TVS Diode Array
General Description
The AOZ8001 is a transient voltage suppressor array
designed to protect high speed data lines from ESD and
lightning.
This device incorporates four surge rated, low capacitance
steering diodes and a TVS in a single package. During
transient conditions, the steering diodes direct the
transient to either the positive side of the power supply
line or to ground. They may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4.
The TVS diodes provide effective suppression of ESD
voltages: ±15kV (air discharge) and ±8kV (contact
discharge).
The AOZ8001 comes in RoHS compliant, SOT-143 and
SC-89 package and is rated over a -40°C to +85°C
ambient temperature range. They are compatible with
both lead free and SnPb assembly techniques.
The very small 1.7 x 1.7 x 0.6mm SC-89 package makes
it ideal for applications where PCB space is a premium.
The SC-89 has a flow through package design for an
optimal and user friendly PCB layout design. The small
size, low capacitance and high ESD protection makes
it ideal for protecting high speed video and data
communication interfaces.
Features
●
ESD protection for high-speed data lines:
– IEC 61000-4-2, level 4 (ESD) immunity test
– ±15kV (air discharge) and ±8kV (contact discharge)
– IEC 61000-4-5 (Lightning) 5A (8/20µs)
– Human Body Model (HBM) ±15kV
●
Small package saves board space
●
Low insertion loss
●
Protects four I/O lines
●
Low capacitance between I/O lines: 0.9pF
●
Low clamping voltage
●
Low operating voltage: 5.0V
Applications
●
USB 2.0 power and data line protection
●
Video graphics cards
●
Monitors and flat panel displays
●
Digital Video Interface (DVI)
●
10/100/1000 Ethernet
●
Notebook computers
Typical Application
Figure 1. USB 2.0 High Speed Port
USB Controller
+5V
D+
D-
GND
USB Controlle
r
+5V
D+
D-
GND
AOZ8001
1
34
6
2 5
AOZ8001
Rev. 1.6 July 2007
www.aosmd.com
Page 2 of 11
Ordering Information
All AOS Products are offering in packaging with Pb-free plating and compliant to RoHS standards.
Please visit wwww.aosmd.com/web/rohs_compliant.jsp for additional information.
Pin Configuration
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Notes:
1. IEC 61000-4-2 discharge with C
Discharge
= 150pF, R
Discharge
= 330
Ω
.
2. Human Body Discharge per MIL-STD-883, Method 3015 C
Discharge
= 100pF, R
Discharge
= 1.5k
Ω
.
Maximum Operating Ratings
Part Number Ambient Temperature Range Package Environmental
AOZ8001KI -40°C to +85°C SC-89 RoHS Compliant
AOZ8001JI SOT-143
SOT-143
(Top View)
1
2
3
6
5
4
CH1
VN
NC
1
2
VN
CH1
NC
VP
CH2
4
3
VP
CH2
SC-89
(Top View)
Parameter Rating
VP – VN 6V
Peak Pulse Current (I
PP
), t
P
= 8/20µs 5A
Peak Power Dissipation (TBD @ 25°C)
SOT-143
SC-89
TBD
TBD
Storage Temperature (T
S
) -65°C to +150°C
ESD Rating per IEC61000-4-2, Contact
(1)
±8kV
ESD Rating per IEC61000-4-2, Air
(1)
±15kV
ESD Rating per Human Body Model
(2)
±15kV
Parameter Rating
Junction Temperature (T
J
) -40°C to +85°C
RoHS
Compliant
AOZ8001
Rev. 1.6 July 2007
www.aosmd.com
Page 3 of 11
Electrical Characteristics
T
A
= 25°C unless otherwise specified. Specifications in
BOLD
indicate a temperature range of -40°C to +85°C.
Notes:
3. The working peak reverse voltage, V
RWM
, should be equal to or greater than the DC or continuous peak operating voltage level.
4. V
BR
is measured at the pulse test current I
T
.
5. Measurements performed with no external capacitor on V
P
(pin 5 floating).
6. Measurements performed with V
P
biased to 3.3 Volts (pin 5 @ 3.3V).
7. Measurements performed using a 100ns Transmission Line Pulse (TLP) system.
Symbol Parameter Conditions Min. Typ. Max. Units
V
RWM
Reverse Working Voltage Between pin 5 and 2
(3)
5.5 V
V
BR
Reverse Breakdown Voltage I
T
= 1mA, between pins 5 and 2
(4)
6.6
V
I
R
Reverse Leakage Current V
RWM
= 5V, between pins 5 and 2
0.1
µA
V
F
Diode Forward Voltage I
F
= 15mA
0.70 0.85 1
V
V
CL
Channel Clamp Voltage
Positive Transients
Negative Transient
I
PP
= 1A, tp = 100ns, any I/O pin to Ground
(5)(7)
9.75
-1.52
V
V
Channel Clamp Voltage
Positive Transients
Negative Transient
I
PP
= 5A, tp = 100ns, any I/O pin to Ground
(5)(7)
10.42
-2.94
V
V
Channel Clamp Voltage
Positive Transients
Negative Transient
I
PP
= 12A, tp = 100ns, any I/O pin to Ground
(5)(7)
13
-5.75
V
V
C
j
Junction Capacitance V
R
= 0V, f = 1MHz, any I/O pin to Ground
(5)
1.85 1.94 pF
V
R
= 0V, f = 1MHz, between I/O pins
(5)
0.9 0.94 pF
V
R
= 0V, f = 1MHz, any I/O pin to Ground
(6)
1.0 1.17 pF
∆
C
j
Channel Input Capacitance
Matching
V
R
= 0V, f = 1MHz, between I/O pins
(5)
0.03 pF
AOZ8001
Rev. 1.6 July 2007
www.aosmd.com
Page 4 of 11
Typical Performance Characteristics
Typical Variation of CIN vs VR
(f = 1MHz, T = 25°C)
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
0.00 1.00 2.00
Vp (Pin 5) = Float
Vp (Pin 5) = 3.3V
3.00 4.00 5.00
Input Voltage (V)
Input Capacitance (pF)
Clamping Voltage vs. Peak Pulse Current
(tperiod = 100ns, tr = 1ns)
14
13
12
11
10
9
8
7
6
Peak Pulse Current, IPP (A)
Clamping Voltage, VCL (V)
0 2 4 6 8 10 12
Forward Voltage vs. Forward Current
(tperiod = 100ns, tr = 1ns)
7
6
5
4
3
2
1
0
Forward Current (A)
Forward Voltage (V)
0 2 4 6 8 10 12
I/O – Gnd Insertion Loss (S21) vs. Frequency
(Vp = 3.3V)
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
Frequency (MHz)
Insertion Loss (dB)
110100 1000
I/O – I/O Insertion Loss (S21) vs. Frequency
(Vp = Float)
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
Frequency (MHz)
Insertion Loss (dB)
110100 1000 10010 1000
Analog Crosstalk (I/O–I/O) vs. Frequency
20
0
-20
-40
-60
-80
Frequency (MHz)
Insertion Loss (dB)
AOZ8001
Rev. 1.6 July 2007
www.aosmd.com
Page 5 of 11
Connector
D+
D-
D+
D-
Protected IC
Flow Through Layout
Application Information
The AOZ8001 TVS is design to protect two data lines
from fast damaging transient over-voltage by clamping it
to a reference. When the transient on a protected data
line exceed the reference voltage the steering diode is
forward bias thus, conducting the harmful ESD transient
away from the sensitive circuitry under protection.
PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8001 devices should be located as close as possible
to the noise source. The placement of the AOZ8001
devices should be used on all data and power lines that
enter or exit the PCB at the I/O connector. In most
systems, surge pulses occur on data and power lines that
enter the PCB through the I/O connector. Placing the
AOZ8001 devices as close as possible to the noise
source ensures that a surge voltage will be clamped
before the pulse can be coupled into adjacent PCB
traces. In addition, the PCB should use the shortest
possible traces. A short trace length equates to low
impedance, which ensures that the surge energy will be
dissipated by the AOZ8001 device. Long signal traces
will act as antennas to receive energy from fields that are
produced by the ESD pulse. By keeping line lengths as
short as possible, the efficiency of the line to act as an
antenna for ESD related fields is reduced. Minimize inter-
connecting line lengths by placing devices with the most
interconnect as close together as possible. The protec-
tion circuits should shunt the surge voltage to either the
reference or chassis ground. Shunting the surge voltage
directly to the IC’s signal ground can cause ground
bounce. The clamping performance of TVS diodes on a
single ground PCB can be improved by minimizing the
impedance with relatively short and wide ground traces.
The PCB layout and IC package parasitic inductances
can cause significant overshoot to the TVS’s clamping
voltage. The inductance of the PCB can be reduced by
using short trace lengths and multiple layers with
separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design. The AOZ8001 ultra-low
capacitance TVS is designed to protect four high speed
data transmission lines from transient over-voltages by
clamping them to a fixed reference. The low inductance
and construction minimizes voltage overshoot during
high current surges. When the voltage on the protected
line exceeds the reference voltage the internal steering
diodes are forward biased, conducting the transient
current away from the sensitive circuitry.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
1. Place the TVS near the IO terminals or connectors to
restrict transient coupling.
2. Fill unused portions of the PCB with ground plane.
3. Minimize the path length between the TVS and the
protected line.
4. Minimize all conductive loops including power and
ground loops.
5. The ESD transient return path to ground should be
kept as short as possible.
6. Never run critical signals near board edges.
7. Use ground planes whenever possible.
8. Avoid running critical signal traces (clocks, resets,
etc.) near PCB edges.
9. Separate chassis ground traces from components
and signal traces by at least 4mm.
10. Keep the chassis ground trace length-to-width ratio
<5:1 to minimize inductance.
11. Protect all external connections with TVS diodes.
AOZ8001
Rev. 1.6 July 2007
www.aosmd.com
Page 6 of 11
SIM Card Port Connection
IEEE1394 Port Connection
SIM
AOZ8001
AOZ8001
AOZ8001
AOZ8001
VCC
Reset
Clock
I/O
GND
IEEE 1394
PHY
IEEE 1394
Connector
TPBIASx
TPAx+
TPAx-
TPBx+
TPBx-
GND
1
2
4
3
VCC
VCC
1
12
2
34
34
1
23
4
AOZ8001
Rev. 1.6 July 2007
www.aosmd.com
Page 7 of 11
10/100 Ethernet Port Connection
Ethernet
Controller
RJ45
Connector
TRD0+
TRD0-
TRD1+
TRD1-
TRD2+
TRD2-
TRD3-
TRD3+
AOZ8001
12
34
AOZ8001
12
34
AOZ8001
12
34
AOZ8001
12
34
AOZ8001
Rev. 1.6 July 2007
www.aosmd.com
Page 8 of 11
Package Dimensions, SOT143-4L
Notes:
1. All dimensions are in millimeters.
2. Tolerances are 0.10mm unless otherwise specified.
3. Package body sizes exclude mold flash and gate burrs.
4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Symbols
A
A1
b
b2
c
D
E
E1
e
e1
L1
S
θ
Dimensions in millimeters
Min.
0.890
0.013
0.370
0.760
0.085
2.800
2.100
1.200
0.450
0°
Nom.
—
—
—
—
—
—
——
—
1.920 BSC
0.200 BSC
0.550 REF
—
—
Max.
1.120
0.100
0.510
0.940
0.180
3.040
2.640
1.400
0.600
8°
Dimensions in inches
RECOMMENDED LAND PATTERN
θ
1.92
0.70
0.70
0.76
1.05
1.90
0.60
A1 A
b2
e1
EE1
Sc
L1
e
D
b
Symbols
A
A1
b
b2
c
D
E
E1
e
e1
L1
S
θ
Min.
0.035
0.001
0.015
0.030
0.003
0.110
0.083
0.047
0.018
0°
Nom.
—
—
—
—
—
—
——
—
0.076 BSC
0.008 BSC
0.022 REF
—
—
Max.
0.044
0.004
0.020
0.037
0.007
0.120
0.104
0.055
0.024
8°
UNIT: mm
AOZ8001
Rev. 1.6 July 2007
www.aosmd.com
Page 9 of 11
Package Dimensions, SC-89
Notes:
1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm
per end. Dimension E1 does not include interlead flash or protrusion.
2. Dimensions D and E1 are determinded at the outmost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs
and interlead flash, but including any mismatch between the top and bottom of the plastic body.
3. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
4. All dimensions are in millimeters.
Symbols
A
A1
b
c
D
E
E1
e
L
L1
Dimensions in millimeters
RECOMMENDED LAND PATTERN Min.
0.53
0.00
0.15
0.10
1.50
1.50
1.10
0.25
0.13
D
b
E1
UNIT: mm
Nom.
0.58
—
0.20
0.11
1.60
1.60
1.20
0.50 BSC
0.35
0.20
Max.
0.62
0.10
0.30
0.18
1.70
1.70
1.30
0.45
0.27
Symbols
A
A1
b
c
D
E
E1
e
L
L1
Dimensions in inches
Min.
0.021
0.000
0.006
0.004
0.059
0.059
0.043
0.010
0.005
Nom.
0.023
—
0.008
0.004
0.063
0.063
0.047
0.020 BSC
0.014
0.008
Max.
0.024
0.004
0.012
0.007
0.067
0.067
0.051
0.018
0.011
ec
A1
E
A
0.45
0.30
0.50
1.25
LL1
AOZ8001
Rev. 1.6 July 2007
www.aosmd.com
Page 10 of 11
Part Marking
AOZ8001KI
(SC-89) AOZ8001JI
(SOT-143)
Top Marking
Bottom Marking
PWL
PNOA
Assembly Location Code
Assembly Lot Code
Part Number Code
Part Number Code
Assembly Lot and
Location Code
Week & Year Code
Option Code
YWLT
Year & Week Code
AOZ8001
Rev. 1.6 July 2007
www.aosmd.com
Page 11 of 11
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
