20-Bit Latc h
f
ax id: 7018
CY74FCT16841T
CY74FCT162841T
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Jul
y
1994 - Revised Octob er 30
,
1997
2
841T
Features
• Low pow er, pin- com pati ble rep lacement for ABT func-
tions
• FCT-C speed at 5.5 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuit ry for signif icantly improved
noise characteristics
• Typical output sk ew < 250 ps
• ESD > 2000V
• TSSOP (19.6 -mil pit ch) and SSOP (25-mil pitc h)
packages
• Industrial temperature range of −40°C to +85°C
•V
CC = 5V ± 10%
CY74FCT16841T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25°C
CY74FCT162841T Featur es:
• Balanced 24 mA output dri vers
• R educed system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25°C
Functional Descripti on
The CY74FCT16841T and CY74FCT162841T are 20-bit
D-type latches designed for use in bus applications requiring
high spee d and low po wer. These de v ices can be used as two
independent 10-bit latches, or as a single 10-bit latch, or as a
single 20-bit latch by connecting the Output Enable (OE) and
Latch (LE) inputs. Flow-through pi nout and sm all shrink pack -
aging aid in simplifying board layout. The output buffers are
designe d with a po wer-off disabl e feat ure to al low li ve inse rtion
of boards.
The CY74FCT16841T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162841T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for mini-
mal undershoot and reduced ground bounce. The
CY74FCT162841T is ideal for driving transm ission lines.
C
GND
1D1
Logic Block Diagrams Pin Configuration
TO 9 OTHER CHANNELS
C
2D1
2Q1
2LE
2OE
D
1Q7
1OE
SSOP/TSSOP
Top View
1Q1
1LE
1OE
1Q1
1Q2
1Q3
1Q4
1D1
1D2
1D3
1D4
1LE
GND
GND
VCC
1Q5
1Q6
1D5
1D6
VCC
GND
2D1
GND
GND
VCC VCC
GND
D
1Q8
1Q10
2Q1
1Q9
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
2Q10
2OE
1D7
GND
1D8
1D9
1D10
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
2D10
2LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FCT16841-1
FCT16841-2
FCT16841-3
TO 9 OTHER CHANNELS
CY74FCT16841T
CY74FCT162841T
2
Maximum Ratings[3, 4]
(Above which the useful life may be impaired. For user
guidelines , not tested.)
Storage Temperature......................................−55°C to +125°C
Ambient Temper ature wit h
Power Appl ied..................................................−55°C to +125°C
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)...........................−60 to +120 mA
Power Dissipation.......................................................... 1.0W
Static Discharge Voltage ...........................................>2001V
(per MIL- STD-883, Method 3015)
Pin Description
Name Description
DData Inputs
LE Latch Enable Inpu t (Activ e HIGH)
OE Output Enable Input (Active LOW)
OThree-State Outputs
Function Table[1]
Inputs Outputs
DLE OE Q
H H L H
L H L L
X L L Q[2]
X X H Z
Operating Range
Range Ambient
Temperature VCC
Industrial −40°C to +85°C 5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ.[5] Max. Unit
VIH Input HIGH Voltage Gua r an teed Log i c HIG H Leve l 2.0 V
VIL Input LO W Volta ge Guaranteed Logic LOW Level 0.8 V
VHInput Hysteresis[6] 100 mV
VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 −1.2 V
IIH Input HIGH Current VCC= M a x ., V I=VCC ±1µA
IIL Input LO W Current VCC= M a x ., V I=GND ±1µA
IOZH High Impedance Output
Current (Thre e-State Output pins) VCC= M a x ., VOUT=2.7V ±1µA
IOZL High Impedance Output
Current (Thre e-State Output pins) VCC= M a x ., VOUT=0.5V ±1µA
IOS Short Circuit Current[7] VCC= Ma x., VOUT=GND −80 −140 −200 mA
IOOutput Drive Current[7] VCC=M a x ., VOUT=2.5V −50 −180 mA
IOFF Power-Off Disable VCC=0V, VOUT≤4.5V[8] ±1µA
Notes:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance.
2. Output level before LE HIGH-to-LOW Transition.
3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
5. Typical values are at VCC= 5.0V, TA= +25°C ambient.
6. This parameter is guaranteed but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
8. Tested at +25°C.
CY74FCT16841T
CY74FCT162841T
3
Output D rive Characteristics for CY74FCT16841T
Parameter Description Test Conditions Min. Typ.[5] Max. Unit
VOH Output HIGH Voltage VCC=Min., IOH=−3 mA 2.5 3.5 V
VCC=Min., IOH=−15 mA 2.4 3.5
VCC=Min., IOH=−32 mA 2.0 3.0
VOL Output LOW Voltage VCC=Min., IOL=64 mA 0.2 0.55 V
Output D rive Characteristics for CY74FCT162841T
Parameter Description Test Conditions Min. Typ.[5] Max. Unit
IODL Output LOW Current[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA
IODH Output HIGH Current[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V −60 −115 −150 mA
VOH Output HIGH Voltage VCC=Min., IOH=−24 mA 2.4 3.3 V
VOL Output LOW Voltage VCC=Min., IOL=24 mA 0.3 0.55 V
Capacitance[6] (TA =+25°C, f = 1.0 MHz)
Symbol Description Conditions Typ.[5] Max. Unit
CIN Input Capacit ance VIN = 0 V 4.5 6.0 pF
COUT Output Capacitance VOUT = 0V 5.5 8.0 pF
Pow er Supply Characteristics
Parameter Description Test Conditions Min. Typ.[5] Max. Unit
ICC Quiesce nt Pow e r Supply
Current VCC=Max. VIN<0.2V
VIN>VCC-0.2V — 5 500 µA
∆ICC Quiesce nt Pow e r Supply
Current (TTL i nputs HIGH) VCC=Max., VIN=3.4V[9] —0.5 1.5 mA
ICCD Dynamic Pow er Supply
Current[10] VCC=Max., One Input
Toggling, 50% Duty
Cycle, Outputs Open,
OE=GND
VIN=VCC or
VIN=GND —60 100 µA/MHz
ICTotal Power Supply Current[11] VCC=Max., f1=10 MHz,
50% Duty Cycle,
Outputs Open, One Bit
Toggling, OE=GND
LE = VCC
VIN=VCC or
VIN=GND —0.6 1.5 mA
VIN=3.4V or
VIN=GND —0.9 2.3
VCC=Max., f1=2.5 MHz,
50% Duty Cycle, Outputs
Open, Twenty Bits
Toggling, OE=GND
LE = VCC
VIN=VCC or
VIN=GND —3.0 5.5[12]
VIN=3.4V or
VIN=GND —8.0 20.5[12]
Notes:
9. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
10. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
11. IC=I
QUIESCENT + IINP UTS + IDYNAMIC
IC=I
CC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH= Duty Cycle for TTL inputs HIGH
NT= Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
12. Values for these conditions are examples of the ICC f ormula. These limits are guaranteed but not tested.
CY74FCT16841T
CY74FCT162841T
4
Swi tch i ng C h ara cter i sti cs Over the Operating Range[13]
74FCT16841AT
74FCT162841AT 74FCT16841BT
74FCT162841BT 74FCT16841CT
74FCT162841CT Fig.
No.[15]
Parameter Description Condition[14] Min. Max. Min. Max. Min. Max. Unit
tPLH
tPHL Propagati on Delay
D to Q
(LE=HIGH)
CL=50 pF
RL=500Ω1.5 9.0 1.5 6.5 1.5 5.5 ns 1, 5
CL=300 pF[16]
RL=500Ω1.5 13.0 1.5 13.0 1.5 13.0
tPLH
tPHL Propagati on Delay
LE to Q CL=50 pF
RL=500Ω1.5 12.0 1.5 8.0 1.5 6.4 ns 1, 5
CL=300 pF[16]
RL=500Ω1.5 16.0 1.5 15.5 1.5 15.0
tPHZ
tPZL Output Enable Time
OE to Q CL=50 pF
RL=500Ω1.5 11.5 1.5 8.0 1.5 6.5 ns 1, 7, 8
CL=300 pF[16]
RL=500Ω1.5 23.0 1.5 14.0 1.5 12.0
tPHZ
tPLZ Output Disable Time
OE to Q CL=5 pF[16]
RL=500Ω1.5 7.0 1.5 6.0 1.5 5.7 ns 1, 7, 8
CL=50 pF
RL=500Ω1.5 8.0 1.5 7.0 1.5 6.0
tSU Set-Up Time
HIGH or LOW,
D to LE
CL=50 pF
RL=500Ω2.5 —2.5 —2.0 —ns 9
tHHold Ti me
HIGH or LOW,
D to LE
2.5 —2.5 —1.5 —ns 9
tWLE Pulse Width HI GH 4.0[17] —4.0[17] —4.0[17] —ns 5
tSK(O) Output Skew[18] —0.5 —0.5 —0.5 ns —
Notes:
13. Minimum limits are guaranteed but not tested on Propagation Delays.
14. See test circuit and waveform.
15. See “P arameter Measurement Information” in the General Information section.
16. These conditions are guaranteed but not tested.
17. These limits are guaranteed but not tested.
18. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
CY74FCT16841T
CY74FCT162841T
5
Document #: 38−00387-B
Or dering Information for CY74FCT16841T
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
5.5 CY74FCT16841CTPAC Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT16841CTPVC O56 56-Lead (300-Mil) SSOP
6.5 CY74FCT16841ATPAC Z56 56-Lead (240-Mil ) TSSOP Industrial
CY74FCT16841ATPVC O56 56-L ead (300-Mil ) SSOP
9.0 CY74FCT16841TPAC Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT16841TPVC O56 56-Lead (300-Mi l) SSOP
Ordering Information CY74FCT162841T
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
5.5 CY74FCT162841CTPAC Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT162841CTPVC O56 56-Lead (300-Mi l) SSOP
6.5 CY74FCT162841ATPAC Z56 56-Lead (240-Mil ) TSSOP Industrial
CY74FCT162841ATPVC O56 56-L ead (300-Mil ) SSOP
9.0 CY74FCT162841TPAC Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT162841TPVC O56 56-Lead (300-Mi l) SSOP
CY74FCT16841T
CY74FCT162841T
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circui try other than circuitry embodied in a Cypress Semiconduc tor produc t. Nor does it conv ey or imply any license under patent or other rights. C ypress Semicond uctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Di ag ra ms
56-LeadShrunk Small Outline PackageO56
56-LeadThinShrunkSmall Outline Package Z56
