High Voltage Latch-Up Proof,
Single SPDT Switch
Data Sheet ADG5419
Rev. A Document Feedback
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FEATURES
Latch-up immune under all circumstances
Human body model (HBM) ESD rating: 8 kV
Low on resistance: 13.5 Ω
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VDD to VSS analog signal range
APPLICATIONS
High voltage signal routing
Automatic test equipment
Analog front-end circuits
Precision data acquisition
Industrial instrumentation
Amplifier gain select
Relay replacement
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. 8-Lead LFCSP
Figure 2. 8-Lead MSOP
GENERAL DESCRIPTION
The ADG5419 is a monolithic industrial, complementary metal
oxide semiconductor (CMOS) analog switch containing a latch-
up immune single-pole/double-throw (SPDT) switch.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked. The ADG5419 exhibits break-before-make
switching action for use in multiplexer applications.
The ultralow on resistance and on-resistance flatness of these
switches make them ideal solutions for data acquisition and gain
switching applications where low distortion is critical. The
latch-up immune construction and high ESD rating make these
switches more robust in harsh environments.
PRODUCT HIGHLIGHTS
1. Trench isolation guards against latch-up. A dielectric trench
separates the P channel and N channel transistors, thereby
preventing latch-up even under severe overvoltage
conditions.
2. Low RON of 13.5 Ω.
3. Dual-supply operation. For applications where the analog
signal is bipolar, the ADG5419 can be operated from dual
supplies up to ±22 V.
4. Single-supply operation. For applications where the analog
signal is unipolar, the ADG5419 can be operated from a
single-rail power supply up to 40 V.
5. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
6. No VL logic power supply required.
7. Available in 8-lead MSOP and 8-lead, 2 mm × 3 mm
LFCSP packages.
11370-001
SA
SB
ADG5419
EN
DECODER
D
SWITCHES SHOWN FOR A LOGIC 0 INPUT.
IN
SA
SB
ADG5419
SWITCHES SHOWN FOR A LOGIC 0 INPUT.
IN
D
11370-101
ADG5419 Data Sheet
Rev. A | Page 2 of 19
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block DiagramS ............................................................ 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±15 V Dual Supply ....................................................................... 3
±20 V Dual Supply ....................................................................... 4
12 V Single Supply ........................................................................ 5
36 V Single Supply ........................................................................ 6
Continuous Current per Channel, Sx or D ................................7
Absolute Maximum Ratings ............................................................8
ESD Caution...................................................................................8
Pin Configurations and Function Descriptions ............................9
Typical Performance Characteristics ........................................... 10
Test Circuits ..................................................................................... 14
Terminology .................................................................................... 17
Applications Information .............................................................. 18
Trench Isolation .......................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
3/15—Rev. 0 to Rev. A
Added 8-Lead LFCSP ......................................................... Universal
Added Figure 1; Renumbered Sequentially .................................. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Changes to Table 4 ............................................................................ 6
Changed Continuous Current, Sx or D to 8-Lead MSOP,
Table 5 ................................................................................................ 7
Added Figure 3 and Table 8; Renumbered Sequentially ............. 9
Changes to Table 7 ............................................................................ 9
Changes to Figure 5 ........................................................................ 10
Added Figure 23 ............................................................................. 13
Changes to Figure 24 Caption ...................................................... 14
Added Figure 25 and Figure 26 .................................................... 14
Deleted Figure 27; Renumbered Sequentially ............................ 14
Added Figure 32 and Figure 33 .................................................... 15
Changes to Terminology Section ................................................. 17
Added Figure 37, Outline Dimensions ........................................ 19
Changes to Ordering Guide .......................................................... 19
9/13—Revision 0: Initial Version
Data Sheet ADG5419
Rev. A | Page 3 of 19
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance, RON 13.5 Ω typ VS = ±10 V, IS = −10 mA; see Figure 27
15 19 23 Ω max VDD = +13.5 V, VSS = −13.5 V
On-Resistance Match Between Channels,
∆RON
0.1 Ω typ VS = ±10 V, IS = −10 mA
0.8 1.3 1.4 Ω max
On-Resistance Flatness, RFLAT (ON) 1.8 Ω typ VS = ±10 V, IS = −10 mA
2.2 2.7 3.1 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off) ±0.1 nA typ VS = ±10 V, VD = 10 V; see Figure 24 and
Figure 25
±0.25 ±1 ±10 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ VS = ±10 V, VD = 10 V; see Figure 25
±0.4 ±4 ±10 nA max
Channel On Leakage, ID (On), IS (On) ±0.1 nA typ VS = VD = ±10 V; see Figure 24 and
Figure 26
±0.4 ±4 ±10 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.002 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 6 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 217 ns typ RL = 300 Ω, CL = 35 pF
260 310 336 ns max VS = 10 V; see Figure 32
tON (EN) 179 ns typ RL = 300 Ω, CL = 35 pF
212 261 298 ns max VS = 10 V; see Figure 33
tOFF (EN) 153 ns typ RL = 300 Ω, CL = 35 pF
176 195 209 ns max VS = 10 V; see Figure 33
Break-Before-Make Time Delay, tD 86 ns typ RL = 300 Ω, CL = 35 pF
45 ns min VS = 10 V; see Figure 34
Charge Injection, QINJ 130 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 35
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29
Channel-to-Channel Crosstalk −80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
Total Harmonic Distortion + Noise 0.01 % typ RL = 1 kΩ, 15 V p-p, f = 20 Hz to 20 kHz; see
Figure 30
−3 dB Bandwidth 190 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 31
Insertion Loss −0.8 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31
CS (Off) 12 pF typ VS = 0 V, f = 1 MHz
CD (Off) 23 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 55 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 45 μA typ Digital inputs = 0 V or VDD
55 70 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
VDD/VSS ±9/±22 V min/V max GND = 0 V
1 Guaranteed by design; not subject to production test.
ADG5419 Data Sheet
Rev. A | Page 4 of 19
±20 V DUAL SUPPLY
VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance, RON 12.5 Ω typ VS = ±15 V, IS = −10 mA; see Figure 27
14 18 22 Ω max VDD = +18 V, VSS = −18 V
On-Resistance Match Between Channels,
∆RON
0.1 Ω typ VS = ±15 V, IS = −10 mA
0.8 1.3 1.4 Ω max
On-Resistance Flatness, RFLAT (ON) 2.3 Ω typ VS = ±15 V, IS = −10 mA
2.7 3.3 3.7 Ω max
LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V
Source Off Leakage, IS (Off) ±0.1 nA typ VS = ±15 V, VD = 15 V; see Figure 24 and
Figure 25
±0.25 ±1 ±10 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ VS = ±15 V, VD = 15 V; see Figure 25
±0.4 ±4 ±10 nA max
Channel On Leakage, ID (On), IS (On) ±0.1 nA typ VS = VD = ±15 V; see Figure 24 and
Figure 26
±0.4 ±4 ±10 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.002 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 6 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 200 ns typ RL = 300 Ω, CL = 35 pF
235 279 294 ns max VS = 10 V; see Figure 32
tON (EN) 199 ns typ RL = 300 Ω, CL = 35 pF
239 300 344 ns max VS = 10 V; see Figure 33
tOFF (EN) 157 ns typ RL = 300 Ω, CL = 35 pF
185 208 227 ns max VS = 10 V; see Figure 33
Break-Before-Make Time Delay, tD 77 ns typ RL = 300 Ω, CL = 35 pF
46 ns min VS = 10 V; see Figure 34
Charge Injection, QINJ 160 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 35
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29
Channel-to-Channel Crosstalk −80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
Total Harmonic Distortion + Noise 0.01 % typ RL = 1 kΩ, 20 V p-p, f = 20 Hz to 20 kHz; see
Figure 30
−3 dB Bandwidth 190 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 31
Insertion Loss −0.7 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31
CS (Off) 11 pF typ VS = 0 V, f = 1 MHz
CD (Off) 22 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 55 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +22 V, VSS = −22 V
IDD 50 μA typ Digital inputs = 0 V or VDD
70 110 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
VDD/VSS ±9/±22 V min/V max GND = 0 V
1 Guaranteed by design; not subject to production test.
Data Sheet ADG5419
Rev. A | Page 5 of 19
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance, RON 26 Ω typ VS = 0 V to 10 V, IS = −10 mA; see
Figure 27
30 38 44 Ω max VDD = 10.8 V, VSS = 0 V
On-Resistance Match Between Channels,
∆RON
0.1 Ω typ VS = 0 V to 10 V, IS = −10 mA
1 1.5 1.6 Ω max
On-Resistance Flatness, RFLAT (ON) 5.5 Ω typ VS = 0 V to 10 V, IS = −10 mA
6.8 8.3 12.3 Ω max
LEAKAGE CURRENTS VDD = +13.2 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.1 nA typ VS = 1 V to 10 V, VD = 10 V to 1 V;
see Figure 24 and Figure 25
±0.25 ±1 ±10 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ VS = 1V to10 V, VD = 10 V to 1V; see Figure 25
±0.4 ±4 ±10 nA max
Channel On Leakage, ID (On), IS (On) ±0.1 nA typ VS = VD = 1 V to 10 V; see Figure 24 and
Figure 26
±0.4 ±4 ±10 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.002 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 6 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 333 ns typ RL = 300 Ω, CL = 35 pF
414 508 567 ns max VS = 8 V; see Figure 32
tON (EN) 327 ns typ RL = 300 Ω, CL = 35 pF
410 526 612 ns max VS = 8 V; see Figure 33
tOFF (EN) 166 ns typ RL = 300 Ω, CL = 35 pF
200 528 611 ns max VS = 8 V; see Figure 33
Break-Before-Make Time Delay, tD 176 ns typ RL = 300 Ω, CL = 35 pF
97 ns min VS = 8 V; see Figure 34
Charge Injection, QINJ 55 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 35
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 29
Channel-to-Channel Crosstalk −80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 28
Total Harmonic Distortion + Noise 0.03 % typ RL = 1 kΩ, 6 V p-p, f = 20 Hz to 20 kHz; see
Figure 30
−3 dB Bandwidth 170 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 31
Insertion Loss −1.7 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 31
CS (Off) 15 pF typ VS = 6 V, f = 1 MHz
CD (Off) 29 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 50 pF typ VS = 6 V, f = 1 MHz
POWER REQUIREMENTS VDD = 13.2 V
IDD 40 μA typ Digital inputs = 0 V or VDD
50 65 μA max
VDD 9/40 V min/V max GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
ADG5419 Data Sheet
Rev. A | Page 6 of 19
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance, RON 14.5 Ω typ VS = 0 V to 30 V, IS = −10 mA; see
Figure 27
16 20 24 Ω max VDD = 32.4 V, VSS = 0 V
On-Resistance Match Between Channels,
∆RON
0.1 Ω typ VS = 0 V to 30 V, IS = −10 mA
0.8 1.3 1.4 Ω max
On-Resistance Flatness, RFLAT (ON) 3.5 Ω typ VS = 0 V to 30 V, IS = −10 mA
4.3 5.5 6.5 Ω max
LEAKAGE CURRENTS VDD = 39.6 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.1 nA typ VS = 1 V to 30 V, VD = 30 V to 1 V; see Figure 24
and Figure 25
±0.25 ±1 ±10 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ VS = 1V to 30 V, VD = 30 V to 1V; see Figure 25
±0.4 ±4 ±10 nA max
Channel On Leakage, ID (On), IS (On) ±0.1 nA typ VS = VD = 1 V to 30 V;
see Figure 24 and Figure 26
±0.4 ±4 ±10 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.002 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 6 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 216 ns typ RL = 300 Ω, CL = 35 pF
250 286 310 ns max VS = 18 V; see Figure 32
tON (EN) 199 ns typ RL = 300 Ω, CL = 35 pF
232 279 315 ns max VS = 18 V; see Figure 33
tOFF (EN) 160 ns typ RL = 300 Ω, CL = 35 pF
193 284 315 ns max VS = 18 V; see Figure 33
Break-Before-Make Time Delay, tD 80 ns typ RL = 300 Ω, CL = 35 pF
47 ns min VS = 18 V; see Figure 34
Charge Injection, QINJ 135 pC typ VS = 18 V, RS = 0 Ω, CL = 1 nF; see
Figure 35
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 29
Channel-to-Channel Crosstalk −80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 28
Total Harmonic Distortion + Noise 0.01 % typ RL = 1 kΩ, 18 V p-p, f = 20 Hz to 20 kHz; see
Figure 30
−3 dB Bandwidth 170 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 31
Insertion Loss −1 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
CS (Off) 14 pF typ VS = 18 V, f = 1 MHz
CD (Off) 26 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 50 pF typ VS = 18 V, f = 1 MHz
POWER REQUIREMENTS VDD = 39.6 V
IDD 80 μA typ Digital inputs = 0 V or VDD
100 130 μA max
VDD 9/40 V min/V max GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
Data Sheet ADG5419
Rev. A | Page 7 of 19
CONTINUOUS CURRENT PER CHANNEL, Sx OR D
Table 5.
Parameter 25°C 85°C 125°C Unit Test Conditions/Comments
8-LEAD MSOP θ
JA = 133.1°C/W
VDD = 15 V, VSS = −15 V 113 73 46 mA maximum
VDD = 20 V, VSS = −20 V 118 76 47 mA maximum
VDD = 12 V, VSS = 0 V 90 60 41 mA maximum
VDD = 36 V, VSS = 0 V 116 74 46 mA maximum
8-LEAD LFCSP θJA = 60.88°C/W
VDD = 15 V, VSS = −15 V 156 92 52 mA maximum
VDD = 20 V, VSS = −20 V 163 95 53 mA maximum
VDD = 12 V, VSS = 0 V 126 78 48 mA maximum
VDD = 36 V, VSS = 0 V 160 93 53 mA maximum
ADG5419 Data Sheet
Rev. A | Page 8 of 19
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND +0.3 V to −48 V
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or 30
mA, whichever occurs first
Digital Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Peak Current, Sx or D Pins 410 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Continuous Current, Sx or D2 Data + 15%
Temperature Range
Operating −40°C to +125°C
Storage −65°C to +150°C
Junction Temperature 150°C
Thermal Impedance, θJA
8-Lead MSOP (4-Layer Board) 133.1°C/W
8-Lead LFCSP 60.88°C/W
Reflow Soldering Peak
Temperature, Pb Free
As per JEDEC J-STD-020
Human Body Model (HBM) ESD 8 kV
1 Overvoltages at the IN, Sx, and D pins are clamped by internal diodes. Limit
current to the maximum ratings given.
2 See Table 5.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Data Sheet ADG5419
Rev. A | Page 9 of 19
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. 8-Lead LFCSP Pin Configuration Figure 4. 8-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic Description
LFCSP MSOP
1 1 D Drain Terminal. This pin can be an input or output.
2 2 SA Source Terminal. This pin can be an input or an output.
3 3 GND Ground (0 V) Reference.
4 4 VDD Most Positive Power Supply Potential.
5 EN Active High Digital Input. When this pin is low, the device is disabled
and all switches are turned off. When this pin is high, the IN logic input
determines the state of the switch.
6 6 IN Logic Control Input.
7 7 VSS Most Negative Power Supply Potential.
8 8 SB Source Terminal. This pin can be an input or an output.
5 NC No Connect. Not internally connected.
Not applicable EPAD Exposed Pad. Exposed pad tied to substrate, VSS.
Table 8. LFCSP Truth Table
EN IN Switch A Switch B
0 X1 Off Off
1 0 On Off
1 1 Off On
1 X = don’t care.
Table 9. MSOP Truth Table
IN Switch A Switch B
0 On Off
1 Off On
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, V
SS
.
TOP VIEW
(Not to Scale)
ADG5419
3GND
4V
DD
1D
2SA
6IN
5EN
8SB
7V
SS
11370-103
D1
SA 2
GND 3
VDD 4
SB8
VSS
7
IN
6
NC
5
NOTES
1. NC = NO CONNECT. NOT INTERNALLY CONNECTED.
ADG5419
TOP VIEW
(Not to Scale)
11370-002
ADG5419 Data Sheet
Rev. A | Page 10 of 19
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. On Resistance as a Function of VS, VD Dual Supply
Figure 6. On Resistance as a Function of VS, VD Dual Supply)
Figure 7. On Resistance as a Function of VS, VD (Single Supply)
Figure 8. On Resistance as a Function of VS, VD (Single Supply)
Figure 9. On Resistance as a Function of VS (VD) for Different Temperatures,
±15 V Dual Supply
Figure 10. On Resistance as a Function of VS (VD) for Different Temperatures,
±20 V Dual Supply
0
5
10
15
20
25
–18 –14 –10 –6 –2 2 6 10 14 18
–16 –12 –8 –4 0 4 8 12 16
ON RESISTANCE (Ω)
VS, VD (V)
TA = 25°C
VDD = +9V
VSS = –9V
VDD = +10V
VSS = –10V
VDD = +11V
VSS = –11V
VDD = +13.5V
VSS = –13.5V VDD = +15V
VSS = –15V
VDD = +16.5V
VSS = –16.5V
11370-003
0
2
4
6
8
10
12
14
16
–25 –20 –15 –10 –5 0 5 10 15 20 25
ON RESISTANCE (Ω)
VS, VD (V)
TA = 25°C
VDD = +22V
VSS = –22V
VDD = +20V
VSS = –20V
VDD = +18V
VSS = –18V
11370-004
0
5
10
15
20
25
30
35
02468101214
ON RESISTANCE (Ω)
VS, VD (V)
TA = 25°C
VDD = 9V
VSS = 0V
VDD = 10V
VSS = 0V VDD = 10.8V
VSS = 0V
VDD =11V
VSS = 0V
VDD = 12V
VSS = 0V
VDD = 13.2V
VSS = 0V
11370-005
0
2
4
6
8
10
12
14
16
0 5 10 15 20 25 30 35 40 45
ON RESISTANCE (Ω)
V
S
, V
D
(V)
T
A
= 25°C
V
DD
= 39.6V
V
SS
= 0V
V
DD
= 36V
V
SS
= 0V
V
DD
= 32.4V
V
SS
= 0V
11370-006
0
5
10
15
20
25
–15 –10 –5 0 5 10 15
ON RESISTANCE (Ω)
V
S
, V
D
(V)
V
DD
= +15V
V
SS
= –15V
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
11370-007
0
5
10
15
20
25
–20 –15 –10 –5 0 5 10 15 20
ON RESISTANCE (Ω)
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40°C
VS, VD (V)
VDD = +20V
VSS = –20V
11370-008
Data Sheet ADG5419
Rev. A | Page 11 of 19
Figure 11. On Resistance as a Function of VS (VD) for Different Temperatures,
12 V Single Supply
Figure 12. On Resistance as a Function of VS (VD) for Different Temperatures,
36 V Single Supply
Figure 13. Leakage Currents as a Function of Temperature, ±15 V Dual Supply
Figure 14. Leakage Currents as a Function of Temperature,
±20 V Dual Supply
Figure 15. Leakage Currents as a Function of Temperature,
12 V Single Supply
Figure 16. Leakage Currents as a Function of Temperature,
36 V Single Supply
0
5
10
15
20
25
30
35
40
024681012
VS, VD (V)
ON RESISTANCE ()
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40°C
VDD = 12V
VSS = 0V
11370-009
0
5
10
15
20
25
0 5 10 15 20 25 30 35 40
ON RESISTANCE ()
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40°C
VS, VD (V)
VDD = 36V
VSS = 0V
11370-010
0 255075100125
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
0.6
0.4
–0.2
0
–0.4
0.2
V
DD
= +15V
V
SS
= –15V
V
BIAS
= +10V/–10V
I
D
, I
S
(ON) + +
I
D
, I
S
(ON) – –
I
S
(OFF) + –
I
D
(OFF) – +
I
D
(OFF) + –
I
S
(OFF) – +
11370-011
0 255075100125
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
0.4
0.2
–0.2
0
–0.4
–0.6
V
DD
= +20V
V
SS
= –20V
V
BIAS
= +15V/–15V I
D
, I
S
(ON) + +
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
, I
S
(ON) – –
I
D
(OFF) – +
11370-012
0 25 50 75 100 125
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
0.4
0.3
–0.2
0
–0.1
0.2
0.1
V
DD
= 12V
V
SS
= 0V
V
BIAS
= 1V/10V
I
D
, I
S
(ON) + +
I
D
, I
S
(ON) – –
I
S
(OFF) + –
I
D
(OFF) – +
I
D
(OFF) + –
I
S
(OFF) – +
11370-013
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
0 255075100125
0.4
0.2
–0.2
0
–0.4
–0.6
V
DD
= 36V
V
SS
= 0V
V
BIAS
= 1V/30V I
D
, I
S
(ON) + +
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
, I
S
(ON) – –
I
D
(OFF) – +
11370-014
ADG5419 Data Sheet
Rev. A | Page 12 of 19
Figure 17. Off Isolation vs. Frequency
Figure 18. Crosstalk vs. Frequency
Figure 19. Charge Injection vs. Source Voltage
Figure 20. THD + N vs. Frequency
Figure 21. Bandwidth
Figure 22. tTRANSITION Times vs. Temperature
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1k 10k 100k 1M 10M 100M 1G
OFF ISOLATION (dB)
FREQUENCY (Hz)
11370-015
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
–120
–100
–80
–60
–40
–20
0
10k 100k 1M 10M 100M 1G
CROSSTALK (dB)
FREQUENCY (Hz)
11370-016
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
0
50
100
150
200
250
300
–20 –10 0 10 20 30 40
CHARGE INJECTION (pC)
V
S
(V)
V
DD
=15V,V
SS
= –15V
V
DD
=20V,V
SS
= –20V
V
DD
=12V,V
SS
=0V
V
DD
=36V,V
SS
=0V
11370-017
0
0.01
0.02
0.03
0.04
0.05
0 5 10 15 20
THD + N (%)
FREQUENCY (kHz)
V
DD
=12V,V
SS
=0V,V
S
=6V p-p
V
DD
=36V,V
SS
=0V,V
S
=18V p-p
V
DD
=15V,V
SS
=–15V,V
S
=15V p-p
V
DD
=20V,V
SS
=–20V,V
S
=20V p-p
11370-018
T
A
= 25°C
R
L
= 1k
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
1k 10k 100k 1M 10M 100M 1G
INSERTION LOSS (dB)
FREQUENCY (Hz)
11370-019
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
0
50
100
150
200
250
300
350
400
450
500
–40 –20 0 20 40 60 80 100 120
TIME (ns)
TEMPERATURE (°C)
V
DD
=12V,V
SS
=0V
V
DD
=36V,V
SS
=0V
V
DD
=15V,V
SS
= –15V
V
DD
=20V,V
SS
= –20V
11370-020
Data Sheet ADG5419
Rev. A | Page 13 of 19
Figure 23. ACPSRR vs. Frequency
–120
–100
–80
–60
–40
–20
0
1k 10k 100k 1M 10M
ACPSRR (dB)
FREQUENCY (Hz)
DECOUPLING
CAPACITORS
NO DECOUPLING
CAPACITORS
TA = 25°C
VDD = +15V
VSS = –15V
11370-123
ADG5419 Data Sheet
Rev. A | Page 14 of 19
TEST CIRCUITS
Figure 24. Channel On and Source Off Leakage (MSOP Only)
Figure 25. Off Leakage (LFCSP Only)
Figure 26. On Leakage (LFCSP Only)
Figure 27. On Resistance
Figure 28. Channel-to-Channel Crosstalk
Figure 29. Off Isolation
11370-021
SA
D
V
NC
S
V
D
I
S
(OFF)
SB
I
D
(ON)
A
A
11370-121
SA
D
V
S
V
D
SB
I
D
(OFF)
A
I
S
(OFF)
A
A
SA
D
V
S
A
VD
ID (ON)
SB
NC
11370-122
11370-022
I
DS
Sx D
V
S
V
R
ON
= V/I
DS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log VOUT
GND
SA
D
SB
VOUT
NETWORK
ANALYZER
RL
50
R
50
VS
VS
VDD VSS
0.1µF
V
DD
0.1µF
V
SS
IN
11370-023
VOUT
50
NETWORK
ANALYZER
RL
50
IN
V
IN
SA
D
VS
VDD VSS
0.1µF
V
DD
0.1µF
V
SS
GND
50
NC
SB
OFF ISOLATION = 20 log VOUT
VS
11370-024
Data Sheet ADG5419
Rev. A | Page 15 of 19
Figure 30. THD + Noise Figure 31. Bandwidth
Figure 32. Transition Time, tTRANSITION
Figure 33. Enable Delay, tON (EN), tOFF (EN) (LFCSP Only)
V
OUT
R
S
AUDIO PRECISION
R
L
1k
IN
V
IN
Sx
D
V
S
V p-p
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
11370-025
V
OUT
50
NETWORK
ANALYZER
R
L
50
IN
V
IN
SA
D
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
50
NC
SB
INSERTION LOSS = 20 log V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
11370-026
11370-127
IN
V
OUT
D
SB*
V
DD
V
SS
V
DD
V
SS
GND
C
L
35pF
SA*
V
IN
V
S
0.1µF0.1µF
R
L
300
50%
50%
0.1V
S
50%
50%
0.9V
S
t
TRANSITION
t
TRANSITION
0V
V
S
V
OUT
V(SB = V
S
)
IN
V(SA = V
S
)
IN
*ALTERNATIVELY, SB CAN BE CONNECTED TO V
S
WITH SA CONNECTED TO GROUND.
V
OUT
ADG5419
IN
50300
GND
SA
SB
D
35pF
V
EN
EN
V
DD
V
SS
V
DD
V
SS
V
S
3V
0V
OUTPUT
(V
OUT
)
50% 50%
t
OFF
(EN)
t
ON
(EN)
0.9V
S
0.1V
S
V
S
0V
ENABLE
DRIVE
(V
EN
)
11370-132
ADG5419 Data Sheet
Rev. A | Page 16 of 19
Figure 34. Break-Before-Make Delay, tD
Figure 35. Charge Injection
IN
V
OUT
D
SA
V
DD
V
SS
V
DD
V
SS
GND
C
L
35pF
SB
V
IN
V
S
0.1µF0.1µF
R
L
300
80%
tDtD
V
OUT
V
IN
11370-028
V
IN
(NORMALLY
CLOSED SWITCH)
V
OUT
V
IN
(NORMALLY
OPEN SWITCH)
OFF
V
OUT
ON
Q
INJ
=C
L
×V
OUT
IN
V
OUT
NC
SA
V
DD
V
SS
V
DD
V
SS
GND
C
L
1nF
D
V
IN
V
S
0.1µF0.1µF
SB
11370-029
Data Sheet ADG5419
Rev. A | Page 17 of 19
TERMINOLOGY
IDD
IDD represents the positive supply current.
ISS
ISS represents the negative supply current.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal S, respec tively.
RON
RON is the ohmic resistance between Terminal D and
Terminal S.
ΔRON
ΔRON represents the difference between the RON of any two
channels.
RFLAT (ON)
The difference between the maximum and minimum value of
on resistance as measured over the specified analog signal range
is represented by RFLAT (ON).
IS (Off)
IS (Off) is the source leakage current with the switch off.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
CIN
CIN represents digital input capacitance.
tON (EN)
tON represents the delay time between the 50% and 90% points
of the digital input and switch on condition. See Figure 33.
tOFF (EN)
tOFF represents the delay time between the 50% and 90% points
of the digital input and switch off condition. See Figure 33.
tTRANSITION
tTRANSITION represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
tD
tD represents the off time measured between the 80% point of
both switches when switching from one address state to another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off channel.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated by
3 dB, from its dc level.
Total Harmonic Distortion + Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR measures the ability of a device to avoid coupling
noise and spurious signals that appear on the supply voltage pin
to the output of the switch. The dc voltage on the device is
modulated by a sine wave of 0.62 V p-p. The ratio of the
amplitude of signal on the output to the amplitude of the
modulation is the ACPSRR. See Figure 23.
ADG5419 Data Sheet
Rev. A | Page 18 of 19
APPLICATIONS INFORMATION
The ADG54xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, aerospace, and
other harsh environments that are prone to latch-up, which is an
undesirable high current state that can lead to device failure and
persists until the power supply is turned off. The ADG5419
high voltage switch allows single-supply operation from 9 V
to 40 V and dual-supply operation from ±9 V to ±22 V. The
ADG5419 (as well as other select devices within this family)
achieves an 8 kV human body model ESD rating, which provides
a robust solution, eliminating the need for separate protection
circuitry designs in some applications.
TRENCH ISOLATION
In the ADG5419, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction-isolated switches, are eliminated, and the result is a
completely latch-up immune switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. The two transistors form a
silicon-controlled rectifier (SCR) type circuit, causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up immune switch.
Figure 36. Trench Isolation
11370-030
NMOS PMOS
P-WELL N-WELL
BURIED OXIDE LAYER
HANDLE WAFER
TRENCH
Data Sheet ADG5419
Rev. A | Page 19 of 19
OUTLINE DIMENSIONS
Figure 37. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
2 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-4)
Dimensions shown in millimeters
Figure 38. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
ADG5419BCPZ-RL7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-8-4 BL
ADG5419BRMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 S48
ADG5419BRMZ-RL7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 S48
1 Z = RoHS Compliant Part.
0
81806-
A
COPLANARITY
0.08
0.50
0.40
0.30
0.20 MI N
0.05 MAX
0.02 NOM
0.15 REF
0.50
PIN 1
INDICATOR
EXPOSED
PAD
BOT TOM V IEW
TOP VIEW
0.30
0.25
0.20
0.80
0.75
0.70
SEATING
PLANE
3.00 BSC
SIDE VIEW
14
85
2.00 BS C
INDEX
AREA
1.90
1.80
1.65
1.75
1.65
1.50
FOR PR OPER CONNEC TI ON OF
THE EXPOSED PAD, REFER TO
THE P I N CONF I GURAT IO N AND
FUN CTI ON DE S CRIP TI ONS
SECTION OF T HIS DATA SHEET.
COM P LI ANT TO JED E C S T ANDA RDS MO-1 87- AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
©2013–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11370-0-3/15(A)
