PCA9549D,112 - NXP Semiconductors / Philips Semiconductors

1. General description

The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlled

by the I2C-bus. The low ON-state resistance of the switch allows connections to be made

with minimal propagation delay. Any individual A to B channel or combination of channels

can be selected via the I2C-bus, determined by the contents of the programmable Control

Port A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,

creating a high-impedance state between the two ports, which stops the data ﬂow.

An active LOW reset input (RESET) allows the PCA9549 to recover from a situation

where the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-bus

state machine and causes all the bits to be open, as does the internal power-on reset

function.

Three address pins allow up to eight devices on the same bus.

2. Features

n8-bit bus switch (CBT)

n5Ω switch connection between two ports

nI2C-bus interface logic; compatible with SMBus standards

nActive LOW RESET input

n3 address pins allowing up to 8 devices on the I2C-bus

nBit selection via I2C-bus, in any combination

nPower-up with all bits deselected

nLow Ron switches

nNo glitch on power-up

nSupports hot insertion

nLow standby current

nOperating power supply voltage range of 2.3 V to 5.5 V

n5 V tolerant inputs

n0 Hz to 400 kHz clock frequency

nESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115 and 1000 V CDM per JESD22-C101

nLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

nPackages offered: SO24, TSSOP24, HVQFN24

PCA9549

Octal bus switch with individually I2C-bus controlled enables

Rev. 02 — 13 July 2009 Product data sheet

Product data sheet Rev. 02 — 13 July 2009 2 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

3. Ordering information

3.1 Ordering options

4. Block diagram

Table 1. Ordering information

Type number Package

Name Description Version

PCA9549D SO24 plastic small outline package; 24 leads;

body width 7.5 mm SOT137-1

PCA9549PW TSSOP24 plastic thin shrink small outline package; 24 leads;

body width 4.4 mm SOT355-1

PCA9549BS HVQFN24 plastic thermal enhanced very thin quad ﬂat package;

no leads; 24 terminals; body 4 ×4×0.85 mm SOT616-1

Table 2. Ordering options

Type number Topside mark Temperature range

PCA9549D PCA9549D −40 °C to +85 °C

PCA9549PW PCA9549 −40 °C to +85 °C

PCA9549BS 9549 −40 °C to +85 °C

Fig 1. Block diagram

SWITCH CONTROL LOGIC

PCA9549

RESET

CIRCUIT

002aaa991

VSS

VDD

RESET

I2C-BUS

CONTROL

INPUT

FILTER

SCL

SDA

Product data sheet Rev. 02 — 13 July 2009 3 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

5. Pinning information

5.1 Pinning

Fig 2. Pin conﬁguration of SO24 Fig 3. Pin conﬁguration of TSSOP24

Fig 4. Pin conﬁguration of HVQFN24 (transparent top view)

PCA9549D

A0 VDD

A1 SDA

RESET SCL

1A A2

1B 8A

2A 8B

2B 7A

3A 7B

3B 6A

4A 6B

4B 5A

VSS 5B

002aaa992

PCA9549PW

A0 VDD

A1 SDA

RESET SCL

1A A2

1B 8A

2A 8B

2B 7A

3A 7B

3B 6A

4A 6B

4B 5A

VSS 5B

002aaa993

002aaa994

PCA9549BS

Transparent top view

2B 7A

2A 8B

1B 8A

1A A2

VSS

RESET

VDD

SDA

SCL

terminal 1

index area

613

514

4 15

3 16

2 17

118

Product data sheet Rev. 02 — 13 July 2009 4 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

5.2 Pin description

[1] HVQFN24 package die supply ground is connected to both the VSS pin and the exposed center pad. The

VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,

and board-level performance, the exposed pad needs to be soldered to the board using a corresponding

thermal pad on the board, and for proper heat conduction through the board thermal vias need to be

incorporated in the PCB in the thermal pad region.

Table 3. Pin description

Symbol Pin Description

SO24, TSSOP24 HVQFN24

A0 1 22 address input 0

A1 2 23 address input 1

RESET 3 24 active LOW reset input

1A 4 1 input

1B 5 2 output

2A 6 3 input

2B 7 4 output

3A 8 5 input

3B 9 6 output

4A 10 7 input

4B 11 8 output

VSS 12 9[1] supply ground

5B 13 10 output

5A 14 11 input

6B 15 12 output

6A 16 13 input

7B 17 14 output

7A 18 15 input

8B 19 16 output

8A 20 17 input

A2 21 18 address input 2

SCL 22 19 serial clock line

SDA 23 20 serial data line

VDD 24 21 supply voltage

Product data sheet Rev. 02 — 13 July 2009 5 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

6. Functional description

6.1 Device addressing

Following a START condition, the bus master must output the address of the slave it is

accessing. The address of the PCA9549 is shown in Figure 5. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW.

The last bit of the slave address deﬁnes the operation to be performed. When set to

logic 1 a read is selected, while a logic 0 selects a write operation.

6.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9549, which will be stored in the Control register. If multiple bytes are

received by the PCA9549, it will save the last byte received. This register can be written

and read via the I2C-bus.

6.2.1 Control register deﬁnition

One or several bits are selected by the contents of the Control register. This register is

written after the PCA9549 has been addressed. The entire control byte is used to

determine which bit is to be selected. When a bit is selected to close, the bit will close

after the Acknowledge has been placed on the I2C-bus.

Fig 5. Slave address

002aaa962

1 1 1 0 A2 A1 A0 R/W

fixed hardware

selectable

Fig 6. Control register

002aab254

B7 B6 B5 B4 B3 B2 B1 B0

channel selection bits

(read/write)

76543210

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

Product data sheet Rev. 02 — 13 July 2009 6 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

[1] Several bits can be enabled at the same time. For example, B7 = 0, B6 = 1, B5 = 0, B4 = 0, B3 = 1, B2 = 1,

B1 = 0, B0 = 0, means that bit 8, bit 6, bit 5, bit 2, and bit 1 are disabled and bit 7, bit 4, and bit 3 are

enabled.

6.3 RESET input

The RESET input is an active LOW signal which may be used to recover from a bus fault

condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9549 will reset its

registers and I2C-bus state machine and will open all bits. The RESET input must be

connected to VDD through a pull-up resistor.

6.4 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9549 in

a reset state until VDD has reached VPOR. At this point, the reset condition is released and

the PCA9549 registers and I2C-bus state machine are initialized to their default states, all

zeroes causing all the bits to be open (high-impedance state).

6.5 CBT characteristic over VDD range

The bus switch is optimized at 5.0 V but can operate over the entire supply range with

lower Vo(sw) voltage and higher gate resistance.

Table 4. Control register

Write = channel selection; read = channel status.

B7 B6 B5 B4 B3 B2 B1 B0 Command

XXXXXXX0 bit 1 disabled

1 bit 1 enabled

XXXXXX0Xbit 2 disabled

1 bit 2 enabled

XXXXX0XX

bit 3 disabled

1 bit 3 enabled

XXXX0XXX

bit 4 disabled

1 bit 4 enabled

XXX0XXXX

bit 5 disabled

1 bit 5 enabled

XX0XXXXX

bit 6 disabled

1 bit 6 enabled

X0XXXXXX

bit 7 disabled

1 bit 7 enabled

0XXXXXXX

bit 8 disabled

1 bit 8 enabled

Product data sheet Rev. 02 — 13 July 2009 7 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

Figure 7 shows the voltage characteristics of the pass gate transistors (note that the

PCA9549 is only tested at the points speciﬁed in Section 9 “Static characteristics”). In

order for the PCA9549 to act as a voltage translator, the Vo(sw) voltage should be equal to,

or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and

the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be equal to or below 2.7 V

to effectively clamp the downstream bus voltages. Looking at Figure 7, we see that Vo(sw)

(maximum) will be at 2.7 V when the PCA9549 supply voltage is 3.5 V or lower so the

PCA9549 supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring

the bus voltages to their appropriate levels (see Figure 16).

(1) maximum.

(2) typical.

(3) minimum.

Fig 7. Vo(sw) voltage versus VDD

VDD (V)

2.0 5.54.53.0 4.0

002aaa964

3.0

2.0

4.0

5.0

Vo(sw)

(V)

1.0 3.5 5.02.5

(1)

(2)

(3)

Product data sheet Rev. 02 — 13 July 2009 8 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

7. Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy.

7.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 8).

7.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is deﬁned as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P) (see Figure 9).

7.2 System conﬁguration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 10).

Fig 8. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 9. Deﬁnition of START and STOP conditions

mba608

SDA

SCL P

STOP condition

START condition

Product data sheet Rev. 02 — 13 July 2009 9 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

7.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 10. System conﬁguration

002aaa966

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

I2C-BUS

MULTIPLEXER

SLAVE

Fig 11. Acknowledgement on the I2C-bus

002aaa987

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

Product data sheet Rev. 02 — 13 July 2009 10 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

7.4 Bus transactions

Data is transmitted to the PCA9549 control register using the Write mode as shown in

Figure 12.

Data is read from the PCA9549 using the Read mode as shown in Figure 13.

8. Limiting values

[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal

environment can create junction temperatures which are detrimental to reliability. The maximum junction

temperature of this integrated circuit should not exceed 125 °C.

Fig 12. Write control register

Fig 13. Read control register

002aac430

B7 B6 B5 B4 B3 B2 B1 B01 1 0 A2 A1 A0 0 AS 1 A P

slave address

START condition R/W acknowledge

from slave acknowledge

from slave

control register

SDA

STOP condition

002aac431

1 1 0 A2 A1 A0 1 AS 1 A P

slave address

START condition R/W acknowledge

from slave no acknowledge

from master

control register

SDA

STOP condition

last byte

B7 B6 B5 B4 B3 B2 B1 B0

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +7.0 V

VIinput voltage −0.5 +7.0 V

IIinput current −20 +20 mA

IOoutput current −25 +25 mA

IDD supply current −100 +100 mA

ISS ground supply current −100 +100 mA

Ptot total power dissipation - 400 mW

Tstg storage temperature −60 +150 °C

Tamb ambient temperature operating −40 +85 °C

Product data sheet Rev. 02 — 13 July 2009 11 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

9. Static characteristics

[1] For operation between published voltage ranges, refer to the worst-case parameters in both ranges.

[2] VDD must be lowered to 0.2 V in order to reset part.

Table 6. Static characteristics at VDD = 2.3 V to 3.6 V

= 0 V; T

amb

−

C to +85

C; unless otherwise speciﬁed. See Table 7 on page 12 for V

= 4.5 V to 5.5 V

[1]

Symbol Parameter Conditions Min Typ Max Unit

Supply

VDD supply voltage 2.3 - 3.6 V

IDD supply current Operating mode; VDD = 3.6 V; no load;

VI=V

DD or VSS; fSCL = 100 kHz -2050µA

Istb standby current Standby mode; VDD = 3.6 V; no load;

VI=V

DD or VSS

- 0.1 1 µA

VPOR power-on reset voltage no load; VI=V

DD or VSS [2] - 1.6 2.1 V

Input SCL; input/output SDA

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -6 V

IOL LOW-level output current VOL = 0.4 V 3 - - mA

VOL = 0.6 V 6 - - mA

ILleakage current VI=V

DD or VSS −1-+1 µA

Ciinput capacitance VI=V

SS - 6 21 pF

Select inputs A0 to A2, RESET

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -V

DD + 0.5 V

ILI input leakage current pin at VDD or VSS −1-+1 µA

Ciinput capacitance VI=V

SS -25 pF

Pass gate

Ron ON-state resistance VDD = 3.0 V to 3.6 V; VO= 0.4 V;

IO=15mA -712Ω

VDD = 2.3 V to 2.7 V; VO= 0.4 V;

IO=10mA -815Ω

Vo(sw) switch output voltage Vi(sw) =V

DD = 3.3 V; Io(sw) =−100 µA - 1.9 - V

Vi(sw) =V

DD = 3.0 V to 3.6 V;

Io(sw) =−100 µA1.6 - 2.8 V

Vi(sw) =V

DD = 2.5 V; Io(sw) =−100 µA - 1.5 - V

Vi(sw) =V

DD = 2.3 V to 2.7 V;

Io(sw) =−100 µA1.0 - 2.0 V

ILleakage current VI=V

DD or VSS −1-+1 µA

Cio input/output capacitance VI=V

SS -35 pF

Product data sheet Rev. 02 — 13 July 2009 12 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

[1] For operation between published voltage ranges, refer to the worst-case parameters in both ranges.

[2] VDD must be lowered to 0.2 V in order to reset part.

Table 7. Static characteristics at VDD = 4.5 V to 5.5 V

= 0 V; T

amb

−

C to +85

C; unless otherwise speciﬁed. See Table 6 on page 11 for V

= 2.3 V to 3.6 V

[1]

Symbol Parameter Conditions Min Typ Max Unit

Supply

VDD supply voltage 4.5 - 5.5 V

IDD supply current Operating mode; VDD = 5.5 V;

no load; VI=V

DD or VSS;

fSCL = 100 kHz

- 65 100 µA

Istb standby current Standby mode; VDD = 5.5 V;

no load; VI=V

DD or VSS

- 0.6 2 µA

VPOR power-on reset voltage no load; VI=V

DD or VSS [2] - 1.7 2.1 V

Input SCL; input/output SDA

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -6 V

IOL LOW-level output current VOL = 0.4 V 3 - - mA

VOL = 0.6 V 6 - - mA

IIL LOW-level input current VI=V

SS 1- 1 µA

IIH HIGH-level input current VI=V

SS 1- 1 µA

Ciinput capacitance VI=V

SS - 6 21 pF

Select inputs A0 to A2, RESET

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -V

DD + 0.5 V

ILI input leakage current pin at VDD or VSS −1 - +50 µA

Ciinput capacitance VI=V

SS -25 pF

Pass gate

Ron ON-state resistance VDD = 4.5 V to 5.5 V; VO= 0.4 V;

IO=15mA -58 Ω

Vo(sw) switch output voltage Vi(sw) =V

DD = 5.0 V;

Io(sw) =−100 µA- 3.6 - V

Vi(sw) =V

DD = 4.5 V to 5.5 V;

Io(sw) =−100 µA2.6 - 4.5 V

ILleakage current VI=V

DD or VSS −10 - +10 µA

Cio input/output capacitance VI=V

SS -35 pF

Product data sheet Rev. 02 — 13 July 2009 13 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

10. Dynamic characteristics

[1] Pass gate propagation delay is calculated from the 6 Ω typical Ron and the 50 pF load capacitance.

[2] After this period, the ﬁrst clock pulse is generated.

[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to

bridge the undeﬁned region of the falling edge of SCL.

[4] Cb= total capacitance of one bus line in pF.

Table 8. Dynamic characteristics

Symbol Parameter Conditions Standard-mode

I2C-bus Fast-mode I2C-bus Unit

Min Max Min Max

tPD propagation delay A to B;

VDD = 4.5 V to 5.5 V - 0.25[1] - 0.25[1] ns

fSCL SCL clock frequency 0 100 0 400 kHz

tBUF bus free time between a STOP and

START condition 4.7 - 1.3 - µs

tHD;STA hold time (repeated) START condition [2] 4.0 - 0.6 - µs

tLOW LOW period of the SCL clock 4.7 - 1.3 - µs

tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs

tSU;STA set-up time for a repeated START

condition 4.7 - 0.6 - µs

tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs

tHD;DAT data hold time 0[3] 3.45 0[3] 0.9 µs

tSU;DAT data set-up time 250 - 100 - ns

trrise time of both SDA and SCL

signals - 1000 20 + 0.1Cb[4] 300 ns

tffall time of both SDA and SCL signals - 300 20 + 0.1Cb[4] 300 ns

Cbcapacitive load for each bus line - 400 - 400 pF

tSP pulse width of spikes that must be

suppressed by the input ﬁlter - 50 - 50 ns

tVD;DAT data valid time HIGH-to-LOW - 1 - 1 µs

LOW-to-HIGH - 0.6 - 0.6 µs

tVD;ACK data valid acknowledge time - 1 - 1 µs

RESET

tw(rst)L LOW-level reset time 4 - 4 - ns

trst reset time SDA clear 500 - 500 - ns

tREC;STA recovery time to START condition 0 - 0 - ns

Product data sheet Rev. 02 — 13 July 2009 14 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

Fig 14. Deﬁnition of timing on the I2C-bus

tSP

tBUF

tHD;STA PP S

tLOW

tHD;DAT

tHIGH tSU;DAT tSU;STA

tHD;STA

tSU;STO

SDA

SCL

002aaa986

Fig 15. Deﬁnition of RESET timing

SDA

SCL

002aac314

50 %

70 %

50 % 50 %

trec(rst) tw(rst)L

RESET

START

trst

ACK or read cycle

Product data sheet Rev. 02 — 13 July 2009 15 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

11. Application information

Remark: B can also be input and A can also be output as shown in bit 8.

Fig 16. Typical application

PCA9549

VSS

SDA

SCL

RESET

VDD = 5.0 V

I2C-bus/SMBus

MASTER

SDA

SCL bit 1

2B bit 2

3B bit 3

4B bit 4

5B bit 5

6B bit 6

7B bit 7

8B bit 8

002aaa995

Fig 17. Custom multiplexer or demultiplexer application

RESET

SCL

SDA

002aac279

AB C D E

ABCDE

Product data sheet Rev. 02 — 13 July 2009 16 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

12. Test information

Fig 18. 2 channel 4-to-1 multiplexer or demultiplexer

RESET

SCL

SDA

002aac280

AA AB

AC AD BA BB BC BD

CL= load capacitance includes jig and probe capacitance.

RL= load resistance.

RT= termination resistance; should be equal to Zo of pulse generator.

Fig 19. Test circuit

PULSE

GENERATOR

50 pF

002aac315

VDD

DUT

2VDD

Product data sheet Rev. 02 — 13 July 2009 17 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

13. Package outline

Fig 20. SO24 package outline (SOT137-1)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 15.6

15.2 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT137-1

detail X

vMA

(A )

0.25

075E05 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.61

0.60 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

99-12-27

03-02-19

Product data sheet Rev. 02 — 13 July 2009 18 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

Fig 21. TSSOP24 package outline (SOT355-1)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 7.9

7.7 4.5

4.3 0.65 6.6

6.2 0.4

0.3 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT355-1 MO-153 99-12-27

03-02-19

0.25 0.5

0.2

112

24 13

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

max.

1.1

Product data sheet Rev. 02 — 13 July 2009 19 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

Fig 22. HVQFN24 package outline (SOT616-1)

0.51 0.2

A1Eh

UNIT ye

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.1

3.9

2.25

1.95

4.1

3.9 2.25

1.95

2.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT616-1 MO-220 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT616-1

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

712

24 19

01-08-08

02-10-22

terminal 1

index area

terminal 1

index area

1/2 e

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 02 — 13 July 2009 20 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

14. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

Product data sheet Rev. 02 — 13 July 2009 21 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

14.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 23) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 9 and 10

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 23.

Table 9. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 10. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 02 — 13 July 2009 22 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

15. Abbreviations

MSL: Moisture Sensitivity Level

Fig 23. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 11. Abbreviations

Acronym Description

CBT Cross Bar Technology

CDM Charged-Device Model

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

I2C-bus Inter-Integrated Circuit bus

MM Machine Model

PCB Printed-Circuit Board

SMBus System Management Bus

TTL Transistor-Transistor Logic

Product data sheet Rev. 02 — 13 July 2009 23 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

16. Revision history

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9549_2 20090713 Product data sheet - PCA9549_1

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Table 8 “Dynamic characteristics”:

–Symbol tf: changed Unit from “µs” to “ns”.

–Symbol Cb: changed Unit from “µs” to “pF”.

•Updated soldering information.

PCA9549_1 20060711 Product data sheet - -

Product data sheet Rev. 02 — 13 July 2009 24 of 25

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors PCA9549

Octal bus switch with individually I2C-bus controlled enables

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 July 2009

Document identifier: PCA9549_2

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 5

6.1 Device addressing . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Control register. . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2.1 Control register deﬁnition . . . . . . . . . . . . . . . . . 5

6.3 RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.5 CBT characteristic over VDD range. . . . . . . . . . 6

7 Characteristics of the I2C-bus. . . . . . . . . . . . . . 8

7.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.1.1 START and STOP conditions . . . . . . . . . . . . . . 8

7.2 System conﬁguration . . . . . . . . . . . . . . . . . . . . 8

7.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.4 Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 10

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10

9 Static characteristics. . . . . . . . . . . . . . . . . . . . 11

10 Dynamic characteristics . . . . . . . . . . . . . . . . . 13

11 Application information. . . . . . . . . . . . . . . . . . 15

12 Test information. . . . . . . . . . . . . . . . . . . . . . . . 16

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17

14 Soldering of SMD packages . . . . . . . . . . . . . . 20

14.1 Introduction to soldering . . . . . . . . . . . . . . . . . 20

14.2 Wave and reﬂow soldering . . . . . . . . . . . . . . . 20

14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 20

14.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 21

15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22

16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 23

17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 24

17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24

17.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

18 Contact information. . . . . . . . . . . . . . . . . . . . . 24

19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25