FEATURES
DBANDWIDTH: 20MHz
DSLEW RATE: 30V/µs
DFAST 16-BIT SETTLING TIME
DLOW NOISE: 6nV/√Hz (typ) at 100kHz
DEXCELLENT CMRR, PSRR, and AOL
DRAIL-TO-RAIL OUTPUT
DCM RANGE INCLUDES GND
DTHD+N: 0.0003% (typ) at 1kHz
DQUIESCENT CURRENT: 5.5mA/ch (max)
DSUPPLY VOLTAGE: 4V to 12V
DSHUTDOWN MODE (OPAx726): 6µA/ch
APPLICATIONS
DOPTICAL NETWORKING
DTRANSIMPEDANCE AMPLIFIERS
DINTEGRATORS
DACTIVE FILTERS
DA/D CONVERTER BUFFERS
DI/V CONVERTER FOR DACs
DPORTABLE AUDIO
DPROCESS CONTROL
DTEST EQUIPMENT
OPA725 RELATED PRODUCTS
FEATURES PRODUCT
10MHz, 16V, 16V/µs, 8.5nV/√Hz at 1kHz TLC080
8MHz, 36V, FET Input, 20V/µs, 8.5nV/√Hz at 1kHz OPA132
100MHz, 5.5V, Precision Transimpedance Amplifier OPA380
500MHz, ±5V, FET Input, 290V/µs, 7nV/√Hz at 100kHz OPA656
7MHz, 12V, RRIO, 10V/µs, 30nV/√Hz at 10kHz OPA743
16-Bit, 250kSPS, 4-Channel, Parallel Output ADC ADS8342
DESCRIPTION
The OPA725 and OPA726 series op amps use a
state-of-the-art 12V analog CMOS process, and combine
outstanding ac performance with low bias current and
excellent CMRR, PSRR, and AOL. The 20MHz
Gain-Bandwidth (GBW) Product is achieved by using a
proprietary and patent-pending output stage design.
These characteristics allow excellent 16-bit settling times
for driving 16-bit Analog-to-Digital converters (ADCs).
Excellent a c characteristics, such as 20MHz GBW, 30V/µs
slew rate and 0.0003% THD+N make the OPA725 and
OPA726 well-suited for communication, high-end audio,
and active filter applications. With a bias current of less
than 200pA, they are well-suited for use as
transimpedance (I/V-conversion) amplifiers for monitoring
optical power in ONET applications.
The OPA725 and OPA726 op amps can be used in
single-supply applications from 4V up to 12V, or
dual-supply from ±2V to ±6V. The output swings to within
150mV of the rails, maximizing dynamic range. The
shutdown versions (OPAx726) reduce the quiescent
current to less than 6µA and feature a reference pin for
easy shutdown operation with standard CMOS logic in
dual-supply applications.
The OPA725 (single) is available in SOT23-5 and SO-8
packages, and the OPA2725 (dual) is available in MSOP-8
and SO-8 packages. The OPA726 (single with shutdown)
is available in MSOP-8 and SO-8. The OPA2726 (dual with
shutdown) is available in MSOP-10. All versions are
specified for operation from −40°C to +125°C.
−VB
VOUT
+12V
Enable
OPA726
λ
75Ω
OPA725 ADS8342
16−Bit ADC
AIN
Common
330pF
VIN
±2.5V
+5V
−5V
+5V
−5V
OPA725, OPA2725
OPA726, OPA2726
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
Very Low Noise, High-Speed, 12V CMOS
Operational Amplifier
! !
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Copyright 2003−2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
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2
ORDERING INFORMATION
PRODUCT PACKAGE-LEAD PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING ORDERING
NUMBER TRANSPORT
MEDIA, QUANTITY
Non-Shutdown
OPA725 SOT23-5 DBV −40°C to +125°C OALI OPA725AIDBVT Tape and Reel, 250
″ ″ ″ ″ ″ OPA725AIDBVR Tape and Reel, 3000
OPA725 SO-8 D −40°C to +125°C OPA725A OPA725AID Rails, 100
″ ″ ″ ″ ″ OPA725AIDR Tape and Reel, 2500
OPA2725 SO-8 D −40°C to +125°C OPA2725A OPA2725AID Rails, 100
″ ″ ″ ″ ″ OPA2725AIDR Tape and Reel, 2500
OPA2725 MSOP-8 DGK −40°C to +125°C BGM OPA2725AIDGKT Tape and Reel, 250
″ ″ ″ ″ ″ OPA2725AIDGKR Tape and Reel, 2500
Shutdown
OPA726 SO-8 D −40°C to +125°C OPA726A OPA726AID Rails, 100
″ ″ ″ ″ ″ OPA726AIDR Tape and Reel, 2500
OPA726 MSOP-8 DGK −40°C to +125°C BHC OPA726AIDGKT Tape and Reel, 250
″ ″ ″ ″ ″ OPA726AIDGKR Tape and Reel, 2500
OPA2726 MSOP-10 DGS −40°C to +125°C BHB OPA2726AIDGST Tape and Reel, 250
″ ″ ″ ″ ″ OPA2726AIDGSR Tape and Reel, 2500
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage +13.2V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Input Terminals, Voltage(2) −0.5V to (V+) + 0.5V. . . . . . . . .
Current(2) ±10mA. . . . . . . . . . . . . . . . . . .
Output Short Circuit(3) Continuous. . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature −55°C to +125°C. . . . . . . . . . . . . . . . . . . . .
Storage Termperature −55°C to +150°C. . . . . . . . . . . . . . . . . . . . . .
Junction Temperature +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead Temperature (soldering, 10s) +300°C. . . . . . . . . . . . . . . . . . . .
ESD Rating (Human Body Model) 1000 V. . . . . . . . . . . . . . . . . . . .
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, a nd
functional operation of the device at these or any other conditions
beyond those specified is not supported.
(2) Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.5V beyond the supply
rails should be current limited to 10mA or less.
(3) Short-circuit to ground, one amplifier per package.
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3
PIN CONFIGURATIONS
(1) NC denotes no internal connection.
(2) DGND = reference voltage for Enable Reference pin. Voltage on this pin
will b e the voltage to which the Enable Reference pin is referenced.
1
2
3
5
4
V+
−IN
Out
V−
+IN
OPA725
SOT23−5
1
2
3
4
8
7
6
5
NC(1)
V+
OUT
NC(1)
NC(1)
−IN
+IN
V−
OPA725
SO−8
1
2
3
4
8
7
6
5
V+
OUT B
−IN B
+IN B
OUT A
−IN A
+IN A
V−
OPA2725
SO−8, MSOP−8
A
B
1
2
3
4
8
7
6
5
Enable
V+
OUT
NC(1)
DGND(2)
−IN
+IN
V−
OPA726
SO−8, MSOP−8
1
2
3
4
5
10
9
8
7
6
V+
OUT B
−IN B
+IN B
Enable
OUT A
−IN A
+IN A
V−
DGND(2)
OPA2726
MSOP−10
A
B
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4
ELECTRICAL CHARACTERISTICS: VS = +4V to +12V or VS = ±2V to ±6V
Boldface limits apply over the specified temperature range, TA = −40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
OPA725, OPA726, OPA2725, OPA2726
PARAMETER CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
Input Offset Voltage VOS
OPA725, OPA726 VS = ±6V, VCM = 0V 1.2 3 mV
OPA2725, OPA2726 VS = ±6V, VCM = 0V 1.5 5 mV
Drift dVOS/dT 4µV/°C
vs Power Supply PSRR VS = ±2V to ±6V, VCM = V− 30 100 µV/V
Over Temperature VS = ±2V to ±6V, VCM = V− 150 mV/V
Channel Separation, DC 1µV/V
INPUT BIAS CURRENT
Input Bias Current IB30 200 pA
Over Temperature See Typical Characteristics
Input Offset Current IOS 10 50 pA
NOISE
Input Voltage Noi se, f = 0. 1Hz t o 10Hz enVS = ±6V, VCM = 0V 10 µVPP
Input Voltage Noi se Dens i ty, f = 10kHz enVS = ±6V, VCM = 0V 10 nV/√Hz
Input Voltage Noise Density, f = 100kHz enVS = ±6V, VCM = 0V 6 nV/√Hz
Input Current Noise Density, f = 1kHz inVS = ±6V, VCM = 0V 2.5 fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM (V−) (V+) − 2 V
Common-Mode Rejection Ratio CMRR (V−) ≤ VCM ≤ (V+) − 2V 88 94 dB
Over Temperature (V−) ≤ VCM ≤ (V+) − 2V 84 dB
(V−) ≤ VCM ≤ (V+) − 3V 94 100 dB
Over Temperature (V−) ≤ VCM ≤ (V+) − 3V 84 dB
INPUT IMPEDANCE
Differential 1011 5 Ω pF
Common-Mode 1011 4 Ω pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain AOL
OPA725, OPA726 RL = 100kΩ, 0.15V < VO < (V+) − 0.15V 110 120 dB
Over Temperature RL = 100kΩ, 0.15V < VO < ( V+) − 0. 15V 100 dB
OPA2725, OPA2726 RL = 100kΩ, 0. 175V < VO < (V+) − 0.175V 110 120 dB
Over Temperature RL = 100kΩ, 0.175V < VO < (V+) − 0.175V 100 dB
OPA725, OPA726 RL = 1kΩ, 0.25V < VO < (V+) − 0.25V 106 116 dB
Over Temperature RL = 1kΩ, 0.25V < VO < (V+) − 0.25V 96 dB
OPA2725, OPA2726 RL = 2kΩ, 0.25V < VO < (V+) − 0.25V 106 116 dB
Over Temperature RL = 2kΩ, 0.25V < VO < (V+) − 0.25V 96 dB
FREQUENCY RESPONSE CL = 20pF
Gain-Bandwidth Product GBW 20 MHz
Slew Rate SR G = +1 30 V/µs
Settling Time, 0.1% tSVS = ±6V, 5V Step, G = +1 350 ns
0.01% VS = ±6V, 5V Step, G = +1 450 ns
Overload Recovery Time VIN • Gain > VS50 ns
Total Harmonic Distortion + Noise THD+N VS = ±6V, VOUT = 2VRMS, RL = 600Ω,
G = +1, f = 1kHz 0.0003 %
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5
ELECTRICAL CHARACTERISTICS: VS = +4V to +12V or VS = ±2V to ±6V (continued)
Boldface limits apply over the specified temperature range, TA = −40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
OPA725, OPA726, OPA2725, OPA2726
PARAMETER UNIT
MAXTYPMIN
CONDITIONS
OUTPUT
Voltage Output Swing from Rail
OPA725, OPA726 RL = 100kΩ, AOL > 110dB 100 150 mV
Over Temperature RL = 100kΩ, AOL > 100dB 150 mV
OPA2725, OPA2726 RL = 100kΩ, AOL > 110dB 125 175 mV
Over Temperature RL = 100kΩ, AOL > 100dB 175 mV
OPA725, OPA726 RL = 1kΩ, AOL > 106dB 200 250 mV
Over Temperature RL = 1kΩ, AOL > 96dB 250 mV
OPA2725, OPA2726 RL = 2kΩ, AOL > 106dB 200 250 mV
Over Temperature RL = 2kΩ, AOL > 96dB 250 mV
Output Current IOUT VS − VOUT < 1V 40 mA
Short-Circuit Current ISC ±55 mA
Capacitive Load Drive CLOAD See Typical Characteristics
Open-Loop Output Impedance f = 1MHz, IO = 0 40 Ω
ENABLE/SHUTDOWN (OPAx726)
tOFF 5µs
tON 30 µs
Enable R eference (DGND) V oltage Range V DGND V− (V+) − 2 V
VL (shutdown) < VDGND +0.8V V
VH (amplifier is active) > VDGND +2V V
Input Disable Current Ref Pin = Enable Pin = V− 5µA
IQSD (per amplifier) 6 15 µA
POWER SUPPLY
Specified Voltage Range VS4 12 V
Operating Voltage Range VS3.5 to 13. 2 V
Quiescent Current (per amplifier) IQIO = 0 4.3 5.5 mA
Over Temperature 6 mA
TEMPERATURE RANGE
Specified Range −40 125 °C
Operating Range −55 125 °C
Storage Range −55 150 °C
Thermal Resistance qJA
SOT23-5 200 °C/W
MSOP-8, MSOP-10, SO-8 150 °C/W
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6
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
GAIN AND PHASE vs FREQUENCY
Frequency (Hz)
10 100 1k 10k 100k 1M 10M 100M
180
160
140
120
100
80
60
40
20
0
−20
180
160
140
120
100
80
60
40
20
0
−20
Gain (dB)
Phase (_)
Gain
Phase
POWER−SUPPLY REJECTION RATIO vs FREQUENCY
Frequency (Hz)
100 1k 10k 100k 1M 10M 100M
100
90
80
70
60
50
40
30
20
10
0
PSRR (dB)
CHANNEL SEPARATION vs FREQUENCY
Frequency (Hz)
1k 10k 100k 1M 10M 100M
140
120
100
80
60
40
20
Channel Separation (dB)
COMMON−MODE REJECTION RATIO vs FREQUENCY
Frequency (Hz)
10 100 1k 10k 100k 1M 10M
120
100
80
60
40
20
0
CMRR (dB)
(V−)≤VCM ≤(V+) −2V
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
Frequency (Hz)
10k 100k 1M 10M
7
6
5
4
3
2
1
0
Amplitude (V)
VS=±6V
Indicates maximum output
for no visible distortion.
INPUT VOLTAGE NOISE SPECTRAL DENSITY
vs FREQUENCY
Frequency (Hz)
10 100 1k 10k 100k 1M 10M
1000
100
10
1
Voltage Noise (nV/√Hz)
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
INPUT BIAS CURRENT vs COMMON−MODE VOLTAGE
Common−Mode Voltage (V)
−6.5
−5.5
−4.5
−3.5
−2.5
−1.5
−0.5
0.5
1.5
2.5
3.5
4.5
5.5
6.5
100k
10k
1k
100
10
−10
−100
−1k
−10k
−100k
Input Bias Current (pA)
IB<±10pA
+125_C
+125_C
+85_C
+85_C
+25_C
+25_C
OPEN−LOOP GAIN vs TEMPERATURE
140
130
120
110
100
90
80
AOL (dB)
Temperature (_C)
−50 −25 0 25 50 75 100 125 150
RL=1k
Ω
RL= 100kΩ
COMMON−MODE REJECTION RATIO vs TEMPERATURE
110
100
90
80
70
60
CMRR (dB)
Temperature (_C)
−50 −25 0 25 50 75 100 125 150
(V−)≤VCM ≤(V+) −2V
OFFSET CURRENT vs TEMPERATURE
10k
1k
100
10
1
0.1
0.01
IOS (pA)
Temperature (_C)
−50 −25 0 25 50 75 100 125 150
POWER−SUPPLY REJECTION RATIO vs TEMPERATURE
120
100
80
60
PSRR (dB)
Temperature (_C)
−50 −25 0 25 50 75 100 125 150
QUIESCENT CURRENT vs TEMPERATURE
5
4
3
2
1
0
IQ(mA)
Temperature (_C)
−50 −25 0 25 50 75 100 125 150
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8
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
QUIESCENT CURRENT vs SUPPLY VOLTAGE
Supply Voltage (V)
34567891011121314
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
IQper Amplifier (mA)
SHORT−CIRCUIT CURRENT vs SUPPLY VOLTAGE
Supply Voltage (V)
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
13.5
90
80
70
60
50
40
30
20
10
0
Short−Circuit Current (mA)
Sourcing
Sinking
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
Frequency (Hz)
10 100 1k 10k 100
k
0.01
0.001
0.0001
THD + Noise (%)
RL=600
Ω
VOUT =2Vrms
BW = 80kHz
SHORT−CIRCUIT CURRENT vs TEMPERATURE
90
80
70
60
50
40
30
20
10
0
Short−Circuit (mA)
Temperature (_C)
−50 −25 0 25 50 75 100 125 150
Sourcing
Sinking
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
Output Current (mA)
01020304050607080
6
4
2
0
−2
−4
−6
Output Voltage (V)
125_C
−40_C
−40_C
25_C
SETTLING TIME vs GAIN
Noninverting Gain (V/V)
1 10 100
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
0
0.01%
0.1%
Settling Time (ns)
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
SMALL−SIGNAL OVERSHOOT vs CAPACITIVE LOAD
Capacitive Load (pF)
10 100 1000
90
80
70
60
50
40
30
20
10
0
Overshoot (%)
G=+1
G=−1
CF=3pF
G=+5
CF= 1pF
VOLTAGE OFFSET DRIFT PRODUCTION DISTRIBUTION
Voltage Offset Drift (µV/_C)
20 4 6 8 10 12 14 16
Population
Typical production distribution
of packaged units.
LARGE−SIGNAL STEP RESPONSE
400ns/div
1V/div
G=+1
RL=10k
Ω
CL=20pF
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
Offset Voltage (mV)
−3.3
−3.0
−2.7
−2.4
−2.1
−1.8
−1.5
−1.2
−0.9
−0.6
−0.3
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
Population
SMALL−SIGNAL STEP RESPONSE
100ns/div
10mV/div
G=+1
RL=10k
Ω
CL=20pF
SMALL−SIGNAL STEP RESPONSE
200ns/div
10mV/div
CF= 2pF CF= 3pF
CF=4pF
10kΩ
CF
CL
20pF
G=−1
RF
10kΩ
OPA725
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
LARGE−SIGNAL STEP RESPONSE
1V/div
400ns/div
10kΩ
RF
10kΩ
CF
4pF
CL
20pF
G=−1
OPA725
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APPLICATIONS INFORMATION
OPA725 and OPA726 series 20MHz CMOS op amps have
a fast slew rate, low noise, and excellent PSRR, CMRR,
and AOL. These op amps can operate on typically 4.3mA
quiescent current from a single (or split) supply in the range
of 4V to 12V (±2V to ±6V), making them highly versatile
and easy to use. They are stable in a unity-gain
configuration.
Power-supply pins should be bypassed with 1nF ceramic
capacitors in parallel with 1µF tantalum capacitors.
OPERATING VOLTAGE
OPA725 series op amps are specified from 4V to 12V
supplies over a temperature range of −40°C to +125°C.
They will operate well in ±5V or +5V to +12V power-supply
systems. Parameters that vary significantly with operating
voltage or temperature are shown in the Typical
Characteristics.
ENABLE/SHUTDOWN
OPA725 series op amps require approximately 4.3mA
quiescent current. The enable/shutdown feature of the
OPA726 allows the op amp to be shut off to reduce this
current to approximately 6µA.
The enable/shutdown input is referenced to the Enable
Reference Pin, DGND (see Pin Configurations). This pin
can be connected to logic ground in dual-supply op amp
configurations to avoid level-shifting the enable logic
signal, as shown in Figure 1.
The Enable Reference Pin voltage, VDGND, must not
exceed (V+) − 2V. It may be set as low as V−. The amplifier
is enabled when the Enable Pin voltage is greater than
VDGND + 2V. The amplifier is disabled (shutdown) if the
Enable Pin voltage is less than VDGND + 0.8V. The Enable
Pin is connected to internal pull-up circuitry and will enable
the device if left unconnected.
COMMON-MODE VOLTAGE RANGE
The input common-mode voltage range of the OPA725
and OPA726 series extends from V− to (V+) − 2V.
Common-mode rejection is excellent throughout the input
voltage range from V− to (V+) − 3V. CMRR decreases
somewhat as the common-mode voltage extends to
(V+) − 2 V, but remains very good and is tested throughout
this range. See the Electrical Characteristics table for
details.
DGND
Digital
Logic
Enable
OPA726
+12V
a) Single−Supply Configuration
b) Dual−Supply Configuration
DGND
Digital
Logic
Enable
OPA726
+5V
−5V
VOUT
VOUT
Figure 1. Enable Reference Pin Connection for
Single- and Dual-Supply Configurations
INPUT OVER-VOLTAGE PROTECTION
Device inputs are protected by ESD diodes that will
conduct if the input voltages exceed the power supplies by
more than approximately 300mV. Momentary voltages
greater than 300mV beyond the power supply can be
tolerated if the current is limited to 10mA. This is easily
accomplished with an input resistor in series with the op
amp, as shown in Figure 2. The OPA725 series features
no phase inversion when the inputs extend beyond
supplies, if the input is current limited.
ROPA725
V+
V−
VIN
VOUT
10mA max
IOVERLOAD
Figure 2. Input Current Protection for Voltages
Exceeding the Supply Voltage
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RAIL-TO-RAIL OUTPUT
A class AB output stage with common-source transistors
is used to achieve rail-to-rail output. This output stage is
capable of driving heavy loads connected to any point
between V+ and V−. For light resistive loads ( > 100kΩ ),
the output voltage can swing to 150mV (175mV for dual)
from the supply rail, while still maintaining excellent
linearity (AOL > 110dB). With 1kΩ (2kΩ for dual) resistive
loads, the output is specified to swing to within 250mV from
the supply rails with excellent linearity (see the Typical
Characteristics curve Output Voltage Swing vs Output
Current).
CAPACITIVE LOAD AND STABILITY
Capacitive load drive is dependent upon gain and the
overshoot requirements of the application. Increasing the
gain enhances the ability of the amplifier to drive greater
capacitive loads (see the Typical Characteristics curve
Small-Signal Overshoot vs Capacitive Load).
One method of improving capacitive load drive in the
unity-gain configuration is to insert a 10Ω to 20Ω resistor
inside the feedback loop, as shown in Figure 3. This
reduces ringing with large capacitive loads while
maintaining DC accuracy.
RS
20Ω
OPA725
CLRL
VIN
VOUT
V+
Figure 3. Series Resistor in Unity-Gain Buffer
Configuration Improves Capacitive Load Drive
DRIVING FAST 16-BIT ADCs
The OPA725 series is optimized for driving fast 16-bit
ADCs such as the ADS8342. The OPA725 op amps buffer
the converter input capacitance and resulting charge
injection, while providing signal gain. Figure 4 shows the
OPA725 in a single-ended method of interfacing to the
ADS8342 16-bit, 250kSPS, 4-channel ADC with an input
range of ±2.5V. The OPA725 has demonstrated excellent
settling time to the 16-bit level within the 600ns acquisition
time of the ADS8342. The RC filter, shown in Figure 4, has
been carefully tuned for best noise and settling
performance. It may need to be adjusted for different op
amp configurations. Please refer to the ADS8342 data
sheet (a v ailable for download at w ww.ti.com) for additional
information on this product.
75Ω
OPA725 ADS8342
16−Bit ADC
AIN
Common
330pF
VIN
±2.5V
+5V
−5V
+5V
−5V
Figure 4. OPA725 Driving an ADC
TRANSIMPEDANCE AMPLIFIER
Wide bandwidth, low input bias current, and low input
voltage and current noise make the OPA725 an ideal
wideband photodiode transimpedance amplifier. Low-
voltage noise is important because photodiode capaci-
tance causes the effective noise gain of the circuit to
increase at high frequency.
The key elements to a transimpedance design, as shown
in Figure 5, are the expected diode capacitance (CD),
which should include the parasitic input common-mode
and di fferential-mode input capacitance (4pF + 5pF for th e
OPA725); the desired transimpedance gain (RF); and the
GBW for the OPA725 (20MHz). With these three variables
set, the feedback capacitor value (CF) can be set to control
the frequency response. CF includes the stray capacitance
of RF, which is 0.2pF for a typical surface-mount resistor.
OPA725 VOUT
10MΩ
+5V
−5V
CD
RF
CF(1)
<1pF
λ
NOTE: (1) CFis optional to prevent gain peaking.
It includes the stray capacitance of RF.
Figure 5. Dual-Supply Transimpedance Amplifier
"#$% #"#$
"#&% #"#&
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
www.ti.com
13
To achieve a maximally-flat, 2nd-order Butterworth
frequency response, the feedback pole should be set to:
1
2pRFCF+GBW
4pRFCD
Ǹ
Bandwidth is calculated by:
f*3dB +GBW
2pRFCD
ǸHz
For even higher transimpedance bandwidth, the
high-speed CMOS OPA354 (100MHz GBW), OPA300
(180 MHz GBW), OPA355 (200MHz GBW), or OPA656,
OPA657 (400MHz GBW) may be used.
For single-supply applications, the +IN input can be biased
with a positive dc voltage to allow the output to reach true
zero when the photodiode is not exposed to any light, and
respond without the added delay that results from coming
out of the negative rail. (Refer to Figure 6.) This bias
voltage also appears across the photodiode, providing a
reverse bias for faster operation.
OPA725 VOUT
10MΩ
V+
RF
CF(1)
<1pF
λ
NOTE: (1) CFis optional to prevent gain peaking.
It includes the stray capacitance of RF.
+VBias
Figure 6. Single-Supply Transimpedance
Amplifier
For additional information, refer to Application Bulletin
SBOA055, Compensate Transimpedance Amplifiers
Intuitively, available for download at www.ti.com.
OPTIMIZING THE TRANSIMPEDANCE
CIRCUIT
To achieve the best performance, components should be
selected according to the following guidelines:
1. For lowest noise, select RF to create the total required
gain. Using a lower value for RF and adding gain after
the transimpedance amplifier generally produces
poorer noise performance. The noise produced by RF
increases with the square-root of RF, whereas the
signal increases linearly. Therefore, signal-to-noise
ratio is improved when all the required gain is placed
in the transimpedance stage.
2. Minimize photodiode capacitance and stray
capacitance at the summing junction (inverting input).
This capacitance causes the voltage noise of the op
amp to be amplified (increasing amplification at high
frequency). Using a low-noise voltage source to
reverse-bias a photodiode can significantly reduce its
capacitance. Smaller photodiodes have lower
capacitance. Use optics to concentrate light on a small
photodiode.
3. Noise increases with increased bandwidth. Limit the
circuit bandwidth to only that required. Use a capacitor
across the RF to limit bandwidth, even if not required
for stability.
4. Circuit board leakage can degrade the performance of
an otherwise well-designed amplifier. Clean the circuit
board carefully. A circuit board guard trace that
encircles the summing junction and is driven at the
same voltage can help control leakage.
For additional information, refer to the Application Bulletins
Noise Analysis of FET Transimpedance Amplifiers
(SBOA060), and Noise Analysis for High-Speed Op Amps
(SBOA066), available for download at the TI web site.
(1)
(2)
"#$% #"#$
"#&% #"#&
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
www.ti.com
14
NOTE: FilterPro is a low-pass filter design program available for download at no cost from TI’s web site (www.ti.com). The program can be used
to determine component values for other cutoff frequencies or filter types.
DC Gain = 1
C1
1nF
C2
330pF
R2
15.9kΩ
R1
1.93kΩ
2.2nF
C3
C4
100pF
R4
22.3kΩ
R3
2.07kΩ
Cutoff Frequency = 50kHz
VOUT
1/2
OPA2725
1/2
OPA2725
Figure 7. Four-Pole Butterworth Sallen-Key Low-Pass Filter
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
OPA2725AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA2725AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA2725AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
OPA2725AIDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
OPA2725AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
OPA2725AIDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
OPA2725AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA2725AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA2726AIDGST ACTIVE MSOP DGS 10 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
OPA2726AIDGSTG4 ACTIVE MSOP DGS 10 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
OPA725AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA725AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA725AIDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA725AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA725AIDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA725AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA725AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
OPA725AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA726AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA726AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA726AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
OPA726AIDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA2725AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2725AIDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2725AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2726AIDGST MSOP DGS 10 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA725AIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
OPA725AIDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
OPA725AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA726AIDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2725AIDGKR VSSOP DGK 8 2500 367.0 367.0 35.0
OPA2725AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0
OPA2725AIDR SOIC D 8 2500 367.0 367.0 35.0
OPA2726AIDGST MSOP DGS 10 250 210.0 185.0 35.0
OPA725AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
OPA725AIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
OPA725AIDR SOIC D 8 2500 367.0 367.0 35.0
OPA726AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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