2008-2014 Microchip Technology Inc. DS70000318G-page 1
dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04
Operating Conditions
• 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
• 3.0V to 3.6V, -40ºC to +85º C, D C to 50 M IPS
Core: 16-Bit dsPIC33F CPU
• Code-Efficient (C and Assembly) Architecture
• Two 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle Mixed-Sign MUL plus Hardware Divide
• 32-Bit Multiply Support
Clock Management
• ±2.0% Internal Oscillator
• Program m able PLLs and Oscillat or C l ock S our ces
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer (WDT)
• Fast Wake-up and Start-u p
Power Management
• Low-Power Managem ent modes (S leep, Idle, Doze)
• Integrat ed Power- on Reset and Br ow n- out Reset
High-Speed PWM
• Up to Four PW M Pai r s w ith In dep endent Timing
• Dead Time for Rising and Falling Ed ges
• 1.04 ns PWM Resolution
• PWM Support for:
- DC/DC, AC/DC, Inverters, PFC and Lighting
• Program m able Faul t Inpu ts
• Flexible Trigger Configurations for ADC Conversions
Advanced Analog Features
• ADC module:
- 10-bit resoluti on with up to 2 Successive Approximation
Register (SAR) converters ( 4 Msps) and up to
six Sample-and- Hold (S&H) ci rcuit s
- Up to 12 input channels grouped i nto six conversi on
pairs, pl us t wo voltage ref erence m oni t oring inputs
- Dedicated result buffer f or each analog channel
• Flexi ble and I ndepe nden t AD C Trigger Sources
Advanced Analog Features (Continued)
• Up to Four High-Speed Comparators with Direct
Connection to the PWM module:
- Pr ogr am mable r ef er enc es with 1024 voltage points
Timers/Output Compare/ Input Capture
• Three G eneral Purpose Timers:
- Three 16-bit and one 32-b it timer/counter
• Two Output C om par e (OC) mod ules
• Two Inp ut Capture (I C) modules
• Peripheral Pin Select (PPS) to all ow Functi on Remap
Communication Interf aces
• UART module (12. 5 M b ps):
- W ith support for LI N /J 2602 protoc ol s an d I rDA®
• 4-Wire SPI module
•I
2C™ modu l e (u p to 1 Mb aud) with SMBu s Support
• PPS to allow Function Remap
Input/Output
• Sink/Source 18 mA on 8 Pins, 10 mA on 10 Pi ns
and 6 mA on 17 Pins
• 5V Toler ant Pi ns
• Selectable Open-Dr ain and Pull-ups
• External Interrupts on up to 30 I/O Pins
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1, -40ºC to +125ºC)
• AEC-Q100 REVG (Grade 0, -40ºC to +150ºC)
• Class B Safety Library, IEC 60730, VDE Certified
• 6x6x0 . 5 m m UQ FN Package Des i gne d and
Opti mized to ea se IPC9592 A 2nd Level Tem perature
Cycle Qualification
Debugger Development Support
• In-Circuit and In-A ppl i cation Progr am ming
• Two Breakpoints
• IEEE 1149.2-Com patible (J TAG) Boundary Scan
• Trace and Run-Time Watch
16-Bit Digital Signal Controllers (up to 16-Kbyte Flash and up to
2-Kbyte SRAM) with High-Speed PWM, ADC and Comparat ors
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 2 2008-2014 Microchip Technology Inc.
dsPIC33 FJ0 6GS101/X0 2 AND
dsPIC33FJ16GSX02/X04 PRODUCT
FAMILIES
The device names, pin counts, memory sizes and
peripheral availability of each device are listed below.
The following pages show their pinout diagrams.
TABLE 1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CONTROLLER FAMILIES
Device
Pins
Program Flash Memory (Kbytes)
RAM (Bytes)
Remappable Peripherals
DAC Output
I2C™
ADC
I/O Pins
Packages
Remappable Pins
16-Bit Timer
Input Capture
Output Compare
UART
SPI
PWM(2)
Analog Comparator
External Interrupts(3)
SARs
Sample-and-Hold (S&H) Circuit
Analog-to-Digital Inputs
dsPIC33FJ06GS101 18 6 256 8 2 0 1 1 1 2x2(1)0 3 0 1 1 3 6 13 SOIC
dsPIC33FJ06GS102 28 6 256 16 2 0 1 1 1 2x2 0 3 0 1 1 3 6 21 SPDIP,
SOIC,
QFN-S
dsPIC33FJ06GS202 28 6 1K 16 2 1 1 1 1 2x2 2 3 1 1 1 3 6 21 SPDIP,
SOIC,
QFN-S
dsPIC33FJ16GS402 28 16 2K 16 3 2 2 1 1 3x2 0 3 0 1 1 4 8 21 SPDIP,
SOIC,
QFN-S
dsPIC33FJ16GS404 44 16 2K 30 3 2 2 1 1 3x2 0 3 0 1 1 4 8 35 QFN,
TQFP,
VTLA
dsPIC33FJ16GS502 28 16 2K 16 3 2 2 1 1 4x2(1)431126821SPDIP,
SOIC,
QFN-S,
UQFN
dsPIC33FJ16GS504 44 16 2K 30 3 2 2 1 1 4x2(1)4 3 1 1 2 6 12 35 QFN,
TQFP,
VTLA
Note 1: The PWM4H:PW M4L pins are remappable.
2: The PWM Fault pins and PWM synchronizat ion pins are remappable.
3: Only two out of three interrupts are remappable.
2008-2014 Microchip Technology Inc. DS70000318G-page 3
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Pin Diagrams
18-Pin SOIC
28-Pin SOIC, SPDIP
dsPIC33FJ06GS101
MCLR
AN0/RA0
AN1/RA1
VDD
VSS
AN2/RA2
TDO/RP5(1)/CN5/RB5
TMS/PGEC2/RP4(1)/CN4/RB4
TCK/PGED2/INT0/RP3(1)/CN3/RB3
VCAP
OSC2/CLKO/AN7/RP2(1)/CN2/RB2
OSC1/CLKI/AN6/RP1(1)/CN1/RB1 VSS
PGEC1/SDA1/RP7(1)/CN7/RB7
PGED1/TDI/SCL1/RP6(1)/CN6/RB6
AN3/RP0(1)/CN0/RB0
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PWM1L/RA3
PWM1H/RA4
MCLR
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14(1)/CN14/RB14
PWM2H/RP13(1)/CN13/RB13
RP12(1)/CN12/RB12
RP11(1)/CN11/RB11VSS
VDD
AN0/RA0
AN1/RA1
AVDD
AVSS
AN2/RA2
PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15
TMS/PGEC2/RP4(1)/CN4/RB4
TCK/PGED2/INT0/RP3(1)/CN3/RB3
VCAP
OSC2/CLKO/RP2(1)/CN2/RB2
OSC1/CLKIN/RP1(1)/CN1/RB1 VSS
TDO/RP5(1)/CN5/RB5
PGEC1/SDA/RP7(1)/CN7/RB7
PGED1/TDI/SCL/RP6(1)/CN6/RB6
AN5/RP10(1)/CN10/RB10
AN4/RP9(1)/CN9/RB9
AN3/RP0(1)/CN0/RB0
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
28-Pin SPDIP, SOIC
MCLR
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14(1)/CN14/RB14
PWM2H/RP13(1)/CN13/RB13
TCK/RP12(1)/CN12/RB12
TMS/RP11(1)/CN11/RB11VSS
VDD
AN0/CMP1A/RA0
AN1/CMP1B/RA1
AVDD
AVSS
AN2/CMP1C/CMP2A/RA2
PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15
PGEC2/EXTREF/RP4(1)/CN4/RB4
PGED2/DACOUT/INT0/RP3(1)/CN3/RB3
VCAP
OSC2/CLKO/RP2(1)/CN2/RB2
OSC1/CLKIN/RP1(1)/CN1/RB1 VSS
TDO/RP5(1)/CN5/RB5
PGEC1/SDA/RP7(1)/CN7/RB7
PGED1/TDI/SCL/RP6(1)/CN6/RB6
AN5/CMP2D/RP10(1)/CN10/RB10
AN4/CMP2C/RP9(1)/CN9/RB9
AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
= Pins are up to 5V tolerant
= Pins are up to 5V tolerant
= Pins are up to 5V tolerant
dsPIC33FJ06GS102
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
dsPIC33FJ06GS202
1
2
3
4
5
6
7
8
9
10
11
12
28
27
26
25
24
23
22
21
20
19
18
17
13
14 16
15
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 4 2008-2014 Microchip Technology Inc.
Pin Diagrams (Continued)
28-Pin SPDIP, SOIC
28-Pin SPDIP, SOIC
MCLR
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14(1)/CN14/RB14
PWM2H/RP13(1)/CN13/RB13
TCK/PWM3L/RP12(1)/CN12/RB12
TMS/PWM3H/RP11(1)/CN11/RB11VSS
VDD
AN0/RA0
AN1/RA1
AVDD
AVSS
AN2/RA2
PGED3/RP8(1)/CN8/RB8 PGEC3/RP15/CN15/RB15
PGEC2/RP4(1)/CN4/RB4
PGED2/INT0/RP3(1)/CN3/RB3
VCAP
OSC2/CLKO/AN7/RP2(1)/CN2/RB2
OSC1/CLKIN/AN6/RP1(1)/CN1/RB1 VSS
TDO/RP5(1)/CN5/RB5
PGEC1/SDA/RP7(1)/CN7/RB7
PGED1/TDI/SCL/RP6(1)/CN6/RB6
AN5/RP10(1)/CN10/RB10
AN4/RP9(1)/CN9/RB9
AN3/RP0(1)/CN0/RB0
MCLR
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14(1)/CN14/RB14
PWM2H/RP13(1)/CN13/RB13
TCK/PWM3L/RP12(1)/CN12/RB12
TMS/PWM3H/RP11(1)/CN11/RB11VSS
VDD
AN0/CMP1A/RA0
AN1/CMP1B/RA1
AVDD
AVSS
AN2/CMP1C/CMP2A/RA2
CN8/RB8/PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15
PGEC2/EXTREF/RP4(1)/CN4/RB4
PGED2/DACOUT/INT0/RP3(1)/CN3/RB3
VCAP
OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2
OSC1/CLKIN/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1 VSS
TDO/RP5(1)/CN5/RB5
PGEC1/SDA/RP7(1)/CN7/RB7
PGED1/TDI/SCL/RP6(1)/CN6/RB6
AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10
AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9
AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
= Pins are up to 5V tolerant
= Pins are up to 5V tolerant
dsPIC33FJ16GS402
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
dsPIC33FJ16GS502
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
14 15
2008-2014 Microchip Technology Inc. DS70000318G-page 5
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Pin Diagrams (Continued)
28-Pin QFN-S(2)
1011
2
3
6
1
18
19
20
21
22
121314 15
8
716
17
232425262728
9
dsPIC33FJ06GS102
PGED2/INT0/RP3(1)/CN3/RB3
5
4
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14(1)/CN14/RB14
PWM2H/RP13(1)/CN13/RB13
TCK/RP12(1)/CN12/RB12
TMS/RP11(1)/CN11/RB11
VSS
VCAP
PGEC1/SDA/RP7(1)/CN7/RB7
PGED1/TDI/SCL/RP6(1)/CN6/RB6
TDO/RP5(1)/CN5/RB5
PGEC3/RP15(1)/CN15/RB15
MCLR
AN0/RA0
AN1/RA1
AN2/RA2
AN3/RP0(1)/CN0/RB0
AN4/RP9(1)/CN9/RB9
AN5/RP10(1)/CN10/RB10
VSS
OSC1/CLKIN/RP1(1)/CN1/RB1
OSC2/CLKO/RP2(1)/CN2/RB2
PGEC2/RP4(1)/CN4/RB4
VDD
PGED3/RP8(1)/CN8/RB8
1011
2
3
6
1
18
19
20
21
22
121314 15
8
716
17
232425262728
9
dsPIC33FJ06GS202
PGED2/DACOUT/INT0/RP3(1)/CN3/RB3
5
4
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14(1)/CN14/RB14
PWM2H/RP13(1)/CN13/RB13
TCK/RP12(1)/CN12/RB12
TMS/RP11(1)/CN11/RB11
VSS
VCAP
PGEC1/SDA/RP7(1)/CN7/RB7
PGED1/TDI/SCL/RP6(1)/CN6/RB6
TDO/RP5(1)/CN5/RB5
PGEC3/RP15(1)/CN15/RB15
MCLR
AN0/CMP1A/RA0
AN1/CMP1B/RA1
AN2/CMP1C/CMP2A/RA2
AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
AN4/CMP2C/RP9(1)/CN9/RB9
AN5/CMP2D/RP10(1)/CN10/RB10
VSS
OSC1/CLKIN/RP1(1)/CN1/RB1
OSC2/CLKO/RP2(1)/CN2/RB2
PGEC2/EXTREF/RP4(1)/CN4/RB4
VDD
PGED3/RP8(1)/CN8/RB8
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be
connected to VSS externally.
= Pins are up to 5V tolerant
= Pins are up to 5V tolerant
28-Pin QFN-S
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 6 2008-2014 Microchip Technology Inc.
Pin Diagrams (Continued)
28-Pin QFN-S(2)
1011
2
3
6
1
18
19
20
21
22
121314 15
8
716
17
232425262728
9
dsPIC33FJ16GS402
PGED2/INT0/RP3(1)/CN3/RB3
5
4
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14(1)/CN14/RB14
PWM2H/RP13(1)/CN13/RB13
TCK/PWM3L/RP12(1)/CN12/RB12
TMS/PWM3H/RP11(1)/CN11/RB11
VSS
VCAP
PGEC1/SDA/RP7(1)/CN7/RB7
PGED1/TDI/SCL/RP6(1)/CN6/RB6
TDO/RP5(1)/CN5/RB5
PGEC3/RP15(1)/CN15/RB15
MCLR
AN0/RA0
AN1/RA1
AN2/RA2
AN3/RP0(1)/CN0/RB0
AN4/RP9(1)/CN9/RB9
AN5/RP10(1)/CN10/RB10
VSS
OSC1/CLKIN/AN6/RP1(1)/CN1/RB1
OSC2/CLKO/AN7/RP2(1)/CN2/RB2
PGEC2/RP4(1)/CN4/RB4
VDD
PGED3/RP8(1)/CN8/RB8
1011
2
3
6
1
18
19
20
21
22
121314 15
8
716
17
232425262728
9
dsPIC33FJ16GS502
PGED2/DACOUT/INT0/RP3(1)/CN3/RB3
5
4
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14(1)/CN14/RB14
PWM2H/RP13(1)/CN13/RB13
TCK/PWM3L/RP12(1)/CN12/RB12
TMS/PWM3H/RP11(1)/CN11/RB11
VSS
VCAP
PGEC1/SDA/RP7(1)/CN7/RB7
PGED1/TDI/SCL/RP6(1)/CN6/RB6
TDO/RP5(1)/CN5/RB5
PGEC3/RP15(1)/CN15/RB15
MCLR
AN0/CMP1A/RA0
AN1/CMP1B/RA1
AN2/CMP1C/CMP2A/RA2
AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9
AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10
VSS
OSC1/CLKIN/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1
OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2
PGEC2/EXTREF/RP4(1)/CN4/RB4
VDD
PGED3/RP8(1)/CN8/RB8
28-Pin QFN-S, UQFN(2,3)
= Pins are up to 5V tolerant
= Pins are up to 5V tolerant
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be
connected to VSS externally.
3: This package is available only in Extended temperature and not Industrial temperature (applies to
dsPIC33FJ16GS502 UQFN package only).
2008-2014 Microchip Technology Inc. DS70000318G-page 7
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Pin Diagrams (Continued)
44 -Pi n VTLA(2)
AN4/RP9(1)/CN9/RB9
AN5/RP10(1)/CN10/RB10
OSC1/CLKI/AN6/RP1(1)/CN1/RB1
OSC2/CLKO/AN7/RP2(1)/CN2/RB2
RP17(1)/CN17/RC1
RP26(1)/CN26/RC10
VDD
RP25(1)/CN25/RC9
VSS
PGED1/TDI/SCL/RP6(1)/CN6/RB6
RP18(1)/CN18/RC2
PGEC3/RP15(1)/CN15/RB15
VDD
PGEC2/RP4(1)/CN4/RB4
RP24(1)/CN24/RC8
VSS
TDO/RP5(1)/CN5/RB5
PGED3/RP8(1)/CN8/RB8
RP23(1)/CN23/RC7
PGED2/INT0/RP3(1)/CN3/RB3
PWM2H/RP13(1)/CN13/RB13
TCK/PWM3L/RP12(1)/CN12/RB12
TMS/PWM3H/RP11(1)/CN11/RB11
VCAP
VSS
RP20(1)/CN20/RC4
RP19(1)/CN19/RC3
RP22(1)/CN22/RC6
RP21(1)/CN21/RC5
PGEC1/SDA/RP7(1)/CN7/RB7
PWM2L/RP14(1)/CN14/RB14
AN3/RP0(1)/CN0/RB0
AN2/RA2
AN1/RA1
AN0/RA0
MCLR
RP29(1)/CN29/RC13
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
RP16(1)/CN16/RC0
RP28(1)/CN28/RC12
RP27(1)/CN27/RC11
= Pins are up to 5V tolerant
1
12
41 40 39 38 37 36 35 34
2
3
4
5
6
7
8
30
29
28
27
26
25
24
23
13 14 15 16 17 18 19
9
10
11 2220 21
33
32
31
424344
dsPIC33FJ16GS404
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be
connected to VSS externally.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 8 2008-2014 Microchip Technology Inc.
Pin Diagrams (Continued)
44-Pin VTLA(2)
AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9
AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10
OSC1/CLKI/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1
OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2
AN8/CMP4C/RP17(1)/CN17/RC1
AN10/RP26(1)/CN26/RC10
VDD
AN11/RP25(1)/CN25/RC9
VSS
PGED1/TDI/SCL/RP6(1)/CN6/RB6
AN9/EXTREF/CMP4D/RP18(1)/CN18/RC2
PGEC3/RP15(1)/CN15/RB15
VDD
PGEC2/RP4(1)/CN4/RB4
RP24(1)/CN24/RC8
VSS
TDO/RP5(1)/CN5/RB5
PGED3/RP8(1)/CN8/RB8
RP23(1)/CN23/RC7
PGED2/DACOUT/INT0/RP3(1)/CN3/RB3
PWM2H/RP13(1)/CN13/RB13
TCK/PWM3L/RP12(1)/CN12/RB12
TMS/PWM3H/RP11(1)/CN11/RB11
VCAP
VSS
RP20(1)/CN20/RC4
RP19(1)/CN19/RC3
RP22(1)/RN22/RC6
RP21(1)/CN21/RC5
PGEC1/SDA/RP7(1)/CN7/RB7
PWM2L/RP14(1)/CN14/RB14
AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
AN2/CMP1C/CMP2A/RA2
AN1/CMP1B/RA1
AN0/CMP1A/RA0
MCLR
RP29(1)/CN29/RC13
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
RP16(1)/CN16/RC0
RP28(1)/CN28/RC12
RP2 7(1)/CN27/RC11
= Pins are up to 5V tolerant
1
12
41 40 39 38 37 36 35 34
2
3
4
5
6
7
8
30
29
28
27
26
25
24
23
13 14 15 16 17 18 19
9
10
11 22
20 21
33
32
31
424344
dsPIC33FJ16GS504
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be
connected to VSS externally.
2008-2014 Microchip Technology Inc. DS70000318G-page 9
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Pin Diagrams (Continued)
44-Pin QFN(2)
44
dsPIC33FJ16GS404
43 42 41 40 39 38 37 36 35
12 13 14 15 16 17 18 19 20 21
330
29
28
27
26
25
24
23
4
5
7
8
9
10
11
1
232
31
6
22
33
34
AN4/RP9(1)/CN9/RB9
AN5/RP10(1)/CN10/RB10
OSC1/CLKI/AN6/RP1(1)/CN1/RB1
OSC2/CLKO/AN7/RP2(1)/CN2/RB2
RP17(1)/CN17/RC1
RP26(1)/CN26/RC10
VDD
RP25(1)/CN25/RC9
VSS
PGED1/TDI/SCL/RP6(1)/CN6/RB6
RP18(1)/CN18/RC2
PGEC3/RP15(1)/CN15/RB15
VDD
PGEC2/RP4(1)/CN4/RB4
RP24(1)/CN24/RC8
VSS
TDO/RP5(1)/CN5/RB5
PGED3/RP8(1)/CN8/RB8
RP23(1)/CN23/RC7
PGED2/INT0/RP3(1)/CN3/RB3
PWM2H/RP13(1)/CN13/RB13
TCK/PWM3L/RP12(1)/CN12/RB12
TMS/PWM3H/RP11(1)/CN11/RB11
VCAP
VSS
RP20(1)/CN20/RC4
RP19(1)/CN19/RC3
RP22(1)/CN22/RC6
RP21(1)/CN21/RC5
PGEC1/SDA/RP7(1)/CN7/RB7
PWM2L/RP14(1)/CN14/RB14 AN3/RP0(1)/CN0/RB0
AN2/RA2
AN1/RA1
AN0/RA0
MCLR
RP29(1)/CN29/RC13
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
RP16(1)/CN16/RC0
RP28(1)/CN28/RC12
RP27(1)/CN27/RC11
= Pins are up to 5V tolerant
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be
connected to VSS externally.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 10 2008-2014 Microchip Technology Inc.
Pin Diagrams (Continued)
44-Pin QFN(2)
44
dsPIC33FJ16GS504
43 42 41 40 39 38 37 36 35
12 13 14 15 16 17 18 19 20 21
330
29
28
27
26
25
24
23
4
5
7
8
9
10
11
1
232
31
6
22
33
34
AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9
AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10
OSC1/CLKI/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1
OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2
AN8/CMP4C/RP17(1)/CN17/RC1
AN10/RP26(1)/CN26/RC10
VDD
AN11/RP25(1)/CN25/RC9
VSS
PGED1/TDI/SCL/RP6(1)/CN6/RB6
AN9/EXTREF/CMP4D/RP18(1)/CN18/RC2
PGEC3/RP15(1)/CN15/RB15
VDD
PGEC2/RP4(1)/CN4/RB4
RP24(1)/CN24/RC8
VSS
TDO/RP5(1)/CN5/RB5
PGED3/RP8(1)/CN8/RB8
RP23(1)/CN23/RC7
PGED2/DACOUT/INT0/RP3(1)/CN3/RB3
PWM2H/RP13(1)/CN13/RB13
TCK/PWM3L/RP12(1)/CN12/RB12
TMS/PWM3H/RP11(1)/CN11/RB11
VCAP
VSS
RP20(1)/CN20/RC4
RP19(1)/CN19/RC3
RP22(1)/RN22/RC6
RP21(1)/CN21/RC5
PGEC1/SDA/RP7(1)/CN7/RB7
PWM2L/RP14(1)/CN14/RB14 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
AN2/CMP1C/CMP2A/RA2
AN1/CMP1B/RA1
AN0/CMP1A/RA0
MCLR
RP29(1)/CN29/RC13
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
RP16(1)/CN16/RC0
RP28(1)/CN28/RC12
RP27(1)/CN27/RC11
= Pins are up to 5V to lerant
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be
connected to VSS externally.
2008-2014 Microchip Technology Inc. DS70000318G-page 11
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Pin Diagrams (Continued)
44-Pin TQFP
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
PGED1/TDI/SCL/RP6(1)/CN6/RB6
RP18(1)/CN18/RC2
PGEC3/RP15(1)/CN15/RB15
VDD
PGEC2/RP4(1)/CN4/RB4
RP16(1)/CN16/RC0
VSS
TDO/RP5(1)/CN5/RB5
PGED3/RP8(1)/CN8/RB8
RP23(1)/CN23/RC7
AN3/RP0(1)/CN0/RB0
AN2/RA2
AN1/RA1
AN0/RA0
MCLR
RP29(1)/CN29/RC13
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
PWM2H/RP13(1)/CN13/RB13
TCK/PWM3L/RP12(1)/CN12/RB12
TMS/PWM3H/RP11(1)/CN11/RB11
VSS
VCAP
RP19(1)/CN19/RC3
RP22(1)/CN22/RC6
RP21(1)/CN21/RC5
PGEC1/SDA/RP7(1)/CN7/RB7
AN4/RP9(1)/CN9/RB9
AN5/RP10(1)/CN10/RB10
OSC1/CLKI/AN6/RP1(1)/CN1/RB1
OSC2/CLKO/AN7/RP2(1)/CN2/RB2
RP17(1)/CN17/RC1
RP20(1)/CN20/RC4
VDD
VSS
RP27(1)/CN27/RC11
RP28(1)/CN28/RC12
PGED2/INT0/RP3(1)/CN3/RB3
dsPIC33FJ16GS404
PWM2L/RP14(1)/CN14/RB14
RP24(1)/CN24/RC8
RP25(1)/CN25/RC9
RP26(1)/CN26/RC10
= Pins are up to 5V tolerant
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 12 2008-2014 Microchip Technology Inc.
Pin Diagrams (Continued)
44-Pin TQFP
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
PGED1/TDI/SCL/RP6(1)/CN6/RB6
AN9/EXTREF/CMP4D/RP18(1)/CN18/RC2
PGEC3/RP15(1)/CN15/RB15
VDD
PGEC2/RP4(1)/CN4/RB4
RP16(1)/CN16/RC0
VSS
TDO/RP5(1)/CN5/RB5
PGED3/RP8(1)/CN8/RB8
RP23(1)/CN23/RC7
AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
AN2/CMP1C/CMP2A/RA2
AN1/CMP1B/RA1
AN0/CMP1A/RA0
MCLR
RP29(1)/CN29/RC13
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
PWM2H/RP13(1)/CN13/RB13
TCK/PWM3L/RP12(1)/CN12/RB12
TMS/PWM3H/RP11(1)/CN11/RB11
VSS
VCAP
RP19(1)/CN19/RC3
RP22(1)/CN22/RC6
RP21(1)/CN21/RC5
PGEC1/SDA/RP7(1)/CN7/RB7
AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9
AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10
OSC1/CLKI/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1
OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2
AN8/CMP4C/RP17(1)/CN17/RC1
RP20(1)/CN20/RC4
VDD
VSS
RP27(1)/CN27/RC11
RP28(1)/CN28/RC12
PGED2/DACOUT/INT0/RP3(1)/CN3/RB3
dsPIC33FJ16GS504
PWM2L/RP14(1)/CN14/RB14
RP24(1)/CN24/RC8
AN11/RP25(1)/CN25/RC9
AN10/RP26(1)/CN26/RC10
= Pins are up to 5V tolerant
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2008-2014 Microchip Technology Inc. DS70000318G-page 13
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Table of Contents
dsPIC33FJ06GS101/X02 AND dsPIC33FJ16GSX02/X04 Product Families......................................................................................... 2
1.0 Device Overview ........................................................................................................................................................................ 17
2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers...................................... .... .... ......... ................................... 21
3.0 CPU............................................................................................................................................................................................ 31
4.0 Memory Organization................................................................................................................................................................. 43
5.0 Flash Prog ram Memory.................. ................. ...... ................. ...... ................. ...... ....................................................................... 83
6.0 Resets ....................................................................................................................................................................................... 89
7.0 Interr u p t Controller.......... ...... ....... ...... ...... ....... ...... ...... ....... ................ ....... ...... ...... ....... .............................................................. 97
8.0 Oscillator Configuration ......................................................................................................................................................... 135
9.0 Power-S a ving Features.................... ...... ................. ...... ................. ...... ................. ....... ............................................................ 147
10.0 I/O Ports........... ....... ................. ...... ................. ................ ................. ....... ................................................................................. 155
11.0 Timer1...................................................................................................................................................................................... 183
12.0 Timer2/3 Features ...... ...... ....... ...... ...... ................. ...... ....... ................ ....... ...... ......................................................................... 185
13.0 Input Capture......................... ....... .... .. .... .. ....... .... .. .... .. .. ......... .. .... .. .. .... ....... .. .... .. .... .. ............................................................... 191
14.0 Output Compare...... ...... ...... ....... ...... ................. ...... ................. ...... ...... ................. ....... ............................................................ 193
15.0 High-Speed PWM.... ...... ...... ................. ...... ................. ....... ................ ....... ................ ............................................................... 197
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 219
17.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 225
18.0 Universal Asynchr onous Receiver Transmitter (UART ).... ....................................................................................................... 233
19.0 High-Speed 10-bit An a l o g -to-Digi ta l Co nve rter (ADC)....... ...... ............ ....... ...... ............. ...... ...... .............................................. 239
20.0 High-Speed Analog Comparator.............. ....... ................ ....... ...... ................. ...... ...... ................ ............................................... 263
21.0 Special Features ...................................................................................................................................................................... 267
22.0 Instruction Set Summary.......................................................................................................................................................... 275
23.0 Development Support. .............................................................................................................................................................. 283
24.0 Electrical Characteristics.......................................................................................................................................................... 287
25.0 High-Temperature Electrical Characteristics............................................................................................................................ 333
26.0 50 MIPS Electrical Characteristics........................................................................................................................................... 341
27.0 DC and AC Device Characteristics Graphs.................................................................................. ............................................ 347
28.0 Packaging Information....... ....... ...... ...... ................. ...... ................. ...... ................. ...... ............................................................... 351
The Micro chip Web Si te.... ...... ...... ....... ................ ................. ....... ................ ................. ...... ............................................................... 393
Customer Change Notification Service.......................................................... ..................... ............................................................... 393
Customer Support.............................................................................................................................................................................. 393
Product Identification System ............................................................................................................................................................ 395
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 14 2008-2014 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications t o better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions o r c omm ents regarding this publication, please contact the Marketing Comm unications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determ ine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Micr ochip’s Worldwide Web site; http://www.microchip.com
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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Customer No tific atio n Syst em
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2008-2014 Microchip Technology Inc. DS70000318G-page 15
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33/PIC24 Family Ref-
erence Manual”. These documents should be
considered as the primary reference for the operation
of a particular module or device feature.
• “Introduction” (DS70197)
• “CPU” (DS70204)
•“Data Memory” (DS70202)
• “Program Memory” (DS70203)
• “Flash Programming” (DS70191)
• “Reset” (DS70192)
• “Watchdog Timer (WDT) and Power-Saving Modes” (DS70196)
• “I/O Ports” (DS70193)
•“Timers” (DS70205)
• “Input Capture” (DS70198)
• “Output Comp a re” (DS70005157)
• “Analog-to-Digital Converter (ADC)” (DS70621)
• “UART” (DS70188)
• “Serial Peripheral Interface (SPI)” (DS70206)
• “Inter-Integrated Circuit™ (I2C™)” (DS70000195)
•“CodeGuard™ Security (DS70199)
• “Programming and Diagnostics” (DS70207)
• “Device Configuration” (DS70194)
• “Interrupts (Part IV)” (DS70300)
•“Oscillator (Part IV)” (DS70307)
• “High- Speed PWM Module” (DS70000323)
•“High-Speed 10-Bit ADC” (DS70000321)
•“High-Speed Analog Comparator” (DS70296)
• “Oscillator (Part VI)” (DS70644)
Note: To access the documents listed below,
browse to the documentation section
of the dsPIC33FJ16GS504 product
page of the Microchip web site
(www.microchip.com).
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 16 2008-2014 Microchip Technology Inc.
NOTES:
2008-2014 Microchip Technology Inc. DS70000318G-page 17
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
1.0 DEVICE OVERVIEW This document contains device-specific information for
the following dsPIC33F Digital Signal Controller (DSC)
devices:
• dsPIC33FJ06GS101
• dsPIC33FJ06GS102
• dsPIC33FJ06GS202
• dsPIC33FJ16GS402
• dsPIC33FJ16GS404
• dsPIC33FJ16GS502
• dsPIC33FJ16GS504
ds
PIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04
devices contain extensive Digital Signal Processor
(DSP) functionality with a high-performance, 16-bit
microcontroller (MCU) architecture.
Figure 1-1 shows a general block diagram of the core and
peripheral modules in the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 devices. Table 1-1 lists the
functions of the various pins shown in the pinout diagrams.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a compre-
hensive re ference source. To complement
the information in this data sheet, refer to
the “dsPIC33F/PIC 24H Family Reference
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
“dsPIC33F/PIC24H Family Reference
Manual” sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 18 2008-2014 Microchip Technology Inc.
FIGURE 1-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 BLOCK DIAGRAM
16
OSC1/CLKI
OSC2/CLKO
VDD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
S t a rt -up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
FRC/LPRC
Oscillators
Regulator
Voltage
VCAP
IC1 I2C1
PORTA
Instruction
Decode &
Control
PCH
16
Program Counter
23
23
24
23
PCU
16 x 16
W Register Array
ROM Latch
16
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Addr e s s La tc h
Program Me mor y
Data La tch
Literal Data
16 16
16
16
Data Latch
Address
Latch
16
X RAM
16
Y Data Bus
X Data Bus
DSP En g i ne
Divide Suppo rt
16
Contr ol Sig nals
to Various Blocks
ADC1
Timers
PORTB
Address Generator Units
1-3
CNx
UART1 PWM
4 x 2
Remappable
Pins
PORTC
SPI1
OC1
OC2
Analog
Comparators 1-4
Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and
features present on each device .
PCL
Data Latch
Address
Latch
Y RAM
EA MUX
Instruction Reg
16-Bit ALU
IC2
2008-2014 Microchip Technology Inc. DS70000318G-page 19
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Name Pin
Type Buffer
Type PPS
Capable Description
AN0-AN11 I Analog No Analog input channels
CLKI
CLKO
I
O
ST/CMOS
—
No
No
External clock source input. Always associated with OSC1 pin
function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC
modes. Always associated with OSC2 pin function.
OSC1
OSC2
I
I/O
ST/CMOS
—
No
No
Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC
modes.
CN0-CN29 I ST No Change Notification inputs. Can be software programmed for
interna l weak pull-ups on all inputs.
IC1-IC2 I ST Yes Capture Inputs 1/2.
OCFA
OC1-OC2 I
OST
—Yes
Yes Compare Fault A input (for Compare Channels 1 and 2)
Compare Outputs 1 throug h 2.
INT0
INT1
INT2
I
I
I
ST
ST
ST
No
Yes
Yes
External Interrupt 0.
External Interrupt 1.
External Interrupt 2.
RA0-RA4 I/O ST No PORTA is a bidirectional I/O port.
RB0-RB15 I/O ST No PORTB is a bidirectional I/O port.
RC0-RC13 I/O ST No PORTC is a bidirectional I/O port.
RP0-RP29 I/O ST No Remappable I/O pins.
T1CK
T2CK
T3CK
I
I
I
ST
ST
ST
Yes
Yes
Yes
Timer 1 external clock in put.
Timer 2 external clock in put.
Timer 3 external clock in put.
U1CTS
U1RTS
U1RX
U1TX
I
O
I
O
ST
—
ST
—
Yes
Yes
Yes
Yes
UART1 Clear-To-Send.
UART1 Ready-To-Send.
UART1 receive.
UART1 transmit.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I/O
ST
ST
—
ST
Yes
Yes
Yes
Yes
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
SCL1
SDA1 I/O
I/O ST
ST No
No Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
TMS
TCK
TDI
TDO
I
I
I
O
TTL
TTL
TTL
—
No
No
No
No
JTAG Test mode sele ct pin .
JTAG test clock in put pin.
JTAG test data input pin.
JTAG test data output pin.
Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input
ST = Schmitt Trigger input with CMOS levels P = Power O = Output
TTL = Transistor-Transistor Logic PPS = Peripheral Pin Select
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 20 2008-2014 Microchip Technology Inc.
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
CMP3A
CMP3B
CMP3C
CMP3D
CMP4A
CMP4B
CMP4C
CMP4D
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Comparator 1 Channel A.
Comparator 1 Channel B.
Comparator 1 Channel C.
Comparator 1 Channel D.
Comparator 2 Channel A.
Comparator 2 Channel B.
Comparator 2 Channel C.
Comparator 2 Channel D.
Comparator 3 Channel A.
Comparator 3 Channel B.
Comparator 3 Channel C.
Comparator 3 Channel D.
Comparator 4 Channel A.
Comparator 4 Channel B.
Comparator 4 Channel C.
Comparator 4 Channel D.
DACOUT O — No DAC output voltage.
ACMP1-ACMP4 O — Yes DAC trigge r to PWM module.
EXTREF I Analog No External voltage reference input for the reference DACs.
REFCLKO O — Yes REFCLKO output signal is a postscaled derivative of the system
clock.
FLT1-FLT8
SYNCI1-SYNCI2
SYNCO1
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
I
I
O
O
O
O
O
O
O
O
O
ST
ST
—
—
—
—
—
—
—
—
—
Yes
Yes
Yes
No
No
No
No
No
No
Yes
Yes
Fault Inputs to PWM module.
External synchronization signal to PWM master time base.
PWM master time base for external device synchronization.
PWM1 low output.
PWM1 high output.
PWM2 low output.
PWM2 high output.
PWM3 low output.
PWM3 high output.
PWM4 low output.
PWM4 high output.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for programming /debugging C om munication C hannel 1.
Clock input pin for programming/debugging Communication
Chann el 1.
Data I/O pin for programming /debugging C om munication C hannel 2.
Clock input pin for programming/debugging Communication
Chann el 2.
Data I/O pin for programming /debugging C om munication C hannel 3.
Clock input pin for programming/debugging Communication
Chann el 3.
MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AVDD P P No Positive supply for analog modules . This pin must be connected a t
all times. AVDD is connected to VDD.
AVSS P P No Ground reference for analog modules. AVSS is connected to VSS.
VDD P — No Positive supply for peripheral logic and I/O pins.
VCAP P — No CPU logic filter capacitor connection.
VSS P — No Ground reference for logic and I/O pins.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin
Type Buffer
Type PPS
Capable Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input
ST = Schmitt Trigger input with CMOS levels P = Power O = Output
TTL = Transistor-Transistor Logic PPS = Peripheral Pin Select
2008-2014 Microchip Technology Inc. DS70000318G-page 21
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
2.0 GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS
2.1 Basic Connection Requirements
Getting started with the dsPIC33FJ06GS101/X02 and
dsPIC33FJ 16GSX02/X04 fam ily of 16- bit Digit al Signal
Control lers (DSC) re quires a ttentio n to a min imal set of
device pin connections before proceeding with
development. The following is a list of pin names, which
must always be connected:
•All V
DD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
•All AV
DD and AVSS pins (regardless if ADC module
is no t used)
(see Section 2.2 “Decoupling Capacitors”)
•VCAP
(see Section 2.3 “Capacitor on Internal Voltage
Regulator (VCAP)”)
•MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP™ Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
2.2 Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
•Value and type of capa cito r: Reco mm endation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be u s ed.
•Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capac itor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
•Handli ng high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, ad d a second c eramic-type capac itor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to th e pri m ary de coupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
•Maximiz ing perform anc e: On the board layout
from the power supply circuit, run the power and
return traces to the decou pli ng ca p ac ito rs first,
and then to the dev ic e pi ns. This en su res that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
Note 1: This data sh eet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data she et for device-specific regis ter
and bit information.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 22 2008-2014 Microchip Technology Inc.
FIGURE 2-1: RECOMMENDE D
MINIMUM CONNECTION
2.2. 1 TANK CAP ACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that con-
nects the power supply source to the device, and the
maximum current drawn by the device in the applica-
tion. In other words, select the tank capacitor so that it
meet s the ac ceptable volta ge sag at th e device. Typical
values range from 4.7 µF to 47 µF.
2.3 Capacitor on Internal Volt age
Regulator (VCAP)
A low-ESR (<5 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connec ted to V DD, and m us t h ave a capac it or b etween
4.7 µF and 10 µF, 16V connected to ground. The ty p e
can be ceramic or tantalum. Refer to Section 24.0
“Electrical Characteristics” for additional information.
The placement of this capacitor should be close to the
VCAP. It is recommended that the trace length not
exceed one-quarter inch (6 mm ). Refer to Section 21.2
“On-Chip Voltage Regulator” for details.
2.4 Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions:
• Device Reset
• Device programming and debugging.
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
dsPIC33F
VDD
VSS
VDD
VSS
VSS
VDD
AVDD
AVSS
VDD
VSS
0.1 µF
Ceramic 0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
C
R
VDD
MCLR
0.1 µF
Ceramic
VCAP
L1(1)
R1
10 µF
Tantalum
Note 1: As an option, instead of a hard-wired connection, an
inductor (L1) can be substitu ted between VDD and
AVDD to improv e ADC noise rej ection. Th e inducto r
impedance should be less than 1 and t he in du c tor
capacity greater than 10 mA.
Where:
fFCNV
2
--------------=
f1
2LC
-----------------------=
L1
2fC
----------------------
2
=
(i.e., ADC conversion rate/2)
Note 1: R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
2: R1 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
C
R1
R
VDD
MCLR
dsPIC33F
JP
2008-2014 Microchip Technology Inc. DS70000318G-page 23
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
2.5 ICS P™ Pi ns
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging
purposes. It is recommended to keep the trace length
betwee n th e ICSP c onn ec tor an d th e ICSP pi ns on th e
device as short as possible. If the ICSP connector is
expect ed to experience an ESD eve nt, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capa citors on the
PGECx and PGEDx pins are not re commended as the y
will interfere with the programmer/debugger
communications to the device. If such discrete
components are an application requirement, they
should be removed from the circuit during program-
ming and debugging. Alternatively, refer to the AC/DC
characteristics and timing requirements information in
the respec ti ve de vi ce Flash pro gramm ing spe cif ic ation
for inform ation on capacitive loa ding limits and pin input
voltage high (VIH) and input low (VIL) requirements.
Ensure that the “Communication Channel Select”
(i.e., PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB® REAL ICE™.
For more information on ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are avai lable on the Microchip web site.
•“Using MPLAB® ICD 3” (poster) DS51765
•“MPLAB® ICD 3 Design Advisory” DS51764
•“MPLAB® REAL ICE™ In-Circuit Debugger
User’s Guide” DS51616
•“Using MPLAB® REAL ICE™” (poster) DS51749
2.6 External Oscillator Pins
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
trac es or powe r trac es ins ide t he gr ound pour. A lso, i f
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggeste d layout is shown in Figure 2-3.
FIGURE 2-3: SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
2.7 Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < FIN < 8 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can init ialize th e PLL SFR s, CLKDIV, and PL LFBD to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration Word.
13
Main Oscillator
Guard Ring
Guard Trace
Secondary
Oscillator
14
15
16
17
18
19
20
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 24 2008-2014 Microchip Technology Inc.
2.8 Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a
debugger, it autom atic al ly ini tia liz es al l of the A/D input
pins (ANx) as “digital” pins, by setting all bits in the
ADPCFG register.
The bit s in th e register s that correspond to the A/D pins
that are initialized by MPLAB ICD 2, ICD 3, or REAL
ICE, must not be cleared by the user application firm-
ware; otherwise, communication errors will result
between the debugger and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
ADPCFG register during initialization of the ADC module.
When MPLAB ICD 2, ICD 3, or REAL ICE is used as a
programmer , the user application firmware must correctly
configure the ADPCFG register. Automatic initialization
of these registers is only done during debugger opera-
tion. Failure to correctly configure the register(s) will
result in all A/D pins being recognized as analog input
pins, resulting in the port value being read as a logic ‘0’,
which may affect user application functionality.
2.9 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternativ ely, connect a 1k to 10k resistor be twee n VSS
and unused pins and drive the output to logic low.
2.10 Typical Application Connection
Examples
Example s of ty pical app licati on con necti ons are shown
in Figure 2-4 through Figure 2-11.
2008-2014 Microchip Technology Inc. DS70000318G-page 25
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 2-4: DIGITAL PFC
FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION
VAC
IPFC
VHV_BUS
ADC Channel ADC Channel ADC ChannelPWM Output
|VAC|
k1
k2
k3
FET
dsPIC33FJ06GS101
Driver
IPFC
VOUTPUT
ADC Channel ADC ADC ChannelPWM
k1
k2
k3
FET
dsPIC33FJ06GS101
VINPUT
Channel Output
Driver
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 26 2008-2014 Microchip Technology Inc.
FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER
FIGURE 2-7: MULTI-PHASE SYNCHRONOUS BUCK CONVERTER
k1
Analog
Comp.
k2
k7
PWM
PWM
ADC
Channel
ADC
Channel
5V Output
I5V
12V Input
dsPIC33FJ06GS202
FET
Driver
k5
k4
k3
k6
k7
Analog Comparator
Analog Comparator
ADC Channel
Analog Comparator
ADC
Channel
PWM
PWM
PWM
PWM
PWM
PWM
3.3V Output
12V Input
FET
Driver FET
Driver
FET
Driver
dsPIC33FJ06GS502
2008-2014 Microchip Technology Inc. DS70000318G-page 27
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 2-8: OFF-LINE UPS
ADC
ADC
ADC
ADC
ADC
PWM PWMPWM
dsPIC33FJ16GS504
PWM PWM PWM
FET
Driver FET
Driver k2k1FET
Driver FET
Driver FET
Driver FET
Driver k4k5
V
BAT
GND
+
V
OUT
+
V
OUT
-
Full-Bridge Inverter
Push-Pull Converter VDC
GND
FET
Driver
ADC
PWM
k3
k6
or
Analog Comp.
Battery Charger
+
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 28 2008-2014 Microchip Technology Inc.
FIGURE 2-9: INTERLEAVED PFC
VAC
VOUT+
ADC Channel PWM ADC
PWM
|VAC|
k4k3
FET
dsPIC33FJ06GS202
Driver
VOUT-
ADC Channel
FET
Driver
ADC
k1k2
Channel Channel
ADC
Channel
2008-2014 Microchip Technology Inc. DS70000318G-page 29
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 2-10: PHASE-SH IFTED FULL-BRIDGE CONVERTER
VIN+
VIN-
S1
Gate 4
Gate 2
Gate 3
Gate 1
Analog
Ground
VOUT+
VOUT-
k2
FET
Driver
k1
FET
Driver
FET
Driver
Gate 1
Gate 2
S1 Gate 3
Gate 4
S3
S3
Gate 6
Gate 5
Gate 6
Gate 5
dsPIC33FJ06GS202
PWM
PWM ADC
Channel PWM ADC
Channel
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 30 2008-2014 Microchip Technology Inc.
FIGURE 2-11: AC-TO-DC POWER SUPPLY WITH PFC AND THREE OUTPUTS (12V, 5V AND 3.3V)
k4
ADC
Channel
PWM
UART
RX
PWM
PWM
IZVT
VHV_BUS VOUT
Isolation
Barrier
ADC
Channel
PWM
PWM
PWM
FET
Driver FET
Driver FET
Driver
dsPIC33FJ16GS504 k6
Analog
Comp.
UART
TX k10
k7
k9
k8
k11
k5
PWM
PWM
ADC
Channel
Analog C om par ato r
Analog C om par ato r
ADC Channel
Analog C om par ato r
ADC
Channel
PWM
PWM
PWM
PWM
PWM
PWM
3.3V Output
5V Output
I5V
12V Input
FET
Driver FET
Driver
FET
Driver
FET
Driver
I3.3V_3
I3.3V_2
I3.3V_1
dsPIC33FJ16GS504
VAC
IPFC
VHV_BUS
|VAC|
k1
k2
k3
FET Driver
ADC
Ch. ADC
Ch. PWM
Output ADC
Ch.
PFC Stage
3.3V Multi-Phase Buck Stage
ZVT with Current Doubler Synchronous Rectifie r
5V Buck Stage
Secondary Controller
Primary Controller
2008-2014 Microchip Technology Inc. DS70000318G-page 31
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
3.0 CPU
The CPU module has a 16-bit (data) modified Harvard
arch itecture wi th an enh anced in struct ion set, includin g
significant support for DSP. The CPU has a 24-bit
instruction word with a variable length opcode field.
The Program Counter (PC) is 23 bits wide and
addresses up to 4M x 24 bits of user program memory
space. The actual amount of program memory
implemented varies from device to device. A single-
cycle instruction prefetch mechanism is used to help
maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any point.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices have sixteen, 16-bit Working registers in
the prog rammer’s model. Each of the Working registers
can serv e as a dat a, addres s or address o ff set register.
The sixteenth Working register (W15) operates as a
software Stack Pointer (SP) for interrupts and calls.
There are two classes of instruction in the
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices: MCU and DSP. These two instruction
classes are seamlessly integrated into a single CPU.
The instruction set includes many addressing modes
and is designed for optimum C compiler efficiency. For
most instructions, the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 is capable of executing a
data (or program data) memory read, a Working
register (data) read, a data memory write and a
program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cy cle.
A block diagram of the CPU is shown in Figure 3-1,
and the programmer’s model is shown in Figure 3-2.
3.1 Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU clas s of in struction s operat es so lely thr ough the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also su pports Bit-Rev ers ed Add r essin g to greatl y
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space V is ibili ty Page (PSVPAG) register. The
program-to-data space mapping feature allows any
instruction access program space as if it were data
space.
3.2 DSP Engine Overview
The DSP e ngine features a high-speed, 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is cap able of shif ting a 40-bit value u p
to 16 bits, right or left, in a single cycle. The DSP
instructions operate seamlessly with all other
instructions and have been designed for optimal real-
time performance. The MAC instruction and other
assoc iated instructi ons can concurre ntly fetch two dat a
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM data space be split
for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain Working
registers to each address space.
Note 1: This data sh eet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “CPU” (DS70204) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Micro c hi p w e b si te (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 32 2008-2014 Microchip Technology Inc.
3.3 Special MCU Features
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX0 2/X04
devices feature a 17-bit by 17-bit single-cycle multi-
plier that is shared by both the MCU ALU and DSP
engine. The multiplier can perform signed, unsigned
and mixed sign multiplication. Using a 17-bit by 17-bit
multiplier for 16-bit by 16-bit multiplication not only
allows you to perform mixed sign multiplication, it
also achieves accurate results for special operations,
such as (-1.0) x (1.0).
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices support 16/ 16 and 32/16 divide oper ations,
both fractional and integer. All divide instructions ar e iter-
ative operations. They must be executed within a REPEAT
loop, resulting in a total execution time of 19 instruction
cycles. The divide operation can be interrupted during any
of those 19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
FIGURE 3-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU CORE
BLOCK DIAGRAM
Instruction
Decode &
Control
PCH
Program Counter
24
23
Instruction Reg
PCU
ROM Latch
EA MUX
Interrupt
Controller
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Address
Latch
Control Signals
to Various Blocks
Literal Data
16 16
16
To Peripher al Modu les
Data Latch
Address
Latch
16
X RAM Y RAM
Address Generator Units
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
16
23
23
16
8
PSV & Table
Data Access
Control Block
16
16
16
16
Program Memory
Data Latch
Address Latch
PCL
16 x 16
W Register Arra y
16-Bit ALU
2008-2014 Microchip Technology Inc. DS70000318G-page 33
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 3-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PROGRAMMER’S MODEL
PC22 PC0
7 0
D0D15
Program Counter
Data Table Page Address
STATUS Register
Working Registers
DSP Operand
Registers
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
DSP Address
Registers
AD39 AD0AD31
DSP
Accumulators ACCA
ACCB
7 0Program Space Visibility Page Address
Z
0
OA OB SA SB
RCOUNT
15 0REPEAT Loop Counter
DCOUNT
15 0DO Loop Counter
DOSTART
22 0 DO Loop Start Address
IPL2 IPL1
SPLIM Stack Pointer Limit Register
AD15
SRL
PUSH.S Shadow
DO Shadow
OAB SAB
15 0Core Configuration Register
Legend
CORCON
DA DC RA N
TBLPAG
PSVPAG
IPL0 OV
W0/WREG
SRH
DO Loop End Address
DOEND
22
C
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 34 2008-2014 Microchip Technology Inc.
3.4 CPU Control Registers
REGISTER 3-1: SR: CPU STATUS REGISTER
R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0
OA OB SA(1)SB(1)OAB SAB(1,4)DA DC
bit 15 bit 8
R/W-0(3)R/W-0(3)R/W-0(3)R-0 R/W-0 R/W-0 R/W-0 R/W-0
IPL2(2)IPL1(2)IPL0(2)RA N OV Z C
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set
0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’
bit 15 OA: Accumulator A Overflow Status bit
1 = Accumulator A has overflowed
0 = Accumulator A has not overflowed
bit 14 OB: Accumulator B Overflow Status bit
1 = Accumulator B has overflowed
0 = Accumulator B has not overflowed
bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Ac cum u lator A is no t saturated
bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Ac cum u lator B is no t saturated
bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulator A or B has overflowed
0 = Neither Accumula tor A or B has over flowed
bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit(1,4)
1 = Accumulator A or B is saturated or has been saturated at some time in the past
0 = Neither Accumulator A or B is saturated
bit 9 DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8 DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out fro m the 4th low-order b it (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2 :0> Status bit s are read-only when NSTDIS = 1 (INTCON1<15>).
4: Clearing this bit will clear SA and SB.
2008-2014 Microchip Technology Inc. DS70000318G-page 35
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progres s
bit 3 N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an ov erflow of a magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1 Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0 C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit (MSb) of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED)
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2 :0> Status bit s are read-only when NSTDIS = 1 (INTCON1<15>).
4: Clearing this bit will clear SA and SB.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 36 2008-2014 Microchip Technology Inc.
REGISTER 3-2: CORCON: CORE CONTROL REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0
— — —USEDT
(1)DL2 DL1 DL0
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0
SATA SATB SATDW ACCSAT IPL3(2)PSV RND IF
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set
0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’
bit 15-1 3 Unimplemented: Read as ‘0’
bit 12 US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
bit 11 EDT: Early DO Loop Termination Control bit(1)
1 = Terminate executing DO loop at end of current loop iteration
0 = No effect
bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops are active
•
•
•
001 = 1 DO loop is active
000 = 0 DO loops are active
bit 7 SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation is enabled
0 = Accumulator A saturation is disabled
bit 6 SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation is enabled
0 = Accumulator B saturation is disabled
bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation is enabled
0 = Data space write saturation is disabled
bit 4 ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
bit 2 PSV: Program Space Visibility in Data Space Enable bit
1 = Pr ogram space is visible i n data space
0 = Pr ogram space is not visib le in data space
Note 1: This bit will always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
2008-2014 Microchip Technology Inc. DS70000318G-page 37
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
bit 1 RND: Rounding Mode Select bit
1 = Biased (conventional) rounding is enabled
0 = Unbiased (convergent) rounding is enabled
bit 0 IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode is enabled for DSP multiply ops
0 = Fractional mode is enabled for DSP multiply ops
REGISTER 3-2: CORCON: CORE CONTROL REGISTER (CONTINUED)
Note 1: This bit will always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 38 2008-2014 Microchip Technology Inc.
3.5 Arithmetic Logic Unit (ALU)
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 ALU is 16 bits wide and is capable of addition,
subtraction, bit shifts and logic operations. Unless
otherwise me ntione d, ar ithmet ic o perat ions are 2’s com-
plement in nature. Depending on the operation, the ALU
can affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC) Status
bits in the SR register. The C and DC St atus bits operate
as Borrow and Digit Borrow bits, respectively, for
subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
Refer to the “16-bit MCU and DSC Programmer’s
Reference Manual” (DS70157) for information on the
SR bi ts affected by each instruction.
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 CPU incorporates hardware support for both multipli-
cation and di vision. This incl udes a dedicated ha rdware
multiplier and support hardware for 16-bit-divisor division.
3.5.1 MULTIPLIER
Using the high-speed, 17-bit x 17-bit multiplier of the
DSP engine, the ALU supports unsigned, signed or
mixed sign operation in several MCU multiplication
modes:
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
3.5.2 DIVIDER
The divide block suppor ts 32-bit/16-bit an d 16-bit/16-bit
signed and un signed i nteg er d iv ide op erat ions with th e
following data sizes:
• 32-bit signed/16-bit signed divide
• 32-bit unsigned/16-bit unsigned divide
• 16-bit signed/16-bit signed divide
• 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0 and
the remainder in W1. The 16-bit signed and unsigned
DIV instru ctions can sp ecif y any W r egis ter fo r bot h the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide
algori thm takes one cycle per bit of divisor , so both 32-bit/
16-bit and 16-bit/16-bit instructions take the same
numbe r of cy cles to ex ecute.
3.6 DSP Engine
The DSP eng ine cons ist s of a high-spee d, 17-b it x 17-bit
multiplier, a barrel shifter and a 40-bit adder/subtracter
(with two target accumulators, round and saturation
logic).
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 is a single-cycle instruction flow architecture;
therefore, concur rent opera tion of th e DSP engine with
MCU instruction flow is not possible. However, some
MCU ALU and DSP engine resources can be used
concurrently by the same instruction (for example, ED,
EDAC).
The DSP engine can also perform inherent
accum ula tor-to -ac cu mulator ope rati on s tha t require no
additional data. These instructions are ADD, SUB and
NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
• Fractional or Integer DSP Multiply (IF)
• Signed or Unsigned DSP Multiply (US)
• Conventional or Convergent Rounding (RND)
• Automatic Saturation On/Off for ACCA (SATA)
• Automatic Saturation On/Off for ACCB (SATB)
• Automatic Saturation On/Off for Writes to Data
Memory (SATDW)
• Accumulator Saturation mode Selection
(ACCSAT)
A block diagram of the DSP engine is shown in
Figure 3-3.
TABLE 3-1: DSP INSTRUCTIONS
SUMMARY
Instruction Algebraic
Operation ACC
Write Back
CLR A = 0 Yes
ED A = (x – y)2No
EDAC A = A + (x – y)2No
MAC A = A + (x * y) Yes
MAC A = A + x2No
MOVSAC No change in A Yes
MPY A = x * y No
MPY A = x 2No
MPY.N A = – x * y No
MSC A = A – x * y Yes
2008-2014 Microchip Technology Inc. DS70000318G-page 39
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM
Zero Backfill
Sign-Extend
Barrel
Shifter
40-Bit Accumulator A
40-Bit Accumulator B Round
Logic
X Data Bus
To/F rom W Array
Adder
Negate
32
32
33
16
16 16
16
40 40
40 40
S
a
t
u
r
a
t
e
Y Data Bus
40
Carry/Borrow Out
Carry/Borrow In
16
40
Saturate
Multiplier/Scaler
17-Bit
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 40 2008-2014 Microchip Technology Inc.
3.6.1 MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsign ed op eration an d can m ultiplex its output u sing a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multi plier /scale r is a 33-bit valu e that i s sign -ext ended
to 40 bits. Integer data is inherently represented as a
signed 2’s complement value, where the Most
Signific ant bit (MSb) is defined as a sign bit. Th e range
of an N-bit 2’s complement integer is -2N-1 to 2N-1 – 1.
• For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF ), incl udi ng 0.
• For a 32-bit integer, the data range is
-2,147,48 3,6 48 (0x 800 0 0000) to 2,147,483,647
(0x7FFF FFFF).
When the multiplier is configured for fractional
multiplication, the data is represented as a 2’s
complement fraction, where the MSb is defined as a
sign bit an d the radi x point i s impli ed to lie just af ter the
sign bit (QX format). The range of an N-bit
2’s complement fraction with this implied radix point is
-1.0 to (1 – 21-N). For a 16-bit fraction, the Q15 data
range is -1.0 (0x8000) to 0.999969482 (0x7FFF)
including 0 and has a precision of 3.01518x10-5. In
Fractional mode, the 16 x 16 multiply operation
generates a 1.31 product that has a precision of
4.65661 x 10-10.
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiply operations.
The MUL instruction can be directed to use byte or
word-size d operands . Byte operan ds will dire ct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3.6.2 DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its pre-
accumulation source and post-accumulation
dest ina tio n. F or the ADD an d LAC instructions, the da t a
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
3.6.2.1 Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero inpu t into on e side, and either tru e or comp leme nt
data into the other input.
• In the case of addition, the Carry/Borrow input is
active-high and the other input is true data (not
complemented).
• In the case of subtraction, the Carry/Borrow input
is activ e-low and the ot her inpu t is comple mente d.
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS Re gister:
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits, 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described previously and the SAT<A:B>
(CORCON<7:6>) and ACCSAT (CORCON<4>) mode
control bits to determine when and to what value to
saturate.
Six STATUS Register bits support saturation and
overflow:
• OA: ACCA overflowed into guard bits
• OB: ACCB overflowed into guard bits
• SA: ACCA saturated (bit 31 overflow and
saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
• SB: ACCB saturated (bit 31 overflow and
saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the correspond-
ing Ov erflow T rap Flag En able bits (OV ATE, OVBTE) in
the INTCON1 register are set (refer to Section 7.0
“Interrupt Controller”). This allows the user applica-
tion to take immediate action, for example, to correct
system gain.
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the u ser applic ation. When set, they indicate
that the accumulator has overflowed its maximum
range (bit 31 for 32-bit saturation or bit 39 for 40-bit
saturation) and will be saturated (if saturation is
enabled). When saturation is not enabled, SA and SB
default to bit 39 overfl ow and thus , indic ate that a ca ta-
strophic ov erfl ow ha s oc c urred . If th e C OVTE bi t in th e
INTCON1 register is set, SA and SB bits will generate
an arit hmetic wa rni ng t rap when sa turation is di sa ble d.
The Overflow and Saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA an d OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). Programmers can check one bit
in the STATUS Register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This is useful for
complex number arithmetic, which typically uses both
accumulators.
The device supports three Saturation and Overflow
modes:
• Bit 39 Overflow and Saturation:
When bit 39 overflow and satu ration occurs , the
saturation logic loads the m aximally positive
9.31 (0x7FFFFFFFFF) or maximally negativ e
9.31 value (0x800000 0000) into the target accumu-
lator. The SA or SB bit is set and remains set until
cleared by the user applicatio n. This cond ition is
referred to as ‘super saturation’ and provides
protection against erroneous dat a or unexpected
algorithm problem s (such a s gain ca lculation s).
• Bit 31 Overflow and Saturation:
When bit 31 overflow and satu ration occurs , the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally nega-
tive 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user application. When
this Satu ration mode is in effect , the guard bit s are
not used, so the OA, OB or OAB bits are never
set.
• Bit 39 Catastrophic Overflow:
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until c leared by the user applic ation. No satura tion
operation is performed, and the accumulator is
allowed to overflow, destroying its sign. If the
COVTE bit in the INTCON1 register is set, a
catastroph ic ov erflo w ca n i nit iate a trap exc eption.
3.6.3 ACCUMULATOR ‘WRITE BACK’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the acc umulator that is not targeted by the i nstruction
into dat a spac e memory. The write is perfo rmed ac ross
the X bus into combined X and Y address space. The
following addressing modes are supported:
• W13, Register Direct:
The rounded contents of the non-target accumulator
are written into W13 as a 1.15 fraction.
• [W13] + = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target
accumulat or are written into the address pointed
to by W13 as a 1.15 fraction. W13 is then
incremented by 2 ( for a word write).
3.6.3.1 Round Logic
The round logic is a combinational block that performs
a conventional (biased) or convergent (unbiased)
round fu nction d uring an accumu lator wri te (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit,
1.15 data value that is passed to the data space write
saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the least significant word is simply discarded.
Conventi onal roundi ng zero-ex tends bit 15 of t he accu-
mulator a nd adds it to the ACCxH word (bits 16 th rough
31 of the accumulator).
• If the ACCxL word (bits 0 through 15 of the
accumulator) is between 0x8000 and 0xFFFF
(0x8000 included) , ACC x H is incremented.
• If ACCxL is betwe en 0x0000 and 0x7F FF, ACCxH
is left unchanged.
A consequence of this algorithm is that over a
succession of random rounding operations, the value
tends to be biased slightly positive.
Convergent (or unbiased) rounding operates in the same
manner as conventional rounding, except when ACCxL
equals 0x8000. In this case, the Least Significant bit
(bit 16 of the accumulator) of ACCxH is examined:
• If it is ‘1’, ACCxH is incremented.
• If it is ‘0’, ACCxH is not modified.
Assuming that bit 16 is effectively random in nature,
this scheme removes any rounding bias that may
accumulate.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 42 2008-2014 Microchip Technology Inc.
The SAC and SAC.R instructions store either a
truncated (SAC), or rounded (SAC.R) version of the
contents of the target accumulator to data memory via
the X bus, subject to data saturation (see
Section 3 .6.3.2 “Data Space Write Saturation”). For
the MAC class of instructions, the accumulator write-
back operation functions in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subje ct to round ing .
3.6.3. 2 Data Space Write Saturation
In addi tion to adder /subtrac ter satur ation, wri tes to data
space can also be saturated, but without affecting the
contents of the source accumulator . The data space write
saturation logic block accepts a 16-bit, 1.15 fractional
value from the round logic block as its input, together with
overflow status from the original source (accumulator)
and the 16 -bit rou nd adder. These in puts are combin ed
and used to select the appropriate 1.15 fractional value
as outpu t to writ e to dat a sp ac e m emor y.
If the SATDW bit in the CORCON register is set, data
(aft er rou ndi ng or trunc at ion ) is test ed for ove rflow and
adjusted accordingly:
• For input data greater than 0x007FFF, data
written to memory is forced to the maximum
pos itive 1.15 value, 0x7FFF.
• For input data less than 0xFF8000, data written to
memory is forced to the maximum negative
1.15 va lue , 0x80 00.
The Most Significan t bit of the sourc e (bit 39) is use d to
determine the sign of the operand being tested.
If the SATDW bit i n the CORCON register is not set, th e
input data is always passed through unmodified under
all con di tion s.
3.6.4 BARREL SHIFTER
The barrel s hif ter can pe rform up to 1 6-bit arit hme tic or
logic right shifts, or up to 16-bit left shifts in a single
cycle. The source can be either of the two DSP
accum ula tors or t he X bus (to support m ult i-bi t s hifts of
register or memory data).
The shi f ter requir es a signe d b ina ry va lue to determ in e
both the magnitude (number of bits) and direct ion of the
shif t operation. A positive value shift s the operand right.
A nega tive val ue shifts th e operand left. A val ue of ‘0’
does not modify the operand.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit r esu lt fo r DSP sh if t o peratio ns a nd a 16-bit resu lt
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between bit positions 16
and 31 for right shifts, and between bit positions 0 and
16 for left shifts.
2008-2014 Microchip Technology Inc. DS70000318G-page 43
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
4.0 MEMORY ORGANIZATION
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 architecture features separate program and data
memory spaces and buses. This architecture also allows
the direct access to program memory from the data
space during code execution.
4.1 Program Address Space
The program address memory space of the
dsPIC33FJ06GS10 1/X02 and dsPIC33FJ16GSX02/X04
devices is 4M instructions. The space is addressable by a
24-bit value derived either from the 23-bit Program
Counter (PC) during program execution, or from table
operation or data space remapping, as described in
Section 4.6 “Interfacing Program and Data Memory
Spaces”.
User app licati on acc ess to the program me mory sp ac e
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The memory maps for the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 devices are shown in Figure 4-1.
FIGURE 4-1: PROGRAM MEMORY MAPS FOR dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 DEVICES
Note: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It i s not intended t o be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
“Program Memory” (DS70202) in the
“dsPIC33F/PIC24H Family Reference Man-
ual”, which is available from the Microchip
web site (www.microchip.com).
Reset Address 0x000000
0x0000FE
0x000002
0x000100
Device Configuration
User Program
Flash Memory
0x001000
0x000FFE
(1792 instructions)
0x800000
0xF80000
Registers 0xF80017
0xF80018
DEVID (2) 0xFEFFFE
0xFF0000
0xFFFFFE
0xF7FFFE
Unimplemented
(Read ‘0’s)
GOTO Instruction
0x000004
Reserved
0x7FFFFE
Reserved
0x000200
0x0001FE
0x000104
Alternate V ector Table
Reserved
Interrupt Vector Table
dsPIC33FJ06GS101/102/202
Configuration Memory Space User Memory Space
Reset Address 0x000000
0x0000FE
0x000002
0x000100
Device Configuration
User Program
Flash Memory
0x002C00
0x002BFE
(5376 instructions)
0x800000
0xF80000
Registers 0xF80017
0xF80018
0xF7FFFE
Unimplemented
(Read ‘0’s)
GOTO Instruction
0x000004
Reserved
0x7FFFFE
Reserved
0x000200
0x0001FE
0x000104
Alternate V ector Table
Reserved
Interrupt Vector Table
dsPIC33FJ16GS402/404/502/504
Configuration Memory Space User Memor y Space
Reserved 0xFF0002 DEVID (2)
Reserved
0xFEFFFE
0xFF0000
0xFFFFFE
0xFF0002
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 44 2008-2014 Microchip Technology Inc.
4.1.1 PROGR AM MEMORY
ORGANIZATION
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate consider each address of
the program memory as a lower and upper word, with
the uppe r byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (see Figure 4-2).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during the code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space access ible.
4.1.2 INTERRUPT AND TR AP VECTORS
All dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices reserve the addresses between 0x00000
and 0x000200 for hard-coded program execution vectors.
A hardware Reset vector is provided to redirect code
execution from the default value of the PC on device
Reset to the actual start of code. A GOTO instruction is
programmed by the user application at 0x000000, with
the actual address for the start of code at 0x000002.
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices also have two interrupt vector tables, located
from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF.
These vector tables allow each of the device interrupt
sources to be handled by separate Interrupt Service
Routines (ISRs). A more detailed discussion of the
interrupt vector tables is provided in Section 7.1
“Interrupt Vector Table”.
FIGURE 4-2: PROGRAM MEMORY ORGANIZATION
0816
PC Address
0x000000
0x000002
0x000004
0x000006
23
00000000
00000000
00000000
00000000
Program Memory
‘Phanto m’ Byte
(read as ‘0’)
least significant word
most significant word
Ins truction Width
0x000001
0x000003
0x000005
0x000007
msw
Address (lsw Address)
2008-2014 Microchip Technology Inc. DS70000318G-page 45
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
4.2 Data Address Space
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 CPU has a separate, 16-bit-wide data memory
space. The data space is accessed using separate
Address Generation Units (AGUs) for read and write
operations. The data memory maps is shown in
Figure 4-3.
All Effective Addresses (EAs) in the data memory sp ace
are 16 bit s wide and point to bytes within the dat a space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see Section 4.6.3 “Reading Data from
Program Memory Using Program Space Visibility”).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 dev ices im plement up to 2 Kbytes o f data memory.
Should a n EA point to a lo cation out side of this area, an
all zero word or byte will be returned.
4.2.1 DATA SPACE WIDTH
The data memory space is organized in byte
address able, 16-bit wide blocks . Dat a is aligned in dat a
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSB s) of each w ord have even ad dresses, whil e
the Most Significant Bytes (MSBs) have odd
addresses.
4.2.2 DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve data space memory usage
efficiency, the dsPIC33FJ06GS101/X02 and
dsPIC33FJ 16GSX0 2/X04 inst ruction se t suppor ts bo th
word and byte operations. As a consequence of byte
accessibility, all Effective Address calculations are
internally scal ed to step through wor d-align ed me mory.
For example, the core recognizes that Post-Modified
Register Indirect Addressing mode [Ws++] that results
in a val ue o f Ws + 1 fo r byte operat ion s a nd W s + 2 for
word operations.
Data byte reads will read the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decode
but sepa rate wri te lines . Data byte w rites o nly write to
the corresponding side of the array or register that
matches the byte address.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misali gned re ad or w rite is attemp ted, an addres s error
trap is generated. If the error occurred on a read, the
instruction underway is compl eted. If the error occ urred
on a write, the instruction is executed but the write does
not occur. In either case, a trap is then executed,
allow ing the syst em and/or user appli cation to ex amine
the machine state prior to execution of the address
Fault.
All byte loads into any W register are loaded into the
Least Signifi can t B yte . T he Most Sig ni fic ant By te is n ot
modified.
A sign-ex tend (SE) ins truc ti on is pro vid ed to all ow us er
applications to translate 8-bit signed data to 16-bit
signed values. Alternatively, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a zero-extend (ZE) instruction on the
appropriate address.
4.2.3 SFR SPACE
The first 2 Kbytes of the Ne ar Data S p ace, from 0x 0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 core and peripheral modules for controlling the
operation of the device.
SFRs are distributed among the modules that they
control, and are genera lly grouped toge ther by mod ule.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
4.2.4 NEAR DATA SPACE
The 8-Kbyte area, between 0x0000 and 0x1FFF, is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Addition ally , th e whole dat a spa ce is addressa ble using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field or by usin g
Indirect Addressing mode using a Working register as
an Address Pointer.
Note: The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and
pinout diagrams for device-specific
information.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 46 2008-2014 Microchip Technology Inc.
FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ06GS101/102 DEVICES WITH 256 BYTES
OF RAM
0x0000
0x07FE
0x08FE
0xFFFE
LSB
Address
16 Bits
LSbMSb
MSB
Address
0x0001
0x07FF
0xFFFF
Optionally
Mapped
into Program
Memory
0x0801 0x0800
0x0900
2-Kbyte
SFR Sp ace
256 Bytes
SRAM Space
0x8001 0x8000
X Data
Unimplemented (X)
0x087E
0x0880
0x087F
0x0881
0x08FF
0x0901
0x1FFF 0x1FFE
0x2001 0x2000
8-Kbyte
Near Data
Space
SFR Space
X Data RAM (X)
Y Data RAM (Y)
2008-2014 Microchip Technology Inc. DS70000318G-page 47
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJ06GS202 DEVICE WITH 1-KBYTE RAM
0x0000
0x07FE
0x0BFE
0xFFFE
LSB
Address
16 Bits
LSbMSb
MSB
Address
0x0001
0x07FF
0xFFFF
Optionally
Mapped
into Program
Memory
0x0801 0x0800
0x0C00
2-Kbyte
SFR Sp ace
1-Kbyte
SRAM Space
0x8001 0x8000
SFR Space
X Data
Unimplemented (X)
0x09FE
0x0A00
0x09FF
0x0A01
0x0BFF
0x0C01
0x1FFF 0x1FFE
0x2001 0x2000
8-Kbyte
Near Data
Space
X Data RAM (X)
Y Data RAM (Y)
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 48 2008-2014 Microchip Technology Inc.
FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJ16GS402/404/502/504 DEVICES WITH
2-KBYTE RAM
0x0000
0x07FE
0x0FFE
0xFFFE
LSB
Address
16 Bits
LSbMSb
MSB
Address
0x0001
0x07FF
0xFFFF
Optionally
Mapped
into Program
Memory
0x0801 0x0800
0x1000
2-Kbyte
SFR Sp ace
2-Kbyte
SRAM Space
0x8001 0x8000
SFR Space
X Data
Unimplemented (X)
0x0BFE
0x0C00
0x0BFF
0x0C01
0x0FFF
0x1001
0x1FFF 0x1FFE
0x2001 0x2000
8-Kbyte
Near Data
Space
Y Data RAM (Y)
X Data RAM (X)
2008-2014 Microchip Technology Inc. DS70000318G-page 49
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
4.2.5 X AND Y DATA SPACES
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instruc tions to concurrent ly fe tch two w ords from RAM ,
thereby ena bling eff icient execution of DSP algorith ms,
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also th e X dat a p refe tch p ath for the dual operand DSP
instructions (MAC class).
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide
two concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for w rites to X dat a sp ac e.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All Effective Addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, though the
implemented memory locations vary by device.
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 50 2008-2014 Microchip Technology Inc.
TABLE 4-1: CPU CORE REGISTER MAP
File Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
WREG0 0000 Wo r ki n g Re gister 0 0000
WREG1 0002 Wo r ki n g Re gister 1 0000
WREG2 0004 Wo r ki n g Re gister 2 0000
WREG3 0006 Wo r ki n g Re gister 3 0000
WREG4 0008 Wo r ki n g Re gister 4 0000
WREG5 000A Wo r ki n g Re gister 5 0000
WREG6 000C Wo r k in g R e gi s t er 6 0000
WREG7 000E Wo r ki n g Re gister 7 0000
WREG8 0010 Wo r ki n g Re gister 8 0000
WREG9 0012 Wo r ki n g Re gister 9 0000
WREG10 0014 Working Register 10 0000
WREG11 0016 Working Register 1 1 0000
WREG12 0018 Working Register 12 0000
WREG13 001A Working Register 13 0000
WREG14 001C Working Register 14 0000
WREG15 001E Working Register 15 0800
SPLIM 0020 S t ack Pointer Limit Register xxxx
ACCAL 0022 ACCAL xxxx
ACCAH 0024 ACCAH xxxx
ACCAU 0026 ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCAU xxxx
ACCBL 0028 ACCBL xxxx
ACCBH 002A ACCBH xxxx
ACCBU 002C ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCBU xxxx
PCL 002E Program Counter Low Word Register 0000
PCH 0030 — — — — — — — — Program Counter High Byte Register 0000
TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register 0000
PSVPAG 0034 — — — — — — — — Program Memory V i sibility P age Addres s Pointer Registe r 0000
RCOUNT 0036 REPEAT Loop Counter Register xxxx
DCOUNT 0038 DCOUNT<15:0> xxxx
DOSTARTL 003A DOSTARTL<15:1> 0xxxx
DOSTARTH 003C — — — — — — — — — —DOSTARTH<5:0>00xx
DOENDL 003E DOENDL<15:1> 0xxxx
DOENDH 0040 — — — — — — — — — — DOENDH 00xx
SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000
CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0020
MODCON 0046 XMODEN YMODEN —— BWM3 BWM2 BWM1 BWM0 YWM3 YWM2 YWM1 YWM0 XWM3 XWM2 XWM1 XWM0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2008-2014 Microchip Technology Inc. DS70000318G-page 51
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ06GS101
TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPI C33FJ1 6GS4 02 AND
dsPIC33FJ16GS502
TABLE 4-4: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ16GS404 AND dsPIC33FJ16GS504
XMODSRT 0048 XS<15:1> 0xxxx
XMODEND 004A XE<15:1> 1xxxx
YMODSRT 004C YS<15:1> 0xxxx
YMODEND 004E YE<15:1> 1xxxx
XBREV 0050 BREN XB14 XB13 XB12 XB11 XB10 XB9 XB8 XB7 XB6 XB5 XB4 XB3 XB2 XB1 XB0 xxxx
DISICNT 0052 —— Disable Interrupts Counter Regi ster xxxx
TABLE 4-1: CPU CORE REGISTER MAP (CONTINUED)
File Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CNEN1 0060 — — — — — — — — CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
CNPU1 0068 — — — — — — — — CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
CNEN2 0062 —— CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000
CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
CNPU2 006A —— CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 52 2008-2014 Microchip Technology Inc.
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS101 DEVICES ONLY
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL —
0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP
0000
IFS0 0084 —— ADIF U1TXIF U1RXIF SPI1IF SPI1EIF —T2IF— — —T1IFOC1IF—INT0IF
0000
IFS1 0086 ——INT2IF— — — — — — — —INT1IFCNIF —MI2C1IFSI2C1IF
0000
IFS3 008A — — — — — — PSEMIF — — — — — — — — —
0000
IFS4 008C — — — — — — — — — — — — — —U1EIF—
0000
IFS5 008E —PWM1IF — — — — — — — — — — — — — —
0000
IFS6 0090 ADCP1IF ADCP0IF — — — — — — — — — — — —PWM4IF—
0000
IFS7 0092 — — — — — — — — — — — — — — ADCP3IF —
0000
IEC0 0094 —— ADIE U1TXIE U1RXIE SPI1IE SPI1EIE —T2IE— — —T1IEOC1IE—INT0IE
0000
IEC1 0096 ——INT2IE— — — — — — — — INT1IE CNIE — MI2C1IE SI2C1IE
0000
IEC2 0098 — — — — — — — — — — — — — — — —
0000
IEC3 009A — — — — — —PSEMIE— — — — — — — — —
0000
IEC4 009C — — — — — — — — — — — — — —U1EIE—
0000
IEC5 009E —PWM1IE — — — — — — — — — — — — — —
0000
IEC6 00A0 ADCP1IE ADCP0IE — — — — — — — — — — — —PWM4IE—
0000
IEC7 00A2 — — — — — — — — — — — — — — ADCP3IE —
0000
IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — — — — — INT0IP2 INT0IP1 INT0IP2
4404
IPC1 00A6 — T2IP2 T2IP1 T2IP0 — — — — — — — — — — — —
4000
IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — — — —
4440
IPC3 00AA — — — — — — — — -— ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0
0044
IPC4 00AC — CNIP2 CNIP1 CNIP0 — — — — — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0
4044
IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP21 INT1IP0
0004
IPC7 00B2 — — — — — — — — — INT2IP2 INT2IP1 INT2IP0 — — — —
0040
IPC14 00C0 — — — — — — — — — PSEMIP2 PSEMIP1 PSEMIP0 — — — —
0040
IPC16 00C4 — — — — — — — — — U1EIP2 U1EIP1 U1EIP0 — — — —
0400
IPC23 00D2 — — — — — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — —
0040
IPC24 00D4 — — — — — — — — — PWM4IP2 PWM4IP1 PWM4IP0 — — — —
4400
IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — —
0040
IPC28 00DC — — — — — — — — — ADCP3IP2 ADCP3IP1 ADCP3IP0 — — — —
0000
INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
Legend:
x
= unk now n valu e on R ese t, — = unim pl em ente d, re ad as ‘
0
’. Rese t va lues a re show n in hex a decim al .
2008-2014 Microchip Technology Inc. DS70000318G-page 53
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS102 DEVICES ONLY
File
Name SFR
Addr Bit 1 5 Bit 14 Bit 1 3 Bit 12 B it 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bi t 3 Bit 2 B it 1 Bit 0 All
Resets
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL —
0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP
0000
IFS0 0084 —— ADIF U1TXIF U1RXIF SPI1IF SPI1EIF —T2IF— — —T1IFOC1IF—INT0IF
0000
IFS1 0086 ——INT2IF— — — — — — — — INT1IF CNIF —MI2C1IFSI2C1IF
0000
IFS3 008A — — — — — —PSEMIF— — — — — — — — —
0000
IFS4 008C — — — — — — — — — — — — — —U1EIF—
0000
IFS5 008E PWM2IF PWM1IF — — — — — — — — — — — — — —
0000
IFS6 0090 ADCP1IF ADCP0IF — — — — — — — — — — — — — —
0000
IFS7 0092 — — — — — — — — — — — — — — — ADCP2IF
0000
IEC0 0094 —— ADIE U1TXIE U1RXIE SPI1IE SPI1EIE —T2IE— — —T1IEOC1IE—INT0IE
0000
IEC1 0096 ——INT2IE— — — — — — — — INT1IE CNIE — MI2C1IE SI2C1IE
0000
IEC3 009A — — — — — — PSEMIE — — — — — — — — —
0000
IEC4 009C — — — — — — — — — — — — — —U1EIE—
0000
IEC5 009E PWM2IE PWM1IE — — — — — — — — — — — — — —
0000
IEC6 00A0 ADCP1IE ADCP0IE — — — — — — — — — — — — — —
0000
IEC7 00A2 — — — — — — — — — — — — — — — ADCP2IE
0000
IPC0 00A4 —T1IP2T1IP1T1IP0 — OC1IP2 OC1IP1 OC1IP0 — — — — — INT0IP2 INT0IP1 INT0IP0
4404
IPC1 00A6 —T2IP2T2IP1T2IP0 — — — — — — — — — — — —
4000
IPC2 00A8 — U1RXIP2 U1RXIP2 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — — — —
4440
IPC3 00AA — — — — — — — — -— ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0
0044
IPC4 00AC — CNIP2 CNIP1 CNIP0 — — — — — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0
4044
IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0
0004
IPC7 00B2 — — — — — — — — — INT2IP2 INT2IP1 INT2IP0 — — — —
0040
IPC14 00C0 — — — — — — — — — PSEMIP2 PSEMIP1 PSEMIP0 — — — —
0040
IPC16 00C4 — — — — — — — — — U1EIP2 U1EIP1 U1EIP0 — — — —
0040
IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — —
4400
IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — —
4400
IPC28 00DC — — — — — — — — — — — — — ADCP2IP2 ADCP2IP1 ADCP2IP0
0004
INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
Legend:
x
= unk now n valu e on R ese t, — = unim pl em ente d, re ad as ‘
0
’. Rese t va lues a re show n in hex a decim al .
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 54 2008-2014 Microchip Technology Inc.
TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06G202 DEVICES ONLY
File
Name SFR
Addr Bit 15 Bit 14 Bit 1 3 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi t 1 Bi t 0 All
Resets
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL —
0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP
0000
IFS0 0084 —— ADIF U1TXIF U1RXIF SPI1IF SPI1EIF —T2IF— — — T1IF OC1IF IC1IF INT0IF
0000
IFS1 0086 ——INT2IF— — — — — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF
0000
IFS3 008A — — — — — — PSEMIF — — — — — — — — —
0000
IFS4 008C — — — — — — — — — — — — — —U1EIF—
0000
IFS5 008E PWM2IF PWM1IF — — — — — — — — — — — — — —
0000
IFS6 0090 ADCP1IF ADCP0IF — — — — — —AC2IF— — — — — — —
0000
IFS7 0092 — — — — — — — — — — — ADCP6IF — — — ADCP2IF
0000
IEC0 0094 —— ADIE U1TXIE U1RXIE SPI1IE SPI1EIE —T2IE— — — T1IE OC1IE IC1IE INT0IE
0000
IEC1 0096 ——INT2IE— — — — — — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE
0000
IEC3 009A — — — — — —PSEMIE— — — — — — — — —
0000
IEC4 009C — — — — — — — — — — — — — —U1EIE—
0000
IEC5 009E PWM2IE PWM1IE — — — — — — — — — — — — — —
0000
IEC6 00A0 ADCP1IE ADCP0IE — — — — — —AC2IE— — — — — — —
0000
IEC7 00A2 — — — — — — — — — — — ADCP6IE — — — ADCP2IE
0000
IPC0 00A4 —T1IP2T1IP1T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0
4444
IPC1 00A6 —T2IP2T2IP1T2IP0 — — — — — — — — — — — —
4000
IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — — — —
4440
IPC3 00AA — — — — — — — — -— ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0
0044
IPC4 00AC — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0
4444
IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0
0004
IPC7 00B2 — — — — — — — — — INT2IP2 INT2IP1 INT2IP0 — — — —
0040
IPC14 00C0 — — — — — — — — — PSEMIP2 PSEMIP1 PSEMIP0 — — — —
0040
IPC16 00C4 — — — — — — — — — U1EIP2 U1EIP1 U1EIP0 — — — —
0040
IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — —
4400
IPC25 00D6 — AC2IP2 AC2IP1 AC2IP0 — — — — — — — — — — — —
4000
IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — —
4400
IPC28 00DC — — — — — — — — — — — — — ADCP2IP2 ADCP2IP1 ADCP2IP0
0004
IPC29 00DE — — — — — — — — — — — — — ADCP6IP2 ADCP6IP1 ADCP6IP0
0004
INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
Legend:
x
= unk now n valu e on R ese t, — = unim pl em ente d, re ad as ‘
0
’. Rese t va lues a re show n in hex a decim al .
2008-2014 Microchip Technology Inc. DS70000318G-page 55
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
TABLE 4-8: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS402/404 DEVICES ONLY
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL —
0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP
0000
IFS0 0084 —— ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF
0000
IFS1 0086 ——INT2IF— — — — — — — — INT1IF CNIF — MI2C1IF SI2C1IF
0000
IFS3 008A — — — — — — PSEMIF — — — — — — — — —
0000
IFS4 008C — — — — — — — — — — — — — —U1EIF—
0000
IFS5 008E PWM2IF PWM1IF — — — — — — — — — — — — — —
0000
IFS6 0090 ADCP1IF ADCP0IF — — — — — — — — — — — — —PWM3IF
0000
IFS7 0092 — — — — — — — — — — — — — — ADCP3IF ADCP2IF
0000
IEC0 0094 —— ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE
0000
IEC1 0096 ——INT2IE— — — — — — — — INT1IE CNIE —MI2C1IESI2C1IE
0000
IEC3 009A — — — — — — PSEMIE — — — — — — — — —
0000
IEC4 009C — — — — — — — — — — — — — —U1EIE—
0000
IEC5 009E PWM2IE PWM1IE — — — — — — — — — — — — — —
0000
IEC6 00A0 ADCP1IE ADCP0IE — — — — — — — — — — — — —PWM3IE
0000
IEC7 00A2 — — — — — — — — — — — — — — ADCP3IE ADCP2IE
0000
IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP2
4444
IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — —
4440
IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 —T3IP2T3IP1T3IP0
4444
IPC3 00AA — — — — — — — — -— ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0
0044
IPC4 00AC — CNIP2 CNIP1 CNIP0 — — — — — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0
4044
IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0
0004
IPC7 00B2 — — — — — — — — — INT2IP2 INT2IP1 INT2IP0 — — — —
0040
IPC14 00C0 — — — — — — — — — PSEMIP2 PSEMIP1 PSEMIP0 — — — —
0040
IPC16 00C4 — — — — — — — — — U1EIP2U1EIP1U1EIP0 — — — —
0040
IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 -— — — — — —
4400
IPC24 00D4 — — — — — — — — — — — — — PWM3IP2 PWM3IP1 PWM3IP0
0004
IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 -— — — — — —
4400
IPC28 00DC — — — — — — — — — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1 ADCP2IP0
0044
INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
Legend:
x
= unk now n valu e on R ese t, — = unim pl em ente d, re ad as ‘
0
’. Rese t va lues a re show n in hex a decim al .
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 56 2008-2014 Microchip Technology Inc.
TABLE 4-9: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS502 DEVICES ONLY
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL —
0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP
0000
IFS0 0084 —— ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF
0000
IFS1 0086 ——INT2IF— — — — — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF
0000
IFS3 008A —————— PSEMIF — — — — — — — — —
0000
IFS4 008C — — — — — — — — — — — — — —U1EIF—
0000
IFS5 008E PWM2IF PWM1IF — — — — — — — — — — — — — —
0000
IFS6 0090 ADCP1IF ADCP0IF ———— AC4IF AC3IF AC2IF — — — — — PWM4IF PWM3IF
0000
IFS7 0092 — — — — — — — — — — — ADCP6IF —— ADCP3IF ADCP2IF
0000
IEC0 0094 —— ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE
0000
IEC1 0096 ——INT2IE— — — — — — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE
0000
IEC3 009A —————— PSEMIE — — — — — — — — —
0000
IEC4 009C — — — — — — — — — — — — — —U1EIE—
0000
IEC5 009E PWM2IE PWM1IE — — — — — — — — — — — — — —
0000
IEC6 00A0 ADCP1IE ADCP0IE ———— AC4IE AC3IE AC2IE — — — — — PWM4IE PWM3IE
0000
IEC7 00A2 — — — — — — — — — — — ADCP6IE —— ADCP3IE ADCP2IE
0000
IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP2
4444
IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 -— — — —
4440
IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0
4444
IPC3 00AA — — — — -— — — — -— ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0
0044
IPC4 00AC — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0
4444
IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0
0004
IPC7 00B2 — — — — — — — — — INT2IP2 INT2IP1 INT2IP0 — — — —
0040
IPC14 00C0 — — — — — — — — — PSEMIP2 PSEMIP1 PSEMIP0 — — — —
0040
IPC16 00C4 — — — — — — — — — U1EIP2 U1EIP1 U1EIP0 — — — —
0040
IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — —
4400
IPC24 00D4 — — — — — — — — — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0
0044
IPC25 00D6 — AC2IP2 AC2IP1 AC2IP0 — — — — — — — — — — — —
4000
IPC26 00D8 — — — — — — — — — AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0
0044
IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 -— — — — — — — —
4400
IPC28 00DC — — — — — — — — — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1 ADCP2IP0
0044
IPC29 00DE — — — — — — — — — — — — — ADCP6IP2 ADCP6IP1 ADCP6IP0
0004
INTTREG 00E0 ———— ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
Legend:
x
= unk now n valu e on R ese t, — = unim pl em ente d, re ad as ‘
0
’. Rese t va lues a re show n in hex a decim al .
2008-2014 Microchip Technology Inc. DS70000318G-page 57
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
TABLE 4-10: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS504 DEVICES ONLY
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bi t 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0 All
Resets
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL —
0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP
0000
IFS0 0084 —— ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF
0000
IFS1 0086 ——INT2IF— — — — — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF
0000
IFS3 008A — — — — — —PSEMIF— — — — — — — — —
0000
IFS4 008C — — — — — — — — — — — — — —U1EIF—
0000
IFS5 008E PWM2IF PWM1IF — — — — — — — — — — — — — —
0000
IFS6 0090 ADCP1IF ADCP0IF — — — — AC4IF AC3IF AC2IF — — — — — PWM4IF PWM3IF
0000
IFS7 0092 — — — — — — — — — — — ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF
0000
IEC0 0094 —— ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE
0000
IEC1 0096 ——INT2IE — — — — — — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE
0000
IEC3 009A — — — — — — PSEMIE — — — — — — — — —
0000
IEC4 009C — — — — — — — — — — — — — —U1EIE—
0000
IEC5 009E PWM2IE PWM1IE — — — — — — — — — — — — — —
0000
IEC6 00A0 ADCP1IE ADCP0IE — — — — AC4IE AC3IE AC2IE — — — — — PWM4IE PWM3IE
0000
IEC7 00A2 — — — — — — — — — — — ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE
0000
IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP2
4444
IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — —
4440
IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0
4444
IPC3 00AA — — — — — — — — -— ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0
0044
IPC4 00AC — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0
4444
IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0
0004
IPC7 00B2 — — — — — — — — —INT2IP2INT2IP1INT2IP0— — — —
0040
IPC14 00C0 — — — — — — — — — PSEMIP2 PSEMIP1 PSEMIP0 — — — —
0040
IPC16 00C4 — — — — — — — — — U1EIP2 U1EIP1 U1EIP0 — — — —
0040
IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — —
4400
IPC24 00D4 — — — — — — — — — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0
0044
IPC25 00D6 — AC2IP2 AC2IP1 AC2IP0 — — — — — — — — — — — —
4000
IPC26 00D8 — — — — — — — — — AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0
0440
IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — —
4400
IPC28 00DC — ADCP5IP2 ADCP5IP1 ADCP5IP0 — ADCP4IP2 ADCP4IP1 ADCP4IP0 — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1 ADCP2IP0
4444
IPC29 00DE — — — — — — — — — — — — — ADCP6IP2 ADCP6IP1 ADCP6IP0
0004
INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
Legend:
x
= unk now n valu e on R ese t, — = unim pl em ente d, re ad as ‘
0
’. Rese t va lues a re show n in hex a decim al .
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 58 2008-2014 Microchip Technology Inc.
TABLE 4-11: TIMER REGISTER MAP FOR dsPIC33FJ06GS101 AND dsPIC33FJ06GSX02
TA BLE 4-12: TIMER REGISTER MAP FOR dsPIC33FJ16GSX02 AND dsPIC33FJ1 6GSX 04
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TMR1 0100 Timer1 Register 0000
PR1 0102 Period Register 1 FFFF
T1CON 0104 TON —TSIDL—————— TGATE TCKPS1 TCKPS0 — TSYNC TCS —0000
TMR2 0106 Timer2 Register 0000
PR2 010C Period Register 2 FFFF
T2CON 0110 TON —TSIDL—————— TGATE TCKPS1 TCKPS0 ——TCS—0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TMR1 0100 Timer1 Register 0000
PR1 0102 Period Register 1 FFFF
T1CON 0104 TON —TSIDL—————— TGATE TCKPS1 TCKPS0 — TSYNC TCS —0000
TMR2 0106 Timer2 Register 0000
TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx
TMR3 010A Timer3 Register 0000
PR2 010C Period Register 2 FFFF
PR3 010E Period Register 3 FFFF
T2CON 0110 TON —TSIDL—————— TGATE TCKPS1 TCKPS0 T32 —TCS—0000
T3CON 0112 TON —TSIDL—————— TGATE TCKPS1 TCKPS0 ——TCS—0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-13: INPUT CAPTURE REGIST ER M AP FOR dsPIC33FJ 06GS 202
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
IC1BUF 0140 Input Capture 1 Register xxxx
IC1CON 0142 ——ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2008-2014 Microchip Technology Inc. DS70000318G-page 59
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
TABLE 4-14: INPUT CAPTURE REGISTER MAP FOR dsPIC33FJ16GSX02 AND dsPIC33FJ1 6GSX 04
TABLE 4-16: OUTPUT COMPARE REGISTER MAP FOR dsPIC33FJ16GSX02 AND dsPIC33FJ06GSX04
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
IC1BUF 0140 Input Capture 1 Register xxxx
IC1CON 0142 ——ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
IC2BUF 0144 Input Capture 2 Register xxxx
IC2CON 0146 ——ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-15: OUTPUT COMPARE REGISTER MAP FOR dsPIC33FJ06GS101 AND dsPIC33FJ06GSX02
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
OC1RS 0180 Output Compare 1 Secondary Register xxxx
OC1R 0182 Output Compare 1 Register xxxx
OC1CON 0184 ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
OC1RS 0180 Output Compare 1 Secondary Register xxxx
OC1R 0182 Out put C ompare 1 Re giste r xxxx
OC1CON 0184 ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000
OC2RS 0186 Output Compare 2 Secondary Register xxxx
OC2R 0188 Out put C ompare 2 Re giste r xxxxx
OC2CON 018A ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-17: HIGH-SPEED PWM REGISTER MAP
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PTCON 0400 PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN — SYNCSRC1 SYNCSRC0 SEVTPS3 SEVTPS2 SEVTPS1 SEVTPS0 0000
PTCON2 0402 — — — — — — — — — — — — — PCLKDIV2 PCLKDIV1 PCLKDIV0 0000
PTPER 0404 PTPER<15:0> FFF8
SEVTCMP 0406 SEVTCMP<15:3> — — — 0000
MDC 040A MDC<15:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 60 2008-2014 Microchip Technology Inc.
TABLE 4-18: HIGH-SPEED PWM GENERATOR 1 REGISTER MAP
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PWMCON1 0420 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 — — — CAM XPRES IUE
0000
IOCON1 0422 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC
0000
FCLCON1 0424 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0
0000
PDC1 0426 PDC1<15:0>
0000
PHASE1 0428 PHASE1<15:0>
0000
DTR1 042A — — DTR1<13:0>
0000
ALTDTR1 042C — — ALTDTR1<13:0>
0000
SDC1 042E SDC1<15:0>
0000
SPHASE1 0430 SPHASE1<15:0>
0000
TRIG1 0432 TRGCMP<15:3> — — —
0000
TRGCON1 0434 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — —DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
0000
STRIG1 0436 STRGCMP<15:3> — — —
0000
PWMCAP1 0438 PWMCAP1<15:3> — — —
0000
LEBCON1 043A PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB6 LEB5 LEB4 LEB3 LEB2 LEB1 LEB0 — — —
0000
Legend:
x
= unk nown value on Reset, — = unimplem ented, read as ‘
0
’. Reset valu es are show n i n hexadecimal.
TABLE 4-19: HIGH-SPEED PWM GENERATOR 2 REGISTER MAP FOR dsPIC33 FJ06GS102 /202 AND dsPIC33FJ16 GSX02/X04 DEVICES ONLY
File
Name SFR
Addr Bit 1 5 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi t 1 B it 0 All
Resets
PWMCON2 0440 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 — — — CAM XPRES IUE
0000
IOCON2 0442 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC
0000
FCLCON2 0444 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0
0000
PDC2 0446 PDC2<15:0>
0000
PHASE2 0448 PHASE2<15:0>
0000
DTR2 044A — — DTR2<13:0>
0000
ALTDTR2 044C — — ALTDTR2<13:0>
0000
SDC2 044E SDC2<15:0>
0000
SPHASE2 0450 SPHASE2<15:0>
0000
TRIG2 0452 TRGCMP<15:3> — — —
0000
TRGCON2 0454 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — —DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
0000
STRIG2 0456 STRGCMP<15:3> — — —
0000
PWMCAP2 0458 PWMCAP2<15:3> — — —
0000
LEBCON2 045A PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB6 LEB5 LEB4 LEB3 LEB2 LEB1 LEB0 — — —
0000
Legend:
x
= unk now n value on Res e t, — = u nim plem en te d, rea d as ‘
0
’. Reset values are shown in hexadecimal.
2008-2014 Microchip Technology Inc. DS70000318G-page 61
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
TABLE 4-20: HIGH-SPEED PWM GENERATOR 3 REGISTER MAP FOR dsPIC33FJ16GSX02/X04 DEVICES ONLY
File
Name SFR
Addr Bit 15 Bit 1 4 Bit 13 Bit 12 Bi t 11 Bit 10 Bit 9 Bit 8 Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 All
Resets
PWMCON3 0460 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 ——— CAM XPRES IUE
0000
IOCON3 0462 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC
0000
FCLCON3 0464 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0
0000
PDC3 0466 PDC3<15:0>
0000
PHASE3 0468 PHASE3<15:0>
0000
DTR3 046C — — DTR3<13:0>
0000
ALTDTR3 046C — — ALTDTR3<13:0>
0000
SDC3 046E SDC3<15:0>
0000
SPHASE3 0470 SPHASE3<15:0>
0000
TRIG3 0472 TRGCMP<15:3> — — —
0000
TRGCON3 0474 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — —DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
0000
STRIG3 0476 STRGCMP<15:3> — — —
0000
PWMCAP3 0478 PWMCAP3<15:3> — — —
0000
LEBCON3 047A PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB6 LEB5 LEB4 LEB3 LEB2 LEB1 LEB0 — — —
0000
Legend:
x
= unk now n value on Res e t, — = u nim plem en te d, rea d as ‘
0
’. Reset values are shown in hexadecimal.
TABLE 4-21: HIGH-SPEED PWM GENERATOR 4 REGISTER MAP FOR dsPIC33FJ06GS101 AND dsPIC33FJ16GS50X DEVICES ONLY
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PWMCON4 0480 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 — — — CAM XPRES IUE
0000
IOCON4 0482 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC
0000
FCLCON4 0484 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0
0000
PDC4 0486 PDC4<15:0>
0000
PHASE4 0488 PHASE4<15:0>
0000
DTR4 048A — — DTR4<13:0>
0000
ALTDTR4 048A — — ALTDTR4<13:0>
0000
SDC4 048E SDC4<15:0>
0000
SPHASE4 0490 SPHASE4<15:0>
0000
TRIG4 0492 TRGCMP<15:3> — — —
0000
TRGCON4 0494 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — —DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
0000
STRIG4 0496 STRGCMP<15:3> — — —
0000
PWMCAP4 0498 PWMCAP4<15:3> — — —
0000
LEBCON4 049A PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB6 LEB5 LEB4 LEB3 LEB2 LEB1 LEB0 — — —
0000
Legend:
x
= unk now n value on Res e t, — = u nim plem en te d, rea d as ‘
0
’. Reset values are shown in hexadecimal.
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 62 2008-2014 Microchip Technology Inc.
TABLE 4-23: UART1 REGISTER MAP
TABLE 4-24: SPI1 REGISTER MAP
TABLE 4-22: I2C1 RE GISTER MAP
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
I2C1RCV 0200 — — — — — — — — I2C1 Receive Register 0000
I2C1TRN 0202 — — — — — — — — I2C1 Transmit Register 00FF
I2C1BRG 0204 — — — — — — — Baud Rate Generator Register 0000
I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000
I2C1ADD 020A — — — — — — I2C1 Address Register 0000
I2C1MSK 020C — — — — — — AMSK<9:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U1TXREG 0224 — — — — — — — UART1 Transmit Register xxxx
U1RXREG 0226 — — — — — — — UART1 Receive Register 0000
U1BRG 0228 Baud Rate Generator Prescaler 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
SPI1STAT 0240 SPIEN — SPISIDL —————— SPIROV — — — — SPITBF SPIRBF 0000
SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000
SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY —0000
SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2008-2014 Microchip Technology Inc. DS70000318G-page 63
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
TABLE 4-25: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS101 DEVICES ONLY
TABLE 4-26: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS102 DEVICES ONLY
File
Name SFR
Addr Bit 1 5 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 B i t 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi t 2 Bit 1 Bit 0 All
Resets
ADCON 0300 ADON — ADSIDL SLOWCLK —GSWTRG— FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0
0003
ADPCFG 0302 — — — — — — — —PCFG7PCFG6—— PCFG3 PCFG2 PCFG1 PCFG0
0000
ADSTAT 0306 — — — — — — — — — — — — P3RDY — P1RDY P0RDY
0000
ADBASE 0308 ADBASE<15:1> —
0000
ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00
0000
ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 — — — — — — — —
0000
ADCBUF0 0320 ADC Data Buffer 0
xxxx
ADCBUF1 0322 ADC Data Buffer 1
xxxx
ADCBUF2 0324 ADC Data Buffer 2
xxxx
ADCBUF3 0326 ADC Data Buffer 3
xxxx
ADCBUF6 032C ADC Data Buffer 6
xxxx
ADCBUF7 032E ADC Data Buffer 7
xxxx
Legend:
x
= unk now n valu e on R ese t, — = unim pl em ente d, re ad as ‘
0
’. Rese t va lues a re show n in hex a decim al .
File
Name SFR
Addr Bit 1 5 Bit 14 Bit 1 3 Bit 12 Bit 11 Bi t 1 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0 All
Resets
ADCON 0300 ADON — ADSIDL SLOWCLK —GSWTRG— FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0
0003
ADPCFG 0302 — — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
0000
ADSTAT 0306 — — — — — — — — — — — — — P2RDY P1RDY P0RDY
0000
ADBASE 0308 ADBASE<15:1> —
0000
ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00
0000
ADCPC1 030C — — — — — — — — IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20
0000
ADCBUF0 0320 ADC Data Buffer 0
xxxx
ADCBUF1 0322 ADC Data Buffer 1
xxxx
ADCBUF2 0324 ADC Data Buffer 2
xxxx
ADCBUF3 0326 ADC Data Buffer 3
xxxx
ADCBUF4 0328 ADC Data Buffer 4
xxxx
ADCBUF5 032A ADC Data Buf fer 5
xxxx
Legend:
x
= unk now n valu e on R ese t, — = unim pl em ente d, re ad as ‘
0
’. Rese t va lues a re show n in hex a decim al .
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 64 2008-2014 Microchip Technology Inc.
TABLE 4-27: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY
TABLE 4-28: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS402/404 DEVICES ONLY
File
Name SFR
Addr Bit 1 5 Bit 14 Bit 13 Bit 1 2 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bi t 3 Bit 2 Bit 1 Bit 0 All
Resets
ADCON 0300 ADON —ADSIDLSLOWCLK —GSWTRG— FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0
0003
ADPCFG 0302 — — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
0000
ADSTAT 0306 — — — — — — — — — P6RDY — — — P2RDY P1RDY P0RDY
0000
ADBASE 0308 ADBASE<15:1> —
0000
ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00
0000
ADCPC1 030C — — — — — — — — IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20
0000
ADCPC3 0310 — — — — — — — — IRQEN6 PEND6 SWTRG6 TRGSRC64 TRGSRC63 TRGSRC62 TRGSRC61 TRGSRC60
0000
ADCBUF0 0320 ADC Data Buffer 0
xxxx
ADCBUF1 0322 ADC Data Buffer 1
xxxx
ADCBUF2 0324 ADC Data Buffer 2
xxxx
ADCBUF3 0326 ADC Data Buffer 3
xxxx
ADCBUF4 0328 ADC Data Buffer 4
xxxx
ADCBUF5 032A ADC Data Buffer 5
xxxx
ADCBUF12 0338 ADC Data Buffer 12
xxxx
ADCBUF13 033A ADC Data Buffer13
xxxx
Legend:
x
= unk now n valu e on R ese t, — = unim pl em ente d, re ad as ‘
0
’. Rese t va lues a re show n in hex a decim al .
File
Name SFR
Addr Bit 1 5 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 B it 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0 All
Resets
ADCON 0300 ADON —ADSIDLSLOWCLK —GSWTRG— FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0
0003
ADPCFG 0302 — — — — — — — — PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
0000
ADSTAT 0306 — — — — — — — — — — — — P3RDY P2RDY P1RDY P0RDY
0000
ADBASE 0308 ADBASE<15:1> —
0000
ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00
0000
ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20
0000
ADCBUF0 0320 ADC Data Buffer 0
xxxx
ADCBUF1 0322 ADC Data Buffer 1
xxxx
ADCBUF2 0324 ADC Data Buffer 2
xxxx
ADCBUF3 0326 ADC Data Buffer 3
xxxx
ADCBUF4 0328 ADC Data Buffer 4
xxxx
ADCBUF5 032A ADC Data Buffer 5
xxxx
ADCBUF6 032C ADC Data Buffer 6
xxxx
ADCBUF7 032E ADC Data Buffer 7
xxxx
Legend:
x
= unk now n valu e on R ese t, — = unim pl em ente d, re ad as ‘
0
’. Rese t va lues a re show n in hex a decim al .
2008-2014 Microchip Technology Inc. DS70000318G-page 65
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
TABLE 4-29: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS502 DEVICES ONLY
File
Name SFR
Addr Bit 1 5 Bit 1 4 Bit 13 Bit 12 Bi t 11 Bit 10 Bi t 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 All
Resets
ADCON 0300 ADON — ADSIDL SLOWCLK —GSWTRG— FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0
0003
ADPCFG 0302 — — — — — — — — PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
0000
ADSTAT 0306 — — — — — — — — — P6RDY —— P3RDY P2RDY P1RDY P0RDY
0000
ADBASE 0308 ADBASE<15:1> —
0000
ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00
0000
ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20
0000
ADCPC3 0310 — — — — — — — — IRQEN6 PEND6 SWTRG6 TRGSRC64 TRGSRC63 TRGSRC62 TRGSRC61 TRGSRC60
0000
ADCBUF0 0320 ADC Data Buffer 0
xxxx
ADCBUF1 0322 ADC Data Buffer 1
xxxx
ADCBUF2 0324 ADC Data Buffer 2
xxxx
ADCBUF3 0326 ADC Data Buffer 3
xxxx
ADCBUF4 0328 ADC Data Buffer 4
xxxx
ADCBUF5 032A ADC Data Buffer 5
xxxx
ADCBUF6 032C ADC Data Buffer 6
xxxx
ADCBUF7 032E ADC Data Buffer 7
xxxx
ADCBUF12 0338 ADC Data Buffer 12
xxxx
ADCBUF13 033A ADC Data Buffer 13
xxxx
Legend:
x
= unk now n valu e on R ese t, — = unim pl em ente d, re ad as ‘
0
’. Rese t va lues a re show n in hex a decim al .
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 66 2008-2014 Microchip Technology Inc.
TABLE 4-30: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS504 DEVICES ONLY
File
Name SFR
Addr Bit 1 5 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 B it 0 All
Resets
ADCON 0300 ADON —ADSIDLSLOWCLK —GSWTRG— FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0
0003
ADPCFG 0302 — — — — PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
0000
ADSTAT 0306 — — — — — — — — — P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY P0RDY
0000
ADBASE 0308 ADBASE<15:1> —
0000
ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00
0000
ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20
0000
ADCPC2 030E IRQEN5 PEND5 SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50 IRQEN4 PEND4 SWTRG4 TRGSRC44 TRGSRC43 TRGSRC42 TRGSRC41 TRGSRC40
0000
ADCPC3 0310 — — — — — — — — IRQEN6 PEND6 SWTRG6 TRGSRC64 TRGSRC63 TRGSRC62 TRGSRC61 TRGSRC60
0000
ADCBUF0 0320 ADC Data Buffer 0
xxxx
ADCBUF1 0322 ADC Data Buffer 1
xxxx
ADCBUF2 0324 ADC Data Buffer 2
xxxx
ADCBUF3 0326 ADC Data Buffer 3
xxxx
ADCBUF4 0328 ADC Data Buffer 4
xxxx
ADCBUF5 032A ADC Data Buffer 5
xxxx
ADCBUF6 032C ADC Data Buffer 6
xxxx
ADCBUF7 032E ADC Data Buffer 7
xxxx
ADCBUF8 0330 ADC Data Buffer 8
xxxx
ADCBUF9 0332 ADC Data Buffer 9
xxxx
ADCBUF10 0334 ADC Data Buffer 10
xxxx
ADCBUF11 0336 ADC Data Buffer 11
xxxx
ADCBUF12 0338 ADC Data Buffer 12
xxxx
ADCBUF13 033A ADC Data Buffer 13
xxxx
Legend:
x
= unk now n valu e on R ese t, — = unim pl em ente d, re ad as ‘
0
’. Rese t va lues a re show n in hex a decim al .
2008-2014 Microchip Technology Inc. DS70000318G-page 67
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
TABLE 4-31: ANALOG COMPARATOR CONTROL REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY
TABLE 4-32: ANALOG COMPARATOR CONTROL REGISTER MAP dsPIC33FJ16GS502/504 DEVICES ONLY
File
Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CMPCON1 0540 CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000
CMPDAC1 0542 — — — — — —CMREF<9:0>0000
CMPCON2 0544 CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000
CMPDAC2 0546 — — — — — —CMREF<9:0>0000
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CMPCON1 0540 CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000
CMPDAC1 0542 — — — — — —CMREF<9:0>0000
CMPCON2 0544 CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000
CMPDAC2 0546 — — — — — —CMREF<9:0>0000
CMPCON3 0548 CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000
CMPDAC3 054A — — — — — —CMREF<9:0>0000
CMPCON4 054C CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000
CMPDAC4 054E — — — — — —CMREF<9:0>0000
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 68 2008-2014 Microchip Technology Inc.
TABLE 4-33: PERIPHERAL PIN SELECT INPUT REGISTER MAP
TABLE 4-34: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ06GS101
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPINR0 0680 —— INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 — — — — — — — — 3F00
RPINR1 0682 — — — — — — — — — — INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 003F
RPINR2 0684 —— T1CKR5 T1CKR4 T1CKR3 T1CKR2 T1CKR1 T1CKR0 — — — — — — — — 0000
RPINR3 0686 —— T3CKR5 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 —— T2CKR5 T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 3F3F
RPINR7 068E —— IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 —— IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 3F3F
RPINR11 0696 — — — — — — — — — — OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 3F3F
RPINR18 06A4 —— U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 —— U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 003F
RPINR20 06A8 —— SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 —— SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 3F3F
RPINR21 06AA — — — — — — — — — — SS1R5 SS1R54 SS1R3 SS1R2 SS1R1 SS1R0 0000
RPINR29 06BA —— FLT1R5 FLT1R4 FLT1R3 FLT1R2 FLT1R1 FLT1R0 — — — — — — — — 3F00
RPINR30 06BC —— FLT3R5 FLT3R4 FLT3R3 FLT3R2 FLT3R1 FLT3R0 —— FLT2R5 FLT2R4 FLT2R3 FLT2R2 FLT2R1 FLT2R0 3F3F
RPINR31 06BE —— FLT5R5 FLT5R4 FLT5R3 FLT5R2 FLT5R1 FLT5R0 —— FLT4R5 FLT4R4 FLT4R3 FLT4R2 FLT4R1 FLT4R0 3F3F
RPINR32 06C0 —— FLT7R5 FLT7R4 FLT7R3 FLT7R2 FLT7R1 FLT7R0 —— FLT6R5 FLT6R4 FLT6R3 FLT6R2 FLT6R1 FLT6R0 3F3F
RPINR33 06C2 —— SYNCI1R5 SYNCI1R4 SYNCI1R3 SYNCI1R2 SYNCI1R1 SYNCI1R0 —— FLT8R5 FLT8R4 FLT8R3 FLT8R2 FLT8R1 FLT8R0 3F3F
RPINR34 06C4 — — — — — — — — — — SYNCI2R5 SYNCI2R4 SYNCI2R3 SYNCI2R2 SYNCI2R1 SYNCI2R0 3F3F
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPOR0 06D0 —— RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 —— RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000
RPOR1 06D2 —— RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 —— RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 0000
RPOR2 06D4 —— RP5R5 RP5R4 RP5R3 RP5R2 RP5R1 RP5R0 —— RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 0000
RPOR3 06D6 —— RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 —— RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 0000
RPOR16 06F0 —— RP33R5 RP33R4 RP33R3 RP33R2 RP33R1 RP33R0 —— RP32R5 RP32R4 RP32R3 RP32R2 RP32R1 RP32R0 0000
RPOR17 06F2 —— RP35R5 RP35R4 RP35R3 RP35R2 RP35R1 RP35R0 —— RP34R5 RP34R4 RP34R3 RP34R2 RP34R1 RP34R0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2008-2014 Microchip Technology Inc. DS70000318G-page 69
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
TABLE 4-35: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402
AND dsPIC33FJ16GS502
TABLE 4-36: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ16GS404 AND dsPIC33FJ16GS504
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPOR0 06D0 —— RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 —— RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000
RPOR1 06D2 —— RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 —— RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 0000
RPOR2 06D4 —— RP5R5 RP5R4 RP5R3 RP5R2 RP5R1 RP5R0 —— RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 0000
RPOR3 06D6 —— RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 —— RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 0000
RPOR4 06D8 —— RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 —— RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 0000
RPOR5 06DA —— RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 —— RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 0000
RPOR6 06DC —— RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 —— RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 0000
RPOR7 06DE —— RP15R5 RP15R4 RP15R3 RP15R2 RP15R1 RP15R0 —— RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 0000
RPOR16 06F0 —— RP33R5 RP33R4 RP33R3 RP33R2 RP33R1 RP33R0 —— RP32R5 RP32R4 RP32R3 RP32R2 RP32R1 RP32R0 0000
RPOR17 06F2 —— RP35R5 RP35R4 RP35R3 RP35R2 RP35R1 RP35R0 —— RP34R5 RP34R4 RP34R3 RP34R2 RP34R1 RP34R0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPOR0 06D0 —— RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 —— RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000
RPOR1 06D2 —— RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 —— RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 0000
RPOR2 06D4 —— RP5R5 RP5R4 RP5R3 RP5R2 RP5R1 RP5R0 —— RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 0000
RPOR3 06D6 —— RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 —— RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 0000
RPOR4 06D8 —— RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 —— RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 0000
RPOR5 06DA —— RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 —— RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 0000
RPOR6 06DC —— RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 —— RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 0000
RPOR7 06DE —— RP15R5 RP15R4 RP15R3 RP15R2 RP15R1 RP15R0 —— RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 0000
RPOR8 06E0 —— RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 —— RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 0000
RPOR9 06E2 —— RP19R5 RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 —— RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 0000
RPOR10 06E4 —— RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 —— RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 0000
RPOR11 06E6 —— RP23R5 RP23R4 RP23R3 RP23R2 RP23R1 RP23R0 —— RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0 0000
RPOR12 06E8 —— RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 —— RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 0000
RPOR13 06EA —— RP27R5 RP27R4 RP27R3 RP27R2 RP27R1 RP27R0 —— RP26R5 RP26R4 RP26R3 RP26R2 RP26R1 RP26R0 0000
RPOR14 06EC —— RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0 —— RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0 0000
RPOR16 06F0 —— RP33R5 RP33R4 RP33R3 RP33R2 RP33R1 RP33R0 —— RP32R5 RP32R4 RP32R3 RP32R2 RP32R1 RP32R0 0000
RPOR17 06F2 —— RP35R5 RP35R4 RP35R3 RP35R2 RP35R1 RP35R0 —— RP34R5 RP34R4 RP34R3 RP34R2 RP34R1 RP34R0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 70 2008-2014 Microchip Technology Inc.
TABLE 4-37: PORTA REGISTER MAP
TABLE 4-38: PORTB REGISTER MAP FOR dsPIC33FJ06GS101
TABLE 4-39: PORTB REGISTER MAP FOR dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402, dsPIC33FJ16GS404,
dsPIC33FJ16GS502 AND dsPIC33FJ16GS504
TABLE 4-40: PORTC REGISTER MAP FOR dsPIC33FJ16GS404 AND dsPIC33FJ16GS504
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISA 02C0 — — — — — — — — — — — TRISA<4:0> 001F
PORTA 02C2 — — — — — — — — — — —RA<4:0>xxxx
LATA 02C4 — — — — — — — — — — —LATA<4:0>0000
ODCA 02C6 — — — — — — — — — — — ODCA<4:3> — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISB 02C8 — — — — — — — — TRISB<7:0> 00FF
PORTB 02CA — — — — — — — —RB<7:0>xxxx
LATB 02CC — — — — — — — — LATB<7:0> 0000
ODCB 02CE — — — — — — — —ODCB<7:6> — ODCB4 — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISB 02C8 TRISB<15:0> FFFF
PORTB 02CA RB<15:0> xxxx
LATB 02CC LATB<15:0> 0000
ODCB 02CE ODCB<15:11> —— ODCB<8:6> — ODCB4(1)— — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This bit is not available on dsPIC33FJ06GS202/502 devices.
SFR
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISC 02D0 — — TRISC<13:0> 3FFF
PORTC 02D2 — — RC<13:0> xxxx
LATC 02D4 — — LATC<13:0> 0000
ODCC 02D6 —— ODCC<13:11> —— ODCC<8:3> —— ODCC0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2008-2014 Microchip Technology Inc. DS70000318G-page 71
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
TABLE 4-41: SYSTEM CONTRO L REGISTER MAP
TABLE 4-42: NVM REGISTER MAP
TABLE 4-43: PMD REGISTER MAP FOR dsPIC33FJ06GS101 DEVICES ONLY
TABLE 4-44: PMD REGISTER MAP FOR dsPIC33FJ06GS102 DEVICES ONLY
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1)
OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK —CF——OSWEN0300(2)
CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN FRCDIV2 FRCDIV1 FRCDIV0 PLLPOST1 PLLPOST0 — PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0 3040
PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0030
REFOCON 074E ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000
OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000
ACLKCON 0750 ENAPLL APLLCK SELACLK —— APSTSCLR2 APSTSCLR1 APSTSCLR0 ASRCSEL FRCSEL — — — — — — 2300
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The RCON register Reset values are dependent on the type of Reset.
2: The OSCCON register Reset values are dependent on the FOSCx Configuration bits and on type of Reset.
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
NVMCON 0760 WR WREN WRERR — — — — — —ERASE—— NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1)
NVMKEY 0766 — — — — — — — — NVMKEY<7:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset value shown is for POR only. The value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PMD1 0770 — — — T2MD T1MD —PWMMD—I2C1MD—U1MD — SPI1MD —— ADCMD 0000
PMD2 0772 — — — — — —IC2MDIC1MD— — — — — —OC2MDOC1MD0000
PMD3 0774 — — — — —CMPMD— — — — — — — — — — 0000
PMD4 0776 — — — — — — — — — — — —REFOMD— — — 0000
PMD6 077A — — — —PWM4MD ——PWM1MD— — — — — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PMD1 0770 — — — T2MD T1MD —PWMMD—I2C1MD—U1MD — SPI1MD —— ADCMD 0000
PMD2 0772 — — — — — —IC2MDIC1MD— — — — — —OC2MDOC1MD0000
PMD3 0774 — — — — —CMPMD— — — — — — — — — — 0000
PMD4 0776 — — — — — — — — — — — —REFOMD— — — 0000
PMD6 077A — — — — — — PWM2MD PWM1MD — — — — — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 72 2008-2014 Microchip Technology Inc.
TABLE 4-45: PMD REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY
TABLE 4-46: PMD REGISTER MAP FOR dsPIC33FJ16GS402 AND dsPIC33FJ16GS404 DEVICES ONLY
TABLE 4-47: PMD REGISTER MAP FOR dsPIC33FJ16GS502 AND dsPIC33FJ16GS504 DEVICES ONLY
SFR
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PMD1 0770 — — — T2MD T1MD —PWMMD—I2C1MD—U1MD — SPI1MD —— ADCMD 0000
PMD2 0772 — — — — — — —IC1MD— — — — — — —OC1MD0000
PMD3 0774 — — — — —CMPMD— — — — — — — — — — 0000
PMD4 0776 — — — — — — — — — — — —REFOMD— — — 0000
PMD6 077A — — — — — — PWM2MD PWM1MD — — — — — — — — 0000
PMD7 077C — — — — — — CMP2MD CMP1MD — — — — — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SFR
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PMD1 0770 —— T3MD T2MD T1MD —PWMMD—I2C1MD—U1MD — SPI1MD —— ADCMD 0000
PMD2 0772 — — — — — —IC2MDIC1MD— — — — — —OC2MDOC1MD0000
PMD3 0774 — — — — — — — — — — — — — — — — 0000
PMD4 0776 — — — — — — — — — — — —REFOMD— — — 0000
PMD6 077A — — — — — PWM3MD PWM2MD PWM1MD — — — — — — — — 0000
PMD7 077C — — — — — — — — — — — — — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SFR
Name SFR
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PMD1 0770 —— T3MD T2MD T1MD —PWMMD—I2C1MD—U1MD — SPI1MD —— ADCMD 0000
PMD2 0772 — — — — — —IC2MDIC1MD— — — — — —OC2MDOC1MD0000
PMD3 0774 — — — — —CMPMD— — — — — — — — — — 0000
PMD4 0776 — — — — — — — — — — — —REFOMD— — — 0000
PMD6 077A — — — — PWM4MD PWM3MD PWM2MD PWM1MD — — — — — — — — 0000
PMD7 077C — — — — CMP4MD CMP3MD CMP2MD CMP1MD — — — — — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2008-2014 Microchip Technology Inc. DS70000318G-page 73
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
4.2.6 SOFTWARE STACK
In addition to its use as a Working register, the W15
register in the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 devices is also used as a
software Stack Pointer. The Stack Pointer always
points to the first available free word and grows from
lower to higher addresses. It predecrements for stack
pops and post-increments for stack pushes, as shown
in Figure 4-6. For a PC push during any CALL instruc-
tion, the MSb of the PC is zero-extended before the
push, ensuring that the MSb is always clear.
The Stack Pointer Limit register (SPLIM) associated
with the S t ack Pointe r set s an upp er address bounda ry
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap will not occur. The stack error trap will occur on a
subsequent push operation. For example, to cause a
stack error trap when the stack grows beyond address
0x1000 in RAM, initialize the SPLIM with the value
0x0FFE.
Similarly, a S t ack Po inter un derflow (stack error) trap i s
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-6: CALL STACK FRAME
4.3 Instruction Addressing Modes
The addressing modes shown in Table 4-48 form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
4.3.1 FILE REGISTER INSTRUCTIONS
Most fil e re gis ter i ns truc tio ns use a 13-bit ad dres s f iel d
(f) to directly address data present in the first
8192 bytes of data memory (Near Data Space). Most
file regis ter instructio ns employ a W orking regist er , W0,
whic h is den oted as WREG in these i nstruc tions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which w rites the re sult t o a re gister or regi ster pair . Th e
MOV instruction allows additional flexibility and can
access the entire data space.
4.3.2 MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where, Operand 1 is always a Working regi ster (t hat is ,
the addressing mode can only be register direct ), which
is referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or a data memory
location. The following addressing modes are
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
Note: A PC push during exception processing
concat enates the SRL regis ter to the M Sb
of the PC prior to the push.
<Free Word>
PC<15:0>
000000000
015
W15 (before CALL)
W15 (after CALL)
Stack Grows Toward
Higher Address
0x0000
PC<22:16>
POP : [--W15]
PUSH : [W15++]
Note: Not all instructions support all the
addressing modes given above. Individ-
ual instructions can support different
subsets of thes e add re ssi ng mod es.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 74 2008-2014 Microchip Technology Inc.
TABLE 4-48: FUNDAMENTAL ADDRESSING MODES SUPPORTED
4.3.3 MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP accumulator class of
instructions to provide a greater addressing flexibility
than other instructions. In addition to the addressing
modes su pported by mo st MCU instru ctions, move and
accum ula tor in stru ct ion s al so s upp ort R eg is ter Ind irec t
with Regis ter Of fs et Addr ess in g mod e, als o refer red to
as Register Indexed mode.
In summary, the following addressing modes are
supported by move and accumulator instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirec t Pre-mo dif ied
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• 16-bit Literal
4.3.4 MAC INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred
to as MAC instructions, use a simplified set of addressing
modes to allow the user application to effectively
manipulate the Data Pointers through register indirect
tables.
The two-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W 8 and W9 a re always direc ted to the X RAGU ,
and W10 and W11 are always directed to the Y AGU.
The Effective Addresses generated (before and after
modification) must, the refore, be valid addre sses within
X dat a sp ace for W 8 and W9 and Y d ata s pace for W10
and W11.
In summary, the following addressing modes are
supported by the MAC class of instructions:
• Register Indirect
• Register Indirect Post-Modified by 2
• Register Indirect Post-Modified by 4
• Register Indirect Post-Modified by 6
• Register Indirect with Register Offset (Indexed)
4.3.5 OTHER INSTRUCTIONS
Besides the addressing modes outlined previously , some
instructions use literal constants of various sizes. For
example, BRA (branch) instructions use 16-bit signed
literals to specify the branch destination directly , whereas
the DISI instruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
opera nd or r esu lt is imp li ed by the o pco de itself . Cer tain
oper at io ns , s uc h as NOP, do not have any operands.
Addressing Mode Description
File Register Direct The address of the file register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn forms the Effective Address (EA).
Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset
(Register Indexed) The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
Note: For the MOV instructions, the addressing
mode spe cified in the ins truction can dif fer
for the source and destination EA. How-
ever, the 4-bit Wb (register offset) field is
shared by both source and destination
(but typically only used by one).
Note: Not all instructions support all the
addressing modes given above. Individu al
inst ruc tio ns m ay su ppo rt diffe r ent sub se ts
of these addressing modes.
Note: Register Indirect with Register Offset
Addressing mode is available only for W9
(in X space) and W11 (in Y space).
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
4.4 Modulo Addressing
Modulo Addressing mode is a method used to provide
an automated means to support circular data buffers
using hardware. The objective is to remove the need
for software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Modulo Addressing can operate in either data or program
space (since the Data Pointer mechanism is essentially
the sam e for both ). One ci rcul ar buf f er can be suppo rted
in each of the X (which also provides the pointers into
progr am space) and Y da ta space s. Modu lo Addr e ssi ng
can operate on any W register Pointer . However , it is not
advisable to use W14 or W15 for Modulo Addressing
since these two registers are used as the Stack Frame
Pointer and St ack Pointer, respectively.
In general, any particular circular buffer can be
configu red to operate in only one dire ction as there are
certain restrictions on the buffer st art address (for incre-
menting buffers), or end address (for decrementing
buffers), based upon the direction of the buffer.
The only exception to the usage restrictions is for
buffers that have a power-of-two length. As these
buffers satisfy the start and end address criteria, they
can operate in a bidirectional mode (that is, address
boundary checks are performed on both the lower and
upper address boundaries).
4.4.1 START AND END ADDRESS
The Modulo Addressing scheme requires that a
starting and ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 4-1).
The leng th of a circular buf fer is not di rectly spec ified. It
is determined by the difference between the
correspo nding st art an d end ad dresses . The maxim um
possible length of the circular buffer is 32K words
(64 Kbytes).
4.4.2 W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control
register, MODCON<15:0>, contains enable flags as
well as a W register field to specify the W Address
registers. The XWM and YWM fields select the
registers that will operate with Modulo Addressing:
• If XWM = 15, X RAGU and X WAGU Modulo
Addressi ng is disab led .
• If YWM = 15, Y AGU Modulo Addressing is
disabled.
The X Address Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Table 4-1). Modul o Addre ssing is
enabled for X data sp ace when XWM is set to any value
other than ‘15’ and the XMODEN bit is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM) to
which Modulo Addressing is to be applied is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than
‘15’ and the YMODEN bit is set at MODCON<14>.
FIGURE 4-7: MODULO ADDRESSING OPERATION EXAM PLE
Note: Y space Modulo Addressing EA calcula-
tions assume word-sized data (LSb of
every EA is always clear).
0x1100
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
Byte
Address MOV #0x1100, W0
MOV W0, XMODSRT ;set modulo start address
MOV #0x1163, W0
MOV W0, MODEND ;set modulo end address
MOV #0x8001, W0
MOV W0, MODCON ;enable W1, X AGU for modulo
MOV #0x0000, W0 ;W0 holds buffer fill value
MOV #0x1110, W1 ;point W1 to buffer
DO AGAIN, #0x31 ;fill the 50 buffer locations
MOV W0, [W1++] ;fill the next location
AGAIN: INC W0, W0 ;increment the fill value
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 76 2008-2014 Microchip Technology Inc.
4.4.3 MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. Address boundaries check for addresses
equal to:
• The upper boundary addresses for incrementing
buffers
• The lower boundary addresses for decrementing
buffers
The addre ss bounda ries check fo r addresse s less than
or greater th an the upper (for i ncrementing buffers) an d
lower (for decrementing buffers) boundary addresses
(not just equal to). Address changes can, therefore,
jump b eyond boundarie s and s till be a djusted c orrect ly.
4.5 Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data re-ordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which can be a constant value or register
content s, is regarded as having its bit ord er reversed. T he
address source and destination are kept in normal order .
Thus, the only operand requiring reversal is the modifier .
4.5. 1 BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing mode is enabled in any of
these situations:
• BWM bits (W register selection) in the MODCON
register are any value other than 15 (the stack
cannot be accessed using Bit-Reversed
Addressing)
• The BREN bit is set in the XBREV register
• The addressing mode us ed is Regist er Indirect
with Pre-Increment or Post-Increment
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
XB<14:0> is the Bit-Reversed Address modifier, or
‘pivot p oint,’ which is typica lly a cons tant. In th e case of
an FFT comput ation, its value is equal to half of the FFT
dat a buffer size.
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or Post-
Increment Addressing and word-sized data writes. It
will not function for any other addressing mode or for
byte-sized data, and normal addresses are generated
instead. When Bit-Reversed Addressing is active, the
W Address Pointer is always added to the address
modifie r (XB), and the of fset a ssociated with the R egis-
ter Indi rect Addres si ng m ode i s ign ore d. In add iti on, as
word-sized data is a requirement, the LSb of the EA is
ignored (and always clear).
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, a write to the
XBREV register sh ou ld not be imm ediate ly follo wed b y
an indire ct read operat ion using th e W register that ha s
been designated as the Bit-Reversed Pointer.
Note: The modulo corrected Effective Address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the Effective Address.
When an address offset (such as
[W7 + W2]) is used, Modulo Addressing
correction is performed but the contents of
the register remain unchanged.
Note: All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Note: Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. If an application attempts to do
so, Bit-Reversed Addressing will assume
priority when active for the X WAGU and X
WAGU; Modulo Addressing will be dis-
abled. However, Modulo Addressing will
continue to function in the X RAGU .
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FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE
TABLE 4-49: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address Bit-Reversed Address
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0000 00000 0
0001 11000 8
0010 20100 4
0011 31100 12
0100 40010 2
0101 51010 10
0110 60110 6
0111 71110 14
1000 80001 1
1001 91001 9
1010 10 0101 5
1011 11 1101 13
1100 12 0011 3
1101 13 1011 11
1110 14 0111 7
1111 15 1111 15
b3 b2 b1 0
b2 b3 b4 0
Bit Locations Swapped Left-to-Right
Around Cente r of Binary Value
Bit-Reversed Address
XB = 0x0008 for a 16-Word Bit-Reversed Buffer
b7 b6 b5 b1
b7 b6 b5 b4
b11 b10 b9 b8
b11 b10 b9 b8
b15 b14 b13 b12
b15 b14 b13 b12
Sequent ial Address
Pivot Poi nt
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 78 2008-2014 Microchip Technology Inc.
4.6 Interfacing Program and Data
Memory Spaces
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 architecture uses a 24-bit-wide program space and a
16-bit-wide data space. The architecture is also a
modified Harvard scheme, meaning that data can also be
present in the program space. To use this data
successfully, it must be accessed in a way that preserves
the alignment of information in both spaces.
Aside from normal execution, th e dsPIC33FJ06GS10 1/
X02 and dsPIC33FJ16GSX02/X04 architecture
provides two methods by which program space can be
acce ssed during operati on:
• Using ta ble instru ctions to ac cess indiv idual bytes
or words anywhere in the program space
• Rema pping a portion of the pr ogram space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an appli cation to access a large b lock of
data on a read-only basis, which is ideal for look ups
from a large table of static data. The application can
only access the least significant word of the program
word.
4.6. 1 ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit da ta regist ers. The soluti on depends on the
interface method to be used.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determ ine if the ope ration occurs in the user mem ory
(TBLPAG<7> = 0) or the configuration memory
(TBLPAG<7> = 1).
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the Most
Signific ant bit of th e EA is ‘1’, PSVPAG is concatenated
with t he lower 15 b its of the EA to form a 23-bit program
space address. Unlike table operations, this limits
remappi ng ope rations stric tly to the u ser m emory are a.
Table 4-50 and Figure 4-9 sho w how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word, and D<15:0> refers to a data space word.
TABLE 4-50: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Type Access
Space Program Space Address
<23> <22:16> <15> <14:1> <0>
Instruction Access
(Code Execution) User 0PC<22:1> 0
0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
(Byte/Word Read/Write) User TBLPAG<7:0> Data EA<15:0>
0xxx xxxx xxxx xxxx xxxx xxxx
Configuration TBLPAG<7:0> Data EA<15:0>
1xxx xxxx xxxx xxxx xxxx xxxx
Program Space Visibility
(Block Remap/Read) User 0PSVPAG<7:0> Data EA<14:0>(1)
0 xxxx xxxx xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always ‘1’ in th is case, b ut i s not us ed in calc ul atin g t he program s p a ce add res s. Bit 15 of
the address is PSVPAG<0>.
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FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
0Program Counter
23 Bits
1
PSVPAG
8 Bits
EA
15 Bits
Program Counter(1)
Select
TBLPAG
8 Bits
EA
16 Bits
Byte Select
0
0
1/0
User/Configuration
Table Operation s(2)
Program Space Visibility(1)
Space Select
24 Bits
23 Bits
(Remapping)
1/0
0
Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to
maintain word alignment of data in the program and data spaces.
2: Table o perations are not required to be wo rd-aligned. Table Re ad operat ions are permitted
in the configuration memory space.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 80 2008-2014 Microchip Technology Inc.
4.6.2 DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper 8 bits of a program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
wide word add res s s p ac es , res id ing si de by si de, each
with the same address range. TBLRDL and TBLWTL
access the space that contains the least significant
data word. TBLRDH and TBLWTH access the space that
cont ains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
•TBLRDL (Table R ead Low):
- In Word mode, this instruction maps the
lower wor d of t he program space location
(P<15:0>) t o a dat a add res s (D<15:0 >).
- In Byte mode, either the upper or lower byte
of the lower program word is mapped to the
lower byte o f a da ta addre ss. The upp er by te
is selected when byte select is ‘1’; the lower
byte is selected when it is ‘0’.
•TBLRDH (Table Read High):
- In Word mode, this instruction maps the entire
upper word of a program address (P<23:16>)
to a data address. Note that D<15:8>, the
‘phantom byte’, will always be ‘0’.
- In Byte mode, this instruction maps the upper
or low er byt e of the progra m word t o D<7: 0> of
the data ad dre s s, in the TBLRDL instruction.
The da ta is a lwa y s ‘0’ wh en th e u pp er
‘ph an tom ’ by te i s se lected (By te Se le c t = 1).
Similarly, two table instructions, TBLWTH and TBLWTL,
are used to write individual bytes or words to a program
space address. The details of their operation are
explained in Section 5.0 “Flash Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPA G). TBLPAG covers the entire program
memory space of the device, including user and con-
figuration spaces. When TBLPAG<7> = 0, the table
page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
sp ace.
FIGURE 4-10: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
081623
00000000
00000000
00000000
00000000
‘Phantom ’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.W
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
23 15 0
TBLPAG
02
0x000000
0x800000
0x020000
0x030000
Program Space
The address for the table operation is determ ined by the data EA
within the page defined by the TBLPAG register.
Only read operations are s hown; write operations are also va lid in
the user memory area.
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
4.6.3 READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 1 6K word p age of the program sp ace.
This option provides transparent access to stored
constant data from the data space without the need to
use special instructions (such as TBLRDL/H).
Program space access through the data space occurs
if the Mo st Significan t bit of the dat a space EA is ‘ 1’ and
Program Space Visibility (PSV) is enabled by setting
the PSV bit in the Core Control register
(CORCON<2>). The location of the program memory
space to be mapped into the data space is determined
by the Program Space Visibility Page register
(PSVPAG). This 8-bit register defines any one of 256
possible pages of 16K words in program space. In
effect, PSVPAG functions as the upper 8 bits of the
program memory address, with the 15 bits of the EA
functioning as the lower bits. By incrementing the PC
by 2 for each program memory word, the lower 15 bits
of data space addresses directly map to the lower
15 bits in the corresponding program space addresses.
Data reads to this area add a cycle to the instruction
being executed, since two program memory fetches
are required.
Although each data space address 8000h and higher
maps directly into a corresponding program memory
address (see Figure 4-11), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions require
one instruction cycle in addition to the specified
execution time. All other instructions require two
ins truction cycles in addition to the specified execution
time.
For operations that use PSV, and are executed inside
a REPEAT loop, the se in stances require two ins truc tio n
cycle s in add iti on to the spe ci fied execution time of th e
instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interr upt is serviced
Any other iteration of the REPEAT loop will allow the
instruction using PSV to access data, to execute in a
single cycle.
FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION
Note: PSV access is tempor arily disabled during
Table Reads/Writes.
23 15 0
PSVPAG Data Space
Program Space
0x0000
0x8000
0xFFFF
02 0x000000
0x800000
0x010000
0x018000
When CORCON<2> = 1 and EA<15> = 1:
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space...
Data EA<14:0>
...while the lower 15 bits
of the EA specify an
exact address within
the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
PSV Area
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 82 2008-2014 Microchip Technology Inc.
NOTES:
2008-2014 Microchip Technology Inc. DS70000318G-page 83
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
5.0 FLASH PROGRAM MEMORY
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices contain int ernal Flash program memory for
storing and executing application code. The memory is
readable, w ritable and e rasable d uring n ormal ope ration
over the entire VDD range.
Flash memory can be programmed in two ways:
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• Run-Time Self-Programming (RTSP)
ICSP allows a dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 device to be serially
progra mmed w hile in t he en d app licati on c ircuit. This is
done with two lines for programming clock and
programming data (one of the alternate programming
pin pairs: PGECx/PGEDx, and three other lines for
power (VDD), ground (VSS) and Master Clear (MCLR).
This allows customers to manufacture boards with
unprogrammed devices and then program the Digital
Signal Co ntro lle r just before shipping the prod uc t. Thi s
also allows the most recent firmware or a custom
firmware to be programmed.
RTSP is accomplished using TBLRD (Table Read) and
TBLWT (Table Write) instructions. With RTSP, the user
application can write program memory data, either in
blocks or ‘ rows ’ of 6 4 ins tructi ons (1 92 by tes) at a t ime,
or a single program memory word, and erase program
memory in blocks or ‘pages’ of 512 instructions
(1536 bytes) at a time.
5.1 Table Instructions and Flash
Programming
Regardless of the method used, all programming of
Flash memory is done with the Table Read and Table
Write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed us ing bit s<7:0> of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
The TBLRDH and TBLWTH instructio ns are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Flash Programming”
(DS70191) in the “dsPIC33F/PIC24H
Family Reference Manual”, w hich is avail-
able from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data she et for device-specific regis ter
and bit information.
0
Program Counter
24 Bi ts
Prog ram C ounter
TBLPAG Reg
8 Bits
Wor king Reg EA
16 Bits
Byte
24-Bit EA
0
1/0
Select
Using
Table Instruction
Using
User/Configuration
Space Select
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 84 2008-2014 Microchip Technology Inc.
5.2 RTSP Operation
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 Flash program memory array is organized into rows
of 64 instructions or 192 bytes. RTSP allows the user
application to erase a page of memory, which consists of
eight rows (512 instructions) at a time, and to program
one row or one word at a time. Table 24-12 shows typical
erase and programming times. The 8-row erase pages
and single row write rows are edge-aligned from the
beginning of program memory, on boundaries of
1536 bytes and 192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basi c sequence for R TSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the co ntro l bits in the NVMCON regi st er. A tota l
of 64 TBLWTL and TBLWTH instructions are required
to load the instru cti ons .
All of the Table Wri te operation s a re si ngl e-w or d w rite s
(two instruction cycles) because only the buffers are
written. A programming cycle is required for
programming each row.
5.3 Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
program ming operation is finished.
The programming time depends on the FRC accuracy
(see Table 24-20) and the value of the FRC Oscillator
Tuning register (see Register 8-4). Use the following
formula to calculate the minimum and maxim um values
for the Row Write Time, Page Erase Time, and Word
Write Cycle Time parameters (see Table 24-12).
EQUATION 5-1: PROGRAMMING TIME
For example, if the device is operating at +125°C, the
FRC accuracy will be ±5%. If the TUN<5:0> bits (see
Register 8-4) are set to ‘b111111, the minimum row
write time is equal to Equation 5-2.
EQUATION 5-2: MINIMUM ROW WRITE
TIME
The maximum row write ti me is equal to Equation 5-3.
EQUATION 5-3: MAXIMUM ROW WRITE
TIME
Setting the WR bit (NVMCON<15>) starts the opera-
tion, and the WR bit is automatically cleared when the
operation is finished.
5.4 Control Registers
Two SFRs are used to read and write the program
Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user application must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 5.3
“Programming Operations” for further details.
T
7.37 MHz FRC Accuracy%FRC Tunin g%
--------------------------------------------------------------------------------------------------------------------------
TRW 11064 C ycles
7.37 MHz 10.05+1 0.00375–
---------------------------------------------------------------------------------------------- 1.435ms==
TRW 11064 Cy cles
7.37 MHz 10.05–1 0.00375–
----------------------------------------------------------------------------------------------1.586ms==
2008-2014 Microchip Technology Inc. DS70000318G-page 85
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 5-1: NVMCON: FLASH ME MORY CONTROL REGISTER
R/SO-0(1)R/W-0(1)R/W-0(1)U-0 U-0 U-0 U-0 U-0
WR WREN WRERR — — — — —
bit 15 bit 8
U-0 R/W-0(1)U-0 U-0 R/W-0(1)R/W-0(1)R/W-0(1)R/W-0(1)
— ERASE ——NVMOP3
(2)NVMOP2(2)NVMOP1(2)NVMOP0(2)
bit 7 bit 0
Legend: SO = Settable Only bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 WR: Write Control bit(1)
1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once the operation is complete
0 = Program or erase operation is complete and inactive
bit 14 WREN: Write Enable bit(1)
1 = Enable Flash program /erase operation s
0 = Inhibit Flash program/erase operations
bit 13 WRERR: Write Sequence Error Flag bit(1)
1 = An improper program or erase sequence attempt, or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12-7 Unimplemented: Read as ‘0’
bit 6 ERASE: Erase/Program Enable bit(1)
1 = Performs the erase operation specified by NVMOP<3:0> on the next WR command
0 = Performs the program operation specified by NVMOP<3:0> on the next WR command
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,2)
If ERASE = 1:
1111 = Memory bulk erase operation
1101 = Erase general segment
0011 = No operation
0010 = Memory page erase operation
0001 = No operation
0000 = Erase a single C onfiguration register byte
If ERASE = 0:
1111 = No operation
1101 = No operation
0011 = Memory word program operation
0010 = No operation
0001 = Memory row program operation
0000 = Program a single Configuration register byte
Note 1: These bits can only be Reset on POR.
2: All other combinations of NVMOP<3:0> are unimplemented.
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REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 NVMKEY<7:0>: Nonvolatile Memory Key bits (write-only)
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5.4.1 PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
One row of program Flash memory can be
prog ram med at a ti me. To ach ieve this, it is ne cess ary
to erase th e 8-row erase pag e that conta ins the desire d
row. The general process is:
1. Read eight rows of program memory
(512 instructions) and store in data RAM.
2. Update the program data in RAM with the desired
new data.
3. Erase the block (see Example 5-1):
a) Set t he NVMOP<3:0> bits (NVMCO N<3:0>) t o
‘0010’ to configure for block erase. Set
the ERASE (NVMCON<6>) and WREN
(NVMCON<14>) bits.
b) Write the starting address of the page to be
erased into the TBLPAG and W registers.
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU st alls for the dur ation
of the erase cycle. When the erase is done, the
WR bit is cleared automatically.
4. Write the first 64 instructions from data RAM into
the program memory buffers ( see Example 5-2).
5. Write the program block to Flash memory:
a) Set the NVMOP<3:0> bits to ‘0001’ to
configure for row programming. Clear the
ERASE bit and set the WREN bit.
b) Write 0x55 to the NVMKEY register.
c) Write 0xAA to the NVMKEY register.
d) Set the WR bit. The programming cycle begins
and th e C PU stal ls fo r t he d urat i on of th e w ri te
cycle. When the write to Flash memory is done,
the WR bit is cleared automatically.
6. Repeat Steps 4 and 5, using the next available
64 instructions f rom the block in data RAM by incre-
menting the value in the TBLPAG register, until all
512 instructions are written back to Flash memory.
For protection against accidental operations, the write
initiate sequence for the NVMKEY register must be
used to allow any erase or program operation to
proceed. After the programming command has been
executed, the user application must wait for the pro-
grammi ng time until program ming is complete . The two
instructions following the start of the programming
sequenc e sho ul d be NOPs, as shown in Example 5-3.
EXAMPLE 5-1: ERASING A PROGRAM MEMORY PAGE
; Set up NVMCON for block erase operation
MOV #0x4042, W0 ;
MOV W0, NVMCON ; Initialize NVMCON
; Init pointer to row to be ERASED
MOV #tblpage(PROG_ADDR), W0 ;
MOV W0, TBLPAG ; Initialize PM Page Boundary SFR
MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer
TBLWTL W0, [W0] ; Set base address of erase block
DISI #5 ; Block all interrupts with priority <7
; for next 5 instructions
MOV #0x55, W0
MOV W0, NVMKEY ; Write the 55 key
MOV #0xAA, W1 ;
MOV W1, NVMKEY ; Write the AA key
BSET NVMCON, #WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted
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EXAMPLE 5-2: LOADING THE WRITE BUFFERS
EXAMPLE 5-3: INITIATING A PROGRAMMING SEQUENCE
; Set up NVMCON for row programming operations
MOV #0x4001, W0 ;
MOV W0, NVMCON ; Initialize NVMCON
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV #0x0000, W0 ;
MOV W0, TBLPAG ; Initialize PM Page Boundary SFR
MOV #0x6000, W0 ; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV #LOW_WORD_0, W2 ;
MOV #HIGH_BYTE_0, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
; 1st_program_word
MOV #LOW_WORD_1, W2 ;
MOV #HIGH_BYTE_1, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
; 2nd_program_word
MOV #LOW_WORD_2, W2 ;
MOV #HIGH_BYTE_2, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
•
•
•
; 63rd_program_word
MOV #LOW_WORD_31, W2 ;
MOV #HIGH_BYTE_31, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
DISI #5 ; Block all interrupts with priority <7
; for next 5 instructions
MOV #0x55, W0
MOV W0, NVMKEY ; Write the 55 key
MOV #0xAA, W1 ;
MOV W1, NVMKEY ; Write the AA key
BSET NVMCON, #WR ; Start the erase sequence
NOP ; Insert two NOPs after the
NOP ; erase command is asserted
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
6.0 RESETS
The Reset module combines all Reset sources and
controls the devi ce Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Rese t
• BOR: Brown-out Reset
•MCLR
: Master Clear Pin Reset
• SWR: Softw are RESET Instruction
• WDTO: Watchdog Timer Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• I OPUWR: Illegal Co nditi on Device Reset
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
A simplified block diagram of the Reset module is
shown in Figure 6-1.
Any active source of Reset will make the SYSRST
signa l active. On sy stem Reset, some of the r egisters
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
All type s of de vi ce Res et set a corres pondi ng st atus bit
in the RCO N reg ister to i ndi cate the typ e o f Res et (se e
Register 6-1).
A POR clears all the bits, except for the POR bit
(RCON<0>), which i s s et. The user app li cat ion can set
or clear any bit at any time during code execution. The
RCON bit s only serve as status bit s. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The functi on of these bits is discusse d in other section s
of this manual.
FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Reset” (DS70192) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Micro c hi p w e b si te (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Refer to the specific peripheral section or
Section 3.0 “CPU” of this data sheet for
register R ese t st ate s.
Note: The status bits in the RCON register
should be cleared after they are read so
that th e n ext R CON re giste r v alu e aft er a
device Reset is meaningful.
MCLR
VDD
Internal
Regulator BOR
Sleep or Idle
RESET Instruction
WDT
Module
Glitch Filter
Trap Conflict
Illegal Opcode
Uninitialized W Register
SYSRST
VDD Rise
Detect POR
Configuration Mismatch
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DS70000318G-page 90 2008-2014 Microchip Technology Inc.
REGISTER 6-1: RCON: RESET CONTROL REGISTER(1)
R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
TRAPR IOPUWR — — — —CMVREGS
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
EXTR SWR SWDTEN(2)WDTO SLEEP IDLE BOR POR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or Uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or Uninitialized W register Reset has not occurred
bit 13-1 0 Unimplemented: Read as ‘0’
bit 9 CM: Configuration Mi smatch Flag bit
1 = A Configuration Mismatch Reset has occurred
0 = A Configuration Mismatch Reset has NOT occurred
bit 8 VREGS: Voltage Regulator Standby During Sleep bit
1 = Voltage regulator is active during Sleep
0 = Voltage regulator goes into Standby mode during Sleep
bit 7 EXTR: External Reset Pin (MCLR) bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset Flag (Instruction) bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5 SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
bit 3 SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2 IDLE: Wake-up from Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
Note 1: All of the Res et sta tus bit s can be set or cleare d in sof twar e. Setting on e of these bit s in so ft ware does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
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bit 1 BOR: Brown-out Re set Flag bi t
1 = A Brown-out Reset has occurred
0 = A Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED)
Note 1: All of the Res et sta tus bit s can be set or cleare d in sof twar e. Setting on e of these bit s in so ft ware does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
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6.1 System Reset
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 families of devices have two types of Reset:
•Cold Reset
•Warm Reset
A Cold Reset is the result of a Power-on Reset (POR)
or a Brown-out Reset (BOR). On a Cold Reset, the
FNOSCx Configuration bits in the FOSC Configuration
register select the device clock source.
A Warm Reset is the result of all the other Reset
sources, including the RESET instruction. On Warm
Reset, the device will continue to operate from the
current clock source as indicated by the Current
Oscillator Selection (COSC<2:0>) bits in the Oscillator
Control (OSCCON<14:12>) register.
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is detai led in Figure 6-2.
TABLE 6-1: OSCILLATOR DELAY
Oscillator Mode Oscillator
Startup Delay Oscillator
Startup Timer PLL Lock Time Total Delay
FRC, FRCDIV16,
FRCDIVN TOSCD(1)——TOSCD(1)
FRCPLL TOSCD(1)—TLOCK(3)TOSCD + TLOCK(1,3)
XT TOSCD(1)TOST(2)—TOSCD + TOST(1,2)
HS TOSCD(1)TOST(2)—TOSCD + TOST(1,2)
EC ——— —
XTPLL TOSCD(1)TOST(2)TLOCK(3)TOSCD + TOST + TLOCK(1,2,3)
HSPLL TOSCD(1)TOST(2)TLOCK(3)TOSCD + TOST + TLOCK(1,2,3)
ECPLL — — TLOCK(3)TLOCK(3)
LPRC TOSCD(1)——TOSCD(1)
Note 1: TOSCD = Os cillator start-up delay (1.1 s max for FRC, 70 s max for LPRC). Crystal oscillator start-up
times vary with crystal characteristic s, load capacitance, etc.
2: TOST = Oscillator Start-up Timer delay (1024 oscillator clock period). For example, TOST = 102.4 s for a
10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.
3: TLOCK = PLL lock time (1.5 ms nominal) if PLL is enabled.
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FIGURE 6-2: SYSTEM RESET TIMING
Reset Run
Device Status
VDD
VPOR
VBOR
POR Reset
BOR Reset
SYSRST
TPWRT
TPOR
TBOR
Oscillator Clock
TOSCD TOST TLOCK
Time
FSCM TFSCM
1
23
4
5
6
Note 1: POR Reset: A P OR circuit holds the device in Re set when the power supply is turned on. The POR c ircuit is active
until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed.
2: BOR Reset: The on-chip voltage regulator has a BO R circuit that keeps the device in Reset until VDD crosses the
VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes
stable.
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of
time (TPWRT) after a BOR. The delay, TPWRT, ensures that the system power supp lies have stabilized at the appro-
priate level for full-speed operation. After the delay, TPWRT has elapsed and the SYSRST becomes inactive, which in
turn, enables the selected oscillator to start generating clock cycles.
4: Oscillator Delay: The total delay for the clock t o be ready for various c lock sourc e select ions is given in Table 6-1.
Refer to Section 8 .0 “Oscillato r Configu rati on” for more information.
5: When the oscillator clock is ready, the processor begins execution from location, 0x000000. The user application
programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up
routine.
6: If the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is ready
and the delay, TFSCM, has elapsed.
TABLE 6-2: OSCILLATOR DELAY
Symbol Parameter Value
VPOR POR Threshold 1.8V nominal
TPOR POR Extension Time 30 s maximum
VBOR BOR Threshold 2.5V nominal
TBOR BOR Extension Time 100 s maximum
TPWRT Programmable
Power-up Time Delay 0-128 ms nominal
TFSCM Fail-Safe Clock Monitor
Delay 900 s maximum
Note: When the device exits the Reset
condition (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges; otherwise,
the device may not function correctly.
The user application must ensure that
the delay between the time power is first
applied, and the time SYSRST becomes
inactive, is long enough to get all
operating parameters within specifica tion.
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6.2 Power-on Reset (POR)
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
VDD cro sses the VPOR threshold and the delay, TPOR,
has elapsed. The delay, TPOR, ensures the internal
device bias circuits become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate
requirements to generate the POR. Refer to
Section 24.0 “Electrical Characteristics” for details.
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
6.2.1 Brown-out Reset (BOR) and
Power-up Timer (PWRT)
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the VDD is too low
(VDD < VBOR) for proper device operation. The BOR
circuit keeps the device in Reset until VDD crosses the
VBOR threshold and the delay, TBOR, has elapsed. The
delay, TBOR, ensures the voltage regulator output
becomes stable.
The BOR status (BOR) bit in the Reset Control
(RCON<1>) register is set to indicate the Brown-out
Reset.
The devi ce will not run at ful l s pee d after a BOR as the
VDD should rise to acceptable levels for full-speed
operation. The PWRT provides power-up time delay
(TPWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The Power-up Timer Delay (TPWRT) is pro gramm ed b y
the Power-on Reset Timer Value Select
(FPWRT<2:0>) bits in the FPOR Configuration
(FPOR<2:0>) register, which provides eight settings
(from 0 ms to 128 ms). Refer to Section 21.0 “Speci al
Features” for further details.
Figure 6-3 shows the typical brown-out scenarios. The
Reset delay (TBOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point.
FIGURE 6-3: BROWN-OUT SITUATIONS
VDD
SYSRST
VBOR
VDD
SYSRST
VBOR
VDD
SYSRST
VBOR
TBOR + TPWRT
VDD Dips before PWRT Expires
TBOR + TPWRT
TBOR + TPWRT
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6.3 External Reset (EXTR)
The External Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt tri gger inpu t with an
additio nal g lit ch fi lter. Rese t puls es t hat ar e l onger than
the minimum pulse width will generate a Reset. Refer
to Section 24.0 “Electrical Characteristics” for
minimum pulse width specifications. The External
Reset (MCLR) pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
6.3.0.1 EXTERNAL SUPER VISO RY
CIRCUIT
Many systems have external supervisory circuits that
generate Reset signals to reset multiple devices in the
system. This External Reset signal can be directly
connected to the MCLR pin to reset the device when
the rest of the system is reset.
6.3.0.2 INTERNAL SUPERVISORY CIRCUIT
When using the internal power supervisory circuit to
reset the device, the External Reset pin (MCLR) should
be tied directly or resistively to VDD. In this case, the
MCLR pin will not be used to generate a Reset. The
External Reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.4 Software RESET Instruction (SWR)
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a
special Reset state. This Reset state will not
re-initia lize t he clo ck. Th e clo ck sourc e in ef fec t pr ior to
the RESET instruction wil l remain. SYSRST is release d
at the next instruction cycle and the Reset vector fetch
will commence.
The Software Reset (SWR) flag (instruction) in the
Reset Control (RCON<6>) register is set to indicate
the Software Reset.
6.5 Watchdog Timer Time-out Reset
(WDTO)
Whenever a Watchdog time-out occurs, the device will
asynchronously assert SYSRST. The cl ock so urc e will
remain unchanged. A WDT time-out during Sleep or
Idle mode wil l w a ke- up the proce ssor, but will n ot res et
the processor.
The Watchdog Timer Time-out (WDTO) flag in the
Reset Control (RCON<4>) register is set to indicate
the Watchdog Timer Reset. Refer to Section 21.4
“Watchdog Timer (WDT)” for more information on
the Watchdog Timer Reset.
6.6 Trap Conflict Reset
If a lower priority hard trap occurs while a higher
priority trap is being processed, a hard Trap Conflict
Reset occurs. The hard traps include exceptions of
Priority Levels 13 through 15, inclusive. The address
error (L evel 13) and osc ill ato r error (Level 14) traps fall
into this cate gory.
The Trap Reset (TRAPR) flag in the Reset Control
(RCON<15>) register is set to indicate the Trap Conflict
Reset. Refer to Section 7.0 “Interru pt Controller” for
more information on Trap Conflict Resets.
6.7 Configuration Mismatch Reset
To maintain the integrity of the Peripheral Pin Select
Control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occur (such as cell
disturba nces caus ed by E SD or o ther external e vent s),
a Configuration Mismatch Reset occurs.
The Configuration Mismatch (CM) flag in the Reset
Control (RCON<9>) register is set to indicate the
Configuration Mismatch Reset. Refer to Section 10.0
“I/O Ports” for more information on the
Configuration Mismatch Reset.
6.8 Illegal Condition Device Reset
An illegal condition device Reset occurs due to the
following sources:
• Illegal Op co de Rese t
• Uninitialized W Register Reset
• Secur ity Reset
The Illegal Opcode or Uninitialized W Access Reset
(IOPUWR) flag in the Reset Control (RCON<14>)
register is set to indicate the illegal condition device
Reset.
6.8.1 ILLEGAL OPCODE RESET
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The Illegal Opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the Illegal Opcode Reset, use only the lower 16 bits of
each pro gram memory s ection to sto re the data v alues.
The upper 8 bits should be programmed with 3Fh,
which is an illegal opcode value.
Note: The Configuration Mismatch Reset
feature and associated Reset flag are not
available on all devices.
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6.8.2 UNINITIALIZED W REGISTER
RESET
Any attempt to use the Uninitialized W register as an
Address Pointer will reset the device. The W register
arra y (with the excepti on of W15) is cleare d durin g all
Resets and is considered uninitialized until written to.
6.8.3 SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (boot and secure segment), that
operation will cause a Security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a call, jump, computed jump,
return, return from subroutine or other form of branch
instruction.
The VFC occurs when the Program Counter is
reloaded with an interrupt or trap vector.
Refer to Section 21.8 “Code Protection and
CodeGuard™ Security” for more information on
Security Reset.
6.9 Using the RCON Status Bit s
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the Reset.
Table 6-3 provides a summary of the Reset flag bit
operation.
TA BLE 6-3: RESET FLAG BIT OPERATION
Note: The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
Flag Bit Set by: Cleared by:
TRAPR (RCON<15>) Trap conflict event POR, BOR
IOPWR (RCON<14>) Illegal opcode or Uninitialized W register
access or Security Reset POR, BOR
CM (RCON<9>) Configuration Mismatch POR, BOR
EXTR (RCON<7>) MCLR Re set POR
SWR (RCON<6>) RESET instruction POR, BOR
WDTO (RCON<4>) WDT time-out PWRSAV instruction, CLRWDT ins truction,
POR, BOR
SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR, BOR
IDLE (RCON<2>) PWRSAV #IDLE instructi on POR, BOR
BOR (RCON<1>) POR, BOR —
POR (RCON<0>) POR —
Note: All Reset flag bits can be set or cleared by user software.
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7.0 INTERRUPT CONTROLLER
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 interrupt controller reduces the numerous
periphera l interru pt reques t signa ls to a si ngle in terrupt
request signal to the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 CPU. It has the following
features:
• Up to eight processor exceptions and software
traps
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
source
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
7.1 Interrupt Vector Table
The Interrupt Vector Table (IVT) is shown in Figure 7-1.
The IVT resides in program memory, starting at location
000004h. The IVT contains 126 vectors, consisting of
eight nonmaskable trap vectors, plus up to 118 sources
of interrupt. In general, each i nterrupt source has its own
vector. Each interrupt vector contains a 24-bit-wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with Vector 0 will take priority over interrupts at any
other ve cto r addres s.
The
ds
PIC33FJ06 GS101/X02 and dsPIC33FJ16GSX02/
X04 devices implement up to 35 unique interrupts and
4 non-maskable traps. These are summarized in
Table 7-1.
7.1.1 ALTERNATE INTERRUPT VE CTOR
TABLE
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 7-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
inst ead of the defa ult vector s. The altern ate vectors a re
organized in the same manner as the default vectors.
The A IVT s up ports debugging b y prov id ing a m ean s to
switch between an application and a support environ-
ment without requiring the interrupt vectors to be
reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addre sses used in the IVT.
7.2 Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 device s clear t heir register s in response to a Reset ,
which forces the PC to zero. The Digital Signal Controller
then begins progr am execut ion at locatio n, 0x00 0 00 0 . A
GOTO instruction at the Reset address can redirect
program execution to the appropriate start-up routine.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Interrupts (Part IV)”
(DS70300) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available on the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Any unimplemented or unused vector
locations in the IVT and AIVT should be
progra mmed wi th th e ad dres s of a de fau lt
interrupt handler routine that contains a
RESET instruction.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 98 2008-2014 Microchip Technology Inc.
FIGURE 7-1: dsPIC33FJ06GS101 /X0 2 and dsPIC33FJ16GSX02/X04 INTERRUPT VECTOR
TABLE
Reset – GOTO Instruction 0x000000
Reset – GOTO Address 0x 000002
Reserved 0x000004
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0 0x 000014
Interrupt Vector 1
~
~
~
Interrupt Vector 52 0x00007C
Interrupt Vector 53 0x00007E
Interrupt Vector 54 0x000080
~
~
~
Interrupt Vector 116 0x0000FC
Interrupt Vector 117 0x0000FE
Reserved 0x000100
Reserved 0x000102
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0 0x 000114
Interrupt Vector 1
~
~
~
Interrupt Vector 52 0x00017C
Interrupt Vector 53 0x00017E
Interrupt Vector 54 0x000180
~
~
~
Interrupt V ector 116
Interrupt Vector 117 0x0001FE
Start of Code 0x000200
Decreasing Natural Order Priority
Interrupt Vector Table (IVT)(1)
Alternate Interrupt Vector Table (AIVT)(1)
Note 1: See Table 7-1 for the list of implemented interrupt vectors.
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 7-1: INTERRUPT VECTORS
Vector
Number
Interrupt
Request
(IQR) IVT Address AIVT Addres s Interrupt Source
Highest Natural Order Priority
8 0 0x000014 0x000114 INT0 – External Interrupt 0
9 1 0x000016 0x000116 IC1 – Input Capture 1
10 2 0x000018 0x000118 OC1 – Output Compare 1
11 3 0x00001A 0x00011A T1 – Timer1
12 40x00001C 0x00011C Reserved
13 5 0x00001E 0x00011E IC2 – Input Capture 2
14 6 0x000020 0x000120 OC2 – Output Compare 2
15 7 0x000022 0x000122 T2 – Timer2
16 8 0x000024 0x000124 T3 – Timer3
17 9 0x000026 0x000126 SPI1E – SPI1 Fault
18 10 0x000028 0x000128 SPI1 – SPI1 Transfer Done
19 11 0x00002A 0x00012A U1RX – UART1 Receiver
20 12 0x00002C 0x0001 2C U1TX – UART1 Transmitter
21 13 0x00002E 0x00012E ADC – ADC Group Convert Done
22-23 14-15 0x000030-0x000032 0x000130-0x000132 Reserved
24 16 0x000034 0x000134 SI2C1 – I2C1 Slave Event
25 17 0x000036 0x000136 MI2C1 – I2C1 Master Event
26 18 0x000038 0x000138 CMP1 – Analog Comparator 1 Interrupt
27 19 0x00003A 0x00013A CN – Input Change Notification Interrupt
28 20 0x00003C 0x00013C INT1 – External Interrupt 1
29-36 21-28 0x00003E-0x00004C 0x00013E-0x00014C Reserved
37 29 0x00004E 0x00014E INT2 – External Interrupt 2
38-64 30-56 0x000050-0x000084 0x000150-0x000184 Reserved
65 57 0x000086 0x000186 PWM PSEM Special Event Match
66-72 58-64 0x000088-0x000094 0x000188-0x000194 Reserved
73 65 0x000096 0x000196 U1E – UART1 Error Interrupt
74-101 66-93 0x000098-0x0000CE 0x000198-0x0001CE Reserved
102 94 0x 0000D0 0x0001 D0 PWM1 – PWM1 Interrupt
103 95 0x 0000D2 0x0001 D2 PWM2 – PWM2 Interrupt
104 96 0x 0000D4 0x0001 D4 PWM3 – PWM3 Interrupt
105 97 0x 0000D6 0x0001 D6 PWM4 – PWM4 Interrupt
106-110 98-102 0x0000D8-0x0000E0 0x0001D8-0x0001E0 Reserved
111 103 0x0000E 2 0x00001E2 CMP2 – Anal og Comparator 2
112 104 0x0000E4 0x0001E4 CMP 3 – An alog Compara tor 3
113 105 0x0000E 6 0x0001E6 CMP4 – Analog Comparator 4
114-117 106-109 0x0000E8-0x0000EE 0x0001E8-0x0001EE Reserved
118 110 0x0000F0 0x0001F0 ADC Pai r 0 Convert Done
119 111 0x0000F2 0x0001F2 ADC Pair 1 Convert Done
120 112 0x0000F4 0x0001F4 ADC Pair 2 Convert Done
121 113 0x0000F6 0x0001F6 ADC Pair 3 Convert Done
122 114 0x0000F8 0x0001F8 ADC Pair 4 Convert Done
123 115 0x0000FA 0x0001FA A DC Pair 5 Co nvert Done
124 116 0x0000FC 0x0001FC ADC Pair 6 Convert Done
125 117 0x0000FE 0x0001FE Reserved
Lowest Natural Order Priority
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 100 2008-2014 Microchip Technology Inc.
7.3 Interrupt Control and Status
Registers
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices implement 27 registers for the interrupt
cont ro l le r:
• INTCON1
• INTCON2
•IFSx
•IECx
•IPCx
•INTTREG
7.3.1 INTCON1 AND INTCON2
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit as well as the
control a nd s tatus f lag s for the proc es sor t rap s ources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
7.3.2 IFSx
The IFSx registers maintain all of the interrupt request
flags. Eac h source of inte rrupt has a st atus bi t, which is
set by th e resp ectiv e periph erals or exter nal si gnal an d
is cleare d via software.
7.3.3 IECx
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
7.3.4 IPCx
The IPCx regi ster s are us ed to se t the Interru pt Priorit y
Level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
7.3.5 INTTREG
The INTTREG register contains the associated
interrupt v ector numbe r and the new CPU Interrup t Pri-
ority Level, which are latched into the Vector Number
(VECNUM<6:0>) and Interrupt Level (ILR<3:0>) bit
fields in the INTTREG register. The new Interrupt
Priority Level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx reg ist ers in th e s ame sequenc e tha t the y a re
listed in Table 7-1. For example, the INT0 (External
Interrupt 0 ) i s sho w n a s h aving Vector Num ber 8 a nd a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, th e INT0IE bit is found in IEC0<0> and the
INT0IP bits are found in the first position of IPC0
(IPC0<2:0>).
7.3.6 STATUS/CONTROL REGISTERS
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.
• The CPU STATUS Register, SR, contains the
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU Interrupt Priority Level. The user can
change the current CPU priority level by writing to
the IPL bits.
• The CORCON register contains the IPL3 bit,
which together with IPL<2:0>, indicates the
current CPU priority level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
All Interrupt registers are described in Register 7-1
through Register 7-35 in the following pages.
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-1: SR: CPU STATUS REGISTER(1)
REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1)
R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0
OA OB SA SB OAB SAB DA DC
bit 15 bit 8
R/W-0(3)R/W-0(3)R/W-0(3)R-0 R/W-0 R/W-0 R/W-0 R/W-0
IPL2(2)IPL1(2)IPL0(2)RA NOV Z C
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
Note 1: For complete register details, see Register 3-1.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Lev el. Th e value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are dis ab led when
IPL<3> = 1.
3: The IPL<2:0> status bits are read-only when NSTDIS (INTCON1<15>) = 1.
U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0
— — — US EDT DL2 DL1 DL0
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0
SATA SATB SATDW ACCSAT IPL3(2)PSV RND IF
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set
0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
Note 1: For complete register details, see Register 3-2.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 102 2008-2014 Microchip Technology Inc.
REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14 OVAERR: Accumulator A Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
bit 13 OVBERR: Accumulator B Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catas trophic overflow of Accumulator A
bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catas trophic overflow of Accumulator B
bit 10 OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap is disabled
bit 9 OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
0 = Trap is disab led
bit 8 COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on catastrophic overflow of Accumulator A or B enabled
0 = Trap is disabled
bit 7 SFTACERR: Shift Accumulator Error Status bit
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
bit 6 DIV0ERR: Arithmetic Error Status bit
1 = Math error trap was caused by a divide-by-zero
0 = Math error trap was not caused by a divide-by-zero
bit 5 Unimplemented: Read as ‘0’
bit 4 MATHERR: Arithmetic Error Status bit
1 = Math error trap has occurred
0 = Math error trap has not occurred
bit 3 ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
bit 2 STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1 OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0 Unimplemented: Read as ‘0’
REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 104 2008-2014 Microchip Technology Inc.
REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
ALTIVT DISI — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — INT2EP INT1EP INT0EP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit
1 = Use alternate vector table
0 = Use standard (default) vector table
bit 14 DISI: DISI Instructio n Stat us bit
1 = DISI instru ction is active
0 = DISI instru ction is not active
bit 13-3 Unimplemented: Read as ‘0’
bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13 ADIF: ADC Group Conversion Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9 SPI1EIF: SPI1 Fault Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8 T3IF: Timer3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7 T2IF: Timer2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4 Unimplemented: Read as ‘0’
bit 3 T1IF: Timer1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 106 2008-2014 Microchip Technology Inc.
bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 INT0IF: External Interrupt 0 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
——INT2IF— — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13 INT2IF: External Interrupt 2 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12-5 Unimplemented: Read as ‘0’
bit 4 INT1IF: External Interrupt 1 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3 CNIF: Input Change Notification Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2 AC1IF: Analog Comparator 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
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DS70000318G-page 108 2008-2014 Microchip Technology Inc.
REGISTER 7-7: IFS3: INTERRUPT FLAG STATUS REGISTER 3
REGISTER 7-8: IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
— — — — — — PSEMIF —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 0 Unimplemented: Read as ‘0’
bit 9 PSEMIF: PWM Special Event Match Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8-0 Unimplemented: Read as ‘0’
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
— — — — — —U1EIF—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-2 Unimplemented: Read as ‘0’
bit 1 U1EIF: UART1 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 Unimplemented: Read as ‘0’
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-9: IFS5: INTERRUPT FLAG STATUS REGISTER 5
R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
PWM2IF PWM1IF — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PWM2IF: PWM2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14 PWM1IF: PWM1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13-0 Unimplemented: Read as ‘0’
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REGISTER 7-10: IFS6: INTERRUPT FLAG ST ATUS REGISTER 6
R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
ADCP1IF ADCP0IF — — — —AC4IFAC3IF
bit 15 bit 8
R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
AC2IF — — — — — PWM4IF PWM3IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADCP1IF: ADC Pair 1 Conversion Done Interru pt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14 ADCP0IF: ADC Pair 0 Conversion Done Interru pt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13-1 0 Unimplemented: Read as ‘0’
bit 9 AC4IF: Analog Comparator 4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8 AC3IF: Analog Comparator 3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7 AC2IF: Analog Comparator 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6-2 Unimplemented: Read as ‘0’
bit 1 PWM4IF: PWM4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 PWM3IF: PWM3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-11: IFS7: INTERRUPT FLAG STATUS REGISTER 7
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4 ADCP6IF: ADC Pair 6 Convers ion D one Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3 ADCP5IF: ADC Pair 5 Convers ion D one Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2 ADCP4IF: ADC Pair 4 Convers ion D one Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 ADCP3IF: ADC Pair 3 Convers ion D one Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 ADCP2IF: ADC Pair 2 Convers ion D one Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 112 2008-2014 Microchip Technology Inc.
REGISTER 7-12: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13 ADIE: ADC1 Conversion Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 10 SPI1IE: SPI1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 9 SPI1EIE: SPI1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 8 T3IE: T im er3 Inte rrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 7 T2IE: T im er2 Inte rrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 4 Unimplemented: Read as ‘0’
bit 3 T1IE: T im er1 Inte rrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
2008-2014 Microchip Technology Inc. DS70000318G-page 113
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0 INT0IE: External Interrupt 0 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
REGISTER 7-12: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 114 2008-2014 Microchip Technology Inc.
REGISTER 7-13: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
——INT2IE— — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13 INT2IE: External Interrupt 2 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12-5 Unimplemented: Read as ‘0’
bit 4 INT1IE: External Interrupt 1 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 3 CNIE: Input Change Notification Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 2 AC1IE: Analog Comparator 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
2008-2014 Microchip Technology Inc. DS70000318G-page 115
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
REGISTER 7-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
— — — — — — PSEMIE —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 0 Unimplemented: Read as ‘0’
bit 9 PSEMIE: PWM Special Event Match Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 8-0 Unimplemented: Read as ‘0’
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
— — — — — —U1EIE—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-2 Unimplemented: Read as ‘0’
bit 1 U1EIE: UART1 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0 Unimplemented: Read as ‘0’
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 116 2008-2014 Microchip Technology Inc.
REGISTER 7-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5
R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
PWM2IE PWM1IE — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PWM2IE: PWM2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 14 PWM1IE: PWM1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13-0 Unimplemented: Read as ‘0’
2008-2014 Microchip Technology Inc. DS70000318G-page 117
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-17: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6
R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
ADCP1IE ADCP0IE — — — —AC4IEAC3IE
bit 15 bit 8
R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
AC2IE — — — — —PWM4IEPWM3IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADCP1IE: ADC Pair 1 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 14 ADCP0IE: ADC Pair 0 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13-1 0 Unimplemented: Read as ‘0
bit 9 AC4IE: Analog Comparator 4 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8 AC3IE: Analog Comparator 3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 7 AC2IE: Analog Comparator 2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6-2 Unimplemented: Read as ‘0’
bit 1 PWM4IE: PWM4 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 PWM3IE: PWM3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 118 2008-2014 Microchip Technology Inc.
REGISTER 7-18: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4 ADCP6IE: ADC Pair 6 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 3 ADCP5IE: ADC Pair 5 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2 ADCP4IE: ADC Pair 4 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1 ADCP3IE: ADC Pair 3 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 ADCP2IE: ADC Pair 2 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
2008-2014 Microchip Technology Inc. DS70000318G-page 119
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-19: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-1 2 T1IP<2:0>: Timer1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 IC1IP<2:0>: Input Capture Chan nel 1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 120 2008-2014 Microchip Technology Inc.
REGISTER 7-20: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— IC2IP2 IC2IP1 IC2IP0 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-1 2 T2IP<2:0>: Timer2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 IC2IP<2:0>: Input Capt ure Channel 2 Interru pt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0’
2008-2014 Microchip Technology Inc. DS70000318G-page 121
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-21: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-1 2 U1RXIP<2:0>: UART1 Rece iv er Interru pt P riori ty bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 122 2008-2014 Microchip Technology Inc.
REGISTER 7-22: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 ADIP<2:0>: ADC1 Conversion Complete Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
2008-2014 Microchip Technology Inc. DS70000318G-page 123
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-23: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-1 2 CNIP<2:0>: Change Notification Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 AC1IP<2:0>: Analog Comparator 1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 124 2008-2014 Microchip Technology Inc.
REGISTER 7-24: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
REGISTER 7-25: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0
— — — — — INT1IP2 INT1IP1 INT1IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— INT2IP2 INT2IP1 INT2IP0 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0’
2008-2014 Microchip Technology Inc. DS70000318G-page 125
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-26: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14
REGISTER 7-27: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— PSEMIP2 PSEMIP1 PSEMIP0 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 PSEMIP<2:0>: PWM Special Event Match Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0’
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— U1EIP2 U1EIP1 U1EIP0 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 U1EIP<2:0>: UAR T1 Error Interr upt Prior ity bit s
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0’
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 126 2008-2014 Microchip Technology Inc.
REGISTER 7-28: IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-1 2 PWM2IP<2:0>: PWM2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 PWM1IP<2:0>: PWM1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7-0 Unimplemented: Read as ‘0’
2008-2014 Microchip Technology Inc. DS70000318G-page 127
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-29: IPC24: INTERRUPT PRIORITY CONTROL REGISTER 24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 PWM4IP<2:0>: PWM4 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 PWM3IP<2:0>: PWM3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 128 2008-2014 Microchip Technology Inc.
REGISTER 7-30: IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— AC2IP2 AC2IP1 AC2IP0 — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-1 2 AC2IP<2:0>: Analog Comparator 2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11-01 Unimplemented: Read as ‘0’
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-31: IPC26: INTERRUPT PRIORITY CONTROL REGISTER 26
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 AC4IP<2:0>: Analog Comparator 4 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 AC3IP<2:0>: Analog Comparator 3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 130 2008-2014 Microchip Technology Inc.
REGISTER 7-32: IPC27: INTERRUPT PRIORITY CONTROL REGISTER 27
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-1 2 ADCP1IP<2:0>: ADC Pair 1 Conversion Done Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 ADCP0IP<2:0>: ADC Pair 0 Conversion Done Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7-0 Unimplemented: Read as ‘0’
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-33: IPC28: INTERRUPT PRIORITY CONTROL REGISTER 28
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— ADCP5IP2 ADCP5IP1 ADCP5IP0 — ADCP4IP2 ADCP4IP1 ADCP4IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1 ADCP2IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-1 2 ADCP5IP<2:0>: ADC Pair 5 Conversion Done Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 ADCP4IP<2:0>: ADC Pair 4 Conversion Done Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 ADCP3IP<2:0>: ADC Pair 3 Conversion Done Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 ADCP2IP<2:0>: ADC Pair 2 Conversion Done Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 132 2008-2014 Microchip Technology Inc.
REGISTER 7-34: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0
— — — — — ADCP6IP2 ADCP6IP1 ADCP6IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 ADCP6IP<2:0>: ADC Pair 6 Conversion Done Interrupt 1 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
2008-2014 Microchip Technology Inc. DS70000318G-page 133
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 7-35: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — — ILR3 ILR2 ILR1 ILR0
bit 15 bit 8
U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
— VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 2 Unimplemented: Read as ‘0’
bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
0001 = CPU Interrupt Priority Level is 1
0000 = CPU Interrupt Priority Level is 0
bit 7 Unimplemented: Read as ‘0’
bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits
0111111 = Interrupt vector pending is Number 135
•
•
•
0000001 = Interrupt vector pending is Number 9
0000000 = Interrupt vector pending is Number 8
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 134 2008-2014 Microchip Technology Inc.
7.4 Interrupt Setup Procedures
7.4.1 INITIALIZATION
Complete the following steps to configure an interrupt
source at initializ ati on:
1. Set the NSTDIS bit (INTCON1<15>) if nested
interru pts are not desir ed.
2. Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
inter rupt source . If multipl e priority le vels are n ot
desired, the IPCx register control bits for all
enabled interrupt sources can be programmed
to the same non-zero value.
3. Clear the int errupt flag st atus bi t associated with
the periphera l in the as sociated IFSx register.
4. Enable the interrupt source by setting the
interrupt enable control bit associated with the
source in the appropriate IECx regis ter.
7.4.2 INTERRUPT SERVICE ROUTINE
The method used to declare an ISR and initialize the
IVT with the correct vector address depends on the
programming language (C or assembler) and the
language development toolsuite used to develop the
application.
In gene ral , the us er a pp lic ati on m ust cle ar the in terru pt
flag in the appropriate IFSx register for the source of
interrupt that the ISR handles. Otherwise, program will
re-enter t he ISR immed iately af ter ex iting the ro utine. If
the ISR is coded in assembly language, it must be
terminated using a RETFIE instruction to unstack the
saved PC value, SRL value and old CPU priority level.
7.4.3 TRAP SERVICE ROUTINE
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
7.4.4 INTERRUPT DISABLE
The following steps outline the procedure to disable all
user interrup ts:
1. Push the current SR value onto the software
stac k using the PUSH instruction.
2. Force the CPU to Priority Level 7 by inclusive
ORing the value 0xE0 with SRL.
To enable user interrupts, the POP instruction can be
used to restore the previous SR value.
The DISI instruction provides a convenient way to
disable interrupts of Priority Levels 1-6 for a fixed
period of time. Level 7 interrupt sources are not
disabled by the DISI instruction.
Note: At a device Reset, the IPCx registers are
initialized such that all user interrupt
sources are assigned to Priority Level 4. Note: Only user interrupt s with a priority level of 7
or lower can be disabled. Trap sources
(level 8-level 15) cannot be disabled.
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
8.0 OSCILLATOR CONFIGURATION The oscillator system provides:
• External and internal oscillator options as
clock source s
• An on-chip Phase-Locked Loop (PLL) to scale the
internal operating frequency to the required system
clock frequency
• An internal FRC osci llator tha t can also be used with
the PLL, thereby allowing full-speed operation
without any external clock generation hardware
• Clock switching between various clock sources
• Programmable clock postscaler for system power
savings
• A Fail-Safe Cl ock Mo nitor (FSC M) that d etects c lock
failure and takes fail-safe measures
• A Clock Control registe r (OSCCON)
• Nonvolatile Configuration bits for main oscillator
selection
• Auxiliary PLL for ADC and PWM
A simplified diagram of the oscillator system is shown
in Figure 8-1.
FIGURE 8-1: OSCILLATOR SYSTEM DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
“Oscillator (Part IV)” (DS70307) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
XTPLL, HSPLL,
XT, HS, EC
FRCDIV<2:0>
WDT, PWRT,
FSCM
FRCDIVN
FRCDIV16
ECPLL, FRCPLL
NOSC<2:0> FNOSC<2:0>
Reset
FRC
Oscillator
LPRC
Oscillator
DOZE<2:0>
S3
S1
S2
S1/S3
S7
S6
FRC
LPRC
S0
S5
÷ 16
Clock Switch
S7
Clock Fail
TUN<5:0>
PLL(1)
F
CY
(3)
FOSC
FRCDIV
DOZE
÷ N ACLK
SELACLK APSTSCLR<2:0>
To PWM/ADC(1)
ENAPLL
POSCMD<1:0>
FVCO(1)
APLL(1)
x16
ASRCSEL FRCSEL
POSCCLK FRCCLK
FRCCLK
POSCCLK
÷ N
ROSEL RODIV<3:0>
REFCLKO
POSCCLK
Reference Clock Generation
Auxiliary Clock Generation
RPx
Note 1: See Section 8.1.3 “PLL Configuration” and Section 8.2 “Auxilia ry Clock Gener at ion” for configuration restrictions.
2: If the oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 M must be connected.
3: The term, FP, refers to the clock source for all the peripherals, while FCY refers to the clock source for the CPU. Throughout this doc-
ument, FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode is used
in any ratio other than 1:1, which is the default.
FVCO(1)
F
OSC
F
P
(3)
OSC2
OSC1 Primary Oscillator
R(2)
÷ 2
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 136 2008-2014 Microchip Technology Inc.
8.1 CPU Clocking System
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices provide six system clock options:
• F as t RC (FRC) Oscillator
• FRC Oscilla tor with PLL
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Low-Power RC (LPRC) Oscill ator
• FRC Osci lla tor with Pos t sc al er
8.1.1 SYSTEM CLOCK SOURCES
The Fas t RC (FRC) i nternal os cillator runs at a n ominal
frequency of 7.37 MHz. User software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This fac tor is selec ted using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
The primary oscillator can use one of the following as
its clock source:
• XT (Crystal): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
• HS (High-Speed Crystal): Crystals in the range of
10 MHz to 40 MHz. The crystal is connected to
the OSC1 and OSC2 pins.
• EC (External Clock): The external clock signal is
directl y applied to the OSC1 pin.
The LPRC internal oscIllator runs at a nominal
frequenc y of 32.7 68 kH z. It is al so us ed as a reference
clock by the Watchdog Timer (WDT) and Fail-Safe
Clock Monitor (FSCM).
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip
Phase-Locked Loop (PLL) to provide a wide range of
output frequencies for device operation. PLL
configuration is described in Section 8.1.3 “PLL
Configuration”.
The FRC frequency depends on the FRC accuracy
(see Table 24-20) and the value of the FRC Oscillator
Tuning register (see Register 8-4).
8.1.2 SYSTEM CLOCK SELECTION
The oscillator source used at a device Power-on
Reset event is selected using Configuration bit
settings. The Oscillator Configuration bit settings are
located in the Configuration registers in the program
memory. (Refer to Section 21.1 “Configuration Bits”
for further details.) The Initial Oscillator Selection Con-
figuration bits, FNOSC<2:0> (FOSCSEL<2:0>), and the
Primary Oscillator Mode Select Configuration bits,
POSCMD<1:0> (FOSC<1:0>), select the oscillator
source that is used at a Power-on Reset. The FRC
primary oscillator is the default (unprogrammed)
selection.
The Configuration bits allow users to choose among
12 different clock modes, shown in Table 8-1.
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected), FOSC, is divided by 2
to ge nerate t he devi ce instr uct ion clock (FCY) and the
peripheral clock time base (FP). FCY defines the
operating speed of the device and speeds up to
40 MHz are supported by the dsPIC33FJ06GS101/
X02 and dsPIC33FJ16GSX02/X04 architecture.
Instruction execution speed or device operating
frequency, FCY, is given by Equation 8-1.
EQUATION 8-1: DEVICE OPERATING
FREQUENCY
TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
FCY = FOSC/2
Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> See Notes
Fast RC Oscillator with Divide-by-N (FRCDIVN) Internal xx 111 1, 2
Fast RC Oscillator with Divide-by-16 (FRCDIV16) Internal xx 110 1
Low-Power RC Oscillator (LPRC) Internal xx 101 1
Reserved Reserved xx 100 —
Primary Oscillator (HS) with PLL (HSPLL) Primary 10 011 —
Primary Oscillator (XT) with PLL (XTPLL) Primary 01 011 —
Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1
Primary Oscillator (HS) Primary 10 010 —
Primary Oscillator (XT) Primary 01 010 —
Primary Oscillator (EC) Primary 00 010 1
Fast RC Oscillator with PLL (FRCPLL) Internal xx 001 1
Fast RC Oscillator (FRC) Internal xx 000 1
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
8.1.3 PLL CONFIGURATION
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in Figure 8-2.
The output of the primary oscillator or FRC, denoted
as ‘FIN’, is d ivide d down by a p resc ale fa ctor (N 1) of 2,
3, ... or 33 before being prov ided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO
must be selected in the range of 0.8 MHz to 8 MHz.
The prescale factor ‘N1’ is selected using the
PLLPRE<4:0> bits (CLKDIV<4:0>).
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor , ‘M’,
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
freq ue nc y is i n the rang e of 10 0 M H z to 2 00 M H z.
The VCO ou tput is further d ivided by a p ostscale fa ctor ,
‘N2’. This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4, or 8, and
must be selected such that the PLL output frequency
(FOSC) is in the range of 12.5 MHz to 80 MHz, which
generates device operating speeds of 6.25-40 MIPS.
For a primary oscillator or FRC oscillator, output ‘FIN’,
the PLL output ‘FOSC’ is given by Equation 8-2.
EQUATION 8-2: FOSC CALCULATION
For example, suppose a 10 MHz crystal is being used
with the selected oscillator mode of XT with PLL (see
Equation 8-3).
• If PLLPRE<4:0> = 0, then N1 = 2. This yields a
VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
• If PLLDIV<8:0> = 0x1E, then M = 32. This yields a
VCO output of 5 x 32 = 160 MHz, which is within
the 100-200 MHz ranged needed.
• If PLLPOST<1:0> = 0, then N2 = 2 . Th is pro vi des
a Fosc of 160/2 = 80 MHz. The resultant device
operating speed is 80/2 = 40 MIPS.
EQUATION 8-3: XT WITH PLL MODE
EXAMPLE
FIGURE 8-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PLL BLOCK DIAGRAM
()
M
N1*N2
FOSC = FIN *
FCY = FOSC
2==
1
2(10000000 * 32
2 * 2 )40 MIPS
0.8-8.0 MHz
Here(1) 100-200 MHz
Here(1)
Divide-by-
2, 4, 8
Divide-by-
2-513
Divide-by-
2-33
Source (Crystal, External PLLPRE XVCO
PLLDIV
PLLPOST
Clock or Internal RC)
12.5-80 MHz
Here(1)
FOSC
FVCO
N1
M
N2
Note 1: This frequency range must be satisfied at all times.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 138 2008-2014 Microchip Technology Inc.
8.2 Auxiliary Clock Generation
The auxil iary clo ck generati on is use d for a periphe rals
that need to operate at a frequency unrelated to the
syste m clock such as a PWM or ADC.
The primary oscillator and internal FRC oscillator
sources can be used with an auxil iary PLL to obtai n the
auxiliary clock. The auxiliary PLL has a fixed 16x
multipl ic ati on fac tor.
The auxiliary clock has the following configuration
restrictions:
• For proper PWM operation, auxiliary clock genera-
tion must be configured for 120 MHz (see
Parameter OS56 in Table 24-18 in Section 24.0
“Elect rical Characteris tics”). If a slo wer frequency
is desired, the PWM Input Clock Prescaler (Divider)
Select bits (PCLKDIV<2:0>) should be used.
• To achieve 1.04 ns PWM resolution, the auxiliary
clock must use the 16x auxiliary PLL (APLL). All
other clock sources will have a minimum PWM
resolution of 8 ns.
• If th e primary PLL is used as a source for the
auxiliary clock, the primary PLL should be config-
ured up to a maximum operation of 30 MIPS or
less
8.3 Reference Clock Generation
The referenc e cloc k output lo gic prov ides th e user wi th
the ability to ou tpu t a clock sig nal base d on th e s ys tem
clock or the crystal oscil lator on a device pin. The user
application can specify a wide range of clock scaling
prior to outputting the reference clock.
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
8.4 Oscillator Control Registers
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,2)
U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y
— COSC2 COSC1 COSC0 —NOSC2
(3)NOSC1(3)NOSC0(3)
bit 15 bit 8
R/W-0 R/W-0 R-0 U-0 R/C-0 U-0 U-0 R/W-0
CLKLOCK IOLOCK LOCK —CF —— OSWEN
bit 7 bit 0
Legend: y = Value set from Configuration bits on POR
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-1 2 COSC<2:0>: Current Oscillator Selection bits (read-only)
111 = Fast RC oscillator (FRC) with divide-by-n
110 = Fast RC oscillator (FRC) with divide-by-16
101 = Low-Power RC oscillator (LPRC)
100 = Reserved
011 = Primary oscillator (XT, HS, EC) with PLL
010 = Primary oscillator (XT, HS, EC)
001 = Fast RC oscillator (FRC) with PLL
000 = Fast RC oscillator (FRC)
bit 11 Unimplemented: Read as ‘0’
bit 10-8 NOSC<2:0>: New Oscillator Selection bits(3)
111 = Fast RC oscillator (FRC) with divide-by-n
110 = Fast RC oscillator (FRC) with divide-by-16
101 = Low-Power RC oscillator (LPRC)
100 = Reserved
011 = Primary oscillator (XT, HS, EC) with PLL
010 = Primary oscillator (XT, HS, EC)
001 = Fast RC oscillator (FRC) with PLL
000 = Fast RC oscillator (FRC)
bit 7 CLKLOCK: Clock Lock Enab le bit
If C lock Switching is En abled and FSCM is Dis abled, (FOSC<FCKSM> = 0b01):
1 = Clock swi tching is disable d, system clock source is lo cked
0 = Clock switching is enabled, system clock source can be modified by clock switching
bit 6 IOLOCK: Periph eral Pin Select Lock bit
1 = Peripheral Pin Select is locked, write to Peripheral Pin Select registers not allowed
0 = Peripheral Pin Select is not locked, write to Peripheral Pin Select registers allowed
bit 5 LOCK: PLL Loc k Status bit (read-o nly )
1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
bit 4 Unimplemented: Read as ‘0’
Note 1: Writes to this register require an unlock sequence. Refer to “ Osci llato r (Part IV)” (DS70307) in the
“dsPIC33F/ PIC24H Family Refe rence Manual ” (available from the Microchip web site) for details.
2: This register is reset only on a Power-on Reset (POR).
3: Direct clock swit ches betw een any pri mary osci llator mod e with PLL and FR CPLL mode are not permi tted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transition clock source between the two PLL modes.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 140 2008-2014 Microchip Technology Inc.
bit 3 CF: Clock Fail Detect bit (read/clear by application)
1 = FSCM has detected clock failure
0 = FSCM has not detected clock failure
bit 2-1 Unimplemented: Read as ‘0’
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Request oscillator switch to selection specified by NOSC<2:0> bits
0 = Oscillator switch is complete
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,2) (CONTINUED)
Note 1: Writes to this register require an unlock sequence. Refer to “ Osci llator (Part IV)” (DS70307) in the
“dsPIC33F/ PIC24H Family Refe rence Manual ” (available from the Microchip web site) for details.
2: This register is reset only on a Power-on Reset (POR).
3: Direct clock swit ches betw een any pri mary oscill ator mod e with PLL and FR CPLL mode are not permitte d.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transition clock source between the two PLL modes.
2008-2014 Microchip Technology Inc. DS70000318G-page 141
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER(1)
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
ROI DOZE2 DOZE1 DOZE0 DOZEN(2)FRCDIV2 FRCDIV1 FRCDIV0
bit 15 bit 8
R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PLLPOST1 PLLPOST0 — PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-1 2 DOZE<2:0>: Processor Cloc k Reduction Select bits
111 = FCY/128
110 = FCY/64
101 = FCY/32
100 = FCY/16
011 = FCY/8 (d efault)
010 = FCY/4
001 = FCY/2
000 = FCY/1
bit 11 DOZEN: Doze Mode Enable bit(2)
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock/peripheral clock ratio forced to 1:1
bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divide-by-256
110 = FRC divide-by-64
101 = FRC divide-by-32
100 = FRC divide-by-16
011 = FRC divide-by-8
010 = FRC divide-by-4
001 = FRC divide-by-2
000 = FRC divide-by-1 (default)
bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11 = Output/8
10 = Reserved
01 = Output/4 (default)
00 = Output/2
bit 5 Unimplemented: Read as ‘0’
bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)
11111 = Input/33
•
•
•
00001 = Input/3
00000 = Input/2 (default)
Note 1: This register is reset only on a Power-on Reset (POR).
2: This bit is cleared when the ROI bit is set and an interrupt occurs.
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DS70000318G-page 142 2008-2014 Microchip Technology Inc.
REGISTER 8-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —PLLDIV<8>
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
PLLDIV<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’
bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
111111111 = 513
•
•
•
000110000 = 50 (default)
•
•
•
000000010 = 4
000000001 = 3
000000000 = 2
Note 1: This register is reset only on a Power-on Reset (POR).
2008-2014 Microchip Technology Inc. DS70000318G-page 143
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— TUN<5:0>(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(2)
011111 = Center frequency + 11.6% (8.2268 MHz)
011110 = Center frequency + 11.2% (8.1992 MHz)
•
•
•
000001 = Center frequency + 0.375% (7.3976 MHz)
000000 = Center frequency (7.37 MHz nominal)
111111 = Center frequency – 0.375% (7.2594 MHz)
•
•
•
100001 = Center frequency – 11.6% (6.5132 MHz)
000000 = Center frequency – 12% (6.4856 MHz)
Note 1: This register is reset only on a Power-on Reset (POR).
2: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC fr equency ov er a wide ran ge of te mperatures . The tunin g step-size is an app roximation a nd is nei ther
characterized nor tested.
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REGISTER 8-5: ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER(1)
R/W-0 R-0 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1
ENAPLL APLLCK SELACLK —— APSTSCLR2 APSTSCLR1 APSTSCLR0
bit 15 bit 0
R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
ASRCSEL FRCSEL — — — — — —
bit 7
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ENAPLL: Auxiliary PLL Enable bit
1 = APLL is enabled
0 = APLL is disabled
bit 14 APLLCK: APLL Locked Status bit (read-only)
1 = Indicates that auxiliary PLL is in lock
0 = Indicates that auxiliary PLL is not in lock
bit 13 SELACLK: Select Auxiliary Clock Source f or Auxi liary Clock Di vider bit
1 = Auxiliary oscillators provides the source clock for auxiliary clock divider
0 = Primary PLL (FVCO) provides the source clock for auxiliary clock divider
bit 12-11 Unimplemented: Read as ‘0’
bit 10-8 APSTSCLR<2:0>: Auxiliary Clock Output Divider bits
111 = Divided by 1
110 = Divided by 2
101 = Divided by 4
100 = Divided by 8
011 = Divided by 16
010 = Divided by 32
001 = Divided by 64
000 = Divided by 256
bit 7 ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit
1 = Primary oscillator is the clock source
0 = No clock input is selected
bit 6 FRCSEL: Select Refer ence Cloc k Source for Auxiliary PLL bit
1 = Select FRC clock for auxiliary PLL
0 = Input clock source is determined by ASRCSEL bit setting
bit 5-0 Unimplemented: Read as ‘0’
Note 1: This register is reset only on a Power-on Reset (POR).
2008-2014 Microchip Technology Inc. DS70000318G-page 145
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 8-6: REFOCON: REFERENCE OSCILLAT OR CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ROON — ROSSLP ROSEL RODIV3(1)RODIV2(1)RODIV1(1)RODIV0(1)
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ROON: Reference Oscillator Output Enable bit
1 = Reference oscillator output is enabled on the REFCLK0 pin(2)
0 = Reference oscillator output is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 ROSSLP: Reference Oscillator Run in Sleep bit
1 = Reference oscillator output continues to r un in Sle ep
0 = Reference oscillator output is disabled in Sleep
bit 12 ROSEL: Reference Oscillator Source Select bit
1 = Oscillator crystal is used as the reference clock
0 = System clock is used as the reference clock
bit 11-8 RODIV<3:0>: Referenc e Os ci lla tor D ivi de r bit s(1)
1111 = Reference clock divided by 32,768
1110 = Reference clock divided by 16,384
1101 = Reference clock divided by 8,192
1100 = Reference clock divided by 4,096
1011 = Reference clock divided by 2,048
1010 = Reference clock divided by 1,024
1001 = Reference clock divided by 512
1000 = Reference clock divided by 256
0111 = Reference clock divided by 128
0110 = Reference clock divided by 64
0101 = Reference clock divided by 32
0100 = Reference clock divided by 16
0011 = Reference clock divided by 8
0010 = Reference clock divided by 4
0001 = Reference clock divided by 2
0000 = Reference clock
bit 7-0 Unimplemented: Read as ‘0’
Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits.
2: This pin is remappable. Refer to Section 10.6 “Peripheral Pin Select” for more information.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 146 2008-2014 Microchip Technology Inc.
8.5 Clock Switching Operation
Users can switch applications among any of the four
clock sources (primary, LP, FRC and LPRC) under
software control at any time. To limit the possible side
effects of this flexibility, dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 devices have a safeguard
lock built into the switch process.
8.5.1 ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration
bit in the Configuration register mu st be programmed to
‘0’. (Refer to Section 21.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is
unprogrammed (‘1’), the clock switching function and
Fail-Safe Clock Monitor function are disabled. This is
the default setting.
The NOSC<2:0> control bits (OSCCON<10:8>) do
not control the clock selection when clock switching
is disabled. However, the COSC<2:0> bits
(OSCCON<14:12 >) refl ect t he cl ock sour ce se lected by
the FNO SCx C onf igura tion bits .
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
8.5.2 OSCILLATOR SWITCHING SEQUENCE
To perform a clock switch, the following basic sequence
is required:
1. If required, read the COSC<2:0 > bits to determ ine
the current oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
3. Write the appropriate value to the NOSC<2:0>
control bits for the new oscillator source.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5. Set the OSWEN bit to initia te the osci ll ator sw itch.
After the basic sequence is completed, the system
clock hardware responds as follows:
1. The clock switching hardware compares the
COSC<2:0> status bits with the new value of the
NOSC<2:0> control bits. If they are the same,
the cloc k switch is a redundant op eration. In thi s
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
2. If a valid cl ock switch has been initiated, th e LOCK
(OSCCON<5>) and the CF (OSCCON<3>) status
bits are cleared.
3. The new oscil la tor is tur ned on by the ha rdw are if
it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillat or St art-up T imer (OST) expire s. If the new
source i s using the PLL, the hardware wa its until a
PLL lock is detected (LOCK = 1).
4. The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
5. The hardware cl ears the OSWEN bit to indicat e a
successful clock transition. In addition, the
NOSC<2:0> bit values are transferred to the
COSC<2:0> status bits.
6. The old c lock sour ce is turne d of f a t t his t ime, with
the exception of LPRC (if WDT or FSCM are
enabled).
8.6 Fail-Safe Clock Monitor (FSCM)
The Fail-Saf e Cl oc k Mo nito r (FSCM) all ow s the devic e
to conti nue to o pe rate eve n in th e even t of an oscil lator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
During an oscillator failure, the FSCM generates a
clock failure trap event and switches the system clock
over to the FRC oscillator. Then, the application
program can either attempt to restart the oscillator or
execute a controlled shutdown. T he trap can be tre ated
as a Warm Reset by simply loading the Reset address
into the oscillator fail trap vector.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
Note: Primary oscillator mode has three different
submodes (XT, HS and EC), which are
determined by the POSCMD<1:0>
Configuration bits. While an application
can switch to and from primary oscillator
mode in software, it cannot switch among
the different primary submodes without
reprogram mi ng the devic e.
Note 1: The process or continue s to execute code
througho ut the clock swi tching sequence.
Timing-sensitive code should not be
executed during this time.
2: Direct clock switches between any pri-
mary oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL modes.
3: Refer to “Oscillator (Part IV)”
(DS70307) in the “dsPIC33F/PIC24H
Family Reference Manual” for details.
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
9.0 POWER-SAVING FEATURES
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices provide the ability to manage power
consumption by selectively managing clocking to the
CPU and the peripherals. In general, a lower clock
frequency and a reduction in the number of circuits
being clocked constitutes lower consumed power.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices can manage power consumption in four
different ways:
• Cloc k Freq uency
• Instruction -Bas ed Slee p and Idle mode s
• Software -C ont roll ed D oze mode
• Selective Peripheral Control in Software
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while sti ll ma intaining critic al applicat ion fea tures, such
as timing-sensitive communications.
9.1 Clock Frequency and Clock
Switching
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X 0 4 de vices allow a wide range of cloc k frequ encie s to
be selected under application control. If the system
clock configuration is not locked, users can choose
low-power or high-precision oscillators by simply
changing the NOSC<2:0> bits (OSCCON<10:8>).
The process of changing a system clock during
operation, as well as limitations to the process, are
discussed in more detail in Section 8.0 “Oscillator
Configuration”.
9.2 Instruction-Based Power-Saving
Modes
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices have two special power- saving modes that
are entered through the execution of a special PWRSAV
instruction. Sleep mode stops clock operation and halts all
code execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembler syntax of the PWRSAV
instruction is shown in Example 9-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake-up.
9.2.1 SLEEP MODE
The following occur in Sleep mode:
• The system clock source is shut down. If an
on-chip oscillator is u sed, i t is turned off
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current
• The Fail-Safe Clock Monitor does not operate,
since the sy ste m clo ck sourc e is dis ab led
• The LPRC clock continues to run in Sleep mode if
the WDT is enabled
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode
• Some devi ce featu res or peripherals may continue
to operate. This includes the items such a s the
Input Change Notification on the I/O po rt s o r
peripherals that use an ex ternal cloc k input.
• Any peripheral that requires the system clock
source for it s ope rati on is dis ab led
The device will wake-up from Sleep mode on any of
these events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
EXAMPL E 9-1: PWRSAV INSTRUCTION SYNTAX
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Watchdog Timer and
Power-Saving Modes” (DS70196) in
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Micro c hi p w e b si te (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode
PWRSAV #IDLE_MODE ; Put the device into IDLE mode
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 148 2008-2014 Microchip Technology Inc.
9.2.2 IDLE MODE
The following occur in Idle mode:
• The CPU stops executing instructions
• The WDT is automatically cleared
• The system clock source remains active. By
default, all peripheral modu les continue to oper ate
normally from the system clock source, but can
also be selectively disabled (see Section 9.4
“Peripheral Mod ule Disab le” ).
• If the WDT or FSCM is enabled, the LPRC also
remains active
The devi ce will wake-up from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle mode, the clock is reapplied to
the CPU an d in st ruction ex ec utio n w il l b egi n (2-4 cl oc k
cycles later), starting with the instruction following the
PWRSAV instruction, or the first instruction in the ISR.
9.2.3 INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAV instruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
9.3 Doze Mode
The preferred strategies for reducing power
consumption are changing clock speed and invoking
one of the power-saving modes. In some
circum stances, this may not be p r act ic al. F or ex am pl e,
it may be necessary for an application to maintain
uninterru pte d synchro nou s commun icati on, eve n whil e
it is doing nothing else. Reducing system clock speed
can introduce communication errors, while using a
power-saving mode can stop communications
completely.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clock ed at the sam e speed, w hile the CPU c lock spee d
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>). There are eight possible configura-
tions, from 1:1 to 1:128, with 1:1 being the default
setting.
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU idles, waiting for something to invoke an
interrupt routine. An auto matic return to ful l-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.
For example, suppose the device is operating at
20 MIPS and the CAN modu le has bee n config ured for
500 kbps based on this device operating speed. If the
device is placed in Doze mode with a clock frequency
ratio of 1:4, the CAN module continues to communi cate
at the required bit rate of 500 kbps, but the CPU now
starts executing instructions at a frequency of 5 MIPS.
9.4 Peripheral Module Disable
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers will have no effect and read
values will be invalid.
A peripheral module is enabled only if both the
associated bit in the PMD register is cleared and the
peripheral is supported by the specific dsPIC® DSC
variant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
Note: If a PMD bit is set, the corresponding
module is disabled after a delay of one
instruction cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of one instruction
cycle (as su mi ng t he mo dul e c ontrol regi s-
ters are already configured to enable
module operation).
2008-2014 Microchip Technology Inc. DS70000318G-page 149
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
—— T3MD T2MD T1MD —PWMMD
(1)—
bit 15 bit 8
R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0
I2C1MD —U1MD— SPI1MD —— ADCMD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13 T3MD: Timer3 Module Disable bit
1 = Timer3 module is disabled
0 = Timer3 module is enabled
bit 12 T2MD: Timer2 Module Disable bit
1 = Timer2 module is disabled
0 = Timer2 module is enabled
bit 11 T1MD: Timer1 Module Disable bit
1 = Timer1 module is disabled
0 = Timer1 module is enabled
bit 10 Unimplemented: Read as ‘0’
bit 9 PWMMD: PWM Modul e Disable bit(1)
1 = PWM module is disabled
0 = PWM module is enabled
bit 8 Unimplemented: Read as ‘0’
bit 7 I2C1MD: I2C1 Module Disable bit
1 = I2C1 module is disabled
0 = I2C1 module is enabled
bit 6 Unimplemented: Read as ‘0’
bit 5 U1MD: UART1 Module Disable bit
1 = UART1 module is disabled
0 = UART1 module is enabled
bit 4 Unimplemented: Read as ‘0’
bit 3 SPI1MD: SPI1 Module Disable bit
1 = SPI1 module is disabled
0 = SPI1 module is enabled
bit 2-1 Unimplemented: Read as ‘0’
bit 0 ADCMD: ADC Module Disable bit
1 = ADC module is disabled
0 = ADC module is enabled
Note 1: Once th e PWM modu le is re -enabl ed (PWMM D is se t to ‘1’ an d then s et to ‘0’ ), all PWM regis ters mu st be
reinitialized.
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REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
——————IC2MDIC1MD
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
——————OC2MDOC1MD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 0 Unimplemented: Read as ‘0’
bit 9 IC2MD: Input Capture 2 Module Disable bit
1 = Input Capture 2 module is disabled
0 = Input Capture 2 module is enabled
bit 8 IC1MD: Input Capture 1 Module Disable bit
1 = Input Capture 1 module is disabled
0 = Input Capture 1 module is enabled
bit 7-2 Unimplemented: Read as ‘0’
bit 1 OC2MD: Output Compare 2 Module Disable bit
1 = Output Compare 2 module is disabled
0 = Output Compare 2 module is enabled
bit 0 OC1MD: Output Compare 1 Module Disable bit
1 = Output Compare 1 module is disabled
0 = Output Compare 1 module is enabled
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
REGISTER 9-4: PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4
U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0
— — — — —CMPMD— —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10 CMPMD: Analog Comparator Module Disable bit
1 = Analog comparator module is disabled
0 = Analog comparator module is enabled
bit 9-0 Unimplemented: Read as ‘0’
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
————REFOMD— — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as ‘0’
bit 3 REFOMD: Reference Clock Generator Module Disable bit
1 = Reference clock generator module is disabled
0 = Reference clock generator module is enabled
bit 2-0 Unimplemented: Read as ‘0’
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REGISTER 9-5: PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
———— PWM4MD PWM3MD PWM2MD PWM1MD
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 2 Unimplemented: Read as ‘0’
bit 11 PWM4MD: PWM Generator 4 Module Disable bit
1 = PWM Generator 4 module is disabled
0 = PWM Generator 4 module is enabled
bit 10 PWM3MD: PWM Generator 3 Module Disable bit
1 = PWM Generator 3 module is disabled
0 = PWM Generator 3 module is enabled
bit 9 PWM2MD: PWM Generator 2 Module Disable bit
1 = PWM Generator 2 module is disabled
0 = PWM Generator 2 module is enabled
bit 8 PWM1MD: PWM Generator 1 Module Disable bit
1 = PWM Generator 1 module is disabled
0 = PWM Generator 1 module is enabled
bit 7-0 Unimplemented: Read as ‘0’
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 9-6: PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
———— CMP4MD CMP3MD CMP2MD CMP1MD
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 2 Unimplemented: Read as ‘0’
bit 11 CMP4MD: Analog Comparator 4 Module Disable bit
1 = Analog Comparator 4 module is disabled
0 = Analog Comparator 4 module is enabled
bit 10 CMP3MD: Analog Compara tor 3 Modu le Di sa ble bit
1 = Analog Comparator 3 module is disabled
0 = Analog Comparator 3 module is enabled
bit 9 CMP2MD: Analog Comp ara tor 2 Modu le Disa ble bit
1 = Analog Comparator 2 module is disabled
0 = Analog Comparator 2 module is enabled
bit 8 CMP1MD: Analog Comp ara t or 1 Module Di sa ble bit
1 = Analog Comparator 1 module is disabled
0 = Analog Comparator 1 module is enabled
bit 7-0 Unimplemented: Read as ‘0’
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 154 2008-2014 Microchip Technology Inc.
NOTES:
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
10.0 I/O PORTS
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKI) are shared among the peripherals and the
parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
10.1 Parallel I/O (PIO) Ports
Generally a parallel I/O port that shares a pin with a
peripheral is subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has own ership of the outp ut dat a and co ntrol si gn als of
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
periphera l that shares the same pin. Figure 10-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as a
general purpose output pin is disabled. The I/O pin can
be read, but the output driver for the parallel port bit is
disabled. If a peripheral is enabled, but the peripheral is
not actively driving a pin, that pin can be driven by a port.
All port pins hav e three registers directly associated w ith
their operation as digital I/O. The data direction register
(TRISx) determines whether the pi n is an input or an out-
put. If the data direction bit is ‘1’, then the pin is an input.
All port pins are defined as inputs after a Reset. Reads
from the latch (LATx) read the latch. Writes to the latch
write the latch. Reads from the port (PORTx) read the
port pins, while writes to the port pins wri te the latch.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a compre-
hens ive reference source. To complement
the informati on in this da ta sheet, refer
to “I/O Ports” (DS70193) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available on Microchip
web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data she et for device-specific regis ter
and bit information.
QD
CK
WR LAT +
TRIS Latch
I/O Pin
WR PORT
Data Bus
QD
CK
Data Latch
Read PORT
Read TRIS
1
0
1
0
WR TRIS
Peripheral Output Data Output Enable
Peripheral Input Data
I/O
Peripheral Module
Periphe ra l Out put Enab le
PIO Modul e
Output Multiplexers
Output Data
Input Data
Peripheral Module Enable
Read LAT
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 156 2008-2014 Microchip Technology Inc.
10.2 Open-Drain Configuration
In addi tion t o t he POR Tx , LATx and TRISx regis ter s for
data control, some digital-only port pins can also be
individually configured for either digital or open-drain
output. This is controlled by the Open-Drain Control
register, ODCx, associated with each port. Setting any
of the bits configures the corresponding pin to act as an
open-drain output.
The open-drain feature allows the generation of
outputs higher than VDD (for example, 5V) on any
desired 5V tolerant pins by using external pull-up
resis tor s. The max imum open -dra in vo ltag e allo wed is
the sa me as the maximum VIH specification.
Refer to “Pin Diagrams” for the available pins and
their functionality.
10.3 Configuring Analog Port Pins
The ADPCFG and TRISx registers control the opera-
tion of the Analog-to-Digital (A/D) port pins. The port
pins that are to function as analog inputs must have
their corresponding TRISx bit set (input). If the TRISx
bit is cleared (output), the digital output level (VOH or
VOL) will be converted.
The ADPCFG register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
When th e PORTx register is read, all pin s configured as
analog in put channels will rea d as cleared (a low le vel).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
10.4 I/O Port Wr ite/Read T iming
One instruction cycle is required between a port direction
change or port write operation and a read operation of
the same port. T ypically , this instruction would be a NOP.
An example is shown in Example 10-1.
10.5 Input Change Notification
The Input Change Notification (ICN) function of the
I/O ports allows the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 devices to g enerate interrupt
requests to the processor in response to a
Change-of-State (COS) on selected input pins. This
feature can detect input Change-of-States even in
Sleep mode, when the cl oc ks are di sa bled. Depending
on the devi ce pin c ount, up to 30 extern al sign als (CN x
pin) can be selected (enabled) for generating an
interrupt request on a Change-of-State.
Four control registers are associated with the CN
module . The C NEN1 and CN EN 2 reg isters contai n th e
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin, and eliminate the need for external resistors when
the push button o r key p ad devi ces are co nne cted. The
pull-ups are enabled separately using the CNPU1 and
CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
EQUATION 10-1: PORT WRITE/READ EXAMPLE
Note: Pull-ups on Change Notification pins
should always be disabled when the port
pin is configured as a digital output.
MOV 0xFF00, W0 ; Con figure PORTB<1 5:8> as inputs
MOV W0, TRISBB ; and PORTB< 7:0> as output s
NOP ; Delay 1 cycle
BTSS PORTB, #13 ; Next Instr uction
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10.6 Peripheral Pin Select
Peripheral Pin Select configuration enables peripheral
set selection and placement on a wide range of I/O
pins. By increasing the pinout options available on a
particular device, programmers can better tailor the
microcontroller to their entire application, rather than
trimming the application to fit the device.
The Peripheral Pin Select configuration feature operates
over a fixed subset of digit al I/O pins. Pro gramme rs can
independently map the input and/or output of most
digital peripherals to any one of these I/O pins.
Peripheral Pi n Select is performed in sof tware, and gen-
erally does not require the device to be reprogrammed.
Hardware safeguards are include d that prevent acciden-
tal or spurious chang es to the peripheral mapping, once
it has been established.
10.6.1 AVAILABLE PINS
The Peripheral Pin Select feature is used with a range
of up to 30 pi ns. Th e num ber o f ava ilable pins dep ends
on the particular device and its pin count. Pins that
support the Peripheral Pin Select feature include the
designation “RPn” in their full pin designation, where
“RP” designat es a remappab le peripheral and “n” is the
remappable pin number.
10.6.2 C ONT RO LLIN G PERIP HERA L PIN
SELECT
Peripheral Pin Select features are controlled through
two sets of Special Function Registers: one to map
peripheral inputs and another one to map outputs.
Because they are separately controlled, a particular
periphera l’s input and output (if the periphe ral has both)
can be placed on any selectable function pin without
constraint.
The association of a peripheral to a peripheral select-
able pi n is h andled in two dif fere nt wa ys, de pendi ng on
whether an input or output is being mapped.
10.6.2.1 Input Mapping
The inputs of the Peripheral Pin Select options are
mapped on the basis of the peripheral. A control
register associated with a peripheral dictates the pin it
will be m apped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 10-1
through Register 10-14). Each r egi ster c ont ains set s of
6-bit fields, with each set associated with one of the
remappable peripherals. Programming a given
peripheral’s bit field with an appropriate 6-bit value
map s the RPn pin with t hat value to that pe riphera l. For
any given device, the valid range of values for any bit
field corresponds to the maximum number of
Peripheral Pin Selections supported by the device.
Figure 10-2 Illustrates remappable pin selection for
U1RX input.
FIGURE 10-2: REMAPPABLE MUX
INPUT FOR U1RX
Note: For inp ut mapping on ly, the Peri pheral Pin
Select (PPS) functionality does not have
priority over the TRISx settings. There-
fore, when configuring the RPx pin for
input, the corresponding bit in the TRISx
register must also be configured for input
(i.e., set to ‘1’).
RP0
RP1
RP2
RP33
0
33
1
2U1RX Input
U1RXR<5:0>
to Peripheral
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 158 2008-2014 Microchip Technology Inc.
TABLE 10-1: SE L EC TAB LE INPUT SOURCES (MAPS INPU T TO F UNCTION)
Input Name Function Name Register Configuration
Bits
External Interrupt 1 INT1 RPINR0 INT1R<5:0>
External Interrupt 2 INT2 RPINR1 INT2R<5:0>
Timer1 External Clock T1CK RPINR2 T1CKR<5:0>
Timer2 External Clock T2CK RPINR3 T2CKR<5:0>
Timer3 External Clock T3CK RPINR3 T3CKR<5:0>
Input Capture 1 IC1 RPINR7 IC1R<5:0>
Input Capture 2 IC2 RPINR7 IC2R<5:0>
Output Compare Fault A OCFA RPINR11 OCFAR<5:0>
UART1 Receive U1RX RPINR18 U1RXR<5:0>
UART1 Clear-to-Send U1CTS RPINR18 U1CTSR<5:0>
SPI Data Input 1 SDI1 RPINR20 SDI1R<5:0>
SPI Clock Input 1 SCK1 RPINR20 SCK1R<5:0>
SPI Slave Select Inpu t 1 SS1 RPINR21 SS1R<5:0>
PWM Fault Input PWM1 FLT1 RPINR29 FLT1R<5:0>
PWM Fault Input PWM2 FLT2 RPINR30 FLT2R<5:0>
PWM Fault Input PWM3 FLT3 RPINR30 FLT3R<5:0>
PWM Fault Input PWM4 FLT4 RPINR31 FLT4R<5:0>
PWM Fault Input PWM5 FLT5 RPINR31 FLT5R<5:0>
PWM Fault Input PWM6 FLT6 RPINR32 FLT6R<5:0>
PWM Fault Input PWM7 FLT7 RPINR32 FLT7R<5:0>
PWM Fault Input PWM8 FLT8 RPINR33 FLT8R<5:0>
External Synchronization signal to PWM Master Time Base SYNCI1 RPINR33 SYNCI1R<5:0>
External Synchronization signal to PWM Master Time Base SYNCI2 RPINR34 SYNCI2R<5:0>
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10.6.2.2 Output Mapping
In contrast to inputs, the outputs of the Peripheral Pin
Select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Like t h e RP IN Rx r egi st ers , ea ch re gi ste r conta in s se ts
of 6-bit fields, with each set associated with one RPn
pin (see Register 10-15 through Register 10-31). The
value of the bit field corresponds to one of the
peripherals, and that peripheral’s output is mapped to
the pin (see Table 10-2 and Figure 10-3).
The lis t of perip he rals for output m appin g also in clude s
a null value of ‘00000’ because of the mapping
technique. This permits any given pin to remain
unconnected from the output of any of the pin
selectable peripherals.
FIGURE 10-3: MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPn
TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
0
45
3
RPORn<5:0>
Default
U1TX Output Enable
U1RTS Output Enable 4
PWM4L Output Enable
19
OC2 Output Enable
0
45
3
Default
U1T X Outpu t
U1RTS Output 4
PWM4L Output 19
OC2 Output
Output Enable
Output Data RPn
Function RPO Rn<5:0> Output Name
NULL 000000 RPn tied to default port pin
U1TX 000011 RPn tied to UART1 transmit
U1RTS 000100 RPn tied to UART1 Ready-to-Send
SDO1 000111 RPn tied to SPI1 data output
SCK1 001000 RPn tied to SPI1 clock output
SS1 001001 RPn tied to SPI1 slave select output
OC1 010010 RPn tied to Output Compare 1
OC2 010011 RPn tied to Output Compare 2
SYNCO1 100101 RPn tied to external device synchronization signal via PWM master time base
REFCLKO 100110 REFCLK output signal
ACMP1 100111 RPn tied to Analog Comparator Output 1
ACMP2 101000 RPn tied to Analog Comparator Output 2
ACMP3 101001 RPn tied to Analog Comparator Output 3
ACMP4 101010 RPn tied to Analog Comparator Output 4
PWM4H 101100 RPn tied to PWM output pins associated with PWM Generator 4
PWM4L 101101 RPn tied to PWM output pins associated with PWM Generator 4
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 160 2008-2014 Microchip Technology Inc.
10.6.2.3 Virtual Pins
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX0 2/X04
devices support four virtual RPn pins (RP32, RP33,
RP34 and RP35), which are identical in functionality to
all othe r RPn pins , with the e xception of pinout s. Thes e
four pins are internal to the devices and are not
connected to a physical device pin.
These pins provide a simple way for inter-peripheral
connection witho ut utilizi ng a phy sical pin. For exa mple,
the output of the anal og comparator can be connected to
RP32 and the PWM Fault input can be configured for
RP32 as well. This configuration allows the analog
comparator to trigger PWM Faults without the use of an
actual physical pin on the devic e.
10.6.3 C ON TRO LLIN G CON F IGU RAT ION
CHANGES
Because periphe ral rem ap pin g ca n be c han ged durin g
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. dsPIC33F devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
10.6.3.1 Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these
registers, they must be unlocked in hardware. The
register lock is controlled by the IOLOCK bit
(OSCCON<6>). Setting IOLOCK prevents writes to the
control registers; clearing IOLOCK allows writes.
To set o r clea r IOLOCK, a s pecific command sequenc e
must be executed:
1. Write 0x46 to OSCCON<7:0>.
2. Write 0x57 to OSCCON<7:0>.
3. Clear (or set) IOLOCK as a single operation.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allow s all of th e Peripheral Pin Select s to be configure d
with a single u nlock s equence followe d by an u pdate to
all control registers, then locked with a second lock
sequence.
10.6.3.2 Continuous State Monitoring
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
const antly monit ored in ha rdwar e by sha dow regis ters.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
10.6.3.3 Configuration Bit Pin Select Lock
As an additional level of safety, the device can be
configured to prevent many write session to the
RPINRx and RPORx registers. The IOL1WAY
(FOSC<5>) Configuration bit blocks the IOLOCK bit
from being cleared after it has been set once. If
IOLOCK re mains set, th e register unl ock procedu re will
not execute and the Peripheral Pin Select Control
registers cannot be writ ten to. The only way t o clear the
bit and re-enable peripheral remapping is to perform a
device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
Peripheral Pin Select registers.
Note: MPLAB® C30 provides built-in C
language functions for unlocking the
OSCCO N register:
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
See the MPLAB C30 Help files for more
information.
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10.7 Peripheral Pin Select Registers
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX0 2/X04
families of devices implement 34 registers for
remappable peripheral configuration:
• 15 Input Remappable Peripheral Registers
• 17 Output Remappable Peripheral Registers
Not all output remappable peripheral registers are
implemented on all devices. See the specific register
description for further details.
Note: Input and output register values can only
be changed if OSCCON<IOLOCK> = 0.
See Section 10.6.3.1 “Control Register
Lock” for a specific command sequence.
REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 INT1R<5:0>: Assign External Interrupt 1 (INTR1) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
bit 7-0 Unimplemented: Read as ‘0’
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 162 2008-2014 Microchip Technology Inc.
REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 INT2R<5:0>: Assign External Interrupt 2 (INTR2) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
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REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— T3CKR5 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0
bit 15 bit 8
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— T2CKR5 T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 T3CKR<5:0>: Assign Timer3 Exte rnal Cloc k (T3CK) to t he Corres ponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 T2CKR<5:0>: Assign Timer 2 External Clock (T2CK) t o the Corresponding RPn P in bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 164 2008-2014 Microchip Technology Inc.
REGISTER 10-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0
bit 15 bit 8
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 IC2R<5:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 IC1R<5:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
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REGISTER 10-5: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 OCFAR<5:0>: Assign Output Capture A (OCFA) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 166 2008-2014 Microchip Technology Inc.
REGISTER 10-6: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 1 8
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0
bit 15 bit 8
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 U1CTSR<5:0>: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 U1RXR<5:0>: Assign UART1 Receive (U1RX) to the Correspondi ng R Pn Pin bit s
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
2008-2014 Microchip Technology Inc. DS70000318G-page 167
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 10-7: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 2 0
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0
bit 15 bit 8
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 SCK1R<5:0>: Assign SPI1 Clock Input (SCK1IN) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 SDI1R<5:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 168 2008-2014 Microchip Technology Inc.
REGISTER 10-8: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 2 1
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 SS1R<5:0>: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
2008-2014 Microchip Technology Inc. DS70000318G-page 169
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 10-9: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 2 9
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— FLT1R5 FLT1R4 FLT1R3 FLT1R2 FLT1R1 FLT1R0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 FLT1R<5:0>: Assign PWM Fault Input 1 (FLT1) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
bit 7-0 Unimplemented: Read as ‘0’
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 170 2008-2014 Microchip Technology Inc.
REGISTER 10-10: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— FLT3R5 FLT3R4 FLT3R3 FLT3R2 FLT3R1 FLT3R0
bit 15 bit 8
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— FLT2R5 FLT2R4 FLT2R3 FLT2R2 FLT2R1 FLT2R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 FLT3R<5:0>: Assign PWM Fault Input 3 (FLT3) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 FLT2R<5:0>: Assign PWM Fault Input 2 (FLT2) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
2008-2014 Microchip Technology Inc. DS70000318G-page 171
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 10-11: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— FLT5R5 FLT5R4 FLT5R3 FLT5R2 FLT5R1 FLT5R0
bit 15 bit 8
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— FLT4R5 FLT4R4 FLT4R3 FLT4R2 FLT4R1 FLT4R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 FLT5R<5:0>: Assign PWM Fault Input 5 (FLT5) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 FLT4R<5:0>: Assign PWM Fault Input 4 (FLT4) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 172 2008-2014 Microchip Technology Inc.
REGISTER 10-12: RPINR32: PERIPHERAL PIN SELECT INPUT REGISTER 32
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— FLT7R5 FLT7R4 FLT7R3 FLT7R2 FLT7R1 FLT7R0
bit 15 bit 8
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— FLT6R5 FLT6R4 FLT6R3 FLT6R2 FLT6R1 FLT6R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 FLT7R<5:0>: Assign PWM Fault Input 7 (FLT7) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 FLT6R<5:0>: Assign PWM Fault Input 6 (FLT6) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
2008-2014 Microchip Technology Inc. DS70000318G-page 173
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 10-13: RPINR33: PERIPHERAL PIN SELECT INPUT REGISTER 33
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— SYNCI1R5 SYNCI1R4 SYNCI1R3 SYNCI1R2 SYNCI1R1 SYNCI1R0
bit 15 bit 8
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— FLT8R5 FLT8R4 FLT8R3 FLT8R2 FLT8R1 FLT8R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 SYNCI1R<5:0>: Assign PWM Master Time Base External Synchronization Signal to the
Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 FLT8R<5:0>: Assign PWM Fault Input 8 (FLT8) to the Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 174 2008-2014 Microchip Technology Inc.
REGISTER 10-14: RPINR34: PERIPHERAL PIN SELECT INPUT REGISTER 34
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— SYNCI2R5 SYNCI2R4 SYNCI2R3 SYNCI2R2 SYNCI2R1 SYNCI2R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 SYNCI2R<5:0>: Assign PWM Master Time Base External Synchronization Signal to the
Corresponding RPn Pin bits
111111 = Input tied to VSS
100011 = Input tied to RP35
100010 = Input tied to RP34
100001 = Input tied to RP33
100000 = Input tied to RP32
•
•
•
00000 = Input tied to RP0
REGISTER 10-15: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP1R<5:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP0R<5:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits
(see Table 10-2 for peripheral function numbers)
2008-2014 Microchip Technology Inc. DS70000318G-page 175
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 10-16: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP3R<5:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP2R<5:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-17: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP5R5 RP5R4 RP5R3 RP5R2 RP5R1 RP5R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP5R<5:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP4R<5:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits
(see Table 10-2 for peripheral function numbers)
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 176 2008-2014 Microchip Technology Inc.
REGISTER 10-18: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP7R<5:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP6R<5:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-19: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP9R<5:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP8R<5:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits
(see Table 10-2 for peripheral function numbers)
Note 1: This register is not implemented in the dsPIC33FJ06GS101 device.
2008-2014 Microchip Technology Inc. DS70000318G-page 177
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 10-20: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP11R<5:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP10R<5:0>: Peripheral Output Function i s Assigned to RP 10 Output Pin bits
(see Table 10-2 for peripheral function numbers)
Note 1: This register is not implemented in the dsPIC33FJ06GS101 device.
REGISTER 10-21: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP13R<5:0>: Peripheral Output Function is Assigned t o RP13 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP12R<5:0>: Peripheral Output Function i s Assigned to RP 12 Output Pin bits
(see Table 10-2 for peripheral function numbers)
Note 1: This register is not implemented in the dsPIC33FJ06GS101 device.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 178 2008-2014 Microchip Technology Inc.
REGISTER 10-22: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP15R5 RP15R4 RP15R3 RP15R2 RP15R1 RP15R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP15R<5:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP14R<5:0>: Periph eral Output Function is Assign ed to RP14 Output Pin bits
(see Table 10-2 for peripheral function numbers)
Note 1: This register is not implemented in the dsPIC33FJ06GS101 device.
REGISTER 10-23: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP17R<5:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP16R<5:0>: Periph eral Output Function is Assign ed to RP16 Output Pin bits
(see Table 10-2 for peripheral function numbers)
Note 1: This register is implemented in the dsPIC33FJ16 GS404 and dsPIC33F J16GS504 devices only.
2008-2014 Microchip Technology Inc. DS70000318G-page 179
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 10-24: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP19R5 RP19R4 RP19R3 RP19R2 RP19R1 RP19R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP19R<5:0>: Peripheral Output Function is Assigned t o RP19 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP18R<5:0>: Peripheral Output Function i s Assigned to RP 18 Output Pin bits
(see Table 10-2 for peripheral function numbers)
Note 1: This register is implemented in the dsPIC33FJ16 GS404 and dsPIC33F J16GS504 devices only.
REGISTER 10-25: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP21R<5:0>: Peripheral Output Function is Assigned t o RP21 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP20R<5:0>: Peripheral Output Function i s Assigned to RP 20 Output Pin bits
(see Table 10-2 for peripheral function numbers)
Note 1: This register is implemented in the dsPIC33FJ16 GS404 and dsPIC33F J16GS504 devices only.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 180 2008-2014 Microchip Technology Inc.
REGISTER 10-26: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP23R5 RP23R4 RP23R3 RP23R2 RP23R1 RP23R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP23R<5:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP22R<5:0>: Periph eral Output Function is Assign ed to RP22 Output Pin bits
(see Table 10-2 for peripheral function numbers)
Note 1: This register is implemented in the dsPIC33FJ16 GS404 and dsPIC33F J16GS504 devices only.
REGISTER 10-27: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP25R<5:0>: Peripheral Output Function is Assigned to RP25 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP24R<5:0>: Periph eral Output Function is Assign ed to RP24 Output Pin bits
(see Table 10-2 for peripheral function numbers)
Note 1: This register is implemented in the dsPIC33FJ16 GS404 and dsPIC33F J16GS504 devices only.
2008-2014 Microchip Technology Inc. DS70000318G-page 181
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 10-28: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13(1)
REGISTER 10-29: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP27R5 RP27R4 RP27R3 RP27R2 RP27R1 RP27R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP26R5 RP26R4 RP26R3 RP26R2 RP26R1 RP26R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP27R<5:0>: Peripheral Output Function is Assigned t o RP27 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP26R<5:0>: Peripheral Output Function i s Assigned to RP 26 Output Pin bits
(see Table 10-2 for peripheral function numbers)
Note 1: This register is implemented in the dsPIC33FJ16 GS404 and dsPIC33F J16GS504 devices only.
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP29R<5:0>: Peripheral Output Function is Assigned t o RP29 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP28R<5:0>: Peripheral Output Function i s Assigned to RP 28 Output Pin bits
(see Table 10-2 for peripheral function numbers)
Note 1: This register is implemented in the dsPIC33FJ16 GS404 and dsPIC33F J16GS504 devices only.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 182 2008-2014 Microchip Technology Inc.
REGISTER 10-30: RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16
REGISTER 10-31: RPOR17: PERIPHERAL PIN SELECT OUTPUT REGISTER 17
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP33R5 RP33R4 RP33R3 RP33R2 RP33R1 RP33R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP32R5 RP32R4 RP32R3 RP32R2 RP32R1 RP32R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP33R<5:0>: Peripheral Output Function is Assigned to RP33 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP32R<5:0>: Periph eral Output Function is Assign ed to RP32 Output Pin bits
(see Table 10-2 for peripheral function numbers)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP35R5 RP35R4 RP35R3 RP35R2 RP35R1 RP35R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP34R5 RP34R4 RP34R3 RP34R2 RP34R1 RP34R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-8 RP35R<5:0>: Peripheral Output Function is Assigned to RP35 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP34R<5:0>: Periph eral Output Function is Assign ed to RP34 Output Pin bits
(see Table 10-2 for peripheral function numbers)
2008-2014 Microchip Technology Inc. DS70000318G-page 183
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
11.0 TIMER1
The Timer1 module is a 16-bit timer, which can serve
as a time counter for the Real-Time Clock (RTC), or
operate as a free-running interval timer/counter.
The Timer1 module has the following unique features
over other timers:
• Can be operated from the low-power 32 kHz
crystal oscillator available on the device
• Can be operated in Asynchronous Counter mode
from an external clock source
• Optionally, the external cloc k inpu t (T1CK) can be
synchronized to the internal device clock and the
clock synchronization is performed after the
prescaler
The unique features of Timer1 allow it to be used for
Real-Time Clock (RTC) applications. A block diagram
of Timer1 is shown in Figure 11-1.
The Timer1 modu le c an op erate in one of t he f oll ow in g
modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
• Asynchronous Counter mode
In Timer and Gated Timer modes, the input clock is
deri ved from th e intern al instru ction cycl e clock (F CY).
In Synchronous and Asynchronous Counter modes,
the input clock is derived from the external clock input
at the T1CK pin.
The Timer modes are dete rmi ne d by the foll ow in g bit s :
• Ti mer Cloc k Sourc e Contro l bit (T CS): T1C ON<1>
• Time r Synchronizat ion C ontr ol bit (TSYNC):
T1CON<2>
• Timer Gate Control bit (TGATE): T1CON<6>
The timer control bit settings for different operating
modes are giv en in the Table 11-1.
TABLE 11-1: TIMER MODE SETTINGS
FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Timers” (DS70205) in
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Micro c hi p w e b si te (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data she et for device-specific regis ter
and bit information.
Mode TCS TGATE TSYNC
Timer 00x
Gated Timer 01x
Synchronous
Counter 1x1
Asynchronous
Counter 1x0
TGATE
TCS
00
10
x1
TMR1
Comparator
PR1
TGATE
Set T1IF Fl a g
0
1
TSYNC
1
0
Sync Equal
Reset
T1CK Prescaler
(/n)
TCKPS<1:0>
Gate
Sync
FCY
Falling Edge
Detect
Prescaler
(/n)
TCKPS<1:0>
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 184 2008-2014 Microchip Technology Inc.
REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON —TSIDL— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0
— TGATE TCKPS1 TCKPS0 — TSYNC TCS —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timer1 On bit
1 = Starts 16-bit Timer1
0 = Stop s 16-b it Timer1
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0> Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 Unimplemented: Read as ‘0’
bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1 = Synchronizes external clock input
0 = Does not synchron iz e exte rnal cloc k inp ut
When TCS = 0:
This bit is ignored.
bit 1 TCS: Ti mer1 Clock Source Select bit
1 = External clock from T1CK pin (on the ris ing edge)
0 = Internal clock (FCY)
bit 0 Unimplemented: Read as ‘0’
2008-2014 Microchip Technology Inc. DS70000318G-page 185
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
12.0 TI MER2/3 FEAT URES Timer 2 is a Type B timer that of fe rs th e following m aj or
features:
• A Type B timer can be concatenated with a
Type C timer to form a 32-bit timer
• External clock input (TxCK) is always synchronized
to the internal device clock and the clock
synchronization is performed after the prescaler.
Figure 12-1 shows a block diagram of the T ype B timer .
Timer 3 i s a Type C tim er tha t offers the foll owin g m aj or
features:
• A Type C timer can be concatenated with a
Type B timer to form a 32-bit timer
• The external clock input (TxCK) is always
synchronized to the internal device clock and the clock
synchronization is performed before the prescaler
A block diagram of the Type C timer is shown in
Figure 12-2.
FIGURE 12-1: TYPE B TIMER BLOCK DIAGRAM (x = 2)
FIGURE 12-2: TYPE C TIMER BLOCK DIAGRAM (x = 3)
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Timers” (DS70205) in
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available on the
Micro c hi p w e b si te (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Timer3 is not available on all devices.
Prescaler
(/n)
TGATE
TCS
00
10
x1
TMRx
Comparator
PRx
TGATE
Set TxIF Flag
0
1
Sync
TCKPS<1:0>
Equal
Reset
TxCK
Gate
Sync
FCY
Falling Edge
Detect
Prescaler
(/n)
TCKPS<1:0>
Prescaler
(/n)
Gate
Sync
TGATE
TCS
00
10
x1
TMRx
Comparator
PRx
FCY
TGATE
Falling E dge
Detect Set TxIF Flag
0
1
Sync
TCKPS<1:0>
Equal
Reset
TxCK
Prescaler
(/n)
TCKPS<1:0>
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 186 2008-2014 Microchip Technology Inc.
The Timer2/3 module can operate in one of the
following modes:
•Timer mode
• Gated Timer mode
• Synchronous Counter mode
In Timer and Gated Timer modes, the input clock is
deri ved from th e intern al instru ction cyc le clock (F CY).
In Synchronous Counter mode, the input clock is
derived from the external clock input at the TxCK pin.
The timer modes are determined by the following bits:
• TCS (TxCON<1>): T imer Clock Source Control bit
• TGATE (TxCON<6>): Timer Gate Control bit
Timer control bit settings for different operating modes
are given in the Table 12-1.
TA BL E 12- 1: TIMER MODE SETTIN GS
12.1 16-Bit Operation
To configure any of the timers for individual 16-bit
operation:
1. Clear the T32 bit corresponding to that timer.
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the TCS
and TGATE bits.
4. Load the timer period value into the PRx
register.
5. If interrupts are required, set the interrupt enable
bit, TxIE. Use the priority bits, TxIP<2:0>, to set
the interrupt priority.
6. Set the TON bit.
12.2 32-Bit Operation
A 32-bit timer module can be formed by combining a
Type B and a Type C 16-bit timer module. For 32-bit
timer ope rati on , the T32 control bit in the Type B Timer
Control (TxCON<3>) register must be set. The Type C
timer holds the most significant word (msw) and the
Type B timer holds the least significant word (lsw)
for 32-bit operation.
When configured for 32-bit operation, only the Type B
Timer Control (TxCON) register bits are required for
setup and control while the Type C Timer Control
register bits are ignored (exce pt the TSIDL bit).
For interrupt control, the combined 32-bit timer uses
the interrupt enable, interrupt flag and interrupt priority
control bits of the Type C timer. The interrupt control
and status bits for the Type B timer are ignored
during 32-bit timer operation.
The T imer2 and T imer 3 that can b e combined to form a
32-bit timer are listed in Table 12-2.
TABLE 12-2: 32-BIT TIMER
A block diagram representation of the 32-bit timer
module is shown in Figure 12-3. The 32-timer module
can operate in one of the following modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
To configure the features of Timer2/3 for 32-bit
operation:
1. Set the T32 control bit.
2. Select the prescaler ratio for Timer2 using the
TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the
corresponding TCS and TGATE bits.
4. Load the timer period value. PR3 contains the
most significant word of the value, while PR2
cont ains the least significant word.
5. If interrupts are required, set the interrupt en able
bit, T3IE. Use the priority bits, T3IP<2:0>, to set
the interrupt priority. While Timer2 controls the
timer, the interrupt appears as a Timer3
interrupt.
6. Set the corresponding TON bit.
The timer value at any point is stored in the register
pair, TMR3:TMR2, which always contains the most
signi f ic an t w o rd of t he co un t , w h ile TM R 2 conta i ns t he
least significant word.
Mode TCS TGATE
Timer 00
Gated Timer 01
Synchronous Counter 1x
Type B Timer (lsw) Type C Timer (msw)
Timer2 Timer3
2008-2014 Microchip Technology Inc. DS70000318G-page 187
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 12-3: 32-BIT TIMER BLOCK DIAGRAM
Prescaler
(/n)
TGATE
TCS
00
10
x1
TMRx(1)
PRx
TGATE
Set TyIF
0
1
Sync
TCKPS<1:0>
Equal
TxCK
Gate
Sync
FCY
Falling Edge
Detect
Prescaler
(/n)
TCKPS<1:0> TMRy(2)
Comparator
PRy
Reset
msw
lsw
TMRyHLD
Data Bus <15:0>
Flag
Note 1: Timerx is a Type B Timer (x = 2).
2: Timery is a Type C Timer (y = 3).
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 188 2008-2014 Microchip Technology Inc.
REGISTER 12-1: TxCON: TIMERx CONTROL REGISTER (x = 2)
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON —TSIDL— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
— TGATE TCKPS1 TCKPS0 T32 —TCS—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timerx On bit
When T32 = 1 (in 32-Bit Timer mode):
1 = Starts 32-bit TMRx:TMRy timer pair
0 = Stops 32-bit TMRx:TMRy timer pair
When T32 = 0 (in 16-Bit Timer mode):
1 = Starts 16-bit timer
0 = Stop s 16-b it tim er
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Timerx Stop in Idle Mode bit
1 = Discontinues timer operation when device enters Idle mode
0 = Continues timer operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3 T32: 32-Bit Timerx Mode Select bit
1 = TMRx and TMRy form a 32-bit timer
0 = TMRx and TMRy form a separate 16-bit timer
bit 2 Unimplemented: Read as ‘0’
bit 1 TCS: Ti merx Clock Source Select bit
1 = External clock from TxCK pin
0 = Internal clock (FOSC/2)
bit 0 Unimplemented: Read as ‘0’
2008-2014 Microchip Technology Inc. DS70000318G-page 189
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 12-2: TyCON: TIMERy CONTROL REGISTER (y = 3)
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON(2) —TSIDL
(1)— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0
— TGATE
(2)TCKPS1(2)TCKPS0(2)——TCS
(2)—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timery On bit(2)
1 = Starts 16-bit Timery
0 = Stop s 16-bit T i me r y
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Timery Stop in Idle Mode bit(1)
1 = Discontinues timer operation when device enters Idle mode
0 = Continues timer operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timery Gated Time Accumulation Enable bit(2)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Time ry Input Clock Prescale Select bits(2)
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3-2 Unimplemented: Read as ‘0’
bit 1 TCS: Timery Clock Source Select bit(2)
1 = External clock from TxCK pin
0 = Internal clock (FOSC/2)
bit 0 Unimplemented: Read as ‘0’
Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
2: When the 32-bit timer op erat ion is enab led (T32 = 1) in the Timerx Control (TxCON<3>) register, these
bits have no effect.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 190 2008-2014 Microchip Technology Inc.
NOTES:
2008-2014 Microchip Technology Inc. DS70000318G-page 191
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
13.0 INPUT CAPTURE
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
devices support up to two input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at th e ICx pi n. The events th at cause a captu re even t
are listed below in three categories:
• Simple Capture Event modes:
- Capture timer value on every falling edge of
input at ICx pin
- Capture timer value on every rising edge of
input at ICx pin
• Capture timer value on every edge (rising and
falling)
• Prescaler Capture Event modes:
- Capture timer value on every 4th rising edge
of input at ICx pin
- Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select one of the
two 16-bit timers (Timer2 or Timer3) for the time
base. The selected timer can use either an internal
or external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
- Interrupt optionally generated after 1, 2, 3 or
4 buf fer locations are fill ed
• Use of input capture to provide additional sources
of external interrupts
FIGURE 13-1: INPUT CAPTURE x BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Input Capture”
(DS70198) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available on the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
ICxBUF
ICx Pin ICM<2:0> (ICxCON<2:0>)
Mode Select
3
10
Set Flag ICxIF
(in IFSx Register)
TMR2 TMR3
Edge Detection Logic
16 16
FIFO
R/W
Logic
ICxI<1:0>
ICOV, ICBNE (ICxCON<4: 3>)
ICxCON Interrupt
Logic
System Bus
From 16-Bit Timers
ICTMR
(ICxCON<7>)
FIFO
Prescaler
Counter
(1, 4, 16) and
Clock Synchronizer
Note 1: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 192 2008-2014 Microchip Technology Inc.
13.1 Input Capture Register
REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER (x = 1, 2)
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
——ICSIDL— — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0 , HC R-0, HC R/W-0 R/W-0 R/W-0
ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13 ICSIDL: Input Capture Module Stop in Idle Control bit
1 = Input capture module halts in CPU Idle mode
0 = Input capture module continues to operate in CPU Idle mode
bit 12-8 Unimplemented: Read as ‘0’
bit 7 ICTMR: Input Capture Timer Select bit s
1 = TM R2 contents are captured on a capt ure event
0 = TM R3 contents are captured on a capt ure event
bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third captur e event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
bit 3 ICBNE: Input Capture Buffer Empt y Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capt ure buffer is empty
bit 2-0 ICM<2:0>: Input Capture Mode Select bits
111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode; rising edge
detect only, all other control bits are not applicable
110 = Unused (module disabled)
101 = Capture mode , every 16th rising edge
100 = Captur e mode, ev ery 4th rising edge
011 = Capture mode, every rising edge
010 = Capture mode, ev ery falli ng edge
001 = Capture mod e, e very ed ge (ris ing an d falling); ICI<1 :0> bit s d o no t c ontro l i nte rrupt gen erat ion
for this mode
000 = Input capture module turned off
2008-2014 Microchip Technology Inc. DS70000318G-page 193
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
14.0 OUTPUT COMPARE The outp ut compare module ca n select either Timer2 or
Timer3 for its time base. The module compares the
value of the timer with the value of one or two Compare
registers depending on the operating mode selected.
The state of the output pin changes when the timer
value m atc he s th e C om p a re reg is ter v alu e. The outp ut
compare module generates either a single output
pulse, o r a se quenc e of outpu t puls es, by c hangi ng the
state of the output pin on the compare match events.
The output compare module can also generate
interrupts on compare match events.
The output compare module has multiple operating
modes:
• Active-Low One-Shot mode
• Active-High One-Shot mode
• Toggle mode
• Delayed One-Sho t mod e
• Continuous Pulse mode
• PWM mode without Fault Protection
• PWM mode with F ault Protection
FIGURE 14-1: OUTPUT COMP ARE x MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Output Compare”
(DS7000 515 7) in th e “dsPIC33F/PIC24H
Family Reference Manual”, which is
available on the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
OCxR
Comparator
Output
Logic
OCM<2:0>
Output Enable
OCx
Set Flag bit
OCxIF
OCxRS
Mode Select
3
01
OCTSEL 01
16
16
OCFA
TMR2 TMR2
QS
R
TMR3 TMR3
Rollover Rollover
Note: An ‘x’ in a signal, register or bit name denotes the number of the output compare channels.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 194 2008-2014 Microchip Technology Inc.
14.1 Output Compare Modes
Configure the Output Compare modes by setting the
appropri ate Output Compare Mod e (OCM<2:0>) bit s in
the Out put C ompare Con trol (O C xCON <2: 0>) regi ste r.
Table 14-1 lists the different bit settings for the Output
Compare modes. Figure 14-2 illustrates the output
compare operation for various modes. The user
application must disable the associated timer when
writing to the Output Compare Control registers to
avoid malfunctions.
TABLE 14-1: OUTPUT COMPARE MODES
FIGURE 14-2: OUTPUT COMPARE OPERATION
Note: Refer to “Output Compare” (DS70209)
in the “dsPIC33F/PIC24H Family
Reference Manual” for OCxR and OCxRS
register res tric tio ns .
OCM<2:0> Mode OCx Pin Initial State OCx Interrupt Generation
111 PWM with Fault Protection ‘0’, if OCxR is zero
‘1’, if OCxR is non-zero OCFA falling edge for OC1 to OC4
110 PWM without Fault Protection ‘0’, if OCxR is zero
‘1’, if OCxR is non-zero No interrupt
101 Continuous Pulse 0OCx falling edge
100 Delayed One-Shot 0OCx fall ing edge
011 Toggle Current output is maintained OCx rising and falling edge
010 Active-High One-Shot 1OCx falling edge
001 Active-Low One-Shot 0OCx rising edge
000 Module Disabled Controlled by GPIO register —
OCxRS
TMRy OCxR
Timer is Reset on
Period Match
Continuous Pulse
(OCM<2:0> = 101)
PWM
(OCM<2:0> = 110 or 111)
Active-Low One-Shot
(OCM<2:0> = 001)
Active-High One-Shot
(OCM<2:0> = 010)
Toggle
(OCM<2:0> = 011)
Delayed One-Shot
(OCM<2:0> = 100)
Output Compare
Mode Enabled
2008-2014 Microchip Technology Inc. DS70000318G-page 195
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2)
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
——OCSIDL — — — — —
bit 15 bit 8
U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0
— — — OCFLT OCTSEL OCM2 OCM1 OCM0
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13 OCSIDL: Stop Output Compare in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
bit 12-5 Unimplemented: Read as ‘0’
bit 4 OCFLT: PWM Fault Condition Status bit
1 = PWM Fault condition has occurred (cleared in hardware only)
0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
bit 3 OCTSEL: Output Compare Timer Select bit
1 = Timer3 is the clock source for Output Compare x
0 = Timer2 is the clock source for Output Compare x
bit 2-0 OCM<2:0>: Output Compar e Mode Select bits
111 = PWM mode on OCx, Fault pin is enabled
110 = PWM mode on OCx, Fault pin is disabled
101 = Initializes OCx pin low, generates continuous output pulses on OCx pin
100 = Initializes OCx pin low, generates single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Init ializes OC x pin high, compare event f orces OCx pin low
001 = Initializes OCx pin low, compare event forces OCx pin high
000 = Output compare channel is disabled
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 196 2008-2014 Microchip Technology Inc.
NOTES:
2008-2014 Microchip Technology Inc. DS70000318G-page 197
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
15.0 HIGH-SPEED PWM
The high-speed PWM module on the
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices supports a wide variety of PWM modes
and output formats. This PWM module is ideal for
power conversion applicatio ns, such as:
• AC/DC Converters
• DC/DC Converters
• Power Fac tor Correction (PFC)
• Uninterruptible Power Supply (UPS)
• Inverters
• Battery Chargers
• Digital Lighting
15.1 Features Overview
The high-speed PWM module incorporates the
following features:
• 2-4 PWM generators with 4-8 outputs
• Individual time ba se and duty cyc le for ea ch of the
eight PWM outp uts
• Dead time for rising and falling edges:
• Duty cycle resolution of 1.04 ns
• Dead-time resolution of 1.04 ns
• Phase-shift resolut ion of 1.04 ns
• Frequency resolution of 1.04 ns
• PWM modes supported:
- Stand ard Edge-Aligned
- True Independent Output
- Complementary
- Center-Aligned
- Push-Pull
- Multiphase
- Variable Phase
- Fixed Off-Time
- Current Reset
- Current-Limit
• Independen t Fault/Current-Lim it inputs for each of
the eight PWM outputs
• Output ov erri de control
• Special Event Trigger
• PWM capture feature
• Prescaler for input clock
• Dual trigger from PWM to ADC
• PWMxH, PWMxL output pin swapping
• PWM4H, PWM4L pins remappable
• On-the-fly PWM frequency, duty cycle and
phase-shift changes
• Disabling o f I ndivi dual PW M gen erators to redu ce
power consumption
• Leading-Edge Blanking (LEB) functionality
Figure 15-1 conceptualizes the PWM module in a
simplified block diagram. Figure 15-2 illustrates how
the module hardware is partitioned for each PWM
output pair for the Complementary PWM mode. Each
functional unit of the PWM module is discussed in
subsequent sections.
The PWM module contains four PWM generators. The
module has up to eight PWM output pins: PWM1H,
PWM1L, PWM2H, PWM2L, PWM3H, PWM3L,
PWM4H and PWM4L. For complementary outputs,
these eight I/O pins are grouped into H/L pairs.
Note 1: This data sheet summarizes the fea-
tures of the dsPIC33FJ06GS101/X02
and dsPIC33FJ16GSX02/X04 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “High- Speed PWM”
(DS70323) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available on the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Duty cycle, dead time, phase shift and
frequency resolution is 8.32 ns in
Center-Aligned PWM mode.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 198 2008-2014 Microchip Technology Inc.
15.2 Feature Description
The PWM module is designed for applications that
require:
• High-resolution at high PWM frequencies
• The ability to drive Standard, Edge-Aligned,
Center- A lig ned Com pl eme ntary mo de, and
Push-Pull mode outputs
• The ability to create multiphase PWM outputs
For Cen ter-Alig ned m ode, th e duty cycle , perio d phase
and dead-time resolutions will be 8.32 ns.
Two common, medium power converter topologies are
push-pull and half-bridge. These designs require the
PWM output signal to be switched between alternate
pins , as pr ovided by the Push-Pull PWM mode.
Phase-shifted PWM describes the situation where
each PWM generator provides outputs, but the phase
relationship between the generator outputs is
specif iable and chang ea ble .
Multiphase PWM is often used to improve DC/DC
Conver ter load transient respons e, and reduce the size
of output filter capacitors and inductors. Multiple DC/
DC Converters are often operated in parallel, but
phase-shifted in time. A single PWM output operating
at 250 kHz has a period of 4 s, but an array of four
PWM channels, staggered by 1 s each, yields an
effective switching frequency of 1 MHz. Multiphase
PWM applications typically use a fixed-phase
relationship.
Variable phase PWM is useful in Zero Voltage
Transition (ZVT) power converters. Here, the PWM
duty cycle is always 50%, and the power flow is
controlled by varying the relative phase shift between
the two PWM generators.
2008-2014 Microchip Technology Inc. DS70000318G-page 199
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 15-1: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF HIGH-S PEED PWM
MUX
Latch
Comparator
Timer
PDC2
Phase
MUX
Latch
Comparator
Timer
PDC3
Phase
MUX
Latch
Comparator
Timer
PDC4
Phase
MUX
Latch
Comparator
Timer
PDC1
PWMCONx
LEBCONx
Channel 1
Dead-Time Generator
PTCON
SEVTCMP
Comparator Special Event
IOCONx
PWM Enable and Mode Control
Channel 3
Dead-Time Generator
Channel 4
Dead-Time Generator
ALTDTRx, DTRx Dead-T ime Control
Special Event
Postscaler
FLTX(1)
PWM3L
PWM3H
PWM2L
PWM2H
1
PWM1L
PWM1H
FCLCONx
Pin and Mode Control
MDC
ADC Trigger Control
Master Duty Cycle Register
Fault Mode and Pin Control
Pin Override Control
Special Event
PTPER
Timer P eri o d
PWM GEN 1
PWM GEN 2
PWM GEN 4
PTMR
Master Time Base
Phase
PWM GEN 3
Channel 2
Dead-Time Generator
PWM4L(1)
PWM4H(1)
PWM User, Current-Limit and Fault Override and Routing Logic
Fault CLMT Override Logic
Trigger
Comparison Value
TRGCONx
Control for Blanking External Input Signals
SYNCO(1)
SYNCIX(1)
Note 1: These pins are remappable.
External Time Base
Synchronization
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 200 2008-2014 Microchip Technology Inc.
FIGURE 15-2: PARTITIONED OUTPUT PAIR, COMPLEMENTARY PWM MODE
15.3 Control Registers
The following registers control the operation of the
high-speed PWM module.
•PTCON: PWM Time Base Control Register
•PTCON2: PWM Clock Divid er Select Register
•PTPER: PWM Master Time Base Register(1)
•SEVTCMP: PWM Sp ec ial Event Compare
Register
•MDC: PWM Master Duty Cycle Register(1,2)
•PWMCONx: PWMx Control Register
•PDCx: PWMx Generator Duty Cycle Register(1,2)
•PHASEx: PWMx Primary Phase-Shift
Register(1,2) (provides the local time base period
for PWMxH)
•DTRx: PWMx Dead-Time Register
•ALTDTRx: PWMx Alternate Dead-Time Register
•SDCx: PWMx Secondary Duty Cycle
Register(1,2)
•SPHASEx: PWMx Secondary Phase-Shift
Register(1,2) (provides the local time base period
for PWMxL)
•TRGCONx: PWMx Trigger Control Register
•IOCONx: PWMx I/O Control Register
•FCLCONx: PWMx Fault Current-Lim it Control
Register
•TRIGx: PWMx Primary Trigger Compare Value
Register
•STRIGx: PWMx Secondary Trigger Compare
Value Register
•LEBCONx: Leading-Edge Blanking Control
Register(1)
•PWMCAPx: Primary PWMx Time Base Capture
Register
PWM Duty Cycle Register
Duty Cycle Comparator
Fault Override Valu es
Channel Override Values
Fault Pin Assignment Logic
Fault Pin
PWMXH
PWMXL
TMR < PDC PWM
Override
Logic
Dead-Time
Logic
Fault Active
Phase Offset
M
U
X
M
U
X
Timer/Counter
2008-2014 Microchip Technology Inc. DS70000318G-page 201
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 15-1: PTCON: PWM TIME BASE CONTROL REGISTER
R/W-0 U-0 R/W-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0
PTEN — PTSIDL SESTAT SEIEN EIPU(1)SYNCPOL(1)SYNCOEN(1)
bit 15 bit 8
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SYNCEN(1)— SYNCSRC1(1)SYNCSRC0(1)SEVTPS3(1)SEVTPS2(1)SEVTPS1(1)SEVTPS0(1)
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PTEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
bit 12 SESTAT: Special Event Interrupt Status bit
1 = Special event interrupt is pending
0 = Special event interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Special event interrupt is enabled
0 = Special event interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit(1)
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWM cycle boundaries
bit 9 SYNCPOL: Synchronization Input/Output Polarity bit(1)
1 = SYNCIx and SYN CO polarity is inve rted (act ive-low)
0 = SYNCIx and SYNCO are active-high
bit 8 SYNCOEN: Primary Time Base Sync Enable bit(1)
1 = SYNCO output is enabled
0 = SYNCO output is disabled
bit 7 SYNCEN: External Time Base Synchronization Enable bit(1)
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5-4 SYNCSRC<1:0>: Synchronous Source Selection bits(1)
11 = Reserved
10 = Reserved
01 = SYNCI2
00 = SYNCI1
Note 1: These bits should be cha nged onl y when PTEN = 0. In additi on, when us ing the SYNCIx feat ure, the us er
applic ation m ust pro gram th e Period regist er with a value th at is s lightl y larg er than t he exp ected p eriod o f
the external synchronization input signal.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 202 2008-2014 Microchip Technology Inc.
bit 3-0 SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits(1)
1111 = 1:16 Postscaler generates a S pecial Event Trigger trigger on every sixteenth compare match event
•
•
•
0001 = 1:2 Postscaler generates a Special Event Trigger on every second compare match event
0000 = 1:1 Postscaler generates a Special Event Trigger on every compare match event
REGISTER 15-1: PTCON: PWM TIME BASE CONTROL REGISTER (CONTINUED)
Note 1: These bits should be cha nged onl y when PTEN = 0. In additi on, when us ing the SYNCIx feat ure, the us er
applic ation m ust pro gram th e Period regist er with a val ue that i s slightl y larg er than t he exp ected p eriod o f
the external synchronization input signal.
2008-2014 Microchip Technology Inc. DS70000318G-page 203
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 15-2: PTCON2: PWM CLOCK DIVIDER SELECT REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — —PCLKDIV<2:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
110 = Divide-by-64, maximum PW M timing resolution
101 = Divide-by-32, maximum PW M timing resolution
100 = Divide-by-16, maximum PW M timing resolution
011 = Divide-by-8, maximum PWM timing resolution
010 = Divide-by-4, maximum PWM timing resolution
001 = Divide-by-2, maximum PWM timing resolution
000 = Divide-by-1, maximum PWM timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
REGISTER 15-3: PTPER: PWM MASTER TIME BASE REGISTER(1)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
PTPER <15:8>
bit 15 bit 8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
PTPER <7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PTPER<15:0>: PWM Master Time Base ( PMTMR) P eriod Value bits
Note 1: The minimum value that can be loaded into the PTPER register is 0x0010 and the maximum value is
0xFFF8.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 204 2008-2014 Microchip Technology Inc.
REGISTER 15-4: SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP <15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
SEVTCMP <7:3> — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 SEVTCMP<12:0>: Special Event Compare Count Value bits
bit 2-0 Unimplemented: Read as ‘0’
REGISTER 15-5: MDC: PWM MASTER DUTY CYCLE REGISTER(1,2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 MDC<15:0>: Master PWM Duty Cycle Value bits
Note 1: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009,
while the maximum pulse width generated corresponds to a value of Period – 0x0008.
2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of
operation), the PWM duty cycle resolution will degrade from 1 LSB to 3 LSBs.
2008-2014 Microchip Technology Inc. DS70000318G-page 205
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER
HS/HC-0 HS/HC-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTSTAT(1)CLSTAT(1)TRGSTAT FLTIEN CLIEN TRGIEN ITB(3)MDCS(3)
bit 15 bit 8
R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
DTC1 DTC0 — — —CAM
(2,3)XPRES(4)IUE
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FLTSTAT: Fault Interrupt Status bit(1)
1 = Fault interrupt is pending
0 = No Fault interrupt is pending; this bit is cleared by setting FLTIEN = 0
bit 14 CLSTAT: Current-Limit Interrupt Status bit(1)
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending; this bit is cleared by setting CLIEN = 0
bit 13 TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending; this bit is cleared by setting TRGIEN = 0
bit 12 FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and the FLTSTAT bit is cleared
bit 11 CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt is enabled
0 = Current-limit interrupt is disabled and the CLSTAT bit is cleared
bit 10 TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrup t requ est
0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared
bit 9 ITB: Independent Time Base Mode bit(3)
1 = PHASEx/SPHASEx register provides time base period for this PWM generator
0 = PTPER register provides timing for this PWM generator
bit 8 MDCS: Master Duty Cycle Register Select bit(3)
1 = MDC register provides duty cycle information for this PWM generator
0 = PDCx/SDCx register provides duty cycle information for this PWM generator
bit 7-6 DTC<1:0>: Dead-Time Co ntrol bi ts
11 = Reserved
10 = Dead-time function is disabled
01 = Negative dead time is actively applied for all output modes
00 = Positive dead time is actively applied for all output modes
bit 5-3 Unimplemented: Read as ‘0’
Note 1: Software must clear the interrupt status here and the corresponding IFSx bit in the interrupt controller.
2: The Indepen de nt T ime Base mode (ITB = 1) must be ena ble d to use C ent er-Al ign ed mo de. If ITB = 0, the
CAM bit is ignored.
3: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
4: To opera te in Externa l Peri od R e se t mo de, configure FC LCO Nx<C L MO D> = 0 a nd PW MCONx<ITB> = 1.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 206 2008-2014 Microchip Technology Inc.
bit 2 CAM: Center-Aligned Mode Enable bit(2,3)
1 = Center-Aligned mode is enabled
0 = Center-Aligned mode is disabled
bit 1 XPRES: External PWM Reset Control bit(4)
1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time
Base (I T B) m ode
0 = External pins do not affect PWM time base
bit 0 IUE: Immediate Update Enable bit
1 = Updates to the active MDC/PDCx/SDCx registers are immediate
0 = Updates to the active MDC/PDCx/SDCx registers are synchronized to the PWM time base
REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER (CONTINUED)
Note 1: Software must clear the interrupt status here and the corresponding IFSx bit in the interrupt controller.
2: The Indepen de nt T ime Base mode (ITB = 1) must be enabled t o u se Cent er-Al ign ed mode. If ITB = 0, the
CAM bit is ignored.
3: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
4: To opera te in Externa l Peri od Re se t mo de, config ure FC LCO N x<CL MO D> = 0 a nd PW MCONx<ITB> = 1.
2008-2014 Microchip Technology Inc. DS70000318G-page 207
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 15-7: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER(1,2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PDCx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PDCx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PDCx<15:0>: PWM Generator # Duty Cycle Value bits
Note 1: In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In Complementary,
Redun dant a nd Pu sh-Pull PW M mo des, the PDC x registe r con trols the d uty cy cle o f bot h the PWMx H and
PWMxL. The smallest pulse width that can be generated on the PWM output corresponds to a value of
0x0009, while the maximum pulse width generated corresponds to a value of Period-0x0008.
2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of
operation), the PWM duty cycle resolution will degrade from 1 LSB to 3 LSBs.
REGISTER 15-8: SDCx: PWMx SECONDARY DUTY CYCLE REGISTER(1,2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SDCx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SDCx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SDCx<15:0>: Secondary Duty Cycle for PWMxL Output Pin bits
Note 1: The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the
SDCx register controls the PWMxL duty cycle. The smallest pulse width that can be generated on the
PWM output co rres pon ds to a value o f 0 x0 009 , w h ile th e m ax im um p uls e w id t h generate d correspon ds to
a value of Period-0x0 008.
2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of
operation), the PWM duty cycle resolution will degrade from 1 LSB to 3 LSBs.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 208 2008-2014 Microchip Technology Inc.
REGISTER 15-9: PHASEx: PWMx PRIMARY PHASE- SHI FT REGISTER(1,2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHASEx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHASEx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PHASEx<15:0>: PWM Phase-Shift Value or Independent Time Base Period for this PWM Generator bits
Note 1: If PWMCONx<ITB> = 0, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or 10);
PHASEx<15:0> = Phase-shift value for PWMxH and PWMxL outputs
• True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11);
PHASEx<15:0> = Phase-shift val ue for PWMxL only
2: If PWMCONx<ITB> = 1, the following applies based on the mode of operation:
• Complementary, Redundant, and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or
10); PHASEx<15:0> = Independent Time Base period value for PWMxH and PWMxL
• True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11); PHASEx<15:0> = Independent
Time Base period value for PWMxL only
• The smal les t p uls e w i d th tha t can be g ene rate d on th e PWM ou tpu t corres po nds to a value of 0x00 08 ,
while the maximum pulse width generated corresponds to a value of Period – 0x0008.
2008-2014 Microchip Technology Inc. DS70000318G-page 209
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 15-10: SPHASEx: PWMx SECONDARY PHASE-SHIFT REGISTER(1,2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SPHASEx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SPHASEx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SPHASEx<15:0>: Secondary Phase Offset for PWMxL Output Pin bits
(used in Independent PWM mode only)
Note 1: If PWMCONx<ITB> = 0, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01
or 10); SPHASEx<15:0> = Not used
• True Independent Output mode (IOCONx<PMOD> = 11);
PHASEx<15:0> = Phase-shift value for PWMxL only
2: If PWMCONx<ITB> = 1, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (IOCONx<PMOD> = 00, 01, or 10);
SPHASEx<15:0> = Not used
• True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11);
PHASEx<15:0> = Independent Time Base period value for PWMxL only
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 210 2008-2014 Microchip Technology Inc.
.
REGISTER 15-1 1: DTRx: PWMx DEAD-TIME REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——DTRx<13:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DTRx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-0 DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
REGISTER 15-12: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— ALTDTRx<13:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ALTDTR <7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 4 Unimplemented: Read as ‘0’
bit 13-0 ALTDTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
2008-2014 Microchip Technology Inc. DS70000318G-page 211
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 15-13: TRGCONx: PWMx TRIGGER CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — —
bit 15 bit 8
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DTM(1)— TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 2 TRGDIV<3:0>: Trigger # Output Divider bits
1111 = Trig ger o utput for every 16th trigger event
1110 = Trig ger o utput for every 15th trigger event
1101 = Trig ger o utput for every 14th trigger event
1100 = Trig ger o utput for every 13th trigger event
1011 = Trig ger o utput for every 12th trigger event
1010 = Trigger output for every 11th trigger event
1001 = Trig ger o utput for every 10th trigger event
1000 = Trigger output for every 9th trigger event
0111 = Trigger output for every 8th trigger event
0110 = Trigger output for every 7th trigger event
0101 = Trigger output for every 6th trigger event
0100 = Trigger output for every 5th trigger event
0011 = Trigger output for every 4th trigger event
0010 = Trigger output for every 3rd trigger event
0001 = Trigger output for every 2nd trigger event
0000 = Trigger output for every trigger event
bit 11-8 Unimplemented: Read as ‘0’
bit 7 DTM: Dual Trigger Mode bit(1)
1 = Secondary trigger event is combined with the primary trigger event to create the PWM trigger.
0 = Secondary trigger eve nt is not combin ed with t he primary trigger ev ent to creat e the PWM trigge r;
two separate PWM triggers are generated
bit 6 Unimplemented: Read as ‘0’
bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits
111111 = Wait 63 PWM cycles before generating the first trigger event after the module is enabled
•
•
•
000010 = Wait 1 PWM cycles before generating the first trigger event after the module is enabled
000001 = Wait 1 PWM cycle before generating the first trigger event after the module is enabled
000000 = Wait 0 PWM cycles before generating the first trigger event after the module is enabled
Note 1: The secon dary genera tor ca nno t genera t e PWM trig ger inte rrup t s.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 212 2008-2014 Microchip Technology Inc.
REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PENH PENL POLH POLL PMOD1(1)PMOD0(1)OVRENH OVRENL
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OVRDAT1 OVRDAT0 FLTDAT1(2)FLTDAT0(2)CLDAT1(2)CLDAT0(2)SWAP OSYNC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PENH: PWMH Output Pin Ownership bit
1 = PWM module controls the PWMxH pin
0 = GPIO module controls the PWMxH pin
bit 14 PENL: PWML Output Pin Ownership bit
1 = PWM module controls the PWMxL p in
0 = GPIO module controls the PWMxL pin
bit 13 POLH: PWMH Output Pin Polarity bit
1 = PWMxH pin is active-low
0 = PWMxH pin is active-high
bit 12 POLL: PWML Output Pin Polarity bit
1 = PWMxL pin is active-low
0 = PWMxL pin is active-high
bit 11-10 PMOD<1:0>: PWM # I/O Pin Mode bits(1)
11 = PWM I/O pin pair is in the True Independent Output mode
10 = PWM I/O pin pair is in the Push-Pull Output mode
01 = PWM I/O pin pair is in the Redundant Output mode
00 = PWM I/O pin pair is in the Complementary Output mode
bit 9 OVRENH: Override Enable for PWMxH Pin bit
1 = OVRDAT<1> provides data for output on the PWMxH pin
0 = PWM generator provides data for the PWMxH pin
bit 8 OVRENL: Over ride Enab le for PWMxL Pin b it
1 = OVRDAT<0> provides data for output on the PWMxL pin
0 = PWM generator provides data for the PWMxL pin
bit 7-6 OVRDAT<1:0>: Data for PWMxH and PWMxL Pins if Override is Enabled bits
If OVERENH = 1, then OVRDAT<1> provides data for PWMxH
If OVERENL = 1, then OVRDAT<0> provides data for PWMxL
bit 5-4 FLTDAT<1:0>: State for PWMxH and PWMxL Pins if FLTMOD is Enabled bits(2)
FCLCONx<IFLTMOD> = 0: Normal Fault mode:
If Fault is active, then FLTDAT<1> provides the state for PWMxH
If Fault is active, then FLTDAT<0> provides the state for PWMxL
FCLCONx<IFLTMOD> = 1: Independent Fault mode:
If current-limit is active, then FLTDAT<1> provides data for PWMxH
If Fault is active, then FLTDAT<0> provides the state for PWMxL
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
2: The state represents the active/inactive state of the PWM module depending on the POLH and POLL bit
settings.
2008-2014 Microchip Technology Inc. DS70000318G-page 213
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
bit 3-2 CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMODE is Enabled bits(2)
FCLCONx<IFLTMOD> = 0: Normal Fault mode:
If current-limit is active, then CLDAT<1> provides the state for PWMxH
If current-limit is active, then CLDAT<0> provides the state for PWMxL
FCLCONx<IFLTMOD> = 1: Independent Fault mode:
CLDAT<1:0> bits are ignored.
bit 1 SWAP<1:0>: Swap PWMxH and PWMxL pins
1 = PWMxH outpu t si gn al i s c on nec ted to the PWMx L p in a nd the PWMxL signal is co nne ct ed to the
PWMxH pins
0 = PWMxH and PWMxL pins are mapped to their respective pins
bit 0 OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base
0 = Output overrides via the OVDDAT<1:0> bits occur on the next CPU clock boundary
REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER (CONTINUED)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
2: The state represents the active/inactive state of the PWM module depending on the POLH and POLL bit
settings.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 214 2008-2014 Microchip Technology Inc.
REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFLTMOD CLSRC4(2,3)CLSRC3(2,3)CLSRC2(2,3)CLSRC1(2,3)CLSRC0(2,3)CLPOL(1)CLMOD
bit 15 bi t 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTSRC4(2,3)FLTSRC3(2,3)FLTSRC2(2,3)FLTSRC1(2,3)FLTSRC0(2,3)FLTPOL(1)FLTMOD1 FLTMOD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 IFLTMOD: Independent Fault Mode Enable bit
1 = Independ ent Fault m ode: Current-l imit inpu t maps FLTDAT1 to PWM xH output a nd the Fau lt input
maps FLTDAT0 to the PWMxL output. The CLDAT<1:0> bits are not used for override functions.
0 = Normal Fault mode: Current-limit feature maps CLDAT<1:0> bits to the PWMxH and PWMxL
outputs. The PWM Fault feature maps FLTDAT<1:0> to the PWMxH and PWMxL outputs.
bit 14-10 CLSRC<4:0>: Current-Limit Control Signal Source Select for PWM # Generator bits(2,3)
11111 = Reserved
•
•
•
01000 = Reserved
00111 = Fault 8
00110 = Fault 7
00101 = Fault 6
00100 = Fault 5
00011 = Fault 4
00010 = Fault 3
00001 = Fault 2
00000 = Fault 1
bit 9 CLPOL: Current-Limit Polarity for PWM Generator # bit(1)
1 = The selected current-limit source is active-low
0 = The selected current-limit source is active-high
bit 8 CLMOD: Current-Limit Mode Enable bit for PWM Generator # bit
1 = Current-limit function is enabled
0 = Current-limit function is disabled
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
2: When Independent Fault mode is enabled (IFLTMOD = 1), and Fault 1 is used for Current-Limit mode
(CLSRC<4:0> = b0000), the Fault Control Sourc e Sele ct bits (FLTSR C<4:0 >) sho ul d be se t to an unused
Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs.
3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode
(FLTSRC<4: 0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an
unused current-limit source to prevent the current-limit source from disabling both the PWMxH and
PWMxL output s .
2008-2014 Microchip Technology Inc. DS70000318G-page 215
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select for PWM Generator # bits(2,3)
11111 = Reserved
•
•
•
01000 = Reserved
00111 = Fault 8
00110 = Fault 7
00101 = Fault 6
00100 = Fault 5
00011 = Fault 4
00010 = Fault 3
00001 = Fault 2
00000 = Fault 1
bit 2 FLTPOL: Fault Polarity for PWM Generator # bit(1)
1 = The selected Fault source is active-low
0 = The selected Fault source is active-high
bit 1-0 FLTMOD<1:0>: Fault Mode for PWM Generator # bits
11 = Fault input is disabled
10 = Reserved
01 = The selected Fault source forces the PWMxH and PWMxL pins to FLTDAT values (cycle)
00 = The selected Fault source forces the PWMxH and PWMxL pins to FL TDAT values (latched condition)
REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
2: When Independent Fault mode is enabled (IFLTMOD = 1), and Fault 1 is used for Current-Limit mode
(CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused
Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs.
3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode
(FLTSRC<4: 0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an
unused current-limit source to prevent the current-limit source from disabling both the PWMxH and
PWMxL output s .
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DS70000318G-page 216 2008-2014 Microchip Technology Inc.
REGISTER 15-16: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TRGCMP<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
TRGCMP<7:3> — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 TRGCMP<15:3>: Trigger Control Value bits
When primary PWM functions in the local time base, this register contains the compare values that can
trigger the ADC modul e.
bit 2-0 Unimplemented: Read as ‘0’
REGISTER 15-17: STRIGx: PWMx SECONDARY TRIGGER COMPARE VALUE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STRGCMP<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
STRGCMP<7:3> — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 STRGCMP<15:3>: Secondary Trigger Control Value bits
When seco ndary PWM func tions in the local time b ase, this regis ter cont ain s the c omp are v alues that
can trigger the ADC module.
bit 2-0 Unimplemented: Read as ‘0’
2008-2014 Microchip Technology Inc. DS70000318G-page 217
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 15-18: LEBCONx: LEADING-EDGE BLANKING CONTROL REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB6 LEB5
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
LEB4 LEB3 LEB2 LEB1 LEB0 — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PHR: PWMxH Rising Edge Trigger Enable bit
1 = Rising edge of PWMxH will trigger the LEB counter
0 = LEB ignores the rising edge of PWMxH
bit 14 PHF: PWMH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger the LEB counter
0 = LEB ignores the falling edge of PWMxH
bit 13 PLR: PWML Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger the LEB counter
0 = LEB ignores the rising edge of PWMxL
bit 12 PLF: PWML Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger the LEB counter
0 = LEB ignores the falling edge of PWMxL
bit 11 FLTLEBEN: Fault Input LEB Enable bit
1 = Leading-Ed ge Bl anking is a pplied to selected Fault input
0 = Leading-Ed ge Bl anking is not applie d to selected Fa ult input
bit 10 CLLEBEN: Current-Limit LEB Enable bit
1 = Leading-Edge Blanking is applied to selected current-limit input
0 = Leading-Edge Blanking is not applied to selected current-limit input
bit 9-3 LEB<6:0>: Leading-Edge Blanking for Current-Limit and Fault Inputs bits
The value is 8.32 nsec increments.
bit 2-0 Unimplemented: Read as ‘0’
Note 1: Configure this register in word format.
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DS70000318G-page 218 2008-2014 Microchip Technology Inc.
REGISTER 15-19: PWMC APx : PRIM ARY PW Mx TIME BASE CAPTURE REGIST ER
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
PWMCAP<15:8>(1,2)
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 U-0 U-0 U-0
PWMCAP<7:3>(1,2)— — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 PWMCAP<15:3>: Captured PWM Time Base Value bits(1,2)
The value in this register represents the captured PWM time base value when a leading edge is
detected on the current-limit input.
bit 2-0 Unimplemented: Read as ‘0’
Note 1: The capture feature is only available on the primary output (PWMxH).
2: This feature is active only after LEB processing on the current-limit input signal is complete.
2008-2014 Microchip Technology Inc. DS70000318G-page 219
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
16.0 SERIAL PERIPHERAL
INTERFACE (SPI) The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices can be serial EEPROMs, shift
registers, display drivers, Analog-to-Digital Converters
and so on. The SPI module is compatible with SPI and
SIOP fro m Moto ro la®.
The SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1), used for shif ting dat a in and out,
and a buffer register, SPIxBUF. A control register,
SPIxCON , configures the module. Add itionally, a statu s
register, SPIxSTAT, indicates status conditions.
The serial interface consists of the following four pins:
• SDIx (Serial Data Input)
• SDOx (Serial Data Output)
• SCKx (Shift Clock Input Or Output)
• SSx (Active-Low Slave Select).
In Master mode operation, SCK is a clock output; in
Slave mo de, it is a clock inp ut.
FIGURE 16-1: SPIx MO DULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the featur es
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Serial Peripheral
Interface (SPI)” (DS70206) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available on the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data she et for device-specific regis ter
and bit information.
Inte rn al Da ta B u s
SDIx
SDOx
SSx
SCKx
SPIxSR
bit 0
Shift Control
Edge
Select
FCY
Primary
1:1/4/16/64
Enable
Prescaler
Sync
SPIxBUF
Control
Transfer
Transfer
Write SPIxBUF
Read SPIxBUF
16
SPIxCON1<1:0>
SPIxCON1<4:2>
Master Clock
Clock
Control
Secondary
Prescaler
1:1 to 1:8
SPIxRXB SPIxTXB
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 220 2008-2014 Microchip Technology Inc.
REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
SPIEN — SPISIDL — — — — —
bit 15 bit 8
U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0
— SPIROV — — — — SPITBF SPIRBF
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 SPIEN: SPIx Enable bit
1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables module
bit 14 Unimplemented: Read as ‘0’
bit 13 SPISIDL: SPIx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 SPIROV: SPIx Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded. The user software has not read the
previous data in the SPIxBUF register.
0 = No overflow has occurred
bit 5-2 Unimplemented: Read as ‘0’
bit 1 SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit not yet started, SPIxTXB is full
0 = T ransmit star ted, SPIxTXB is empty . Automatically set in hardware when CPU writes the SPIxBUF
location, loading SPIxTXB. Automatically cleared in hardware when the SPIx module transfers
data from SPIxTXB to SPIxSR.
bit 0 SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive complete, SPIxRXB is full
0 = Recei ve is not com ple te, SPIxR XB is empt y. Au toma tica lly set i n hard war e when SPI x tran sfe rs
data fr om SPIxSR to SPIxRXB. Automa tically cl eared in hardware when core reads the SPIx BUF
location, reading SPIxRXB.
2008-2014 Microchip Technology Inc. DS70000318G-page 221
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 16-2: SPIXCON1: SPIx CONTROL RE GISTER 1
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DISSCK DISSDO MODE16 SMP CKE(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEN(3)CKP MSTEN SPRE2(2)SPRE1(2)SPRE0(2)PPRE1(2)PPRE0(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 3 Unimplemented: Read as ‘0’
bit 12 DISSCK: Disable SCKx Pin bit (SPI Master modes only)
1 = Internal SPI clock is disabled; pin functions as I/O
0 = Internal SPI clock is enabled
bit 11 DISSDO: Disable SDOx Pin bit
1 = SDOx pin is not used by module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10 MODE16: Word/By te Commu nic ati on Sele ct bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9 SMP: SPIx Data Input Sample Phase bit
Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8 CKE: SPIx Clock Edge Select bit(1)
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
bit 7 SSEN: Slave Select Enable bit (Slave mode)(3)
1 = SSx pin is used f or Slave mode
0 = SSx pin is not used by module; pin controlled by port function
bit 6 CKP: Clock Polarity Select bit
1 = Idle stat e for clock is a high l evel; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI mod es
(FRMEN = 1).
2: Do not set both primary and secondary prescalers to a value of 1:1.
3: This bit must be cleared when FRMEN = 1.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 222 2008-2014 Microchip Technology Inc.
bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(2)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
•
•
•
000 = Secondary prescale 8:1
bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(2)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
2: Do not set both primary and secondary prescalers to a value of 1:1.
3: This bit must be cleared when FRMEN = 1.
2008-2014 Microchip Technology Inc. DS70000318G-page 223
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
FRMEN SPIFSD FRMPOL — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
— — — — — — FRMDLY —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FRMEN: Framed SPIx Support bit
1 = Framed SPIx support is enabled (SSx pin used as frame sync pulse input/output)
0 = Framed SPIx support is disabled
bit 14 SPIFSD: SPIx Frame Sync Pulse Direction Control bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
bit 13 FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame sync pulse is active-high
0 = Frame sync pu lse is active- low
bit 12-2 Unimplemented: Read as ‘0’
bit 1 FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
bit 0 Unimplemented: This bit must not be set to ‘1’ by the user appl ication
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 224 2008-2014 Microchip Technology Inc.
NOTES:
2008-2014 Microchip Technology Inc. DS70000318G-page 225
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
17.0 INTER-INTEGRATED CIRCUIT
(I2C™)
The Inter-Integrated Circuit (I2C) module provides
complete hardware support for both Slave and
Multi-Master modes of the I2C serial communication
standard with a 16-bit interface.
The I2C module has a 2-pin interface, where:
• The SCLx pin is clock
• The SDAx pin is data
The I2C module offers the following key features:
•I
2C interface supporting both Master and Slave
modes of opera tion
•I
2C Slave mode suppo rts 7-bit a nd 10-b it addr essin g
•I
2C Master mode supports 7-bit and 10-bit
addressing
•I
2C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for I2C port can be used
as a han dshake mecha nism to sus pend and resum e
serial transfer (SCLREL con trol )
•I
2C supports multi-master operation, detects bus
collision and arbitrates accordingly
17.1 Operating Modes
The hardw are fully im plements all the maste r and slave
functions of the I2C Standard and Fast mode
specifications, as well as 7-bit and 10-bit addressing.
The I2C module can operate either as a slave or a
master on an I2C bus.
The following types of I2C operation are supported:
•I
2C slave operation with 7-bit addressing
•I
2C slave operation with 10-bit addressing
•I
2C master operation with 7-bit or 10-bit addressing
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this
data sheet, refer to “Inter-Integrated
Circuit (I2C™)” (DS70000195) in the
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available on the Microchip
web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 226 2008-2014 Microchip Technology Inc.
FIGURE 17-1: I2Cx BLOCK DIAGRAM (X = 1)
Internal
Data Bus
SCLx
SDAx
Shift
Match Detect
I2CxADD
Start and Stop
Bit Detect
Clock
Address Match
Clock
Stretching
I2CxTRN LSb
Shift Clock
BRG Down Counter
Reload
Control
TCY/2
Start and Stop
Bit Generation
Acknowledge
Generation
Collision
Detect
I2CxCON
I2CxSTAT
Control Logic
Read
LSb
Write
Read
I2CxBRG
I2CxRSR
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
I2CxMSK
I2CxRCV
2008-2014 Microchip Technology Inc. DS70000318G-page 227
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
17.2 I2C Registers
I2CxCON and I2CxSTAT are control and status
registers. The I2CxCON register is readable and
writable. The lower six bits of I2CxSTAT are read-only.
The remaining bits of the I2CxSTAT are read/write:
• I2CxRSR is the shift register used for shifting data
internal to the module and the user application
has no acces s to it
• I2CxRCV is the receive buffer and the register to
which data bytes are written, or from which data
byt es are read
• I2CxTRN is the transmit register to which bytes
are written during a transmit operation
• The I2CxADD register holds the slave address
• A status bit, ADD10, indicates 10-Bit Addressing
mode
• The I2CxBRG acts as the Baud Rate Generator
(BRG) reload value
In receive o perations, I2CxRSR an d I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 228 2008-2014 Microchip Technology Inc.
REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0
I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend: U = Unimplemented bit, read as ‘0’
R = Readable bit W = Writable bit HC = Hardware Clearable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module, and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module; all I2C™ pins are controlled by port functions.
bit 14 Unimplemented: Read as ‘0’
bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode
0 = Continues module operation in Idle mode
bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stre tch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear
at beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1 = IPMI mode is enabled; all addresses are Acknowledged
0 = IPMI mode is disabled
bit 10 A10M: 10-Bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2C xADD is a 7 -bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8 SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with SMBus specification
0 = Disables SMBus input thresholds
bit 7 GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enables inte rrup t wh en a g ene ral call address is receive d in th e I2C x RS R (m od ule i s en abled fo r
reception)
0 = General call address is disabled
bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1 = Enables software or receive clock stretching
0 = Disabl es software or receiv e clock str etching
2008-2014 Microchip Technology Inc. DS70000318G-page 229
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applica ble during mast er receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit.
Hardware is clear at end of master Acknowledge sequence.
0 = Acknowledge sequence is not in progress
bit 3 RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables R ece ive m od e fo r I2C. Hard w are i s cle ar a t en d o f ei ghth bit of ma ste r rec ei ve data byte.
0 = Receive sequence is not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I2C maste r )
1 = Initiates Stop con dition on SDAx and SCLx pins. Hardware is clear at end of master S top sequence.
0 = Stop condition is not in progress
bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware is clear at end of master
Repeated Start sequence.
0 = R epeated Start condition is not in prog ress
bit 0 SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at end of master Start
sequence.
0 = Start condition is not in progress
REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 230 2008-2014 Microchip Technology Inc.
REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER
R-0, HS C R-0, HSC U-0 U-0 U- 0 R/C-0, HSC R-0, HS C R-0, HSC
ACKSTAT TRSTAT — — — BCL GCSTAT ADD10
bit 15 bit 8
R/C-0 , HS R/C-0 , HS R-0 , HS C R/C-0, HS C R/C-0, HSC R-0, HS C R-0, HS C R-0 , HSC
IWCOL I2COV D_A P S R_W RBF TBF
bit 7 bit 0
Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
HS = Hardware Settable bit
bit 15 ACKSTAT: Acknowledge Status bit
(when operating as I2C™ master, applicable to master transmit operation)
1 = NACK received from slave
0 = ACK received from slave
Hardware is set or clear at end of slave Acknowledge.
bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware is set at beginning of master transmission. Hardware is clear at end of slave Acknowledge.
bit 13-11 Unimplemented: Read as ‘0’
bit 10 BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware is set at detection of bus collision.
bit 9 GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware is set when address matches general call address. Hardware is clear at Stop detection.
bit 8 ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware is set at match of 2nd byte of matched 10-bit address. Hardware is clear at Stop detection.
bit 7 IWCOL: I2Cx Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware is set at occurrence of write to I2CxTRN while busy (cleared by software).
bit 6 I2COV: I2Cx Receive Overflow Flag bit
1 = A byte was received while the I 2CxRC V registe r is st ill holding the previous byte
0 = No overflow
Hardware is set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5 D_A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was a device address
Hardware is clear at device address match. Hardware is set by reception of slave byte.
2008-2014 Microchip Technology Inc. DS70000318G-page 231
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware is se t or clear w hen Start, Repeated Start or Stop is de tected.
bit 3 S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware is se t or clear w hen Start, Repeated Start or Stop is de tected.
bit 2 R_W: Read/Write Information bit (when operating as I2C slave)
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
Hardware is set or clear after reception of an I2C device address byte.
bit 1 RBF: Receive Buffer Full Status bit
1 = Receive is complete, I2CxRCV is full
0 = Receive is not complete, I2CxRCV is empty
Hardware is set when I2CxRCV is written with a received byte. Hardware is clear when software rea ds
I2CxRCV.
bit 0 TBF: Transmit Buffer Full Status bit
1 = Transmit is in progress, I2CxTRN is full
0 = Transmit is complete, I2CxTRN is empty
Hardware is set wh en software writes to I2CxTRN. Hardware is clear at completion of dat a transmission.
REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 232 2008-2014 Microchip Technology Inc.
REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — AMSK<9:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AMSK<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 0 Unimplemented: Read as ‘0’
bit 9-0 AMSK<9:0>: Mask for Address bit x Select bits
1 = Enables masking for bit x of incoming message address; bit match is not required in this position
0 = Disables masking for bit x; bit match is required in this position
2008-2014 Microchip Technology Inc. DS70000318G-page 233
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
18.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRAN SMITTER
(UART)
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 device families. The UART
is a full-du plex, asyn chronous system that ca n commu-
nicate with peripheral devices, such as personal
comput ers, LIN/J26 02, RS-23 2 and RS-4 85 interfa ces.
The module also supports a hardware flow control
option with the UxCTS and UxRTS pins and also
includ es an IrD A® encoder and decoder.
The primary features of the UART module are:
• Full-Duplex, 8-Bit or 9-Bit Data Transmission
through the UxTX and UxRX Pins
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Con trol Option with UxCTS and
UxRTS Pins
• Fully Integrated Baud Rate Generator with 16-Bit
Prescaler
• Baud Rates Ranging from 12.5 Mbps to 38 bps at
50 MIPS
• 4-Deep First-In First-Out (FIFO) Transmit Data
Buffer
• 4-D eep FIFO Receive Data Buffer
• Parity, Framing and Buf fer Overrun Error Detection
• Support for 9-Bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive Interrupts
• A Separate Interrupt for all UAR T Error Conditi ons
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Support for Automatic Baud Rate Detection
• IrDA Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA® Support
A simplified block diagram of the UART module is
shown in Figure 1. The UAR T module con sists of thes e
key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 1: UART1 SIM PLIFIED BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “UART” (DS70188) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available on the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
U1RX
Hardware Flow Control
UART Receiver
UART Transmitte r U1TX
Baud Rate Gene rator
U1RTS/BCLK1
IrDA®
U1CTS
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 234 2008-2014 Microchip Technology Inc.
REGISTER 18-1: UxMODE: UARTx MODE REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
UARTEN(1)— USIDL IREN(2)RTSMD —UEN1UEN0
bit 15 bit 8
R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 UARTEN: UARTx Enable bit(1)
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by port latches, UARTx power consumption
is minimal
bit 14 Unimplemented: Read as ‘0’
bit 13 USIDL: UARTx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = C ontinues m odule operation in Idle mode
bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11 RTSMD: Mode Selection for UxRTS Pin bit
1 =UxRTS pin is in Simplex mode
0 =UxRTS
pin is in Flow Control mode
bit 10 Unimplemented: Read as ‘0’
bit 9-8 UEN<1:0>: UARTx Enable bits
11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin is controlled by port latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins are controlled by
port latches
bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx w ill c ont inu e to s amp le the U xRX pin; in terru pt is gen era t ed on fal lin g e dge , bi t is cleared
in hardware on the following rising edge
0 = No wake-up is enabled
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Enables Loopback mode
0 = Loopback mode is disabled
bit 5 ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0 = Baud rate measurement is disabled or has completed
Note 1: Refer to “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on
enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
2008-2014 Microchip Technology Inc. DS70000318G-page 235
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
bit 4 URXINV: UARTx Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3 BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
Note 1: Refer to “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on
enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 236 2008-2014 Microchip Technology Inc.
REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1
UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1)UTXBF TRMT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0
URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA
bit 7 bit 0
Legend: HC = Hardware Clearable bit C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
bit 14 UTXINV: UARTx Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IREN = 1:
1 =IrDA
® encoded UxTX Idle state is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 12 Unimplemented: Read as ‘0’
bit 11 UTXBRK: UARTx Transmit Break bit
1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop
bit; cleared by ha rdware upon comp letion
0 = Sync Break transmission is disabled or has completed
bit 10 UTXEN: UARTx Transmi t Enable bit (1)
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and buffer is reset; UxTX pin is
controlled by port
bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full; at least one more character can be written
bit 8 TRMT: Transmit Shift Register Empty bit (read-only)
1 = Trans mit Shift Regi ster is empty and transmit buf fer is empty (the last transm ission has com pleted)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6 URXISEL<1:0>: UARTx Receive Interru pt Mo de Sele cti on bits
11 = Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on Ux RSR tran sfer, making the rece ive bu ff er 3/4 ful l (i.e., h as 3 da ta c harac ters)
0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer; receive buffer has one or more characters
Note 1: Refer to “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on
enabling the UART module for transmit operation.
2008-2014 Microchip Technology Inc. DS70000318G-page 237
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enable; if 9-bit mode is not selected, this does not take effect
0 = Address Detect mode is disabled
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = R eceiver is Idle
0 = R eceiver is active
bit 3 PERR: Parity Error Status bit (read-only)
1 = Parity error has been de tected for the c urrent charac ter (cha racter a t the to p of the receive F IFO)
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive
FIFO)
0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Recei ve buffer has overflowed
0 = Receive buf fer has not ove rflowed; clearin g a previously set OERR bit ( 10 transition) will reset
the receiver buffer and the UxRSR to the empty state
bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = R eceive buffer is empty
REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
Note 1: Refer to “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on
enabling the UART module for transmit operation.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 238 2008-2014 Microchip Technology Inc.
NOTES:
2008-2014 Microchip Technology Inc. DS70000318G-page 239
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
19.0 HIGH-SPEED 10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
dsPIC33FJ06GS101/X02 and dsPIC 33FJ16GSX02/X 04
devices provide high-speed, successive approximation
Analog-to-Digital conversions to support applications,
such as AC/DC and DC/DC power converters.
19.1 Features Overview
The ADC module comprises the following features:
• 10-bit resolution
• Unipolar inputs
• Up to two Su ccessive A pproximation Regist ers
(SARs)
• Up to 12 external input channels
• Up to two internal analog inputs
• Dedicated result register for each analog input
• ±1 LSB accuracy at 3.3V
• Single supply operation
• 4 Msps conversion r ate at 3.3V (devices with
two SARs)
• 2 Msps conversion r ate at 3.3V (devices with
one SAR)
• Low-power CMOS technology
19.2 Module Description
This ADC module is designed for applications that require
low latency b etween the request f or conversion and t he
resultant output data. Typical applications include:
• AC/DC power supplies
• DC/DC Converters
• Power Fac tor Correction (PFC)
This ADC works with the high-speed PWM module in
power control applications that require high-frequency
control lo ops. This mod ule can sample and conv ert two
analog i nputs in a 0.5 microse cond when two SARs are
used. This small conversion delay reduces the “phase
lag” between measurement and control system
response.
Up to five inputs may be sampled at a time (four inputs
from the dedicated Sample-and-Hold circuits and one
from the shared Sample-and-Hold circuit). If multiple
input s request con version, the ADC will convert them in
a sequential manner, starting with the lowest order
input.
This ADC design provides each pair of analog inputs
(AN1, AN0), (AN3 , AN2),..., the a bility to spe cify its o wn
trigger source out of a maximum of sixteen different
trigger sources. This capability allows this ADC to
sample and convert analog inputs that are associated
with PWM generators operating on Independent Time
Bases (ITBs).
The user application typically requires synchronization
between analog data sampling and PWM output to the
application circuit. The very high-speed operation of
this ADC module allows “data on demand”.
In addition, several hardware features have been
added to the peripheral interface to improve real-time
performance in a typical DSP-based application.
• Result alignment options
• Automated sampling
• External conversion start control
• T wo internal i nputs to moni tor the INTREF int ernal
reference and the EXTREF input signal
19.3 Module Functionality
The high-speed, 10-bit ADC module is designed to
support p ower con versio n a pplicatio ns w hen us ed with
the high-speed PWM m od ule. The ADC ma y h av e on e
or two SAR modules, d epe ndi ng o n th e device va rian t.
If two SARs are present on a device, two conversions
can be processed at a ti me, yieldi ng 4 Msp s conversio n
rate. If only one SAR is present on a device, only one
conversion can be processed at a time, yielding 2 Msps
conversion rate. The high-speed 10-bit ADC produces
two 10-bit conversion results in a 0.5 microsecond.
The ADC module supports up to 12 external analog
inputs and two internal analog inputs. To monitor
reference voltage, two internal input s, AN12 and AN13,
are connected to the EXTREF and INTREF voltages,
respectively.
The analog reference voltage is defined as the device
supply voltage (AVDD/AVSS).
Block diagrams of the ADC module are shown in
Figure 19-1 through Figure 19-6.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a compre-
hensive re ference source. To complement
the information in this data sheet, refer to
“High-Speed 10-Bit Analog-to-Digital
Converter (ADC)” (DS70000321) in the
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available on the Microchip
web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 240 2008-2014 Microchip Technology Inc.
FIGURE 19-1: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS101 DEVICES WITH ONE SAR
Even Numbered Inputs with Dedicated
Shared Sample-and-Hold
Data
Format
SAR
Core
Six
Registers
16-Bit
Sample-and-Hold (S&H) Circuits
Bus Interface
AN0
AN1
AN3
AN6
AN7
AN2
2008-2014 Microchip Technology Inc. DS70000318G-page 241
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 19-2: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS102 DEVICES WITH ONE SAR
Even Numbered Inputs with Dedicated
Shared Sample-and-Hold
Data
Format
SAR
Core
Six
Registers
16-Bit
Sample-and-H old (S&H) Circuits
Bus Interface
AN0
AN2
AN1
AN4
AN5
AN3
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 242 2008-2014 Microchip Technology Inc.
FIGURE 19-3: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS202 DEVICES WITH ONE SAR
AN12(1)
AN13(2)
Even Numbered Inputs with Dedicated
Shared Sample-and-Hold
Data
Format
SAR
Core
Eight
Registers
16-Bit
Sample-and-Hold (S&H) Circuits
Bus Interface
AN0
AN2
AN1
AN4
AN5
AN3
(INTREF)
(EXTREF)
Note 1: AN12 (EXTREF) is an internal analog input. To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled
and EXTREF must be selected as the comparator reference.
2: AN13 (INTREF) is an internal analog input and i s not available on a pin.
2008-2014 Microchip Technology Inc. DS70000318G-page 243
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 19 - 4: ADC BLOCK D IAGRA M FO R dsPI C3 3F J16GS40 2/4 04 DEVIC ES WITH ONE SAR
Even Numbered Inputs with Dedicated
Shared Sample-and-Hold
Data
Format
SAR
Core
Eight
Registers
16-bit
Sample-and-Hold (S&H) Circuits
Bus Interface
AN0
AN2
AN1
AN5
AN6
AN7
AN3
AN4
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 244 2008-2014 Microchip Technology Inc.
FIGURE 19-5: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS502 DEVICES WITH TWO SARS
AN12(1)
AN13(2)
Even Numbered Inputs with Dedicated
Odd Numbered Inputs
with Shared S&H
Even Numbered Inputs
with Shared S&H
Data
Format
SAR
Core
Five
Registers
16-Bit
SAR
Core
Sample-and-Hold (S&H ) Circuits
Bus Interfac e
AN0
AN2
AN6
AN1
AN3
Data
Format
Five
Registers
16-Bit
AN4
AN5
AN7
(INTREF)
(EXTREF)
Note 1: AN12 (EXTREF) is an internal analog input. To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled
and EXTREF must be selected as the comparator reference.
2: AN13 (INTREF) is an internal analog input and is not available on a pin.
2008-2014 Microchip Technology Inc. DS70000318G-page 245
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 19-6: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS504 DEVICES WITH TWO SARS
AN12(1)
AN13(2)
Even Numbered Inputs with Dedicated
Odd Numbered Inputs
with Shared S&H
Even Numbered Inputs
with Shared S&H
Data
Format
SAR
Core
Seven
Registers
16-Bit
SAR
Core
Sample-and-Hold (S&H) Circuits
Bus Interface
AN0
AN2
AN6
AN1
AN3
AN8
AN10
Data
Format
Seven
Registers
16-Bit
AN4
AN5
AN7
AN9
AN11
(INTREF)
(EXTREF)
Note 1: AN12 (EXTREF) is an internal analog input. To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled
and EXTREF must be selected as the comparator reference.
2: AN13 (INTREF) is an internal analog input and is not available on a pin.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 246 2008-2014 Microchip Technology Inc.
19.4 ADC Control Registers
The ADC modul e uses the followi ng contro l and status
registers:
•ADCON: Analog-to-Digital Control Register
•ADSTAT: Analog-to-Digit al Status Registe r
•ADBASE: Analog-to-Digital Base Register(1,2)
•ADPCFG: Analog-to-Digital Port Configuration
Register
•ADCPC0: Analog-to-Digital Convert Pair Control
Register 0
•ADCPC1: Analog-to-Digital Convert Pair Control
Register 1
•ADCPC2: Analog-to-Digital Convert Pair Control
Regist er 2(1)
•ADCPC3: Analog-to-Digital Convert Pair Control
Register 3(1)
The ADCON register controls the operation of the
ADC module. The ADSTAT register displays the
status of the conversion processes. The ADPCFG
registers configure the port pins as analog inputs or
as digital I/O. The ADCPCx registers control the
triggering of the ADC conversions. See Register 19-1
through Register 19-8 for detailed bit configurations.
Note: A unique feature of the ADC module is its
ability to sample input s in an asynchronous
manner. Individual Sample-and-Hold
circuits can be triggered independently of
each other.
2008-2014 Microchip Technology Inc. DS70000318G-page 247
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 19-1: ADCON: ANALOG-TO-DIGITAL CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0
ADON — ADSIDL SLOWCLK(1)—GSWTRG—FORM
(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-1 R/W-1
EIE(1)ORDER(1,2)SEQSAMP(1,2)ASYNCSAMP(1)— ADCS2(1)ADCS1(1)ADCS0(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADON: Analog-to-Digital Operating Mode bit
1 = Analog-to-Digital Converter (ADC) module is operating
0 = ADC Converter is off
bit 14 Unimplemented: Read as ‘0’
bit 13 ADSIDL: ADC Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 SLOWCLK: Enable The Slow Clock Divider bit(1)
1 = ADC is clocked by the auxiliary PLL (ACLK)
0 = ADC is clock by the primary PLL (FVCO)
bit 11 Unimplemented: Read as ‘0’
bit 10 GSWTRG: Global Software Trigger bit
When this bit is set by the user, it will trigger conversions if selected by the TRGSRC<4:0> bits in the
ADCPCx regi ste rs. Thi s b it m us t be cl ea red b y t he u se r pri or to initia tin g an oth er gl ob al t r igg er (i .e., thi s
bit is not auto-clearing).
bit 9 Unimplemented: Read as ‘0’
bit 8 FORM: Data Output Format bit(1)
1 = Fractional (DOUT = dddd dddd dd00 0000)
0 = Integer (DOUT = 0000 00dd dddd dddd)
bit 7 EIE: Early Interrupt Enable bit(1)
1 = Interrupt is generated after first conversion is completed
0 = Interrupt is generated after second conversion is completed
bit 6 ORDER: Conversion Order bit(1,2)
1 = Odd numbered analog input is converted first, followed by conversion of even numbered input
0 = Even numbered analog input is converted first, followed by conversion of odd numbered input
bit 5 SEQSAMP: Sequential Sample Enable bit(1,2)
1 = Shared Sample-and-Hold (S&H) circuit is sampled at the start of the second conversion if
ORDER = 0. If ORDER = 1, then the shared S&H is sampled at the start of the first conversion.
0 = Shar ed S&H is sampl ed at th e same t ime the de dicat ed S&H is sampl ed if th e shar ed S&H is not
currently busy with an existing conversion process. If the shared S&H is busy at the time the
dedicat ed S&H is sampled, then the shared S&H will sample at th e start of the new con version cycle.
Note 1: These control bits can only be changed while ADC is disabled (ADON = 0).
2: These bits are only available on devices with one SAR.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 248 2008-2014 Microchip Technology Inc.
bit 4 ASYNCSAMP: Asynchronous Dedicated S&H Sampling Enable bit(1)
1 = The dedicated S&H is constantly sampling and then terminates sampling as soon as the trigger
pulse is detected
0 = The dedicated S&H star ts sampling w hen the trig ger even t is detect ed and comple tes the sa mplin g
process in two ADC clock cycles
bit 3 Unimplemented: Read as ‘0’
bit 2-0 ADCS<2:0>: Analog-to-Digital Conversion Clock Divider Select bits(1)
111 = FADC/8
110 = FADC/7
101 = FADC/6
100 = FADC/5
011 = FADC/4 (default)
010 = FADC/3
001 = FADC/2
000 = FADC/1
REGISTER 19-1: ADCON: ANALOG-TO-DIGITAL CONTROL REGISTER (CONTINUED)
Note 1: These control bits can only be changed while ADC is disabled (ADON = 0).
2: These bits are only available on devices with one SAR.
2008-2014 Microchip Technology Inc. DS70000318G-page 249
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 19-2: ADSTAT: ANALOG-TO-DIGITAL STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/C-0, HS R/C-0, HS R/C-0, HS R/C- 0, HS R/C-0, HS R/C-0, HS R/C-0, HS
— P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY P0RDY
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6 P6RDY: Conversion Data for Pair 6 Rea dy bit
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 5 P5RDY: Conversion Data for Pair 5 Rea dy bit
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 4 P4RDY: Conversion Data for Pair 4 Rea dy bit
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 3 P3RDY: Conversion Data for Pair 3 Rea dy bit
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 2 P2RDY: Conversion Data for Pair 2 Rea dy bit
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 1 P1RDY: Conversion Data for Pair 1 Rea dy bit
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 0 P0RDY: Conversion Data for Pair 0 Rea dy bit
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 250 2008-2014 Microchip Technology Inc.
REGISTER 19-3: ADBASE: ANALOG-TO-DIGITAL BASE REGISTER(1,2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADBASE<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
ADBASE<7:1> —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 ADBASE<15:1>: Analog-to-Digital Base bits
This register contains the base address of the user’s ADC Interrupt Service Routine jump table. This
register, when read , contains the su m of the ADBASE reg ist er conte nts and the enc od ed v alu e of the
PxRDY status bits.
The encoder logic provides the bit number of the highest priority PxRDY bits, where P0RDY is the
highest priority and P6RDY is the lowest priority.
bit 0 Unimplemented: Read as ‘0’
Note 1: The encoding results are shifted left two bits, so bits 1-0 of the result are always zero.
2: As an alternative to usi ng the ADBASE regis ter, the ADCP0-6 ADC Pair Conversion Complete interrup t s
can be used to invoke A to D conversion completion routines for individual ADC input pairs.
REGISTER 19-4: ADPCFG: ANALOG-TO-DIGITAL PORT CONFIGURATION REGISTER
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — —PCFG<11:8>
(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG<7:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 2 Unimplemented: Read as ‘0’
bit 11-0 PCFG<11:0>: Analog-to-Digital Port Configuration Control bits(1)
1 = Port pin in Digital mode; port read input is enabled, Analog-to-Digital input multiplexer is
connected to AVSS
0 = Port pin in Analog mode; port read input is disabled, Analog-to-Digital samples the pin voltage
Note 1: Not all PCFGx bits are available on all devices. See Figure 19-1 through Figure 19-6 for the available
analog pins (PCFGx = ANx, where x = 0-11).
2008-2014 Microchip Technology Inc. DS70000318G-page 251
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 19-5: ADCPC0: ANALOG-TO-DIGITAL CONVERT PAIR
CONTROL REGISTER 0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 IRQEN1: Inte rrupt Re quest Enable 1 bit
1 = Enables IRQ generation when requested conversion of Channels AN3 and AN2 is completed
0 = IRQ is not generated
bit 14 PEND1: Pending Conversion Status 1 bit
1 = Conversion of Channels AN3 and AN2 is pending; set when selected trigger is asserted
0 = Conver sion is complete
bit 13 SWTRG1: Software Trigger 1 bit
1 = Starts conversion of AN3 and AN2 (if selected by the TRGSRCx bits)(1)
This bit is automatically cleared by hardware when the PEND1 bit is set.
0 = C onver s ion has no t started
Note 1: The trigger source must be set as a global softw are trigger prior to setting this bit to ‘1’. If other conversion s
are in progress, then the conversion will be performed when the conversion resources are available.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 252 2008-2014 Microchip Technology Inc.
bit 12-8 TRGSRC1<4:0>: Trigger 1 Source Selection bits
Selects trigger source for conversion of Analog Channels AN3 and AN2.
11111 = Timer2 period match
•
•
•
11011 = Reserved
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = Reserved
•
•
•
10010 = Reserved
10001 = PWM Generator 4 secondary trigger is selected
10000 = PWM Generator 3 secondary trigger is selected
01111 = PWM Generator 2 secondary trigger is selected
01110 = PWM Generator 1 secondary trigger is selected
01101 = Reserved
01100 = Timer1 period match
•
•
•
01000 = Reserved
00111 = PWM Generator 4 primary trigger is selected
00110 = PWM Generator 3 primary trigger is selected
00101 = PWM Generator 2 primary trigger is selected
00100 = PWM Generator 1 primary trigger is selected
00011 = PWM Special Event Trigger is selected
00010 = Global software trigger is se lected
00001 = Individual software trigger is selected
00000 = No conversion is enabled
bit 7 IRQEN0: Interrupt Request Enable 0 bi t
1 = Enables IRQ generation when requested conversion of Channels AN1 and AN0 is completed
0 = IRQ is not generated
bit 6 PEND0: Pending Conversion Status 0 bit
1 = Conversion of Channels AN1 and AN0 is pending; set when selected trigger is asserted
0 = Conver sion is complete
bit 5 SWTRG0: Software Trigger 0 bit
1 = Starts conversion of AN1 and AN0 (if selected by the TRGSRCx bits)(1)
This bit is automatically cleared by hardware when the PEND0 bit is set.
0 = C onver s ion has not started
REGISTER 19-5: ADCPC0: ANALOG-TO-DIGITAL CONVERT PAIR
CONTROL REGISTER 0 (CONTINUED)
Note 1: The trigger source must be set as a global softw are trigger prior to setting this bit to ‘1’. If other conversion s
are in progress, then the conversion will be performed when the conversion resources are available.
2008-2014 Microchip Technology Inc. DS70000318G-page 253
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
bit 4-0 TRGSRC0<4:0>: Trigger 0 Source Selection bits
Selects trigger source for conversion of Analog Channels AN1 and AN0.
11111 = Timer2 period match
•
•
•
11011 = Reserved
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = Reserved
•
•
•
10010 = Reserved
10001 = PWM Generator 4 secondary trigger is selected
10000 = PWM Generator 3 secondary trigger is selected
01111 = PWM Generator 2 secondary trigger is selected
01110 = PWM Generator 1 secondary trigger is selected
01101 = Reserved
01100 = Timer1 period match
•
•
•
01000 = Reserved
00111 = PWM Generator 4 primary trigger is selected
00110 = PWM Generator 3 primary trigger is selected
00101 = PWM Generator 2 primary trigger is selected
00100 = PWM Generator 1 primary trigger is selected
00011 = PWM Special Event Trigger is selected
00010 = Global software trigger is se lected
00001 = Individual software trigger is selected
00000 = No conversion is enabled
REGISTER 19-5: ADCPC0: ANALOG-TO-DIGITAL CONVERT PAIR
CONTROL REGISTER 0 (CONTINUED)
Note 1: The trigger source must be set as a global softw are trigger prior to setting this bit to ‘1’. If other conversion s
are in progress, then the conversion will be performed when the conversion resources are available.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 254 2008-2014 Microchip Technology Inc.
REGISTER 19-6: ADCPC1: ANALOG-TO-DIGITAL CONVERT PAIR
CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN3(1)PEND3(1)SWTRG3(1)TRGSRC34(1)TRGSRC33(1)TRGSRC32(1)TRGSRC31(1)TRGSRC30(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN2(2)PEND2(2)SWTRG2(2)TRGSRC24(2)TRGSRC23(2)TRGSRC22(2)TRGSRC21(2)TRGSRC20(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 IRQEN3: Interrupt Request Enable 3 bit(1)
1 = Enables IRQ generation when requested conversion of Channels AN7 and AN6 is completed
0 = IRQ is not generated
bit 14 PEND3: Pending Conversion Status 3 bit(1)
1 = Conversion of Channels AN7 and AN6 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 13 SWTRG3: Software Trigger 3 bit(1)
1 = Starts conversion of AN7 and AN6 (if selected by the TRGSRCx bits)(3)
This bit is automatically cleared by hardware when the PEND3 bit is set.
0 = Con version has not started
Note 1: These bits are available in the dsPIC33FJ16GS402/404, dsPIC33FJ16GS504, dsPIC33FJ16GS502 and
dsPIC33FJ06GS101 devices only.
2: These bits are available in the dsPIC33FJ16GS502, dsPIC33FJ16GS504, dsPIC33FJ06GS102,
dsPIC33FJ06GS202 and dsPIC33FJ16GS402/404 devices only.
3: The trigg er source m ust be set as a glo bal so ft ware trig ger prior t o settin g this bit to ‘ 1’. If oth er convers ions
are in progress, then the conversion will be performed when the conversion resources are available.
2008-2014 Microchip Technology Inc. DS70000318G-page 255
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
bit 12-8 TRGSRC3<4:0>: Trigger 3 Source Selection bits(1)
Selects trigger source for conversion of Analog Channels AN7 and AN6.
11111 = Timer2 period match
•
•
•
11011 = Reserved
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = Reserved
•
•
•
10010 = Reserved
10001 = PWM Generator 4 secondary trigger is selected
10000 = PWM Generator 3 secondary trigger is selected
01111 = PWM Generator 2 secondary trigger is selected
01110 = PWM Generator 1 secondary trigger is selected
01101 = Reserved
01100 = Timer1 period match
•
•
•
01000 = Reserved
00111 = PWM Generat or 4 primar y trig ger is se lec ted
00110 = PWM Generat or 3 primar y trig ger is se lec ted
00101 = PWM Generat or 2 primar y trig ger is se lec ted
00100 = PWM Generat or 1 primar y trig ger is se lec ted
00011 = PWM Special Event Trigger is selected
00010 = Global softwar e trigger is sele cted
00001 = Individual software trigger is selected
00000 = No conversion is enabled
bit 7 IRQEN2: Interrupt Request Enable 2 bit((2))
1 = Enables IRQ generation when requested conversion of Channels AN5 and AN4 is completed
0 = IRQ is not generated
bit 6 PEND2: Pending Conversion Status 2 bit((2))
1 = Conversion of Channels AN5 and AN4 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 5 SWTRG2: Software Trigger 2 bit((2))
1 = Starts conversion of AN5 and AN4 (if selected by the TRGSRCx bits)(3)
This bit is automatically cleared by hardware when the PEND2 bit is set.
0 = Con version has not started
REGISTER 19-6: ADCPC1: ANALOG-TO-DIGITAL CONVERT PAIR
CONTROL REGISTER 1 (CONTINUED)
Note 1: These bits are available in the dsPIC33FJ16GS402/404, dsPIC33FJ16GS504, dsPIC33FJ16GS502 and
dsPIC33FJ06GS101 devices only.
2: These bits are available in the dsPIC33FJ16GS502, dsPIC33FJ16GS504, dsPIC33FJ06GS102,
dsPIC33FJ06GS202 and dsPIC33FJ16GS402/404 devices only.
3: The trigg er source m ust be set as a glo bal so ft ware trig ger prior t o settin g this bit to ‘ 1’. If oth er convers ions
are in progress, then the conversion will be performed when the conversion resources are available.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 256 2008-2014 Microchip Technology Inc.
bit 4-0 TRGSRC2<4:0>: Trigger 2 Source Selection bits(2)
Selects trigger source for conversion of Analog Channels AN5 and AN4.
11111 = Timer2 period match
•
•
•
11011 = Reserved
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = Reserved
•
•
•
10010 = Reserved
10001 = PWM Generator 4 secondary trigger is selected
10000 = PWM Generator 3 secondary trigger is selected
01111 = PWM Generator 2 secondary trigger is selected
01110 = PWM Generator 1 secondary trigger is selected
01101 = Reserved
01100 = Timer1 period match
•
•
•
01000 = Reserved
00111 = PWM Generator 4 primary trigger is selected
00110 = PWM Generator 3 primary trigger is selected
00101 = PWM Generator 2 primary trigger is selected
00100 = PWM Generator 1 primary trigger is selected
00011 = PWM Special Event Trigger is selected
00010 = Global software trigger is se lecte d
00001 = Individual software trigger is selected
00000 = No conversion is enabled
REGISTER 19-6: ADCPC1: ANALOG-TO-DIGITAL CONVERT PAIR
CONTROL REGISTER 1 (CONTINUED)
Note 1: These bits are available in the dsPIC33FJ16GS402/404, dsPIC33FJ16GS504, dsPIC33FJ16GS502 and
dsPIC33FJ06GS101 devices only.
2: These bits are available in the dsPIC33FJ16GS502, dsPIC33FJ16GS504, dsPIC33FJ06GS102,
dsPIC33FJ06GS202 and dsPIC33FJ16GS402/404 devices only.
3: The trigg er source m ust be set as a glo bal so ft ware trig ger prior t o settin g this bit to ‘ 1’. If oth er convers ions
are in progress, then the conversion will be performed when the conversion resources are available.
2008-2014 Microchip Technology Inc. DS70000318G-page 257
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 19-7: ADCPC2: ANALOG-TO-DIGITAL CONVERT PAIR
CONTROL REGISTER 2(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN5 PEND5 SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN4 PEND4 SWTRG4 TRGSRC44 TRGSRC43 TRGSRC42 TRGSRC41 TRGSRC40
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 IRQEN5: Inte rrupt Re quest Enable 5 bit
1 = Enables IRQ generation when requested conversion of Channels AN11 and AN10 is completed
0 = IRQ is not generated
bit 14 PEND5: Pending Conversion Status 5 bit
1 = Conversion of Channels AN11 and AN10 is pending; set when selected trigger is asserted
0 = Conver sion is complete
bit 13 SWTRG5: Software Trigger 5 bit
1 = Starts conversion of AN11 and AN10 (if selected by the TRGSRCx bits )(2)
This bit is automatically cleared by hardware when the PEND5 bit is set.
0 = C onver s ion has not started
Note 1: This register is only implemented in the dsPIC33FJ16GS504 devices.
2: The trigger source must be set as a gl obal software trigger prior to setting this bit to ‘1’. If other conversion s
are in progress, then the conversion will be performed when the conversion resources are available.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 258 2008-2014 Microchip Technology Inc.
bit 12-8 TRGSRC5<4:0>: Trigger 5 Source Selection bits
Selects trigger source for conversion of Analog Channels AN11 and AN10.
11111 = Timer2 period match
•
•
•
11011 = Reserved
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = Reserved
•
•
•
10010 = Reserved
10001 = PWM Generator 4 secondary trigger is selected
10000 = PWM Generator 3 secondary trigger is selected
01111 = PWM Generator 2 secondary trigger is selected
01110 = PWM Generator 1 secondary trigger is selected
01101 = Reserved
01100 = Timer1 period match
•
•
•
01000 = Reserved
00111 = PWM Generat or 4 prim ary trig ger is se lec ted
00110 = PWM Generat or 3 prim ary trig ger is se lec ted
00101 = PWM Generat or 2 prim ary trig ger is se lec ted
00100 = PWM Generat or 1 prim ary trig ger is se lec ted
00011 = PWM Special Event Trigger is selected
00010 = Global software trigger is se lected
00001 = Individual software trigger is selected
00000 = No conversion is enabled
bit 7 IRQEN4: Interrupt Request Enable 4 bi t
1 = Enables IRQ generation when requested conversion of Channels AN9 and AN8 is completed
0 = IRQ is not generated
bit 6 PEND4: Pending Conversion Status 4 bit
1 = Conversion of Channels AN9 and AN8 is pending; set when selected trigger is asserted
0 = Conver sion is complete
bit 5 SWTRG4: Software Trigger 4 bit
1 = Starts conversion of AN9 and AN8 (if selected by the TRGSRCx bits)(2)
This bit is automatically cleared by hardware when the PEND4 bit is set.
0 = C onver s ion has not started
REGISTER 19-7: ADCPC2: ANALOG-TO-DIGITAL CONVERT PAIR
CONTROL REGISTER 2(1) (C O NT I N U ED )
Note 1: This register is only implemented in the dsPIC33FJ16GS504 devices.
2: The trigger source must be set as a gl obal software trigger prior to setting this bit to ‘1’. If other conversion s
are in progress, then the conversion will be performed when the conversion resources are available.
2008-2014 Microchip Technology Inc. DS70000318G-page 259
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
bit 4-0 TRGSRC4<4:0>: Trigger 4 Source Selection bits
Selects trigger source for conversion of Analog Channels AN9 and AN8.
11111 = Timer2 period match
•
•
•
11011 = Reserved
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = Reserved
•
•
•
10010 = Reserved
10001 = PWM Generator 4 secondary trigger is selected
10000 = PWM Generator 3 secondary trigger is selected
01111 = PWM Generator 2 secondary trigger is selected
01110 = PWM Generator 1 secondary trigger is selected
01101 = Reserved
01100 = Timer1 period match
•
•
•
01000 = Reserved
00111 = PWM Genera tor 4 prima r y trig ger is se lec ted
00110 = PWM Genera tor 3 prima r y trig ger is se lec ted
00101 = PWM Genera tor 2 prima r y trig ger is se lec ted
00100 = PWM Genera tor 1 prima r y trig ger is se lec ted
00011 = PWM Special Event Trigger is selected
00010 = Global software trigger is se lected
00001 = Individual software trigger is selected
00000 = No conversion is enabled
REGISTER 19-7: ADCPC2: ANALOG-TO-DIGITAL CONVERT PAIR
CONTROL REGISTER 2(1) (C O NT I N U ED )
Note 1: This register is only implemented in the dsPIC33FJ16GS504 devices.
2: The trigger source must be set as a gl obal software trigger prior to setting this bit to ‘1’. If other conversion s
are in progress, then the conversion will be performed when the conversion resources are available.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 260 2008-2014 Microchip Technology Inc.
REGISTER 19-8: ADCPC3: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 3(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN6 PEND6 SWTRG6 TRGSRC6<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7 IRQEN6: Interrupt Request Enable 6 bi t
1 = Enables IRQ generation when requested conversion of Channels AN13 and AN12 is completed
0 = IRQ is not generated
bit 6 PEND6: Pending Conversion Status 6 bit
1 = Conversion of Channels AN13 and AN 12 is pending; set when selected trigger is asserted
0 = Conver sion is complete
bit 5 SWTRG6: Software Trigger 6 bit
1 = Starts conversion of AN13 (INTREF) and AN12 (EXTREF) (if selected by the TRGSRCx bits)(2)
This bit is automatically cleared by hardware when the PEND6 bit is set.
0 = C onver s ion has no t started
Note 1: This register is only implemented on the dsPIC33FJ16GS502 and dsPIC33FJ16GS504 devices.
2: The trigge r sou rce must be set as glo bal software trigger prior to se ttin g thi s bi t to ‘1’ . If oth er co nv ers ion s
are in progress , conversion will be performed when the co nversion resou rces a re available.
2008-2014 Microchip Technology Inc. DS70000318G-page 261
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
bit 4-0 TRGSRC6<4:0>: Trigger 6 Source Selection bits
Selects trigger source for conversion of Analog Channels AN13 and AN12.
11111 = Timer2 period match
•
•
•
11011 = Reserved
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = Reserved
•
•
•
10010 = Reserved
10001 = PWM Generator 4 secondary trigger is selected
10000 = PWM Generator 3 secondary trigger is selected
01111 = PWM Generator 2 secondary trigger is selected
01110 = PWM Generator 1 secondary trigger is selected
01101 = Reserved
01100 = Timer1 period match
•
•
•
01000 = Reserved
00111 = PWM Generator 4 primary trigger is selected
00110 = PWM Generator 3 primary trigger is selected
00101 = PWM Generator 2 primary trigger is selected
00100 = PWM Generator 1 primary trigger is selected
00011 = PWM Special Event Trigger is selected
00010 = Global software trigger is se lected
00001 = Individual software trigger is selected
00000 = No conversion is enabled
REGISTER 19-8: ADCPC3: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 3(1)
Note 1: This register is only implemented on the dsPIC33FJ16GS502 and dsPIC33FJ16GS504 devices.
2: The trigge r sou rce must be set as glo bal software trigger prior to se ttin g thi s bi t to ‘1’ . If oth er co nv ersi on s
are in progress , conversion will be performed when the co nversion resou rces a re available.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 262 2008-2014 Microchip Technology Inc.
NOTES:
2008-2014 Microchip Technology Inc. DS70000318G-page 263
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
20.0 HIGH-SPEED ANALOG
COMPARATOR
The dsPIC33F SMPS comparator module monitors
current and/or voltage transients that may be too fast
for the CPU and ADC to capture.
20.1 Features Overview
The SMPS comparator module contains the following
major features:
• 16 selectable comparator inputs
• Up to four analog comparators
• 10-bit DAC for each analog comparator
• Programmable output polarity
• Interrupt generation capability
• DACOUT pin to provide DAC output
• DAC has three ranges of operation:
-AV
DD/2
- Internal Re fere nc e (INTR EF)
- External Refere nc e (EXTR EF)
• ADC sample and convert trigger capability
• Disable capability reduces power consumption
• Functional support for PWM module:
- PWM duty cycle control
- PW M period control
- PWM Fault detect
20.2 Module Description
Figure 20-1 shows a functional block diagram of one
analog comparator from the SMPS comparator
module. The analog comparator provides high-speed
operat ion wit h a typ ical delay of 20 n s. The co mp arator
has a typical offset voltage of ±5 mV. The negative
input of the comparator is always connected to the
DAC circuit. The positive input of the comparator is
connected to an analog multiplexer that selects the
desired source pin.
The analog comparator input pins are typically shared
with pins used by t he Analog-to-Digital Conv erter (AD C)
module. Both the comparator and the ADC can use the
same pins at the same time. This capability enables a
user to measure an input voltage with the ADC and
detect voltage transients with the comparator.
FIGURE 20-1: HIGH-SPEED ANALOG COMPARATOR MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the
features of the dsPIC33FJ06GS101/X02
and dsPIC33FJ16GSX02/X04 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “High-Speed Analog
Comparator” (DS70296) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available on the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
CMPxA
(1)
CMPxC
(1)
DAC
CMPPOL
0
1
AV
DD
/2
INTREF
(2)
M
U
X
M
U
X
CMREF
CMPx
(1)
INSEL<1:0>
10
ACMPx (Trigger to PWM)(1)
Interrup t Reque st
CMPxB
(1)
CMPxD
(1)
EXTREF(2)
Status
AVSS
RANGE
DACOUT
DACOE
Note 1: x = 1, 2, 3 and 4.
2: For the INTREF and EXTREF values, refer to the DAC Module Specific ations (Table 24-43) in Section 24.0
“Electrical Characteristics”.
Glitch Filter Pulse
Generator
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 264 2008-2014 Microchip Technology Inc.
20.3 Module Applications
This module provides a means for the SMPS dsPIC®
DSC devices to monitor voltage and currents in a
power conversion application. The ability to detect
transient conditions and stimulate the dsPIC DSC
processor and/or peripherals, without requiring the
processor and ADC to constantly monitor voltages or
currents, frees the dsPIC DSC to perform other tasks.
The comparator module has a high-speed comparator
and an associated 10-bit DAC that provides a
programmable reference voltage to the inverting input
of the comparator. The polarity of the comparator out-
put is user-programmable. The output of the module
can be used in the following modes:
• Generate an Interrupt
• Trigger an ADC Sample and Convert Process
• Truncate the PWM Signal (current limit)
• Tru nc ate the PWM Period (current minimum)
• Disable the PWM Outputs (Fault latch)
The output of the comparator module may be used in
multiple modes at the same time, such as: 1) generate
an interrupt, 2) have the ADC take a sample and con-
vert it, and 3) truncate the PWM output in response to
a voltage being detected beyond its expected value.
The comparator module can also be used to wake-up
the system from Sleep or Idle mode when the analog
input voltage exceeds the programmed threshold
voltage.
20.4 DAC
The range of the DAC is controlled through an analog
multiplexer that selects either AVDD/2, an internal ref-
erence source, INTREF, or an external reference
source, EXTREF. The full range of the DAC (AVDD/2)
will ty pically be u sed w hen the c hosen input s ource pi n
is shared with the ADC. The reduced range option
(INTREF) will likely be used when monitoring current
levels using a current sense resistor. Usually, the
measured voltages in such applications are small
(<1.25V); therefore the option of using a reduced ref-
erence range for the comparator extends the available
DAC resolution in these applications. The use of an
external reference enables the user to connect to a
reference that better suits their application.
DACOUT, shown in Figure 20-1, can only be
associated with a single comparator at a given time.
20.5 Interaction with I/O Buffers
If the comparator module is enabled and a pin has
been selected as the source for the comparator, then
the chos en I/O p ad must dis ab le th e d igi tal inp ut b uf fer
associated with the pad to prevent excessive currents
in the digital buffer due to analog input voltages.
20.6 Digital Logic
The CMPCONx register (see Register 20-1) provides
the control logic that configures the comparator
module. The digital logic provides a glitch filter for the
comparator output to mask transient signals in less
than two instruction cycles. In Sleep or Idle mode, the
glitch filter is bypassed to enable an asynchronous
path from the comparator to the interrupt controller.
This asynchronous path can be used to wake-up the
proce ssor from Sleep or Idle mo de.
The comparator can be disabled while in Idle mode if
the CMPSIDL bit is set. If a device has multiple
comparators, if any CMPSIDL bit is set, then the entire
group of comparators will be disabled while in Idle
mode. This behavior reduces complexity in the design
of the clock control logic for this module.
The digital logic also provides a one TCY width pulse
generator for triggering the ADC and generating
interrupt requ es ts.
The CMPDACx (see Register 20-2) register provides
the digital input value to the reference DAC.
If the modu le i s di sa ble d, the DAC and c om p ar ator are
disabled to reduce power consumption.
20.7 Comparator Input Range
The comparator has a limitation for the input
Common-Mode Ran ge (CMR) of (AVDD – 1.5V) , typical.
This means that both inputs should not exceed this
range. As long as one of the inputs is within the
Common-Mode Range, the comparator output will be
correct. However, any input exceeding the CMR
limitation will cause the comparator input to be saturated.
If both inputs exceed the CMR, the comparator output
will be indeterminate.
20.8 DAC Output Range
The DAC has a limitation for the maximum reference
voltage input of (AVDD – 1.6) volts. An external
reference vo lta ge inpu t shoul d not ex ceed t his va lue or
the reference DAC output will become indeterminate.
20.9 Comparator Registers
The comparator module is controlled by the following
registers:
•CMPCONx: Comparator Control x Regis ter
•CMPDACx: Com parator DAC x Control Register
Note: It should be ensured in software that
multiple DACOE bits are not set. The
output on the DACOUT pin will be indeter-
minate if multiple comparators enable the
DAC output.
2008-2014 Microchip Technology Inc. DS70000318G-page 265
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
REGISTER 20-1: CMPCONx: COMPARATOR CONTROL x REGISTER
R/W-0 U-0 R/W-0 r-0 r-0 r-0 r-0 R/W-0
CMPON — CMPSIDL r r r rDACOE
bit 15 bit 8
R/W-0 R/W-0 R/W-0 r-0 R/W-0 r-0 R/W-0 R/W-0
INSEL1 INSEL0 EXTREF r CMPSTAT r CMPPOL RANGE
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CMPON: Comparator Operating Mode bit
1 = Comparator module is enabled
0 = Comparator module is disabled (reduces power consumption)
bit 14 Unimplemented: Read as ‘0’
bit 13 CMPSIDL: Comparator Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode.
0 = C ontinues m odule operation in Idle mode
If a device has multiple comparators, any CMPSIDL bit set to ‘1’ disables ALL comparators while in
Idle mode.
bit 12-9 Reserved: Read as ‘0’
bit 8 DACOE: DAC Output Enable
1 = DAC analog voltage is output to the DACOUT pin(1)
0 = DAC analog voltage is not connected to the DACOUT pin
bit 7-6 INSEL<1:0>: Input Source Select for Comparator bits
00 = Selects CMPxA input pin
01 = Selects CMPxB input pin
10 = Selects CMPxC input pin
11 = Selects CMPxD input pin
bit 5 EXTREF: Enable External Reference bit
1 = External source provides reference to the DAC (maximum DAC voltage determined by the
external voltage source)
0 = Internal reference sources provide reference to the DAC (maximum DAC voltage determined by
the RANGE bit settin g)
bit 4 Reserved: Read as ‘0’
bit 3 CMPSTAT: Current State of Comparator Output Including CMPPOL Selection bit
bit 2 Reserved: Read as ‘0’
bit 1 CMPPOL: Comparator Output Polarity Control bit
1 = Output is inverted
0 = Output is non-inverted
bit 0 RANGE: Selects DAC Output Voltage Range bit
1 = High Range: Max DAC Value = AVDD/2, 1.65V at 3.3V AVDD
0 = Low Range: Max DAC Value = INTREF(2)
Note 1: DACOUT can be associated only with a single comparator at any given time. The software must ensure
that multiple comparators do not enable the DAC output by setting their respective DACOE bit.
2: Refer to the DAC Module Specifications (Table 24-43) in Section 24.0 “Electrical Ch aracteristics” for
the INTREF value.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
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REGISTER 20-2: CMPDACx: COMPARATOR DAC x CONTROL REGISTER
r-0 r-0 r-0 r-0 r-0 r-0 R/W-0 R/W-0
r r r r r rCMREF<9:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CMREF<7:0>
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 0 Reserved: Read as ‘0’
bit 9-0 CMREF<9:0>: Comparator Reference Voltage Select bits
1111111111 = (CMREF<9:0> * INTREF/1024) or (CMREF<9:0> * (AVDD/2)/1024) volts depending
on the RANGE bit or (CMREF<9:0> * EXTREF/1024) if EXTREF is set
•
•
•
0000000000 = 0.0 volts
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
21.0 SPECIAL FEATURES
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX0 2/X04
devices include several features intended to maximize
application flexibility and reliability, and minimize cost
through elimination of external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Inte rfac e
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
• Brown-out Reset (BOR)
21.1 Configuration Bits
dsPIC33FJ06GS10 1/X02 and dsPIC33FJ16GSX02/X04
devices provide nonvolatile memory implementations
for device C onfigurati on bits . Refer to “Device Con fig-
uration” (DS70194) in the “dsPIC33F/PIC24H Family
Reference Manual” for more information on this
implementation.
The Configuration bits can be programmed (read
as ‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The individual Configuration bit descriptions for the
Configuration re gisters are shown in Table 21-2.
Note that address, 0xF80000, is beyond the user pro-
gram memory space. It belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using Table Reads and Table Writes.
The device Configuration register map is shown in
Table 21-1.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 devices. It is
not intended to be a comprehensive
reference source. To complement the
informat ion in th is data sh eet , re fer to the
“dsPIC33F/PIC24H Family Reference
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
“dsPIC33F/PIC24H Family Reference
Manual” sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
TABLE 21-1: DEVICE CONFIGURATION REGISTER MAP
Add ress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0xF80000 FBS — — — — BSS2 BSS1 BSS0 BWRP
0xF80002 Reserved — — — — — — — —
0xF80004 FGS — — — — —GSS1GSS0GWRP
0xF80006 FOSCSEL IESO — — — FNOSC2 FNOSC1 FNOSC0
0xF80008 FOSC FCKSM1 FCKSM0 IOL1WAY —— OSCIOFNC POSCMD1 POSCMD0
0xF8000A FWDT FWDTEN WINDIS — WDTPRE WDTPOST3 WDTPOST2 WDTPOST1 WDTPOST0
0xF8000C FPOR — — — — Reserved
(2)
FPWRT2 FPWRT1 FPWRT0
0xF8000E FICD Reserved
(1)
JTAGEN — — — ICS1 ICS0
0xF80010 FUID0 User Unit ID Byte 0
0xF80012 FUID1 User Unit ID Byte 1
Legend:
— = unim plem en ted bit , read as ‘
0
’.
Note 1:
These bits are reserved for use by development tools and must be programmed to ‘
1
’.
2:
This bit reads the current programmed value.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 268 2008-2014 Microchip Technology Inc.
TABLE 21-2: dsPIC33F CONFIGURATION BITS DESCRIPTION
Bit Field Register RTSP Effect Description
BWRP FBS Immediate Boot Segment Program Flash Write Protection bit
1 = Boot segment can be written
0 = Boot segment is write-protected
BSS<2:0> FBS Immediate Boot Segment Program Flash Code Protection Size bits
x11 = No boot program Flash segment
Boot Space is 256 Instruction Words (except interrupt vectors):
110 = Standard security; boot program Flash segment ends at
0x0003FE
010 = High security; boot program Flash segment ends at
0x0003FE
Boot Space is 768 Instruction Words (except interrupt vectors):
101 = Standard security; boot program Flash segment ends at
0x0007FE
001 = High security; boot program Flash segment ends at
0x0007FE
Boot Space is 1792 Instruction Words (except interrupt vectors):
100 = Standard security; boot program Flash segment ends at
0x000FFE
000 = High security; boot program Flash segment ends at
0x000FFE
GSS<1:0> FGS Immediate General Segment Code-Protect bits
11 = User program me mory i s not co de-protected
10 = Standard security
0x = High security
GWRP FGS Immediate General Segment Writ e-Protect bit
1 = User program memory is not writ e-prote c ted
0 = User program memory is write-protected
IESO FOSCSEL Immediate Two-speed Oscillator Start-up Enable bit
1 = Start-up device with FRC, then automatically switch to the
user-selected oscillator source when ready
0 = Start-up device with user-selected oscillator source
FNOSC<2:0> FOSCSEL If clock switch
is enabled,
RTSP effect
is on any
device Reset;
otherwise,
Immediate
Initial Os cillator Source Selection bit s
111 = Internal Fast RC (FRC) Oscillator with Postscaler
110 = Internal Fast RC (FRC) Oscillator with Divide-by-16
101 = LPRC Oscillator
100 = Reserved
011 = Primary (XT, HS, EC) Oscillator with PLL
010 = Primary (XT, HS, EC) Oscillator
001 = Internal Fast RC (FRC) Oscillator with PLL
000 = FRC Oscillator
FCKSM<1:0> FOSC Immediate Clock Switching Mode bits
1x = Clock swi t ch i ng i s di sa bled, F ai l-Sa f e Clock Mo ni to r i s disabl ed
01 = Cloc k switc hing is enable d, Fail- Safe Cl ock M onitor is disab led
00 = Clock switc hi ng is enab led, Fail-Saf e Cloc k M oni tor is enab le d
IOL1WAY FOSC Immediate Peripheral Pin Select Configuration bit
1 = Allows only one reconfiguration
0 = Allows multiple reconfigurations
OSCIOFNC FOSC Immediate OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is the clock output
0 = OSC2 is the general purpose digital I/O pin
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
POSCMD<1:0> FOSC Immediate Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
FWDTEN FWDT Immediate Watch dog Timer Enable bit
1 = Watchdog Timer is always enabled (LPRC oscillator cannot be
disabled; clearing the SWDTEN bit in the RCON register will have
no effect)
0 = Watchdog T imer is enabled/disabled by user software (LPRC can
be disabled by clearing the SWDTEN bit in the RCON register)
WINDIS FWDT Immediate Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
WDTPRE FWDT Immediate Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
WDTPOST<3:0> FWDT Immediate Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
FPWRT<2:0> FPOR Immediate Power-on Reset Timer Value Select bits
111 = PWRT = 128 ms
110 = PWRT = 64 ms
101 = PWRT = 32 ms
100 = PWRT = 16 ms
011 = PWRT = 8 ms
010 = PWRT = 4 ms
001 = PWRT = 2 ms
000 = PWRT = Disabled
JTAGEN FICD Immediate JTAG Enable bit
1 = JTAG is enabled
0 = JTAG is disabled
ICS<1:0> FICD Immediate ICD Communication Channel Select Enable bits
11 = Communicates on PGEC1 and PGED1
10 = Communicates on PGEC2 and PGED2
01 = Communicates on PGEC3 and PGED3
00 = Reserved, do not use.
TABLE 21-2: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field Register RTSP Effect Description
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 270 2008-2014 Microchip Technology Inc.
21.2 On-Chip Voltage Regulator
The dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 devices power their core
digital logic at a nominal 2.5V. This can create a conflict
for designs that are required to operate at a higher typical
voltage, such as 3.3V. To simplify system design, all
devices in the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families incorporate an on-chip
regulator that allows the device to run its core logic fr om
VDD.
The regul ator provides power to the c ore from the other
VDD pins. When the regulator is enabled, a low-ESR
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be connected to the VCAP pin
(Figure 21-1). This helps to maintain the stability of the
regulator. The recommended value for the filter
capacitor is provided in Table 24-13 located in
Section 24.1 “DC Ch aracteristics”.
On a POR, it take s approxim ately 20 s for the on- chip
voltage regulator to generate an output voltage. During
this time, designated as TSTARTUP, code execution is
disabled. TSTARTUP is applied every time the device
resumes operation after any power-down.
FIGURE 21-1: CONNECTIONS FOR THE
ON-CHIP VO LTAGE
REGULATOR(1,2,3)
21.3 BOR: Brown-out Reset
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit. The main purpose of
the BOR mod ule is to generate a d ev ice R ese t whe n a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines, or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an osci llator m ode is sel ected , the BOR ac tivates th e
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and
a crystal oscillator is being used, then a nominal delay
of TFSCM = 100 is applied. The total delay in this case
is TFSCM.
The BOR Status bit (RCON<1 >) is set to in dicate tha t a
BOR has occurred. The BOR circuit continues to
operate while in Sleep or Idle modes and resets the
device should VDD fall below the BOR threshold
voltage.
Note: It i s import ant fo r the lo w-ESR capa citor to
be plac ed as close as possible to t he VCAP
pin.
Note 1: These are typical operating voltages. Refer
to Table 24-13 located in Sect ion 2 4.1 “DC
Characteristics” for the full operating
ranges of VDD.
2: It is important for the low-ESR capacitor to
be placed as close as possible to the
VCAP pin.
3: Typical VCAP pin voltage = 2.5V when
VDD VDDMIN.
VDD
VCAP
VSS
dsPIC33F
CEFC
3.3V
10 µF
Tantalum
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
21.4 W atchdog Timer (WDT)
For the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 devices, the WD T is driven
by the LPRC oscillator. When the WDT is enabled, the
clock sour ce is also enabled.
21.4.1 PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.
This feed s a pres caler th at can b e confi gured fo r either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The presc aler is set by the WDTPRE Con figurati on bit.
With a 32 kHz input, the prescaler yields a nominal
WDT time-out period (TWDT) of 1 ms in 5-bit mo de, or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>) which allow the
select ion of 16 settings , from 1:1 to 1:32,768. U sing the
prescal er and postscaler , time-out pe riods ranging from
1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC<2:0> bits) or by
hardware (i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
•By a CLRWDT instruction during normal execution
21.4.2 SL EEP AND IDLE MODES
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP bit (RCON<3>)
or IDLE bit (RCON<2>) will need to be cleared in
software after the device wakes up.
21.4.3 ENABLING WDT
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configura tion bit is s et, the WDT is
always enabled.
The WDT can be optiona lly controll ed in softwa re when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN
control bi t is cleared on any device Reset. The software
WDT option allows the user application to enable the
WDT for critical code segments and disable the WDT
during non-critical segments for maximum power
savings.
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT event s, the flag m ust be c leared in s oftware.
FIGURE 21-2: WDT BLOCK DIAGRAM
Note: The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
Note: If the WINDIS bit (FWDT<6>) is cleared,
the CLRWDT instruction should be executed
by the application software only during the
last 1/4 of the WDT period. This CLRWDT
window can be determined by using a timer.
If a CLRWDT instruction is executed before
this wi nd ow, a WDT Rese t o c cu rs.
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
0
1
WDTPRE WDTPOST<3:0>
Watchdog Timer
Prescaler
(Divide-by-N1) Postscaler
(Divide-by-N2)
Sleep/Idle
WDT
WDT Window Select
WINDIS
WDT
CLRWDT Instruction
SWDTEN
FWDTEN
LPRC Clock
RS RS
Wake-up
Reset
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 272 2008-2014 Microchip Technology Inc.
21.5 JTAG Interface
The dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 dev ices imp lement a J TA G
interface, which supports boundary scan device
testing. Detailed information on this interface will be
provided in future revisions of the document.
21.6 In-Circuit Serial Programming
The dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 family of Digital Signal
Controllers can be serially programmed while in the
end application circuit. This is done with two lines for
clock and data and three other lines for power, ground
and the programming sequence. Serial programming
allows customers to manufacture boards with
unprogrammed devices and then program the Digital
Signal Controller just before shipping the product.
Serial programming also allows the most recent
firmware or a custom firmware to be programmed.
Refer to the “dsPIC33F/PIC24H Flash Programming
Specification” (DS70152) for details about In-Circuit
Serial Programming (ICSP).
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
21.7 In-Circuit Debugger
The dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 devices provide simple
debugging functionality through the PGECx (Emula-
tion/Debug Clock) and PGEDx (Emulation/Debug
Data) pin functions.
Any of the three p airs of debu gging cloc k/dat a pins can
be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS, and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins.
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
21.8 Code Protection and
CodeGuard™ Security
The dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 devices offer the intermediate
implementation of CodeGuard™ Security. CodeGuard
Security enables multiple parties to securely share
resources (memory, interrupts and peripherals) on a
single chip. This feature helps protect individual
Intellectual Property (IP) in collaborative system designs.
When co upled with software encryption librari es, Code-
Guard™ Se curity can be used to securely update Flash
even when multiple IPs reside on a single chip.
TABLE 21-3: CODE FLASH SECURITY
SEGMENT SIZES FOR
6-Kbyte DEVICES
The code protection features are controlled by the
Configuration registers: FBS and FGS.
Secure segment and RAM protection is not implemented
in dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 devices.
TABLE 21-4: CODE FLASH SECURITY
SEGMENT SIZES FOR
16-Kbyte DEVICES
Configur ation Bits
BSS<2:0> = x11
0K
BSS<2:0> = x10
256
BSS<2:0> = x01
768
BSS<2:0> = x00
1792
002BFEh
0001FEh
000200h
000000h
VS = 256 IW
0003FEh
000400h
0007FEh
000800h
GS = 1792 IW 000FFEh
001000h
002BFEh
0001FEh
000200h
000000h
VS = 256 IW
0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
GS = 1536 IW
BS = 256 IW
002BFEh
0001FEh
000200h
000000h
VS = 256 IW
0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
GS = 1024 IW
BS = 768 IW
002BFEh
0001FEh
000200h
000000h
VS = 256 IW
0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
BS = 1792 IW
Note: Refer to “CodeGuard™ Security”
(DS70199) for further information on
CodeGuard Security usage, configuration
and operation.
Configur ation Bits
BSS<2:0> = x11
0K
BSS<2:0> = x10
256
BSS<2:0> = x01
768
BSS<2:0> = x00
1792
002BFEh
0001FEh
000200h
000000h
VS = 256 IW
0003FEh
000400h
0007FEh
000800h
GS = 5376 IW 000FFEh
001000h
002BFEh
0001FEh
000200h
000000h
VS = 256 IW
0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
GS = 5120 IW
BS = 256 IW
002BFEh
0001FEh
000200h
000000h
VS = 256 IW
0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
GS = 4608 IW
BS = 768 IW
002BFEh
0001FEh
000200h
000000h
VS = 256 IW
0003FEh
000400h
0007FEh
000800h
GS = 3584 IW
000FFEh
001000h
BS = 1792 IW
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 274 2008-2014 Microchip Technology Inc.
NOTES:
2008-2014 Microchip Technology Inc. DS70000318G-page 275
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
22.0 INSTRUCTION SET SUMMARY
The dsPIC33F instruction set is identical to that of the
dsPIC30F.
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operatio n of the i nstruction.
The instruction set is highly orthogonal and is grouped
into five bas ic ca tegories:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• DSP operations
• Control operations
Table 22-1 shows the general symbols used in
des c ribing the instructions.
The dsPIC33F instruction set summary in Table 22-2
lists all the instructions, along with the status flags
affected by each instr uction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is t ypica lly a
register ‘Ws’ with or without an address modifier
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
However , word or byte-oriented file register instructions
have two operands:
• The file register specified by the value, ‘f’
• The destination, which could be either the file
register, ‘f ’, or the W0 register, which is denoted
as ‘WREG’
Most bit-oriented instructions (including simple
rotate/shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register ‘Wb’)
The literal inst ruc tion s th at i nv olv e d ata movem ent can
use some of the following operands:
• A literal val ue to b e load ed into a W regi ster or fil e
register (spe cified by ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ‘Wb’
without any address modifi er
• The second source operand, which is a literal
value
• The de stination of the result (only if not the s ame
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The MAC class of DSP instruc tions ca n use so me of the
following operands:
• The accumulator (A or B) to be used (required
operand)
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The ac cumulator write-back destination
The other DSP instructions do not involve any
multiplication and can include:
• The accumulator to be used (required)
• The source or des tination operan d (design ated as
Wso or Wdo, respectively) with or without an
address modifier
• The amount of shift specified by a W register,
‘Wn’, or a literal value
The co nt rol i nstru cti ons can us e so me of the fol lowi ng
operands:
• A program memory address
• The mode of the Table Read and Table Write
instructions
Note: This data sheet summarizes the features
of the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
latest sections in the “dsPIC33F/PIC24H
Family Reference Manual”, which are
available on the Microchip web site
(www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 276 2008-2014 Microchip Technology Inc.
Most instructions are a single word. Certain
double-word instructions are designed to provide all the
required information in these 48 bits. In the second
word, the 8 MSbs are ‘0’s. If this second word is
exe cuted as an ins tr uctio n (b y itsel f), it w ill e xec ute as
a NOP.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
Program Counter is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles with the additional instruction cycle(s)
executed as a NOP. Notable exceptions are the BRA
(unconditional/computed branch), indirect CALL/GOTO,
all Table Re ads an d Table Writes and RETURN/RETFIE
instructions, which are single-word instructions but take
two or three cycles. Certain instructions that involve
skipping over the subsequent instruction require either
two or three cycles if the skip is performed, depending
on whether the instruction being skipped is a single-word
or two-word instruction. Moreover, double-word moves
require two cycles.
Note: For more details on the instruction set,
refer to the “16-bit MCU and DSC
Programmer’s Reference Manual”
(DS70157).
TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field Description
#text Means literal defined by “text”
(text) Means “content of text”
[text] Means “the location addressed by text”
{ } Optional field or operation
<n:m> Register bit field
.b Byte mode selection
.d Double-Word mode selection
.S Shadow register select
.w Word mode selection (default)
Acc O ne of two accumu lators {A , B}
A WB Accumulator Write-Back Destination Address register {W13, [W13]+ = 2}
bit4 4-bit bit selection field (used in word-addressed instructions) {0...15}
C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr Absolute address, label or expression (resolved by the linker)
f File register address {0x0000...0x1FFF}
lit1 1-bit unsigned literal {0,1}
lit4 4-bit unsigned literal {0...15}
lit5 5-bit unsigned literal {0...31}
lit8 8-bit unsigned literal {0...255}
lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14 14-bit unsigned literal {0...16384}
lit16 16-bit unsigned literal {0...65535}
lit23 23-bit unsigned literal {0...8388608}; LSb must be ‘0’
None Field does not require an entry, can be blank
OA, OB, SA, SB DSP Status bit s: ACCA Over flow, ACCB Overflow, ACCA Saturate, ACCB Satu rate
PC Program Counter
Slit10 10-bit signed literal {-512...511}
Slit16 16-bit signed literal {-32768...32767}
Slit6 6-bit signed literal {-16...16}
Wb Base W register {W0..W15}
Wd Destination W register { Wd, [Wd], [Wd++], [Wd- -], [++Wd], [--Wd] }
Wdo Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn Dividend, Divisor Working register pair (Direct Addressing)
2008-2014 Microchip Technology Inc. DS70000318G-page 277
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Wm*Wm Multiplicand and Multiplier Working register pair for Square instructions
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn Multiplicand and Multiplier Working register pair for DSP instructions
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn One of 16 Working registers {W0..W15}
Wnd One of 16 Destination Working registers {W0...W15}
Wns One of 16 Source Working registers {W0...W15}
WREG W0 (Working register used in file register instructions)
Ws Source W register { Ws , [Ws], [Ws++ ], [Ws--], [++W s], [-- W s ] }
Wso Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx X Data Space Prefetch Address regist er for DSP instructions
{[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd X Data Space Prefetch Destination register for DSP instructions {W4...W7}
Wy Y Data Space Prefetch Address regist er for DSP instructions
{[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd Y Data Space Prefetch Destination register for DSP instructions {W4...W7}
TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field Description
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 278 2008-2014 Microchip Technology Inc.
TABLE 22-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
Assembly
Mnemonic Asse mbly S yntax Descr ipt ion # of
Words # of
Cycles Status Flags
Affected
1ADD ADD Acc Add Accum ulat ors 1 1 OA ,OB,SA,SB
ADD f f = f + WREG 1 1 C,DC,N,OV,Z
ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z
ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z
ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB
2ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z
3AND AND f f = f .AND. WREG 1 1 N,Z
AND f,WREG WREG = f .AND. WREG 1 1 N,Z
AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z
AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z
AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z
4ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z
ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z
ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z
5BCLR BCLR f,#bit4 Bit Clear f 1 1 None
BCLR Ws,#bit4 Bit Clear Ws 1 1 None
6BRA BRA C,Expr Bran ch if Carry 1 1 (2) None
BRA GE,Expr Branch if Greater Than or Equal 1 1 (2) None
BRA GEU,Expr Branch if Unsig ned Grea ter Th an or Equa l 1 1 (2) N o ne
BRA GT,Expr Branch if Greater Than 1 1 (2) None
BRA GTU,Expr Branch if Unsigned Greater Th an 1 1 (2) None
BRA LE,Expr Branch if Less Than or Equal 1 1 (2) None
BRA LEU,Expr Branch if Unsigned Less Than or Equal 1 1 (2) None
BRA LT,Expr Branch if Less Than 1 1 (2) None
BRA LTU,Expr Branch if Unsigned Less Than 1 1 (2) None
BRA N,Expr Branch if Negative 1 1 (2) None
BRA NC,Expr Branch if Not Carry 1 1 (2) No ne
BRA NN,Expr Branch if Not Nega tive 1 1 (2) None
BRA NOV,Expr Branch if Not Overflow 1 1 (2) None
BRA NZ,Expr Branc h if Not Ze ro 1 1 (2) No ne
BRA OA,Expr Branch if Accumula tor A Overflow 1 1 (2) None
BRA OB,Expr Branch if Accumula tor B Overflow 1 1 (2) None
BRA OV,Expr Branch if Overflow 1 1 (2) None
BRA SA,Expr Branch if Accumulator A Saturated 1 1 (2) None
BRA SB,Expr Branch if Accumulator B Saturated 1 1 (2) None
BRA Expr Branch Unconditionally 1 2 No ne
BRA Z,Expr Branch if Zero 1 1 (2) None
BRA Wn Computed Branch 1 2 None
7BSET BSET f,#bit4 Bit Set f 1 1 None
BSET Ws,#bit4 Bit Set Ws 1 1 None
8BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None
BSW.Z Ws,Wb Write Z b it to Ws<Wb> 1 1 None
9BTG BTG f,#bit4 Bit Toggle f 1 1 None
BTG Ws,#bit4 Bit Toggle Ws 1 1 None
2008-2014 Microchip Technology Inc. DS70000318G-page 279
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1
(2 or 3) None
BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1
(2 or 3) None
11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1
(2 or 3) None
BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1
(2 or 3) None
12 BTST BTST f,#bit4 Bit Test f 1 1 Z
BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C
BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z
BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C
BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z
13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z
BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C
BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z
14 CALL CALL lit23 Call Subroutine 2 2 None
CALL Wn Call Indirect Subroutine 1 2 None
15 CLR CLR f f = 0x0000 1 1 None
CLR WREG WREG = 0x0000 1 1 None
CLR Ws Ws = 0x0000 1 1 None
CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB
16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep
17 COM COM f f = f 11 N,Z
COM f,WREG WREG = f 11 N,Z
COM Ws,Wd Wd = Ws 11 N,Z
18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z
CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z
CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z
19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z
CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z
20 CPB CPB f Co mpare f with WREG, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,Ws Compare W b with Ws, with Borrow
(Wb – Ws – C)1 1 C,DC,N,OV,Z
21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, Skip if = 1 1
(2 or 3) None
22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, Skip if > 1 1
(2 or 3) None
23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, Skip if < 1 1
(2 or 3) None
24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, Skip if 11
(2 or 3) None
25 DAW DAW Wn Wn = Decimal Adjust Wn 1 1 C
26 DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z
DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z
DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z
27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z
DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z
DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z
28 DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Asse mbly S yntax Descr ipt ion # of
Words # of
Cycles Status Flags
Affected
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 280 2008-2014 Microchip Technology Inc.
29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV
30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV
31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 None
DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None
32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OA B,
SA,SB,SAB
33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB,
SA,SB,SAB
34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None
35 FBCL FBCL Ws,Wnd Find Bi t Change from Left (MSb) S ide 1 1 C
36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C
37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C
38 GOTO GOTO Expr Go to Address 2 2 None
GOTO Wn Go to Indirect 1 2 None
39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z
INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z
INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z
INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z
41 IOR IOR f f = f .IOR. WREG 1 1 N,Z
IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z
IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z
IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z
IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z
42 LAC LAC Wso,#Slit4,Acc Lo ad Ac cum ulato r 1 1 OA, O B,OA B,
SA,SB,SAB
43 LNK LNK #lit14 Link Frame Pointer 1 1 None
44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z
LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z
LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z
LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z
LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z
45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
,
AWB
Multiply and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB
MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB
46 MOV MOV f,Wn Move f to Wn 1 1 None
MOV f Move f to f 1 1 N,Z
MOV f,WREG Move f to WREG 1 1 None
MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None
MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None
MOV Wn,f Move Wn to f 1 1 None
MOV Wso,Wdo Move Ws to Wd 1 1 None
MOV WREG,f Move WREG to f 1 1 None
MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None
47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and Store Accumulator 1 1 None
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Asse mbly S yntax Descr ipt ion # of
Words # of
Cycles Status Flags
Affected
2008-2014 Microchip Technology Inc. DS70000318G-page 281
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
48 MPY MPY
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
49 MPY.N MPY.N
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None
50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
,
AWB
Multiply and Subtract from Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None
MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd } = sign ed (Wb ) * un s i gned (W s) 1 1 None
MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd } = unsi gn ed (Wb ) * s ign ed (W s) 1 1 None
MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws) 11 None
MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wn d} = si gn ed (Wb ) * unsi g ne d( li t5 ) 1 1 None
MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5) 11 None
MUL f W3:W2 = f * WREG 1 1 None
52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
NEG f f = f + 1 1 1 C,DC,N,OV,Z
NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
53 NOP NOP No Operation 1 1 None
NOPR No Operation 1 1 None
54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None
POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None
POP.D Wnd Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1) 12 None
POP.S Pop Shadow Registe rs 1 1 All
55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None
PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None
PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-St ack (TOS) 1 2 None
PUSH.S Push Shadow Registers 1 1 None
56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep
57 RCALL RCALL Expr Relative Call 1 2 None
RCALL Wn Computed Call 1 2 None
58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None
REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None
59 RESET RESET Software Device Reset 1 1 None
60 RETFIE RETFIE Return from interrupt 1 3 (2) None
61 RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None
62 RETURN RETURN Return from Subroutine 1 3 (2) None
63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z
RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z
RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z
64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z
RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z
RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z
65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z
RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z
RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Asse mbly S yntax Descr ipt ion # of
Words # of
Cycles Status Flags
Affected
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 282 2008-2014 Microchip Technology Inc.
66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z
RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z
RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z
67 SAC SAC Acc,#Slit4,Wdo Store Acc umu lato r 1 1 None
SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None
68 SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C,N,Z
69 SETM SETM f f = 0xFFFF 1 1 Non e
SETM WREG WREG = 0xFFFF 1 1 None
SETM Ws Ws = 0xFFFF 1 1 None
70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB,
SA,SB,SAB
SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB,
SA,SB,SAB
71 SL SL f f = Left Shift f 1 1 C,N,OV,Z
SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z
SL Wb,Wns,Wnd Wnd = Lef t Shift Wb by Wns 1 1 N,Z
SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z
72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB,
SA,SB,SAB
SUB f f = f – WREG 1 1 C,DC,N,OV,Z
SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z
SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z
SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z
SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z
73 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z
74 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z
SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z
SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z
SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z
75 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z
76 SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None
SWAP Wn Wn = Byte Swap Wn 1 1 None
77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd< 7:0> 1 2 None
78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None
79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None
80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None
81 ULNK ULNK Unlink Frame Pointer 1 1 None
82 XOR XOR f f = f .XOR. WREG 1 1 N,Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z
XOR #lit10,Wn W d = lit10 .XOR. Wd 1 1 N,Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z
83 ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C,Z,N
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Asse mbly S yntax Descr ipt ion # of
Words # of
Cycles Status Flags
Affected
2008-2014 Microchip Technology Inc. DS70000318G-page 283
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
23.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® Digital
Signal Controllers (DSC) are supported with a full
range of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
23.1 MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for high-
performance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With com plete projec t managem ent, visual cal l graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multipl e project s with simu ltane ous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic cod e f orm atti ng bas ed on us er-d efined
rules
• Live parsin g
User-Friendly, Cust omiz abl e Interfa ce :
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project -Bas ed Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 284 2008-2014 Microchip Technology Inc.
23.2 MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16 and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers pro vide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Co mpilers inc lude an asse mbler , li nker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other
relocatable object files and archives to create an exe-
cutable file. MPLAB XC Compiler uses the assembler
to produce its object file. Notable features of the
assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
23.3 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly co de
• Conditional assembly for multipurpose
sour ce fil es
• Directives that allow complete control over the
assembly process
23.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB O bject Li brarian manage s the cre ation an d
modification of library files of precompiled code. When
a rout in e from a l ibra ry is cal led from a so urc e f ile , o nly
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion an d extraction
23.5 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archive d o r li nk ed with other rel oca table ob jec t
files and archives to create an executable file. Notable
features of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
2008-2014 Microchip Technology Inc. DS70000318G-page 285
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
23.6 MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most pe ripherals an d internal regi sters.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool .
23.7 MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL IC E offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cable s.
23.8 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 int erface and is connected to t he target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
23.9 PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and program-
ming of PIC and dsPIC Flash microcontrollers at a most
af fordable pr ice point us ing the powerfu l graphica l user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a full-
speed USB interface and can be connected to the
target via a Microchip debug (RJ-11) connector (com-
patib le with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
23.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a mod-
ular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Devic e Programmer ca n read, verif y and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 h as high-spe ed co mmunicat ions an d
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 286 2008-2014 Microchip Technology Inc.
23.11 Demonstration/Development
Boards, Evaluati on Kits and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide applica-
tion firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
use d in teaching envi ronments, for prototyping c ustom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a l ine of evaluation k its and demonstra-
tion software for analog fil ter desi gn, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience t he specified d evice. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
23.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Softwa re Too ls from companies, such as Gimpel
and Trace S ystems
• Protocol Anal yz ers fro m comp anies, su ch as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
2008-2014 Microchip Technology Inc. DS70000318G-page 287
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
24.0 ELECTRICAL CHARACTERIS TICS
This s ection provi des a n ove rview of dsPIC 33FJ 06GS101/X0 2 and dsPIC33F J16G SX02/X04 ele ctrica l cha racteri stics .
Additional information will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family are listed below.
Exposure to the se m aximu m rati ng con dition s for e xtend ed peri ods m ay af fec t dev ice relia bility. Functi onal operati on of
the device at t hes e o r any other con di t ion s a bo ve the parameters indic ate d i n the operat ion li stings of thi s s pecificatio n
is no t implied .
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Volta ge on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to VSS(3) ...................................................-0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS, when VDD 3.0V(3) ................................................. -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to Vss, when VDD < 3.0V(3)........................................-0.3V to (VDD + 0.3V)
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2)...........................................................................................................................250 mA
Maximum current sourced/sunk by any 4x I/O pin..................................................................................................15 mA
Maximum current sourced/sunk by any 8x I/O pin..................................................................................................25 mA
Maximum current sourced/sunk by any 16x I/O pin................................................................................................45 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2)...............................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device . This is a stress rat ing only, and funct ion al op erat ion of the de vi ce at thos e or any othe r con ditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 24-2).
3: See the “Pin Diagrams” section for 5V tole rant pins.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 288 2008-2014 Microchip Technology Inc.
24.1 DC Characteristics
TABLE 24-1: OPERATING MIPS VS. VOLTAGE
Characteristic VDD Range
(in Volts) Temp Range
(in °C)
Max MIPS
dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04
— 3.0-3.6V(1)-40°C to +85°C 40
— 3.0-3.6V(1)-40°C to +125°C 40
Note 1: Overal l function al de vi ce opera tion at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer
to Parameter BO10 in Table 24-11 for BOR values.
TABLE 24-2: THERMAL OPERATING CONDITIONS
Rating Symbol Min Typ Max Unit
Industri al Temperature De vi ces
Operating Junction Temperature Range TJ-40 — +125 °C
Operating Ambient Temperature Range TA-40 — +85 °C
Extended Temperature Devices
Operating Junction Temperature Range TJ-40 — +140 °C
Operating Ambient Temperature Range TA-40 — +125 °C
Power Dissipation:
Internal ch ip pow er dis sipatio n:
PINT = VDD x (IDD – IOH) PDPINT + PI/OW
I/O Pin Power Dissipation:
I/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipa tion PDMAX (TJ – TA)/JA W
TABLE 24-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic Symbol Typ Max Unit Notes
Package Thermal Resistance, 44-Pin QFN JA 28 — °C/W 1
Package Thermal Resistance, 44-Pin TFQP JA 39 — °C/W 1
Package Thermal Resistance, 28-Pin SPDIP JA 42 — °C/W 1
Package Thermal Resistance, 28-Pin SOIC JA 47 — °C/W 1
Package Thermal Resistance, 28-Pin QFN-S JA 34 — °C/W 1
Package Thermal Resistance, 18-Pin SOIC JA 57 — °C/W 1
Package Thermal Resistance, 44-Pin VTLA JA 25 — °C/W 1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
2008-2014 Microchip Technology Inc. DS70000318G-page 289
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 24-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
Operating Voltage
DC10 VDD Supply Voltage(4)3.0 — 3.6 V Industri al and Extend ed
DC12 VDR RAM Data Retention Voltage(2)1.8 — — V
DC16 VPOR VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
——V
SS V
DC17 SVDD VDD Rise Rate(3)
to Ensure Internal
Power-on Reset Signal
0.03 — — V/ms 0V-3.0V in 0.1 secon ds
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: This is the limit to which VDD may be lowered without losing RAM data.
3: These parameters are characterized but not tested in manufacturing.
4: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer
to Parameter BO10 in Table 24-11 for BOR values.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 290 2008-2014 Microchip Technology Inc.
TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
No. Typical(1)Max Units Conditions
Operating Current (IDD)(2)
DC20d 55 70 mA -40°C
3.3V 10 MIPS
See Note 2
DC20a 55 70 mA +25°C
DC20b 55 70 mA +85°C
DC20c 55 70 mA +125°C
DC21d 68 85 mA -40°C
3.3V 16 MIPS
See Note 2 and Note 3
DC21a 68 85 mA +25°C
DC21b 68 85 mA +85°C
DC21c 68 85 mA +125°C
DC22d 78 95 mA -40°C
3.3V 20 MIPS
See Note 2 and Note 3
DC22a 78 95 mA +25°C
DC22b 78 95 mA +85°C
DC22c 78 95 mA +125°C
DC23d 88 110 mA -40°C
3.3V 30 MIPS
See Note 2 and Note 3
DC23a 88 110 mA +25°C
DC23b 88 110 mA +85°C
DC23c 88 110 mA +125°C
DC24d 98 120 mA -40°C
3.3V 40 MIPS
See Note 2
DC24a 98 120 mA +25°C
DC24b 98 120 mA +85°C
DC24c 98 120 mA +125°C
DC25d 128 160 mA -40°C
3.3V
40 MIPS
See Note 2, except PWM is
operating at maximum speed
(PTCON2 = 0x0000)
DC25a 125 150 mA +25°C
DC25b 121 150 mA +85°C
DC25c 119 150 mA +125°C
DC26d 115 140 mA -40°C
3.3V
40 MIPS
See Note 2, except PWM is
operating at 1/2 speed
(PTCON2 = 0x0001)
DC26a 112 140 mA +25°C
DC26b 110 140 mA +85°C
DC26c 108 140 mA +125°C
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
2: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from
rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are
zeroed)
• CPU executing while(1) statemen t
• JTAG disabled
3: These parameters are characterized but not tested in manufacturing.
2008-2014 Microchip Technology Inc. DS70000318G-page 291
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
DC27d 111 140 mA -40°C
3.3V
40 MIPS
See Note 2, except PWM is
operating at 1/4 speed
(PTCON2 = 0x0002)
DC27a 108 130 mA +25°C
DC27b 105 130 mA +85°C
DC27c 103 130 mA +125°C
DC28d 102 130 mA -40°C
3.3V
40 MIPS
See Note 2, except PWM is
operating at 1/8 speed
(PTCON2 = 0x0003)
DC28a 100 120 mA +25°C
DC28b 100 120 mA +85°C
DC28c 100 120 mA +125°C
TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (C ONTI N UE D )
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
No. Typical(1)Max Units Conditions
Operating Current (IDD)(2)
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
2: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from
rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inpu ts and pulle d to VSS
•MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are
zeroed)
• CPU executing while(1) statemen t
• JTAG disabled
3: These parameters are characterized but not tested in manufacturing.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 292 2008-2014 Microchip Technology Inc.
TABLE 24-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +1 25°C for Extended
Parameter
No. Typical(1)Max Units Conditions
Idle Current (IIDLE): Core Off Clock On Base Current(2)
DC40d 48 — mA -40°C
3.3V 10 MIPS
DC40a 48 — mA +25°C
DC40b 48 — mA +85°C
DC40c 48 — mA +125°C
DC41d 60 — mA -40°C
3.3V 16 MIPS(3)
DC41a 60 mA +25°C—
DC41b 60 — mA +85°C
DC41c 60 — mA +125°C
DC42d 68 — mA -40°C
3.3V 20 MIPS(3)
DC42a 68 — mA +25°C
DC42b 68 — mA +85°C
DC42c 68 — mA +125°C
DC43d 77 — mA -40°C
3.3V 30 MIPS(3)
DC43a 77 — mA +25°C
DC43b 77 — mA +85°C
DC43c 77 — mA +125°C
DC44d 86 — mA -40°C
3.3V 40 MIPS
DC44a 86 — mA +25°C
DC44b 86 — mA +85°C
DC44c 86 — mA +125°C
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
2: Base Idle current (IIDLE) is measured as follo ws:
• CPU core i s o ff, os c ill ato r is c on figured in EC m od e a nd ex tern al clock is activ e, OS C1 i s d riv en w ith
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits
are zeroed)
• JTAG is disabled
3: These parameters are characterized but not tested in manufacturing.
2008-2014 Microchip Technology Inc. DS70000318G-page 293
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 24-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operati ng tem pera ture -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
No. Typical(1)Max Units Conditions
Power-Down Current (IPD)(2,4)
DC60d 125 500 A-40°C
3.3V Base Power-Down Current
DC60a 135 500 A+25°C
DC60b 235 500 A+85°C
DC60c 565 950 A +125°C
DC61d 40 50 A-40°C
3.3V Watchdog Timer Current: IWDT(3)
DC61a 40 50 A+25°C
DC61b 40 50 A+85°C
DC61c 80 90 A +125°C
Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated.
2: IPD (Sleep) current is me asured as follo ws:
• CPU core is off, oscillator is configured in EC mode and external clock active, OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• All peripheral modules are disabled (PMDx bits are all ones)
• The VREGS bit (RCON<8>) = 0 (i.e., core regulator is set to stand-by while the device is in
Sleep mode)
• JTAG disabled
3: The current is the additional current consumed when the WDT module is enabled. This current should
be added to the base IPD curren t.
4: These currents are measured on the device containing the most memory in this family.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 294 2008-2014 Microchip Technology Inc.
TABLE 24-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extende d
Parameter No. Typical(1)Max Doze
Ratio Units Conditions
Doze Current (IDOZE)(2)
DC73a 75 105 1:2 mA -40°C 3.3V 40 MIPSDC73f 60 105 1:64 mA
DC73g 60 105 1:128 mA
DC70a 75 105 1:2 mA +25°C 3.3V 40 MIPSDC70f 60 105 1:64 mA
DC70g 60 105 1:128 mA
DC71a 75 105 1:2 mA +85°C 3.3V 40 MIPSDC71f 60 105 1:64 mA
DC71g 60 105 1:128 mA
DC72a 75 105 1:2 mA +125°C 3.3V 40 MIPSDC72f 60 105 1:64 mA
DC72g 60 105 1:128 mA
Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated.
2: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDOZE measurements are as follows:
• Oscillator is configured in EC mode and external clock active, OSC1 is driven with external square
wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are
zeroed)
• CP U executing while(1) statement
• JTAG disabled
2008-2014 Microchip Technology Inc. DS70000318G-page 295
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
VIL Input Low Voltage
DI10 I/O Pins VSS —0.2VDD V
DI15 MCLR VSS —0.2VDD V
DI16 I/O Pins with OSC1 VSS —0.2VDD V
DI18 I/O Pins with SDAx, SCLx VSS — 0.3 VDD V SMBus disabled
DI19 I/O Pins with SDAx, SCLx VSS — 0.8 V SMBus enabled
VIH Input High Voltage
DI20
DI21 I/O Pins Not 5V Tolerant(4)
I/O Pins 5V Tolerant(4)0.7 VDD
0.7 VDD —
—VDD
5.5 V
V
DI28
DI29 SDA1, SCL1
SDA1, SCL1 0.7 VDD
2.1 —
—5.5
5.5 V
VSMBus disabled
SMBus enabled
ICNPU CNx Pull-up Current
DI30 — 250 — AV
DD = 3.3V, VPIN = VSS
IIL Input Leakage Current(2,3,4)
DI50 I/O Pins with:
4x Driver Pins - RA0-RA2,
RB0-RB2, RB5-RB10, RB15,
RC1, RC2, RC9, RC10
8x Driver Pins - RC0, RC3-RC8,
RC11-RC13
16x Driv er Pins - RA3, RA4, RB3,
RB4, RB11-RB14
—
—
—
—
—
—
±2
±4
±8
A
A
A
VSS VPIN VDD,
Pin at high-impedance
VSS VPIN VDD,
Pin at high-impedance
VSS VPIN VDD,
Pin at high-impedance
DI55 MCLR ——±2AVSS VPIN VDD
DI56 OSC1 — — ±2 AVSS VPIN VDD,
XT and HS modes
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See “Pin Diagrams” for the list of 5V tolerant I/O pins.
5: VIL source < (VSS – 0.3). Characterized but not tested.
6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-
vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 296 2008-2014 Microchip Technology Inc.
IICL Input Low Injection Current
DI60a 0 — -5(5,8)mA All pins except VDD, VSS,
AVDD, AVSS, MCLR ,
VCAP and RB5
IICH Input High Injection Current
DI60b 0 — +5(6,7,8)mA All pins except VDD, VSS,
AVDD, AVSS, MCLR ,
VCAP, RB5 and digital
5V-tolerant designated
pins
IICT Tot al Input Injection Current
DI60c (sum of all I/O and control pins) -20(9)—+20
(9)mA Absolute instant aneous
sum of all ± input
injection currents from
all I/O pins
(| I
ICL + | IICH |) IICT
TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
lev els represent normal operating co nditions . Higher leakage current may be me asured at differ ent input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See “Pin Diagrams” for the list of 5V tolerant I/O pins.
5: VIL source < (VSS – 0.3). Characterized but not tested.
6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-
vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
2008-2014 Microchip Technology Inc. DS70000318G-page 297
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 24-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise st ated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic Min. Typ. Max. Units Conditions
DO10 VOL
Output Low Voltage
I/O Pins:
4x Sink Driver Pins – RA0-RA2,
RB0-RB2, RB5-RB10, RB15,
RC1, RC2, RC9, RC10
——0.4V
IOL 6 mA, VDD = 3.3V
See Note 1
Output Low Voltage
I/O Pins:
8x Sink Driver Pins – RC0,
RC3-RC8, RC11-RC13
——0.4V
IOL 10 mA, VDD = 3.3V
See Note 1
Output Low Voltage
I/O Pins:
16x Sink Driv er Pins – RA3,
RA4, RB3, RB4, RB11-RB14
——0.4V
IOL 18 mA, VDD = 3.3V
See Note 1
DO20 VOH
Output High Voltage
I/O Pins:
4x Source Driver Pins –
RA0-RA2, RB0-RB2, RB5-
RB10, RB15, RC1, RC2, RC9,
RC10
2.4 — — V IOH -6 mA, VDD = 3.3V
See Note 1
Output High Voltage
I/O Pins:
8x Source Driver Pins – RC0,
RC3-RC8, RC11-RC13
2.4 — — V IOH -10 mA, VDD = 3.3V
See Note 1
Output High Voltage
I/O Pins:
16x Source Driver Pins – RA3,
RA4, RB3, RB4, RB11-RB14
2.4 — — V IOH -18 mA, VDD = 3.3V
See Note 1
DO20A VOH1
Output High Voltage
I/O Pins:
4x Source Driver Pins –
RA0-RA2, RB0-RB2,
RB5-RB10, RB15, RC1, RC2,
RC9, RC10
1.5 — —
V
IOH -12 mA, VDD = 3.3V
See Note 1
2.0 — — IOH -11 mA, VDD = 3.3V
See Note 1
3.0 — — IOH -3 mA, VDD = 3.3V
See Note 1
Output High Voltage
8x Source Driver Pins – RC0,
RC3-RC8, RC11-RC13
1.5 — —
V
IOH -16 mA, VDD = 3.3V
See Note 1
2.0 — — IOH -12 mA, VDD = 3.3V
See Note 1
3.0 — — IOH -4 mA, VDD = 3.3V
See Note 1
Output High Voltage
I/O Pins:
16x Source Driver Pins – RA3,
RA4, RB3, RB4, RB11-RB14
1.5 — —
V
IOH -30 mA, VDD = 3.3V
See Note 1
2.0 — — IOH -25 mA, VDD = 3.3V
See Note 1
3.0 — — IOH -8 mA, VDD = 3.3V
See Note 1
Note 1: Parameters are charac teri ze d, but not tes ted .
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 298 2008-2014 Microchip Technology Inc.
TABLE 24-11: ELECTRICAL CHARACTERISTICS: BOR
DC CHARACTERISTICS
Standard Operating Conditions (see Note 3): 3.0V to 3.6V
(unless otherwise stated)
Operati ng tem per ature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min(1)Typ Max Units Conditions
BO10 VBOR BOR Event on VDD Transition
High-to-Low
BOR Event is Tied to VDD Core
Voltage Decrease
2.55 — 2.79 V See Note 2
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
2: The device will operate as normal until the VDDMIN threshold is reached.
3: Overal l fun cti ona l de vic e operatio n at VBORMIN < VDD < VDDMIN is tested but not c hara cte riz ed. All de vic e
analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN.
2008-2014 Microchip Technology Inc. DS70000318G-page 299
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TABLE 24-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
TABLE 24-12: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Indu stri al
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
Program Flash Memory
D130 EPCell Endurance 10,000 — — E /W -40C to +125C
D131 VPR VDD for Read VMIN —3.6VVMIN = Minimum operating
voltage
D132B VPEW VDD for Self-Timed Write VMIN —3.6VVMIN = Minimum operating
voltage
D134 TRETD Characteristic Re tention 20 — — Year Provided no other specifica tion s
are viola ted, -40C to +125C
D135 IDDP Supply Current during
Programming —10—mA
D136a TRW R ow Write Time 1.477 — 1.538 ms TRW = 11064 FRC cycles,
TA = +85°C, See Note 2
D136b TRW R ow Write Time 1.435 — 1.586 ms TRW = 11064 FRC cycles,
TA = +125°C, See Note 2
D137a TPE Page Erase Time 22.5 — 23.4 ms TPE = 168517 FRC cycles,
TA = +85°C, See Note 2
D137b TPE Page Erase Time 21.9 — 24.2 ms TPE = 168517 FRC cycles,
TA = +125°C, See Note 2
D138a TWW Wor d Write Cycle Time 47.4 — 49.3 µs TWW = 355 FRC cycles,
TA = +85°C, See Note 2
D138b TWW Wor d Write Cycl e Time 46 — 50.9 µs TWW = 355 FRC cycles,
TA = +125°C, See Note 2
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: Ot her co nditi ons: FRC = 7.37 MHz, TUN<5: 0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max).
This parameter depends on the FRC accuracy (see Table 24-20) and the value of the FRC Oscillator Tun-
ing register (see Register 9-4). For complete details on calculating the Minimum and Maximum time see
Section 5.3 “Programming Operations”.
Operating Condit ions : -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristics Min Typ Max Units Comments
—C
EFC External Filter Cap ac itor
Value(1)4.7 10 — F Capacitor must be low
series res is t anc e
(< 5 ohms)
Note 1: Typical VCAP voltage = 2.5 volts when VDD VDDMIN.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 300 2008-2014 Microchip Technology Inc.
24.2 AC Characteristics and Timing Parameters
This section def ines dsPIC33FJ06GS101/X02 a nd dsPIC33FJ16GSX02/ X04 AC charac teristics and timing parameters.
TABLE 24-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
FIGURE 24-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
TABLE 24-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise st ated)
Operati ng tem pera ture -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operati ng voltag e VDD range as described in Table 24-1.
Param
No. Symbol Characteristic Min Typ Max Units Conditions
DO50 COSCO OSC2 Pin — — 15 pF In XT and HS mod es when external
clock is used to drive OSC1
DO56 CIO All I/O Pins and OSC2 — — 50 pF EC mode
DO58 CBSCLx, SDAx — — 400 pF In I2C™ mode
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL=464
CL= 50 pF for all pins except OSC2
15 pF for OSC2 output
Load Cond itio n 1 – for all pins except OSC2 Load Condition 2 – for OSC2
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FIGURE 24-2: EXTER NAL CLOCK TIMING
Q1 Q2 Q3 Q4
OSC1
CLKO
Q1 Q2 Q3 Q4
OS20
OS25 OS30 OS30
OS40
OS41
OS31 OS31
TABLE 24-16: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industri al
-40°C TA +125°C for Extended
Param
No. Symb Characteristic Min Typ(1)Max Units Conditions
OS10 FIN External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC — 40 MHz EC
Oscilla tor C rys tal Freque ncy 3.5
10 —
—10
40 MHz
MHz XT
HS
OS20 TOSC TOSC = 1/FOSC 12.5 — DC ns
OS25 TCY Instruction Cycle Time(2)25 — DC ns
OS30 TosL,
TosH External Clock in (OSC1)
High or Low Time 0.375 x TOSC — 0.625 x TOSC ns EC
OS31 TosR,
TosF External Clock in (OSC1)
Rise or Fall Time — — 20 ns EC
OS40 TckR CLKO Rise Time(3) —5.2—ns
OS41 TckF CLKO Fall Time(3)—5.2—ns
OS42 GMExternal Oscillator
Transconductance(4)14 16 18 mA/V VDD = 3.3V,
TA = +25ºC
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“max.” cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
4: Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 302 2008-2014 Microchip Technology Inc.
TABLE 24-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
AC CHARACTERISTICS Standard Operating C on diti ons : 3 .0 V to 3. 6V (un les s otherw is e s tated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
OS50 FPLLI PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
0.8 — 8 MHz ECPLL, XTPLL modes
OS51 FSYS On-C hip VCO System
Frequency 100 — 200 MHz
OS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 mS
OS53 DCLK CLKO Stabilit y (Jitt er)(2)-3 0.5 3 % Measured over 100 ms
period
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
2: These p arameters a re c ha r ac teriz ed by s imilarity, but are n ot t est ed in manuf act uring. Thi s specification is
based on c lock cyc le by clo ck cycle mea surement s. To calculat e the ef fective jitter for in dividual time bases
or communication clocks use this formula:
TABLE 24-18: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
AC CHARACTERISTICS Standard Operating C on diti ons : 3 .0 V to 3. 6V (un les s otherw is e s tated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
OS56 FHPOUT On-Chip 16x PLL CCO
Frequency 112 118 120 MHz
OS57 FHPIN On-Chip 16x PLL Phase
Detector Input Frequency 7.0 7.37 7.5 MHz
OS58 TSU Frequency Generator Lock
Time ——10µs
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
Peripheral Clock Jitter DCLK
FOSC
Peripheral Bit Rate Clock
--------------------------------------------------------------
------------------------------------------------------------------------=
For example: FOSC = 32 MHz, DCLK = 3%, SPI bit rate clock (i.e., SCKx) is 2 MHz.
SPI SCK Jitter DCLK
32 MHz
2 MHz
--------------------
------------------------------3%
16
----------3%
4
--------0.75%====
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 24-19: AC CHARACTERISTICS: INTERNAL FRC ACCURACY
AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for Extended
Param
No. Characteristic Min Typ Max Units Conditions
Internal FRC Accuracy @ FRC Frequency = 7. 37 MHz(1)
F20a FRC -2 — +2 % -40°C TA +85°C VDD = 3.0-3.6V
F20b FRC -5 — +5 % -40°C TA +125°C VDD = 3.0- 3.6V
Note 1: Frequency calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.
TABLE 24-20: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Characteristic Min Typ Max Units Conditions
LPR C @ 32.768 kHz(1)
F21a LPRC -20 ±6 +20 % -40°C TA +85°C VDD = 3.0-3.6 V
F21b LPRC -70 — +70 % -40°C TA +125°C VDD = 3.0-3.6V
Note 1: Change of LPRC frequency as VDD chang es .
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 304 2008-2014 Microchip Technology Inc.
FIGURE 24-3: I/O TIMING CHARACTERISTICS
Note: Refer to Figure 24-1 for load conditions.
I/O Pin
(Input)
I/O Pin
(Output)
DI35
Old Value New Value
DI40
DO31
DO32
TABLE 24-21: I/O TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
DO31 TIOR Port Output Rise Time:
4x Source Driver Pins – RA0-RA2,
RB0-RB2, RB5-RB10, RB15, RC1,
RC2, RC9, RC10
—1025nsRefer to Figure 24-1
for test conditions
8x Source Driver Pins – RC0,
RC3-RC8, RC11-RC13 — 8 20 ns
16x Source Driver Pins – RA3,
RA4, RB3, RB4, RB11-RB14 — 6 15 ns
DO32 TIOF Port Output Fall Time:
4x Source Driver Pins – RA0-RA2,
RB0-RB2, RB5-RB10, RB15, RC1,
RC2, RC9, RC10 —1025ns
Refer to Figure 24-1
for test conditions
8x Source Driver Pins – RC0,
RC3-RC8, RC11-RC13 — 8 20 ns
16x Source Driver Pins – RA3,
RA4, RB3, RB4, RB11-RB14 — 6 15 ns
DI35 TINP INTx Pin High or Low Time (input) 20 — — ns
DI40 TRBP CNx High or Low Ti me (input) 2 — — TCY
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
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dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 24-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER T IMING CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY11
SY10
SY20
SY13
I/O Pins
SY13
Note: Refer to Figure 24-1 for load conditions.
FSCM
Delay
SY35
SY30
SY12
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 306 2008-2014 Microchip Technology Inc.
TABLE 24-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SY10 TMCLMCLR Pulse Width (low) 2 — — s -40°C to +85°C
SY11 TPWRT Power-up Timer Period — 2
4
8
16
32
64
128
— ms -40°C to +85°C,
User programmable
SY12 TPOR Power-on Reset Delay 3 10 30 s -40°C to +85°C
SY13 TIOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset 0.68 0.72 1.2 s
SY20 TWDT1 Wa tchdog T imer T ime-out Pe riod — — — ms S ee Section 21.4 “Watch-
dog Timer (WDT)” and
LPRC Param e t er F21a
(Table 24-20)
SY30 TOST Oscillator Start-up Time — 1024 TOSC ——TOSC = OSC1 period
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2008-2014 Microchip Technology Inc. DS70000318G-page 307
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 24-5: TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS
Note: Refer to Figure 24-1 for load conditions.
Tx11
Tx15
Tx10
Tx20
TMRx OS60
TxCK
TABLE 24-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +1 25°C for Extended
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
TA10 TTXH T1CK High
Time Synchronous,
no prescaler TCY + 20 — — ns Must also meet
Parameter TA15,
N = Prescale value
(1, 8, 64, 256)
Synchronous,
with prescaler (TCY + 20)/N — — ns
Asynchronous 20 — — ns
TA11 TTXLT1CK Low
Time Synchronous,
no prescaler TCY + 20 — — ns Must also meet
Parameter TA15,
N = Prescale value
(1, 8, 64, 256)
Synchronous,
with prescaler (TCY + 20)/N — — ns
Asynchronous 20 — — ns
TA15 TTXP T1CK Input
Period Synchronous,
no prescaler 2 TCY + 40 — — ns
Synchronous,
with prescaler Greater of:
40 ns or
(2 TCY + 40)/N
— — — N = Prescale value
(1, 8, 64, 256)
Asynchronous 40 — — ns
OS60 FT1 T1CK Oscillator Input
Frequency Range (oscillator
enabled by setting bit, TCS
(T1CON<1>))
DC — 50 kHz
TA20 TCKEXTMRL Delay from External T1CK
Clock Edge to T imer Incr ement 0.75 TCY + 40 — 1.75 TCY + 40 —
Note 1: Timer1 is a Type A timer.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 308 2008-2014 Microchip Technology Inc.
TABLE 24-24: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwis e stated)
Operating temperature -40 °C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
TB10 TTXH T2CK High
Time Synchronou s G re a t e r o f :
20 ns or
(TCY + 20)/N
— — ns Must also meet
Parameter TB15,
N = Prescale value
(1, 8, 64, 256)
TB11 TTXL T2CK Low
Time Synchronou s G re a t e r o f :
20 ns or
(TCY + 20)/N
— — ns Must also meet
Parameter TB15,
N = Prescale value
(1, 8, 64, 256)
TB15 TTXP T2CK Input
Period Sync hronou s Gr e a t e r o f:
40 ns or
(2 TCY + 40)/N
— — ns N = Prescale value
(1, 8, 64, 256)
TB20 TCKEXTMRL Delay from External T2CK
Clock Edge to Timer
Increment
0.75 TCY + 40 — 1.75 TCY + 40 ns
TABLE 24-25: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ Max Units Conditions
TC10 TTXH T3CK High
Time Synchronous TCY + 20 — — ns Must also meet
Parameter TC15
TC11 TTXLT3CK Low
Time Synchronous TCY + 20 — — ns Must also meet
Parameter TC15
TC15 TTXP T3CK Input
Period Synchronous,
with pr esc al er 2 TCY + 40 — — ns
TC20 TCKEXTMRL Delay fr om External T3CK
Clock Edge to Timer
Increment
0.75 TCY + 40 — 1.75 TCY + 40 —
2008-2014 Microchip Technology Inc. DS70000318G-page 309
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 24-6: INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
FIGURE 24-7: OUTPUT COMPARE x MODULE (OCx) TIMING CHARACTERISTICS
TABLE 24-26: INPUT CAPTURE x TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Indu stri al
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Max Units Conditions
IC10 TccL ICx Input Low Time No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
IC11 TccH ICx Input High Time No prescaler 0 .5 TCY + 20 — ns
With prescaler 10 — ns
IC15 TccP ICx Input Period (TCY + 40)/N — ns N = Prescale
value (1, 4, 16)
Note 1: These parameters are characterized but not tested in manufacturing.
TABLE 24-27: OUTPUT COMPARE x MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwis e stated)
Ope rati ng temperature -40 °C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ Max Units Conditions
OC10 TccF OCx Outpu t Fall Time — — — ns See Parameter DO32
OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31
Note 1: These parameters are characterized but not tested in manufacturing.
ICx
IC10 IC11
IC15
Note: Refer to Figure 24-1 for load conditions.
OCx
OC11 OC10
(Output Compare
Note: Refer to Figure 24-1 for load conditions.
or PWM Mode)
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 310 2008-2014 Microchip Technology Inc.
FIGURE 24-8: OCx/PWMx MODULE TIMING CHARACTERISTICS
OCFA
OCx
OC15
Active Tri-State
OC20
TABLE 24-28: SIMPLE OCx/PWMx MODE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwis e stated)
Ope rati ng temperature -40 °C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ Max Units Conditions
OC15 TFD Fault Input to PWMx I/O
Change ——TCY + 20 ns
OC20 TFLT Fault Input Pulse Width TCY + 20 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
2008-2014 Microchip Technology Inc. DS70000318G-page 311
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 24-9: HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS
FIGURE 24-10: HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS
FLTx
PWMx
MP20
MP30
PWMx
MP11 MP10
Note: Refer to Figure 24-1 for load conditions.
TABLE 24-29: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwis e stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ Max Units Conditions
MP10 TFPWM PWMx Output Fall Time — 2.5 — ns
MP11 TRPWM PWMx Output Rise Time — 2.5 — ns
MP20 TFD Fault Input to PWM
I/O Chan ge ——15ns
MP30 TFH Minimu m PWMx Fault Pulse
Width 8 — — ns DTC<1:0> = 10
MP31 TPDLY Tap Delay 1.04 — — ns ACLK = 120 MHz
MP32 ACLK PWMx Input Clock — — 120 MHz See Note 2
Note 1: These parameters are characterized but not tested in manufacturing.
2: This parameter is a maximum allowed input clock for the PWMx module.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 312 2008-2014 Microchip Technology Inc.
TABLE 24-30: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY
FIGURE 24-11: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING
CHARACTERISTICS
FIGURE 24-12: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING
CHARACTERISTICS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise sta ted)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex) CKE CKP SMP
15 MHz Table 24-31 ——0,10,10,1
9 MHz — Table 24-32 —10,11
9 MHz — Table 24-33 —00,11
15 MHz — — Table 24-34 100
11 MHz — — Table 24-35 110
15 MHz — — Table 24-36 010
11 MHz — — Table 24-37 000
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SP10
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
SP30, SP31
Note: Refer to Figure 24-1 for load conditions.
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
Note: Refer to Figure 24-1 for load conditions.
SP36
SP10
2008-2014 Microchip Technology Inc. DS70000318G-page 313
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 24-31: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
AC CHARACTERISTICS
St a ndard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP10 TscP Maximum SCKx Frequency — — 15 MHz See Note 3
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32
and Note 4
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV SDOx Data Ou tput Valid after
SCKx Edge —620ns
SP36 TdiV2scH,
TdiV2scL SDOx Data Output Setup to
First SCKx Edge 30 — — ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 314 2008-2014 Microchip Technology Inc.
FIGURE 24-13: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
CHARACTERISTICS
TABLE 24-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP10 TscP Maximum SCKx Frequency — — 9 MHz See Note 3
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32
and Note 4
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDO x Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV SDOx Data Output Valid after
SCKx Edge —620ns
SP36 TdoV2sc,
TdoV2scL SDOx Data Output Setup to
First SCKx Edge 30——ns
SP40 TdiV2scH,
TdiV2scL Setup Time of SDIx Data
Input to SCKx Edge 30——ns
SP41 TscH2diL,
TscL2diL Hold Time of SDIx Data Input
to SCKx Edge 30——ns
Note 1: These p aram et ers are charac teri ze d, but are not tes ted in manufa ct urin g.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
Note: Refer to Figure 24-1 for load conditions.
SP36
SP41
LSb In
Bit 14 - - - -1
SDIx
SP40
SP10
MSb In
2008-2014 Microchip Technology Inc. DS70000318G-page 315
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 24-14: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
CHARACTERISTICS
TABLE 24-33: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP10 TscP Maximum SCKx Frequency — — 9 MHz -40ºC to +125ºC and
see Note 3
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32
and Note 4
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and Note 4
SP31 TdoR SDO x Data Output Rise Time — — — ns See Parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV SDOx Data Output Valid after
SCKx Edge —620ns
SP36 TdoV2scH,
TdoV2scL SDOx Data Output Setup to
First SCKx Edge 30——ns
SP40 TdiV2scH,
TdiV2scL Setup Time of SDIx Data
Input to SCKx Edge 30——ns
SP41 TscH2diL,
TscL2diL Hold Time of SDIx Data Input
to SCKx Edge 30——ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
SP40 SP41
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
LSb In
Bit 14 - - - -1
SP30, SP31
SP30, SP31
Note: Refer to Figure 24-1 for load conditions.
SP10
MSb In
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 316 2008-2014 Microchip Technology Inc.
FIGURE 24-15 : SPIx SLAV E MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
SP60
SP30, SP31
MSb Bit 14 - - - - - -1 LSb
SP51
Bit 14 - - - -1 LSb In
SP35
SP52
SP73
SP72
SP72
SP73
SP70
SP40
SP41
Note: Refer to Figure 24-1 for load conditions.
SP50
MSb In
2008-2014 Microchip Technology Inc. DS70000318G-page 317
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 24-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise st ated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP70 TscP Maximum SCKx Input
Frequency ——15MHzSee Note 3
SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32
and No te 4
SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31
and No te 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and No te 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and No te 4
SP35 TscH2doV,
TscL2doV SDOx Data Output Valid after
SCKx Edge —620ns
SP36 TdoV2scH,
TdoV2scL SDOx Data Output Setup to
First SCKx Edge 30 — — ns
SP40 TdiV2scH,
TdiV2scL Setup Time of SDIx Data Input
to SCKx Edge 30 — — ns
SP41 TscH2diL,
TscL2diL Hold Time of SDIx Data Input
to SCKx Edge 30 — — ns
SP50 TssL2scH,
TssL2scL SSx to SCKx or SCKx Input 120 — — ns
SP51 TssH2doZ SSx to SDOx Output
High-Impedance(4) 10 — 50 ns
SP52 TscH2ssH
TscL2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4
SP60 TssL2doV SDOx Data Output Valid after
SSx Edge ——50ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the Master must
not violate this specif ication.
4: Assumes 50 pF load on all SPIx pins.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 318 2008-2014 Microchip Technology Inc.
FIGURE 24-16 : SPIx SLAV E MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
SP60
SP30, SP31
MSb Bit 14 - - - - - -1 LSb
SP51
Bit 14 - - - -1 LSb In
SP35
SP52
SP52
SP73
SP72
SP72
SP73
SP70
SP40
SP41
Note: Re fe r to Figure 24-1 for load conditions.
MSb In
SP50
2008-2014 Microchip Technology Inc. DS70000318G-page 319
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 24-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise st ated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP70 TscP Maximum SCKx Input
Frequency ——11MHzSee Note 3
SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32
and No te 4
SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31
and No te 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and No te 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and No te 4
SP35 TscH2doV,
TscL2doV SDOx Data Output Valid after
SCKx Edge —620ns
SP36 TdoV2scH,
TdoV2scL SDOx Data Output Setup to
First SCKx Edge 30 — — ns
SP40 TdiV2scH,
TdiV2scL Setup Time of SDIx Data Input
to SCKx Edge 30 — — ns
SP41 TscH2diL,
TscL2diL Hold Time of SDIx Data Input
to SCKx Edge 30 — — ns
SP50 TssL2scH,
TssL2scL SSx to SCKx or SCKx Input 120 — — ns
SP51 TssH2doZ SSx to SDOx Output
High-Impedance(4) 10 — 50 ns
SP52 TscH2ssH
TscL2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4
SP60 TssL2doV SDOx Data Output Valid after
SSx Edge ——50ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The min imum cloc k period f or SCKx is 91 ns. Theref ore, the SCKx clock ge nerated by the Master m ust not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 320 2008-2014 Microchip Technology Inc.
FIGURE 24-17 : SPIx SLAV E MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS
SSX
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SDOX
SP50
SP40
SP41
SP30, SP31 SP51
SP35
MSb LSb
Bit 14 - - - - - -1
Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
Note: Refer to Figure 24-1 for load conditions.
SDIX
SP70
MSb In
2008-2014 Microchip Technology Inc. DS70000318G-page 321
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 24-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise st ated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP70 TscP Maximum SCKx Input
Frequency ——15MHzSee Note 3
SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32
and No te 4
SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31
and No te 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and No te 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and No te 4
SP35 TscH2doV,
TscL2doV SDOx Data Output Valid after
SCKx Edge —620ns
SP36 TdoV2scH,
TdoV2scL SDOx Data Output Setup to
First SCKx Edge 30 — — ns
SP40 TdiV2scH,
TdiV2scL Setup Time of SDIx Data Input
to SCKx Edge 30 — — ns
SP41 TscH2diL,
TscL2diL Hold Time of SDIx Data Input
to SCKx Edge 30 — — ns
SP50 TssL2scH,
TssL2scL SSx to SCKx or SCKx Input 120 — — ns
SP51 TssH2doZ SSx to SDOx Output
High-Impedance 10 — 50 ns See Note 4
SP52 TscH2ssH
TscL2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the Master must
not violate this specif ication.
4: Assumes 50 pF load on all SPIx pins.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 322 2008-2014 Microchip Technology Inc.
FIGURE 24-18 : SPIx SLAV E MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS
SSX
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SDOx
SP50
SP40
SP41
SP30, SP31 SP51
SP35
MSb LSb
Bit 14 - - - - - -1
Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
Note: Refer to Figure 24-1 for load conditions.
SDIx
SP70
MSb In
2008-2014 Microchip Technology Inc. DS70000318G-page 323
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 24-37: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise st ated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min Typ(2)Max Units Conditions
SP70 TscP Maximum SCKx Input
Frequency ——11MHzSee Note 3
SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32
and No te 4
SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31
and No te 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
and No te 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
and No te 4
SP35 TscH2doV,
TscL2doV SDOx Data Output Valid after
SCKx Edge —620ns
SP36 TdoV2scH,
TdoV2scL SDOx Data Output Setup to
First SCKx Edge 30 — — ns
SP40 TdiV2scH,
TdiV2scL Setup Time of SDIx Data Input
to SCKx Edge 30 — — ns
SP41 TscH2diL,
TscL2diL Hold Time of SDIx Data Input
to SCKx Edge 30 — — ns
SP50 TssL2scH,
TssL2scL SSx to SCKx or SCKx Input 120 — — ns
SP51 TssH2doZ SSx to SDOx Output
High-Impedance 10 — 50 ns See Note 4
SP52 TscH2ssH
TscL2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: The min imum cloc k period f or SCKx is 91 ns. Theref ore, the SCKx clock ge nerated by the Master m ust not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 324 2008-2014 Microchip Technology Inc.
FIGURE 24-19: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
FIGURE 24-20: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
SCLx
SDAx
Start
Condition Stop
Condition
Note: Refer to Figure 24-1 for load conditions.
IM30
IM31
IM33
IM34
IM11 IM10 IM33
IM11 IM10
IM20
IM26 IM25
IM40 IM40 IM45
IM21
SCLx
SDAx
In
SDAx
Out
Note: Refer to Figure 24-1 for load conditions.
2008-2014 Microchip Technology Inc. DS70000318G-page 325
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 24-38: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min(1)Max Units Conditions
IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM20 TF:SCL SDAx and SCLx
Fall Time 100 kHz mode — 300 ns CB is specified to be
from 10 pF to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(2)— 100 ns
IM21 TR:SCL SDAx and SCLx
Rise Time 100 kHz mode — 1000 ns CB is specified to be
from 10 pF to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(2)— 300 ns
IM25 TSU:DAT Data Input
Setup Time 100 kHz mode 250 — ns
400 kHz mode 100 — ns
1 MHz mode(2)40 — ns
IM26 THD:DAT Data Input
Hold Time 100 kHz mode 0 — s
400 kHz mode 0 0.9 s
1 MHz mode(2)0.2 — s
IM30 TSU:STA Start Cond ition
Setup Time 100 kHz mode TCY/2 (BRG + 1) — s Only relevant for
Repeated Start
condition
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM31 THD:STA Start Condition
Hold Time 100 kHz mode TCY/2 (BRG + 1) — s After this period the
first clock pulse is
generated
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM33 TSU:STO Stop Condit ion
Setup Time 100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns
Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns
1 MHz mode(2)TCY/2 (BRG + 1) — ns
IM40 TAA:SCL Output Valid
From Clock 100 kHz mode — 3500 ns
400 kHz mode — 1000 ns
1 MHz mode(2)— 400 ns
IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be
free before a new
transmission can start
400 kHz mode 1.3 — s
1 MHz mode(2)0.5 — s
IM50 CBBus Capacitive Loading — 400 pF
IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 3
Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to “Inter-Integrated Circuit (I2C™)”
(DS70000195) in the “dsPIC33/PIC24 Family Reference Manual ”.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 326 2008-2014 Microchip Technology Inc.
FIGURE 24-21: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
FIGURE 24-22: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
SDAx
Start
Condition Stop
Condition
IS31
IS30
IS34
IS33
IS30 IS31 IS33
IS11
IS10
IS20
IS26 IS25
IS40 IS40 IS45
IS21
SCLx
SDAx
In
SDAx
Out
2008-2014 Microchip Technology Inc. DS70000318G-page 327
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 24-39: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwis e stated)
Operati ng tem pe rature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic Min Max Units Conditions
IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
1 MHz mode(1)0.5 — s
IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
1 MHz mode(1)0.5 — s
IS20 TF:SCL SDAx and SCLx
Fall Time 100 kHz mode — 300 ns CB is specified to be from
10 pF to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(1)— 100 ns
IS21 TR:SCL SDAx and SCLx
Rise Time 100 kHz mode — 1000 ns CB is specified to be from
10 pF to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(1)— 300 ns
IS25 TSU:DAT Data Input
Setup Time 100 kHz mode 250 — ns
400 kHz mode 100 — ns
1 MHz mode(1)100 — ns
IS26 THD:DAT Data Input
Hold Time 100 kHz mode 0 — s
400 kHz mode 0 0.9 s
1 MHz mode(1)00.3s
IS30 TSU:STA Start Condi tion
Setup Time 100 kHz mode 4.7 — s Only relevant for Repeated
Start conditio n
400 kHz mode 0.6 — s
1 MHz mode(1)0.25 — s
IS31 THD:STA Start Condition
Hold Time 100 kHz mode 4.0 — s After this period, the first
clock pulse is generated
400 kHz mode 0.6 — s
1 MHz mode(1)0.25 — s
IS33 TSU:STO Stop Condition
Setup Time 100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
1 MHz mode(1)0.6 — s
IS34 THD:STO Stop Condition
Hold Time 100 kHz mode 4000 — ns
400 kHz mode 600 — ns
1 MHz mode(1)250 — ns
IS40 TAA:SCL Output Valid
From Clock 100 kHz mode 0 3500 ns
400 kHz mode 0 1000 ns
1 MHz mode(1)0 350 ns
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free
before a new tr ansmission
can start
400 kHz mode 1.3 — s
1 MHz mode(1)0.5 — s
IS50 CBBus Capaciti ve Loading — 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 328 2008-2014 Microchip Technology Inc.
=
TABLE 24-40: 10-BIT HIGH-SPEED ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions (see Note 2): 3.0V and 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +1 25°C for Exten de d
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
Device Supply
AD01 AVDD Module VDD Supply — — — — AVDD is internally connected to
VDD; s e e Pa rame te r DC10 in
Table 24-4
AD02 AVSS Module VSS Supply — — — — AVSS is internally connected
to VSS
Analog Input
AD10 VINH-VINL Full-Scale Input Span VSS —VDD V
AD11 VIN Absolute Input Voltage AVSS —AVDD V
AD12 IAD Operating Current — 8 — mA
AD13 — Leakage Current — ±0.6 — AVINL = A VSS = 0V, A VDD = 3.3V ,
Source Impedance = 100
AD17 RIN Recommended Impedance
Of Analog Voltage Source — — 100
DC Accuracy @ 1.5 Msps
AD20A Nr Reso lut ion 10 Dat a Bit s
AD21A INL Integral Nonlinearity -0.5 -0.3/+0.5 +1.2 LSb
AD22A DNL Differential Nonlinearity -0.9 ±0.6 +0.9 LSb
AD23A GERR Gain Error 13 15 22 LSb
AD24A EOFF Offset Error 6 7 8 LSb
AD25A — Monotonicity(1)— — — — Guaranteed
DC Accuracy @ 1.7 Msps
AD20B Nr Reso lut ion 10 Dat a Bit s
AD21B INL Integral Nonlinearity -0.5 -0.4/+1.1 +1.8 LSb
AD22B DNL Differential Nonlinearity -1.0 ±1.0 +1.5 LSb
AD23B GERR Gain Error 13 15 22 LSb
AD24B EOFF Offset Error 6 7 8 LSb
AD25B — Monotonicity(1)— — — — Guaranteed
DC Accuracy @ 2.0 Msps
AD20C Nr Resolution 10 Data Bits
AD21C INL Integral Nonlinearity -0.8 -0.5/+1.8 +2.8 LSb
AD22C DNL Differential Nonlinearity -1.0 -1.0/+1.8 +2.8 LSb
AD23C GERR Gain Error 14 16 23 LSb
AD24C EOFF Offset Error 6 7 8 LSb
AD25C — Monotonicity(1)— — — — Guaranteed
Dynamic Performance
AD30 THD Total Harmoni c Disto r tio n — -73 — dB
AD31 SINAD Signal to Noise and Distortion — 58 — dB
AD32 SFDR Spurious Free Dynamic Range — -73 — dB
AD33 FNYQ Input Signal Bandwidth — — 1 MHz
AD34 ENOB Effective Number of Bits — 9.4 — bits
Note 1: The Analog-to-Digital conversion result never decreases with an increase in input voltage, and has no
missing codes.
2: Module is functional at VBOR < VDD < VDDMIN, but with degrade d perfo r ma nc e. Module function ali ty is
tested but not characterized.
2008-2014 Microchip Technology Inc. DS70000318G-page 329
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
FIGURE 24-23: ANALOG-TO-DIGITA L CONVERSION TIMING PER INPUT
TABLE 24-41: 10-BIT, HIGH-SPEED ADC MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions (see Note 2): 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ(1)Max. Units Conditions
Clock Parameters
AD50b TAD ADC Clock Perio d 35.8 — — ns
Conversion Rate
AD55b tCONV Conversion Time — 14 TAD ——
AD56b FCNV Throughput Rate
Devices with Si ngle SAR — — 2.0 Msps
Device s with Dual SARs — — 4. 0 Msps
Timing Parameters
AD63b tDPU Time to Stabilize Analog Stage
from ADC Off to ADC On 1.0 — 10 s
Note 1: These parameters are characterized but not tested in manufacturing.
2: Module is functional at VBOR < VDD < VDDMIN, but with degrade d perfo r ma nc e. Mod ule funct ion ali ty is
tested but not characterized.
TAD
ADC Data
ADBUFxx
98 210
Old Data N ew Data
CONV
ADC Clock
Trigger Pulse TCONV
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 330 2008-2014 Microchip Technology Inc.
TABLE 24-42: COMPARATOR MODULE SPECIFICATIONS
DC CHARACTERISTICS Standard Operating Conditions (see Note 2): 3.0V to 3.6V
Operating temperature: -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
No. Symbol Characteristic Min Typ Max Units Comments
CM10 VIOFF Input Offset Voltage -58 +14/-40 66 mV
CM11 VICM Input Commo n-Mode
Voltage Range(1)0—AVDD – 1.5 V
CM12 VGAIN Open Loop Gai n(1) 90 — — db
CM13 CMRR Common-Mode
Rejecti o n Ratio(1)70 — — db
CM14 TRESP Large Signal Response 21 30 49 ns V+ input step of 100 mv while
V- input held at AVDD/2. Delay
measure d from anal og in put p in to
PWM output pin .
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
2: Module is functional at VBOR < VDD < VDDMIN, but with degraded performance. Module functionality is
tested but not characterized.
TABLE 24-43: DAC MODULE SPECIFICATIONS
AC and DC CHARACTERISTICS Standard Operating Conditions (see Note 2): 3.0V to 3.6V
Operating temperature: -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
No. Symbol Characteristic Min Typ Max Units Comments
DA01 EXTREF External Voltage Reference(1)0AVDD – 1.6 V
DA08 INTREF Internal Voltage Reference(1)1.25 1.32 1.41 V
DA02 CVRES Resolution 10 Bits
DA03 INL Integral Nonlinearity Error -7 -1 +7 LSB AVDD = 3.3V,
DACREF = (AVDD/2)V
DA04 DNL Differential Nonlinearity Error -5 -0.5 +5 LSB
DA05 EOFF Offset Erro r 0.4 -0.8 2.6 %
DA06 EG Gain Error 0.4 -1.8 5.2 %
DA07 TSET Settling Time(1)711 1551 2100 n se c Measu red wh en
range = 1 (high range),
and CMREF< 9:0>
transitions from 0x1FF
to 0x300.
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
2: Module is functional at VBOR < VDD < VDDMIN, but with degraded performance. Module functionality is
tested but not characterized.
2008-2014 Microchip Technology Inc. DS70000318G-page 331
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 24-44: DAC OUTPUT BUFFER DC SPECIFICATIONS
DC CHARACTERISTICS Standard Operating Conditions (see Note 1): 3 .0V t o 3.6V
Operating temperature: -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
No. Symbol Characteristic Min Typ Max Units Comments
DA10 RLOAD Resistive Output Load
Impedance 3K — —
DA11 CLOAD Output Load Capacitance — 20 35 pF
DA12 IOUT Output Current Drive
Strength -1740 ±1400 +1770 A Sink and sour c e
DA13 VRANGE Ful l Output Drive S treng th
Voltage Range AVSS + 250 mV — AVDD – 900 mV V
DA14 VLRANGE Output Drive Voltage
Range at Reduced
Current Drive of 50 A
AVSS + 50 mV — AVDD – 500 mV V
DA15 IDD Current Consumed when
Module is Enabled,
High-Power Mode
369 626 948 A Modu le w ill always
consume this
current even if no
load is connected to
the output
DA16 ROUTON Output Impedance when
Module is Enabled — 1200 —
Note 1: Module is functional at VBOR < VDD < VDDMIN, but with degraded performance. Module functionality is
tested but not characterized.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 332 2008-2014 Microchip Technology Inc.
NOTES:
2008-2014 Microchip Technology Inc. DS70000318G-page 333
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
25.0 HIGH-TEMPERATURE EL ECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 electrical characteristics
for devices operating in an ambient temperature range of -40°C to +150°C.
The spec ifications be tween -40°C to +15 0°C are identical to those s hown in Section 24.0 “Electri cal Charac teristics”
for operation between -40°C to +125°C, with the exception of the parameters listed in this section.
Parameters in this section begin with an H, which denotes High temperature. For example, Parameter DC10 in
Section 24.0 “Electrical Characteristics” is the Industrial and Extended temperature equivalent of HDC10.
Absolute maximum ratings for the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 high-temperature devices
are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability.
Functional operation of the device at these or any other conditions above the parameters indicated in the operation
listings of this specification is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias(3).........................................................................................................-40°C to +150°C
Storage temperature.............................................................................................................................. -65°C to +160°C
Volta ge on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(4) ....................................................-0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(4) ....................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(4) .................................................... -0.3V to 5.6V
Maximum current out of VSS pin .............................................................................................................................60 mA
Maximum current into VDD pin(2).............................................................................................................................60 mA
Maximum junction temperature.............................................................................................................................+155°C
Maximum current sourced/sunk by any 4x I/O pin....................................................................................................4 mA
Maximum current sourced/sunk by any 8x I/O pin....................................................................................................8 mA
Maximum current sourced/sunk by any 16x I/O pin................................................................................................16 mA
Maximum current sunk by all ports combined ......................................................................................................180 mA
Maximum current sourced by all ports combined(2)..............................................................................................180 mA
Note: Programming of the Flash memory is not allowed above +125°C.
Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the
device . This is a stress rat ing only, and funct ion al op erat ion of the de vi ce at thos e or any othe r con ditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods can affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 25-2).
3: AEC-Q100 rel iability t est ing for de vi ces in tend ed to operate at 150 °C is 1 ,00 0 hou rs. Any design i n whic h
the tot al operating tim e from 125°C to 150°C wi ll be greater than 1, 000 hours is not warrante d without prior
written approval from Microchip Technology Inc.
4: Refer to the “Pin Diagrams” section for 5V tolerant pins.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 334 2008-2014 Microchip Technology Inc.
25.1 High-Temperature DC Characteristics
TABLE 25-1: OPERATING MIPS VS. VOLTAGE
Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog m odul es suc h as t he ADC, e tc., wil l func tion bu t with degrad ed perfo rmanc e belo w VDDMIN. Refer to
Parameter BO10 in Table 24-11 for BOR values.
TABLE 25-2: THERMAL OPERATING CONDITIONS
TABLE 25-3: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Characteristic VDD Range
(in Volts) Temperature Range
(in °C)
Max MIPS
dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04
— 3.0V to 3.6V(1)-40°C to +150°C 20
Rating Symbol Min Typ Max Unit
High-Temperature Devices
Operating Junction Temperature Range TJ-40 — +155 °C
Operating Ambient Temperature Range TA-40 — +150 °C
Power Dissipation:
Internal ch ip pow er dis sipatio n:
PINT = VDD x (IDD - IOH) PDPINT + PI/OW
I/O Pin Power Dissipation:
I/O = ({VDD - VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipa tion PDMAX (TJ - TA)/JA W
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise st ated)
Operating temperature -40°C TA +150°C for High Temperature
Parameter
No. Symbol Characteristic Min Typ Max Units Conditions
Operating Voltage
HDC10 Supply Voltage
VDD — 3.0 3.3 3.6 V -40°C to +150°C
2008-2014 Microchip Technology Inc. DS70000318G-page 335
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 25-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operati ng tem per ature -40°C TA +150°C for High Temperature
Parameter
No. Typical(1)Max Units Conditions
Power-Down Current (IPD)(2,4)
HDC60e 1000 2000 A +150°C 3.3V Base Power-Down Current
HDC61c 100 110 A +150°C 3.3V Watchdog Timer Current: IWDT(3)
Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated.
2: IPD (Sleep) current is me asured as follo ws:
• CPU core is off, oscillator is configured in EC mode and external clock active, OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• All peripheral modules are disabled (PMDx bits are all ones)
• The VREGS bit (RCON<8>) = 0 (i.e., core regulator is set to stand-by while the device is in
Sleep mode)
• JTAG disabled
3: The current is the additional current consumed when the WDT module is enabled. This current should
be added to the base IPD curren t.
4: These currents are measured on the device containing the most memory in this family.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 336 2008-2014 Microchip Technology Inc.
TABLE 25-5: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise st ated)
Operating temperature -40°C TA +150° C for High
Temperature
Param. Symbol Characteristic Min. Typ. Max. Units Conditions
DO10 VOL
Output Low Voltage
I/O Pins:
4x Sink Driver Pins –
RA0-RA2, RB0-RB2, RB5-
RB10, RB15, RC1, RC2 , RC9,
RC10
——0.4VIOL 3.6 mA, VDD = 3.3V
See Note 1
Output Low Voltage
I/O Pins:
8x Sink Driver Pins – RC0,
RC3-RC8, RC11-RC13
——0.4V IOL 6 mA, VDD = 3.3V
See Note 1
Output Low Voltage
I/O Pins:
16x Sink Driv er Pins – RA3,
RA4, RB3, RB4, RB11-RB14
——0.4VIOL 12 mA, VDD = 3.3V
See Note 1
DO20 VOH
Output High Voltage
I/O Pins:
4x Source Driver Pins –
RA0-RA2, RB0-RB2, RB5-
RB10, RB15, RC1, RC2 , RC9,
RC10
2.4 — — V IOL -4 mA, VDD = 3.3V
See Note 1
Output High Voltage
I/O Pins:
8x Source Driver Pins – RC0,
RC3-RC8, RC11-RC13
2.4 — — V IOL -8 mA, VDD = 3.3V
See Note 1
Output High Voltage
I/O Pins:
16x Sourc e Driver Pins – RA3,
RA4, RB3, RB4, RB11-RB14
2.4 — — V IOL -16 mA, VDD = 3.3V
See Note 1
DO20A VOH1
Output High Voltage
I/O Pins:
4x Source Driver Pins –
RA0-RA2, RB0-RB2, RB5-
RB10, RB15, RC1, RC2 , RC9,
RC10
1.5 — —
V
IOH -3.9 mA, VDD = 3.3V
See Note 1
2.0 — — IOH -3.7 mA, VDD = 3.3V
See Note 1
3.0 — — IOH -2 mA, VDD = 3.3V
See Note 1
Output High Voltage
I/O Pins:
8x Source Driver Pins – RC0,
RC3-RC8, RC11-RC13
1.5 — —
V
IOH -7.5 mA, VDD = 3.3V
See Note 1
2.0 — — IOH -6.8 mA, VDD = 3.3V
See Note 1
3.0 — — IOH -3 mA, VDD = 3.3V
See Note 1
Output High Voltage
I/O Pins:
16x Sourc e Driver Pins – RA3,
RA4, RB3, RB4, RB11-RB14
1.5 — —
V
IOH -15 mA, VDD = 3.3V
See Note 1
2.0 — — IOH -14 mA, VDD = 3.3V
See Note 1
3.0 — — IOH -7 mA, VDD = 3.3V
See Note 1
Note 1: Parameters are characterized, but not tested.
2008-2014 Microchip Technology Inc. DS70000318G-page 337
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 25-6: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +150°C for High Temperature
Param
No. Symbol Characteristic(1)Min Typ Max Units Conditions
Program Flash Memory
HD130 EPCell Endurance 10,0 00 — — E/W -40C to +150C(2)
HD134 TRETD Characteristic Retention 20 — — Year 1000 E/W cycles or less and no
other specifications are violated
Note 1: These parameters are assured by design, but are not characterized or tested in manufacturing.
2: Programming of the Flash memory is not allowed above +125°C.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 338 2008-2014 Microchip Technology Inc.
25.2 AC Characteristics and T iming
Parameters
The information contained in this section defines
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 AC char acteristi cs and t iming p arameters for high-
temperature devices. However, all AC timing
specifications in this section are the same as those in
Section 24.2 “AC Characteristics and Timing
Parameters”, with the exception of the parameters
listed in this section.
Parameters in this section begin with an H, which denotes
High temperature. For example, Parameter OS53 in
Section 24.2 “AC Characteristics and Timing
Parameters” is the Industrial and Extended temperature
equivalent of HOS53.
TABLE 25-7: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
FIGURE 25-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
TABLE 25-8: PLL CLOCK TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise st ated)
Operati ng tem pera ture -40°C TA +1 50°C for High Temperature
Operati ng voltag e VDD range as described in Table 25-1.
AC
CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +150°C for High Temperature
Param
No. Symbol Characteristic Min Typ Max Units Conditions
HOS53 DCLK CLKO Stability (Jitter)(1)-5 0.5 5 % Measured over 100 ms
period
Note 1: These p aram et ers are charac teri ze d, but are not tes ted in manufa ct urin g.
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL= 464
CL= 50 pF for all pins except OSC2
15 pF for OSC2 output
Load Cond itio n 1 – for all pins except OSC2 Load Condition 2 – for OSC2
2008-2014 Microchip Technology Inc. DS70000318G-page 339
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 25-9: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
TABLE 25-10: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Ope rati ng temperature -40 °C TA +150°C for High Temperature
Param
No. Symbol Characteristic(1)Min Typ Max Units Conditions
HSP35 TscH2doV,
TscL2doV SDOx Data Output Valid after
SCKx Edge —1025ns
HSP40 TdiV2scH,
TdiV2scL Setup Time of SDIx Data Input
to SCKx Edge 28 — — ns
HSP41 TscH2diL,
TscL2diL Hold Time of SDIx Data Input
to SCKx Edge 35 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +150°C for High Temperature
Param
No. Symbol Characteristic(1)Min Typ Max Units Conditions
HSP35 TscH2doV,
TscL2doV SDOx Data Output Valid after
SCKx Edge —1025ns
HSP36 TdoV2sc,
TdoV2scL SDOx Data Output Setup to
First SCKx Edge 35 — — ns
HSP40 TdiV2scH,
TdiV2scL Setup Time of SDIx Data Input
to SCKx Edge 28 — — ns
HSP41 TscH2diL,
TscL2diL Hold Time of SDIx Data Input
to SCKx Edge 35 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 340 2008-2014 Microchip Technology Inc.
TABLE 25-11: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
TABLE 25-12: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +150°C for High Temperature
Param
No. Symbol Characteristic(1)Min Typ Max Units Conditions
HSP35 TscH2doV,
TscL2doV SDOx Data Output Valid after
SCKx Edge ——35ns
HSP40 TdiV2scH,
TdiV2scL Setup Ti me of SDIx Data Input
to SCKx Edge 25 — — ns
HSP41 TscH2diL,
TscL2diL Hold T im e of SDIx Dat a Inp ut to
SCKx Edge 25 — — ns
HSP51 TssH2doZ SSx to SDOx Output
High-Impedance 15 — 55 ns See Note 2
Note 1: These parameters are characterized but not tested in manufacturing.
2: Assumes 50 pF load on all SPIx pins.
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +150°C for High Temperature
Param
No. Symbol Characteristic(1)Min Typ Max Units Conditions
HSP35 TscH2doV,
TscL2doV SDOx Data Output Valid after
SCKx Edge ——35ns
HSP40 TdiV2scH,
TdiV2scL Setup T i me of SDIx Dat a Input
to SCKx Edge 25 — — ns
HSP41 TscH2diL,
TscL2diL Hold Time of SDIx Data Input
to SCKx Edge 25 — — ns
HSP51 TssH2doZ SSx to SDOX Output
High-Impedance 15 — 55 ns See Note 2
HSP60 TssL2doV SDOx Data Output Valid after
SSx Edge ——55ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Assumes 50 pF load on all SPIx pins.
2008-2014 Microchip Technology Inc. DS70000318G-page 341
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
26.0 50 MIPS ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 electrical characteristics
for devices operating at 50 MIPS.
The specifications for 50 MIPS are identical to those shown in Section 24.0 “Electrical Characteristics”, with the
exception of the parameters listed in this section.
Paramete rs in thi s section begin wi th the le tter “M”, w hich den otes 50 MIPS ope ration. F or exam ple, Para meter DC 29a
in Section 24.0 “Electrical Characteristics”, is the up to 40 MIPS operation equivalent of MDC29a.
Absolute maximum ratings for the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 50 MIPS devices are listed
below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional
operation of the device at these or any other conditions above the parameters indicated in the operation listings of this
specification is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias...............................................................................................................-40°C to +85°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Volta ge on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to VSS(3) ...................................................-0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS, when Vdd 3.0V(3) ................................................. -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to Vss, when VDD < 3.0V(3)........................................-0.3V to (VDD + 0.3V)
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2)...........................................................................................................................250 mA
Maximum current sourced/sunk by any 4x I/O pin..................................................................................................15 mA
Maximum current sourced/sunk by any 8x I/O pin..................................................................................................25 mA
Maximum current sourced/sunk by any 16x I/O pin................................................................................................45 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2)...............................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device . This is a stress rat ing only, and funct ion al op erat ion of the de vi ce at thos e or any othe r con ditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 24-2).
3: See the “Pin Diagrams” section for 5V tole rant pins.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 342 2008-2014 Microchip Technology Inc.
26.1 DC Characteristics
TABLE 26-1: OPERATING MIPS VS. VOLTAGE
Characteristic VDD Range
(in Volts) Temp Range
(in °C)
Max MIPS
dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04
— 3.0-3.6V(1)-40°C to +85°C 50
Note 1: Overal l function al de vi ce operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog mo dules , such as the ADC, etc. , will fun ction but wi th degrad ed perform ance be low VDDMIN. Refer
to Parameter BO10 in Table 24-11 for BOR values.
TABLE 26-2: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
DC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Parameter
No. Typical Max Units Conditions
Operating Current (IDD)(1)
MDC29d 105 125 mA -40°C 3.3V 50 MIPSMDC29a 105 125 mA +25°C
MDC29b 105 125 mA +85°C
Note 1: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from
rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits
are zeroed)
• CPU executing while(1) statemen t
• JTAG is disabled
2008-2014 Microchip Technology Inc. DS70000318G-page 343
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
TABLE 26-3: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
DC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Parameter
No. Typical Max Units Conditions
Idle Current (IIDLE): Core Off, Clock On Base Current(1)
MDC45d 64 105 mA -40°C 3.3V 50 MIPSMDC45a 64 105 mA +25°C
MDC45b 64 105 mA +85°C
Note 1: Base Idle current (IIDLE) is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock active, OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits
are zeroed)
• The NVMSIDL bit (NVMCON<12>) = 1 (i.e., Flash regulator is set to standby while the device is in
Idle mode)
• JTAG is disabled
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 344 2008-2014 Microchip Technology Inc.
TABLE 26-4: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)(1)
DC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Parameter No. Typical Max Doze
Ratio Units Conditions
MDC74a 80 105 1:2 mA -40°C 3 .3V 50 MIPSMDC74f 65 105 1:64 mA
MDC74g 65 105 1:128 mA
MDC75a 81 105 1:2 mA +25°C 3.3V 50 MIPSMDC75f 65 105 1:64 mA
MDC75g 65 105 1:128 mA
MDC76a 81 105 1:2 mA +85°C 3.3V 50 MIPSMDC76f 65 105 1:64 mA
MDC76g 65 105 1:128 mA
Note 1: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDOZE measurements are as follows:
• Oscillator is configured in EC mode and external clock active, OSC1 is driven with external square
wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits
are zeroed)
• CP U executing while(1) statement
• JTAG is disabled
2008-2014 Microchip Technology Inc. DS70000318G-page 345
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
26.2 AC Characteristics and Timing Parameters
This section defines the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 AC characteristics and timing
parameters for 50 MIPS devices.
TABLE 26-5: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industri a l
Param
No. Symb Characteristic Min Typ(1)Max Units Conditions
MOS10 FIN External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC — 50 MHz EC
Oscilla tor C rys tal Freque ncy 3.5
10 —
—10
50 MHz
MHz XT
HS
MOS20 TOSC TOSC = 1/FOSC 10 — DC ns
MOS25 TCY Instruction Cycle Time(2)20 — DC ns
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “Min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“Max.” cycle time limit is “DC” (no clock) for all devices.
TABLE 26-6: SIMPLE OCx/PWMx MODE TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V
(unless otherwis e stated)
Operating temperature -40°C TA +85°C for Industrial
Param
No. Symbol Characteristic(1)Min Typ Max Units Conditions
MOC15 TFD Fault Input to PWMx I/O
Change ——TCY + 10 ns
MOC20 TFLT Fault Input Pulse Width TCY + 10 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 346 2008-2014 Microchip Technology Inc.
NOTES:
2008-2014 Microchip Technology Inc. DS70000318G-page 347
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
27.0 DC AND AC DEVICE CHARACTE RISTICS GRAPHS
FIGURE 27-1: VOH – 4x DRIVER PINS
FIGURE 27-2: VOH – 8x DRIVER PINS
FIGURE 27-3: VOH – 16x DRIVER PINS
Note: The grap hs provi ded fo llowin g this not e are a stati stica l summary based on a li mite d number of samples an d are pro vided for des ign guidance purposes
only. The performan ce characteris tics listed herei n are not tested or gua ranteed. In some graphs, the dat a presented may be ou tside the sp ecified operat ing
range (e.g., outside specified power supply range) and therefore, outside the warranted range.
-0.030
-0.025
-0.020
-0.015
-0.010
IOH (A)
-0.030
-0.025
-0.020
-0.015
-0.010
-0.005
0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
IOH (A)
VOH (V)
3V
3.3V
3.6V
Absolute Maximum
-0.040
-0.035
-0.030
-0.025
-0.020
-0.015
IOH (A)
-0.040
-0.035
-0.030
-0.025
-0.020
-0.015
-0.010
-0.005
0.000
0.00 1.00 2.00 3.00 4.00
IOH (A)
VOH (V)
3V
3.3V
3.6V
Absolute Maximum
-0.080
-0.070
-0.060
-0.050
-0.040
-0.030
-0.020
IOH (A)
-0.080
-0.070
-0.060
-0.050
-0.040
-0.030
-0.020
-0.010
0.000
0.00 1.00 2.00 3.00 4.00
IOH (A)
VOH (V)
3.3V
3.6V
Absolute Maximum
3V
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 348 2008-2014 Microchip Technology Inc.
FIGURE 27-4: VOL – 4x DRIVER PINS
FIGURE 27-5: VOL – 8x DRIVER PINS
FIGURE 27-6: VOL – 16x DRIVER PINS
0.010
0.015
0.020
0.025
0.030
0.035
0.040
IOL (A)
0.000
0.005
0.010
0.015
0.020
0.025
0.030
0.035
0.040
0.00 1.00 2.00 3.00 4.00
IOL (A)
VOL (V)
3V
3.3V
3.6V
Absolute Maximum
0.020
0.030
0.040
0.050
0.060
IOL (A)
0.000
0.010
0.020
0.030
0.040
0.050
0.060
0.00 1.00 2.00 3.00 4.00
IOL (A)
VOL (V)
3V
3.3V
3.6V
Absolute Maximum
0.040
0.060
0.080
0.100
0.120
IOL (A)
0.000
0.020
0.040
0.060
0.080
0.100
0.120
0.00 1.00 2.00 3.00 4.00
IOL (A)
VOL (V)
3V
3.3V
3.6V
Absolute Maximum
2008-2014 Microchip Technology Inc. DS70000318G-page 349
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
FIGURE 27-7: TYPICAL IPD CURRENT @ VDD = 3 .3V
FIGURE 27-8: TYPICAL IDD CURRENT @ VDD = 3.3V
FIGURE 27-9: TYPICAL IDOZE CURRENT @ VDD = 3.3V
FIGURE 27-10: TYPICAL IIDLE CURRENT @ VDD = 3.3V
420
620
820
1020
1220
IPD Current (µA)
20
220
420
620
820
1020
1220
-40256585125150
IPD Current (µA)
Temperature (Celsius)
70
80
90
100
110
120
Average (mA)
40
50
60
70
80
90
100
110
120
10 20 30 40 50
Average (mA)
MIPS
48
58
68
78
88
98
108
118
O
ZE Current (mA)
18
28
38
48
1:1 1:2 1:64 1:128
ID
O
Doze Ratio
50 MIPS
40 MIPS
50
55
60
65
70
Average (mA)
40
45
50
55
60
65
70
10 20 30 40 50
Average (mA)
MIPS
dsPIC33FJ06GS10 1/X02 an d dsPIC33FJ 16GSX02/X04
DS70000318G-page 350 2008-2014 Microchip Technology Inc.
FIGURE 27-11: TYPICAL FRC FREQUENCY @ VDD = 3.3V
FIGURE 27-12: TYPICAL LPRC FREQUENCY @ VDD = 3.3V
FIGURE 27-13: TYPICAL INTREF @ VDD = 3.3V
71
7.15
7.2
7.25
7.3
7.35
7.4
7.45
F
RC Frequency (MHz)
7
7.05
7.1
7.15
7.2
7.25
7.3
7.35
7.4
7.45
-40 25 85 125 150
FRC Frequency (MHz)
Temperature (Celsius)
22
24
26
28
30
32
34
L
PRC Frequency (kHz)
18
20
22
24
26
28
30
32
34
-40 25 85 125 150
LPRC Frequency (kHz)
Temperature (Celsius)
1.31
1.32
1.33
1.34
1.35
1.36
INTREF (V)
1.29
1.3
1.31
1.32
1.33
1.34
1.35
1.36
-40 25 85 125 150
INTREF (V)
Temperature (Celsius)
2008-2014 Microchip Technology Inc. DS70000318G-page 351
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
28.0 P ACKAGING INFORMATION
28.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: If the full Mic rochi p pa rt nu mber ca nnot be marke d on one line, i t is ca rried ov er to the next
line, thus limiting the number of available characters for customer-specific information.
3
e
3
e
28-Lead SPDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
dsPIC33FJ06GS
0830235
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
dsPIC33FJ06GS
0830235
202-E/SP
202-E/SO
3
e
3
e
18-Lead SOIC (.300”)
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
dsPIC33FJ06
0830235
GS101-I/SO
3
e
28-Lead QFN-S
XXXXXXXX
XXXXXXXX
YYWWNNN
Example
33FJ06GS
202EMM
0830235
3
e
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 352 2008-2014 Microchip Technology Inc.
28.1 Package Marking Information (Continued)
28-Lead UQFN
XXXXXXXX
XXXXXXXX
YYWWNNN
Example
33FJ06GS
202EMX
0830235
XXXXXXXXXX
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC33FJ16
Example
GS504-E/ML
0830235
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
dsPIC33FJ
16GS504
0830235
-E/PT
3
e
3
e
3
e
XXXXXXXXXX
44-Lead VTLA (TLA)
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC33FJ
Example
-E/TL
0830235
16GS504
3
e
2008-2014 Microchip Technology Inc. DS70000318G-page 353
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
28.2 Package Details
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 354 2008-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2014 Microchip Technology Inc. DS70000318G-page 355
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 356 2008-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2014 Microchip Technology Inc. DS70000318G-page 357
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 358 2008-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2014 Microchip Technology Inc. DS70000318G-page 359
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2008-2014 Microchip Technology Inc. DS70000318G-page 363
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2008-2014 Microchip Technology Inc. DS70000318G-page 365
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DS70000318G-page 366 2008-2014 Microchip Technology Inc.
2008-2014 Microchip Technology Inc. DS70000318G-page 367
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2008-2014 Microchip Technology Inc. DS70000318G-page 369
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 370 2008-2014 Microchip Technology Inc.
B
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For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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44-Terminal Very Thin Leadless Array Package (TL) – 6x6x0.9 mm Body
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2008-2014 Microchip Technology Inc. DS70000318G-page 371
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing C04-157D Sheet 2 of 2
0.300.20 0.25Terminal Length L
Terminal-to-Exposed Pad
REF: Reference Dimension, usually without tolerance, for information purposes only.
3. Dimensioning and tolerancing per ASME Y14.5M.
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Notes:
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dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 372 2008-2014 Microchip Technology Inc.
2008-2014 Microchip Technology Inc. DS70000318G-page 373
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
APPENDIX A: REVISION HISTORY
Revision A (January 2008)
This is the initial revision of this document.
Revision B (June 2008)
This revision includes minor typographical and
formatting changes throughout the data sheet text. In
addition, redundant information was removed that is
now available in the respective chapters of the
dsPIC33F/PIC24H Family Reference Manual, which
can be obtained from the Microchip web site
(www.microchip.com).
The major changes are referenced by their respective
section in the following table.
TABLE A-1: MAJOR SECTION UPDATES
Section Name Update Descripti on
“High-Performance, 16-bit Digital
Signal Controll er s” Moved location of Note 1 (RPn pin) references (see “Pin Diagrams”).
Section 3.0 “Memory Organization” Updated CPU Core Register map SFR reset value for CORCON (see
Table 3-1).
Removed Interrupt Controller Register Map SFR IPC29 and updated reset
values for IPC0, IPC1, IPC1 4, IPC16, IPC23, IPC24, IPC27, and IPC28 (s ee
Table 3-5).
Removed Interrupt Controller Register Map SFR IPC24 and IPC29 and
updated reset values for IPC0, IPC1, IPC2, IPC14, IPC16, IPC23, IPC27,
and IPC28 (s ee Table 3-6).
Removed Interrupt Controller Register Map SFR IPC24 and updated reset
values for IPC1, IPC2, IPC4, IPC14, IPC16, IPC23, IPC24, IPC27, and
IPC28 (see Table 3-7).
Updated Interrupt Controller Register Map SFR reset values for IPC1,
IPC14, IPC16, IPC23, IPC24, IPC27, and IPC28 (see Table 3-8).
Updated Interrupt Controller Register Map SFR reset values for IPC1,
IPC14, IPC16, IPC23, IPC24, IPC25, IPC26, IPC27, IPC28, and IPC29 (see
Table 3-9).
Updated Interru pt Contr oller Regi ster Map SFR reset valu es for IPC1, IPC4,
IPC14, IPC16, IPC23, IPC24, IPC25, IPC26, IPC27, IPC28, and IPC29 (see
Table 3-10).
Added SFR definitions for RPOR16 and RPOR17 (see Table 3-34,
Ta ble 3-35, and Table 3-36).
Updated bit def ini tio ns for POR TA, PORTB, and PORTC SFRs (ODCA,
ODCB, and ODCC) (see Table 3-37, Table 3-38, Table 3-39, and
Table 3-40).
Updated bit def ini tio ns and reset val ue for System Cont rol Regist er map
SFR CLKDIV (see Table 3-41).
Added device-specific information to title of PMD Register Map (see
Table 3-47).
Added devi ce-sp ecific PMD Register Ma ps (se e Table 3-46, Table 3-45, and
Table 3-43).
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 374 2008-2014 Microchip Technology Inc.
Section 7 .0 “Oscillator
Configuration” Re moved the fi rst sentenc e of the third cloc k source item (External Cl ock) in
Section 7.1.1 “System Clock sources”
Updated the default bit values for DOZE and FRCDIV in the Clock Divisor
Register (see Register 7-2).
Section 8.0 “Power-Saving
Features” Added the following six registers:
• “PMD1: Peripheral Module Disable Control Register 1”
• “PMD2: Peripheral Module Disable Control Register 2”
• “PMD3: Peripheral Module Disable Control Register 3”
• “PMD4: Peripheral Module Disable Control Register 4”
• “PMD6: Peripheral Module Disable Control Register 6”
• “PMD7: Peripheral Module Disable Control Register 7”
Section 9 .0 “I/O Ports” Added paragraph and Table 9-1 to Section 9.1.1 “Open-Drain
Configuration”, which provides details on I/O pins and their functionality.
Removed 9.1.2 “5V Tolerance”.
Updated MUX range and removed virtual pin details in Figure 9-2.
Updated PWM Input Name descriptions in Table 9-1.
Added Section 9.4.2.3 “Virtual Pins”.
Updated bit values in all Peripheral Pin Select Input Registers (see
Register 9-1 through Register 9-14).
Updated bit name information for Peripheral Pin Select Output Registers
RPOR16 and RPOR17 (see Register 9-30 and Register 9-31).
Added the following two registers:
• “RPOR16: Peripheral Pin Select Output Register 16”
• “RPOR17: Peripheral Pin Select Output Register 17”
Removed the following sections:
• 9.4.2 “Available Peripherals”
• 9.4.3.2 “Virtual Input Pins ”
• 9.4.3.4 “Peripheral Ma ppi ng”
• 9.4.5 “Considera tions f or Periph eral Pin Se lecti on” (and a ll subse ctions)
Section 14.0 “High-Speed PWM” Added Note 1 (remappable pin reference) to Figure 14-1.
Added Note 2 (Duty Cycle resolution) to PWM Master Duty Cycle Register
(Register 14-5), PWM Generator Duty Cycle Register (Register 14-7), and
PWM Secondary Duty Cycle Register (Register 14-8).
Added Note 2 and Note 3 and updated bit information for CLSRC and
FLTSRC in the PWM Fault Current-Limit Control Register (Register 14-15).
Section 15.0 “Serial Peripheral
Interface (SPI)” Removed the following sections, which are now available in the related
section of the dsPIC33F/PIC24H Family Reference Manual:
• 15.1 “Interrupts”
• 15.2 “Receive Operations”
• 15. 3 “Transmit Operations”
• 15. 4 “SPI Setup” (retaine d Figure 15-1: SPI Module Bloc k Diagram)
TABLE A-1: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Descripti on
2008-2014 Microchip Technology Inc. DS70000318G-page 375
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Section 1 6.0 “Inter-Integrated
Circuit (I2C™)” Removed the following sections, which are now available in the related
section of the dsPIC33F/PIC24H Family Reference Manual:
• 16.3 “I2C Interrupts”
• 16.4 “Baud Rate Generator” (retained Figure 16-1: I2C Block Diagram)
• 16.5 “I2C Module Addresses
• 16.6 “Slave Address Masking”
• 16.7 “IPMI Support”
• 16.8 “General Call Address Support”
• 16.9 “Automatic Clock Stretch”
• 16.10 “Software Controlled Clock Stretching (STREN = 1)”
• 16.11 “Slope Control”
• 16. 12 “Clock Arbitrati on”
• 16.13 “Multi-Master Communication, Bus Collision, and Bus Arbitration
Section 17.0 “Universal
Asynchronous Receiver Transmitter
(UART)”
Removed the following sections, which are now available in the related
section of the dsPIC33F/PIC24H Family Reference Manual:
• 17.1 “UART Baud Rate Generator”
• 17. 2 “Transmittin g in 8- bit Data Mode
• 17. 3 “Transmittin g in 9- bit Data Mode
• 17.4 “Break and Sync Transmit Sequence”
• 17.5 “Receiving in 8-bit or 9-bit Data Mode”
• 1 7.6 “Flow Control Using UxCTS and UxRTS Pins”
• 17.7 “Infrared Support”
Removed IrDA references and Note 1, and updated the bit and bit value
descriptions for UTXINV (UxSTA<14>) in the UARTx Status and Control
Register (see Register 17-2).
Section 1 8.0 “High-Speed 10-bit
Analog-to-Digital Converter (ADC)” Updated bit value information for Analog-to-Digital Control Register (see
Register 18-1).
Updated TRGSRC6 bit value for Ti mer1 period match in the Analog-to-
Digital Convert Pair Control Register 3 (see Register 18-8).
TABLE A-1: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Descripti on
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 376 2008-2014 Microchip Technology Inc.
Section 23.0 “Electrical
Characteristics” Updated Typ values for Thermal Packaging Characteristics (Table 23-3).
Remove d Typ value for DC Tempe ratu r e and Volt age Specifica tio ns
Parameter DC12 (Table 23-4).
Updated all Typ values and conditions for DC Characteristics: Operating
Current (IDD), updated last sentence in Note 2 (Table 23-5).
Updated all Typ values for DC Characteristics: Idle Current (IIDLE) (see
Table 23-6).
Updated all Typ values for DC Characteristics: Power Down Current (IPD)
(see Table 23-7).
Updated all Typ values for DC Characteristics: Doze Current (IDOZE) (see
Table 23-8).
Added Note 4 (reference to n ew table containing digit a l-on ly and analog pin
informatio n, as we ll as Curren t Sink /Sou rce c ap a bil iti es ) in the I/O Pin Input
Specifications (Table 23-9).
Updated Max v alu e for BO R electrical c har acteristics Pa ram eter BO 10 (s ee
Table 23-11).
Sw apped Min and Typ values for Pr ogram Memor y Parameters D136 and
D137 (Table 23-12).
Updated Typ values for Internal RC Accuracy Parameter F20 and added
Extended temperature range to table heading (see Table 23-19).
Removed all values for Reset, Watchdog Timer, Oscillator Start-up Timer,
and Power-up Timer Parameter SY20 and updated conditions, which now
refers to Section 20.4 “Watchdog Timer (WDT)” and LPRC Parameter
F21a (see Table 23-22).
Added specifications to High-Speed PWM Module Timing Requirements for
Tap Delay (Table 23-29).
Updated Min and Max values for 10-bit High-Speed Analog-to-Digital
Module Parameters AD01 and AD11 (see Table 23-36).
Updated Max value and unit of measure for DAC AC Specification (see
Table 23-40).
TABLE A-1: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Descripti on
2008-2014 Microchip Technology Inc. DS70000318G-page 377
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Revision C and D (March 2009)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
Global changes include:
• Changed all instances of OSCI to OSC1 and
OSCO to OSC2
• Changed all instances of PGCx/EMUCx and
PGDx/EMUDx (where x = 1, 2, or 3) to PGECx
and PGEDx
• Changed all instances of VDDCORE and VDDCORE/
VCAP to VCAP/VDDCORE
Other major changes are referenced by their respective
section in the following table.
TABLE A-2: MAJOR SECTION UPDATES
Section Name Update Descripti on
“High-Performance, 16-bit Digital
Signal Controll er s” Added “Application Examples” to list of features
Updated all pin diagrams to denote the pin voltage tolerance (see “Pin
Diagrams”).
Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which
references pin connections to VSS.
Section 1.0 “Device Overview” Added ACMP1-ACMP4 pin names and Peripheral Pin Select capability
column to Pinout I/O Descriptions (see Table 1-1).
Section 2 .0 “Guidelines for Getting
Started with 16-bit Digital Signal
Controllers”
Added new section to the data sheet that provides guidelines on getting
started with 16-bit Digital Signal Controllers.
Section 3.0 “CPU” Updated CPU Core Block Diagram with a connection from the DSP Engine
to the Y Data Bus (see Figure 3-1).
Vertically extended the X and Y Data Bus lines in the DSP Engine Block
Diagram (see Figure 3-3).
Section 4.0 “Memory Organization” Updated Reset value for ADCON in Table 4-25.
Removed reference to dsPIC33FJ06GS102 devices in the PMD Register
Map and updated bit definitions for PMD1 and PMD6, and removed PMD7
(see Table 4-43).
Added a new PMD Register Map, which references dsPIC33FJ06GS102
devices (see Table 4-44).
Updated RAM stack address and SPLIM values in the third paragraph of
Section 4.2.6 “Software Stack”
Removed Section 4.2.7 “Data Ram Protection Feature”.
Section 5 .0 “Flash Program
Memory” Updated Section 5.3 “Programming Operations” with programming time
formula.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 378 2008-2014 Microchip Technology Inc.
Section 8 .0 “Oscillator
Configuration” Added Note 2 to the Oscillator System Diagram (see Figure 8-1).
Added a paragraph regarding FRC accuracy at the end of Section 8.1.1
“System Clock Sources”.
Added Note 1 and Note 2 to the OSCON register (see Register ).
Added Note 1 to the OSCTUN register (see Register 8-4).
Added Note 3 to Section 8.4.2 “Oscillator Switching Sequence”.
Section 10.0 “I/O Ports” Removed Table 9-1 and added reference to pin diagrams for I/O pin
availability and functionality.
Added paragraph on ADPCFG register default values to Section 10.3
“Configuring Analog Port Pins”.
Added Note box regarding PPS functionality with input mapping to
Section 10.6. 2.1 “In put Map ping”.
Section 15.0 “High-Speed PWM” Updated Note 2 in the PTCON register (see Register 15-1).
Added Note 4 to the PWMCONx register (see Register 15-6).
Updated Notes fo r the PHASEx an d SPHASEx reg isters (s ee Re gis ter 15-9
and Regi st er 15-10, respectively ).
Section 16.0 “Serial Peripheral
Interface (SPI)” Added Note 2 and Note 3 to the SPIxCON1 register (see Register 16-2).
Section 18.0 “Universal
Asynchronous Receiver Transmitter
(UART)”
Updated the Notes in the UxMode register (see Register 18-1).
Updated the UTXINV bit settings in the UxSTA register and added Note 1
(see Reg is ter 1 8-2) .
Section 1 9.0 “High-Speed 10-bit
Analog-to-Digital Converter (ADC)” Updated the SLOWCLK and ADCS<2:0> bit settings and updated Note 1in
the ADCON register (see Register 19-1).
Remove d a ll not es in the ADPC FG reg is ter and rep lac ed th em with a s in gle
note (see Register 19-4).
Updated the SWTRGx bit settings in the ADCPCx registers (see
Register 19-5, Register 19-6, Register 19-7, and Register 19-8).
TABLE A-2: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Descripti on
2008-2014 Microchip Technology Inc. DS70000318G-page 379
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Section 24.0 “Electrical
Characteristics” Updated Typical values for Thermal Packaging Characteristics (see
Table 24-3).
Updated Min and Max values for Parameter DC12 (RAM Data Retention
Voltage) and added Note 4 (see Table 24-4).
Updated Chara cte ris tic s for I/O Pin Inpu t Specifica tions (see Table 24-9).
Added ISOURCE to I/O Pin Output Specifications (see Table 24-10).
Updated Program Memory values for Parameters 136, 137, and 138
(renamed to 136a, 137a, and 138a), added Parameters 136b, 137b, and
138b, and added No te 2 (see Table 24-12).
Added Parameter OS42 (GM) to the External Clock Timing Requirements
(see Table 24-16).
Updated Conditions for symbol TPDLY (Tap Delay) and added symbol ACLK
(PWM Input Clock) to the High-Speed PWM Module Timing Requirements
(see Table 24-29).
Updated Paramet ers AD01 and AD02 in the 10-bit High- Speed Analog -to-
Digital Module Specifications (see Table 24-36).
Updated Parameters AD50b, AD55b, and AD56b, and removed
Parameters AD5 7b and AD60b from the 10-bit Hi gh-S peed Analog-t o-Digita l
Module Timing Requirements (see Table 24-37).
TABLE A-2: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Descripti on
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 380 2008-2014 Microchip Technology Inc.
Revision E (December 2009)
The revision includes the following global update:
• Added Note 2 to the s had ed t abl e tha t app ear s at
the beginning of each chapter. This new note
provides information regarding the availability of
registers and their associated bits
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in the following table.
TABLE A-3: MAJOR SECTION UPDATES
Section Name Update Description
“16-bit Microc ontrol lers and Digital
Signal Controllers (up to 16-Kbyte
Flash and up to 2-Kbyte SRAM) with
High-Speed PWM, ADC and
Comparators”
Change d CN6 to CN5 on pin 16 of dsPIC33FJ16GS502 28-pin S PDIP,
SOIC pin diagra m.
Section 2 .0 “Guidelines for Getting
Started with 16-bit Digital Signal
Controllers”
Removed the 10 Ohm resistor from Figure 2-1.
Section 4.0 “Memory Organization” Renamed bit 13 of the REFOCON SFR in the System Control Register
Map from ROSIDL to ROSSLP and changed the All Resets value from
‘0000’ to ‘2300’ for the ACLKCON SFR (see 4-41).
Section 8 .0 “Oscillator Configuration” Updated the default reset values from R/W-0 to R/W-1 for the SELACLK
and APSTSCLR<2:0> bits in the ACLKCON register (see Register 8-5).
Renamed the ROSIDL bit to ROSSLP in the REFOCON register (see
Register 8-6).
Section 9.0 “Power-Saving Features” Updated the last paragraph of Section 9.2.2 “Idle Mode” to clarify when
instruction execution begins.
Added Note 1 to the PMD1 register (see Register 9-1).
Section 10.0 “I/O Ports” Changed the reference to digital-only pins to 5V tolerant pins in the
second paragraph of Section 10.2 “Open-Drain Configuration”.
Section 15.0 “High-Speed PWM” U pdated the smallest pulse width value from 0x0008 to 0x 0009 in Note 1
of the shaded note that follows the MDC register (see Register 15-5).
Updated the smallest pulse width value from 0x0008 t o 0x0009 and the
maximum pulse width value from 0x0FFEF to 0x0008 in Not e 2 of the
shaded note that fol lows the PDCx and SDCx regi sters (see Regi ster 15-7
and Regi st er 15-8).
Added Note 2 and updated the FLTDAT<1:0> and CLDAT<1:0> bits,
changing the word ‘data’ to ‘state’ in the IOCONx register (see
Register 15-14).
Section 18.0 “Universal
Asynchronous Receiver Transmitter
(UART)”
Updated the two baud rate range features to: 10 Mbps to 38 bps at 40
MIPS.
2008-2014 Microchip Technology Inc. DS70000318G-page 381
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Section 1 9.0 “High-Speed 10-bit
Analog-to-Digital Converter (ADC)” Updated Note 1 in the ADCPC0 register (see Register 19-5).
Updated Note 3 in the ADCPC1 register (see Register 19-6).
Updated Note 2 in the ADCPC2 and ADCPC3 registers (see Register 19-
7 and Register 19-8).
Section 21.0 “Special Features” Updated the second paragraph and removed the fourth paragraph in
Section 21.1 “C on figuration Bits”.
Updated the Dev ice Con fig urati on Register Map (see Table 21-1).
Section 24.0 “Electrical
Characteristics” Updated the Absolute Maximum Ratings for high temperature and added
Not e 4 .
Updated Idle Current (I IDLE) Typical values in Table 24-6.
Updated the Typ and Max values for Parameter DI50 in the I/O Pin Input
Specifications table (see Table 24-9).
Updated the T y p and M ax values for Parame ters DO10 and DO27 and the
Min and Typ values for Parameter DO20 in the I/O Pin Output
Specifications (see Table 24-10).
Added parameter numbers to the Auxiliary PLL Clock Timing
Specifications (see Table 24-18).
Added parameters numbers and updated the Internal RC Accuracy Min,
Typ, and Max value s (see Table 24-19 and Table 24-20).
Added parameter numbers, Note 2, updated the Min and Typ parameter
values for MP31 and MP32, and removed the conditions for MP10 and
MP11 in the High-Speed PWM Module Timing Requireme nt s (see
Table 24-29).
Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics
(see Table 24-14).
Added Parameter IM51 to the I2Cx Bus Data Timing Requirements
(Master Mode) (see Table 24-34).
Updated the Max value for Parameter AD33 in the 10-bit High-Speed
Analog-to-Digital Module Specifications (see Table 24-36).
Updated the titles and added parameter numbers to the Comparator and
DAC Module Specifications (see Table 24-38 and Table 24-39) and the
DAC Output Buf fer Specifications (see Table 24-40).
TABLE A-3: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 382 2008-2014 Microchip Technology Inc.
Revision F (January 2012)
All occurrences of VDDCORE have been removed
throughout the document.
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in the following table.
TABLE A-4: MAJOR SECTION UPDATES
Section Name Update Descripti on
“16-Bit Digital Signal Controllers (up
to 16-Kbyte Fla sh and up to 2-Kbyte
SRAM) with High-Speed PWM, ADC
and Comparators”
Added the VTLA package to the dsPIC33FJ16GS404 and
dsPIC33FJ16GS504 devices (see TABLE 1: “ dsPI C33F J06GS101/ X02
and dsPIC33FJ16GSX02/X04 Controller Families”).
Added the “Referenced Sources” section.
The following updates were made to the “Pin Diagrams” sect ion:
• Added 5V toleran t p in s ha din g t o pi ns 24 -26 in the 28-p in SPDIP, SOIC
package for the dsPIC33FJ16GS402
• Upda ted pin 31 of th e 4 4-pi n Q FN package for the ds PIC33 F J16G S40 4
• Added VTLA pin diagrams for the dsPIC33FJ16GS404 and
dsPIC33FJ16GS504 devices
Section 1.0 “Device Overview” Remove d the Precis ion Band G ap Referenc e from the de vice blo ck diagram
(see Figure 1-1).
Updated the Pinout I/O Descriptions for AVDD, and AVSS (see Table 1-1).
Section 2 .0 “Guidelines for Getting
Started with 16-bit Digital Signal
Controllers”
Updated the Minimum Recommended Connection (see Figure 2-1).
Section 8 .0 “Oscillator
Configuration” Updated the Oscillator System Diagram (see Figure 8-1).
Added auxiliary clock configuration restrictions in Section 8.2 “Auxiliary
Clock Generation”.
Updated or added notes regarding register reset on a POR
(see Register 8-1 through Register 8-5).
Section 1 9.0 “High-Speed 10-bit
Analog-to-Digital Converter (ADC)” Added Note 2 to ADCON: Analog-to-Digital Control Register
(see Register 19-1).
Removed all notes from ADSTAT: Analog-to-Digital Status Register
(see Register 19-2).
Section 2 0.0 “High-Speed Analog
Comparator” Updated the Comparator Module Block Diagram (see Figure 20-1).
Section 21.0 “Special Features” Add a new paragraph at the beginning of Secti on 21.1 “ Configuration
Bits”.
Added the RTSP Effect column to the dsPIC33F Configuration Bits
Description table (see Table 21-2).
Updated the Connections for the On-chip Voltage Regulator diagram
(see Figure 21-1).
Updated the first p aragraph of Section 21.7 “In-Circuit Debugger”.
2008-2014 Microchip Technology Inc. DS70000318G-page 383
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Section 24.0 “Electrical
Characteristics” Updated the Abs olu te Maxim um Rating s.
Updated the Operating MIPS vs. Voltage (see Table 24-1).
Updated Parameter DC10 and Note 4, and removed Parameter DC18 from
the DC Temperature and Voltage Specificat io ns (see Table 24-4).
Updated Note 2 in the IDD Operating Current specification (see Table 24-5).
Updated all Typical values and Note 2 in the IIDLE Operating Curre nt
specific ati on (see Table 24-6).
Updated Typical values for Parameters DC60d, DC60a, DC60b, and
DC60c, and Note 2 in the IPD Operating Current specification
(see Table 24-7).
Added all Typical values and Note 2 in the IDOZE Operating Current
specific ati on (see Table 24-8).
Updated Parameters DI19 and DI50, added Parameters DI128, DI129,
DI60a, DI60b , and DI60c , and re mo ved Param ete r DI57 in the I/O Pin Input
Specifications (see Table 24-9).
Revised all I/O Pinout Output Specifications (see Table 24-10).
Added Notes 2 and 3 to the BOR Electrical Characteristics (see Table 24-
11).
Added Note 1 to Internal Voltage Regulator Specifications
(see Table 24-13).
Updated the External Clock Timing diagram (see Figure 24-2).
Added Note 2 to the PLL Clock Timing Specifications (see Table 24-17).
Removed Note 2 from the Internal FRC Accuracy (see Table 24-19).
Updated Parameters DO31 and DO32 in the I/O Timing Requirements
(see Table 24-21).
Updated the External Clock Timing Requirements for Timer1, Timer2, and
Timer3 (see Table 24-23, Table 24-24, and Table 24-25, respectively).
Updated Para meters OC15 and OC20 in the Simple OC/PW M Mode T iming
Requirem en t s (se e Table 24-28).
Revised all SPIx Module Timing Characteristics diagrams and all Timing
Requirem en t s (se e Figure 24-11 through Figure 24-18 and Table 24-30
through Table 24-37, respectively).
Added Note 2 to the 10-bit High-Speed ADC Module Specifications (see
Table 24-40).
Added Note 2 to the 10-bit High-Speed ADC Module Timing Requirements
(see Table 24-41).
Added Note 2 to the Comparator Module Specifications (see Table 24-42).
Added Parameter DA08 and Note 2 in the DAC Module Specifications
(see Table 24-43).
Updated Parameter DA16 and Note 2 in the DAC Output Buffer DC
Specifications
(see Table 24-44).
TABLE A-4: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Descripti on
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 384 2008-2014 Microchip Technology Inc.
Section 26.0 “50 MIPS Electrical
Characteristics” Added new chapter in support of 50 MIPS devices.
Section 27.0 “DC and AC Device
Characteristics Graphs” Added new chapter.
Section 28.0 “Packaging
Information” Added 44-pin VTLA package marking information and diagrams (see
Section 28.1 “Package Marking Information” and Section 28.2
“Package Details”, respectively).
“Product Identification System” Added the TL package definition.
TABLE A-4: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Descripti on
2008-2014 Microchip Technology Inc. DS70000318G-page 385
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Revision G (May 2014)
The values for the TUN<5:0> bits in Register 8-4
(OSCTUN) have changed.
The DC Characteristics Idle Current values in
Section 2 4.0 “Electrical Characteristics” have been
updated.
The timer specifications in Section 26.0 “50 MIPS
Electrical Character ist ics” have been removed.
All diagrams in Section 28.0 “Packaging Information”
have be en upda ted.
Minor text edits have been applied throughout the
document.
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 386 2008-2014 Microchip Technology Inc.
NOTES:
2008-2014 Microchip Technology Inc. DS70000318G-page 387
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
INDEX
A
AC Characteristics ............................................300, 338, 345
Internal FRC Accuracy..............................................303
Internal LPRC Accuracy............................................303
Load Conditions............................... .. .... .. .. .. .....300, 338
ADCControl Regis te rs.. ............ ...... ............. ...... ....... ...... ..246
Functionality..............................................................239
Arithm e tic Logic Unit (ALU).................. ...... ............. ...... ......38
Assembler
MPASM Assembler...................................................284
Auxiliary Clock Generation................................................138
B
Barrel Shifter.......................................................................42
Bit-Reversed Add ressing................... ...... ...... ................. ....76
Example......................................................................77
Implementation ...........................................................76
Sequence Table (16-Entry).........................................77
Block Diagrams
16-Bit Timer1 Module.......................................... .... ..183
Connections for On-Chip Voltage Regulator. . ...........270
DSP Engin e.......... ...... ...... ...... ................. ................. ..39
dsPIC33F06GS101 Devices with 1 SAR..................240
dsPIC33F06GS102 Devices with 1 SAR..................241
dsPIC33F06GS202 Devices with 1 SAR..................242
dsPIC33F16GS402/404 Devices with 1 SAR...........243
dsPIC33F16GS502 Devices with 2 SARs ................244
dsPIC33F16GS504 Devices with 2 SARs ................245
dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04...................................18
dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 CPU Core..................32
High-Sp eed An a log Comparato r.......... ...... ....... ...... ..263
I2CX Module............. .. .. .. .... .. .. ..... .. .. .... .. .. .. .. ..... .... .. ..226
Input Capture x .................................. .... .. .... ....... .. ....191
Multiplexing of Remappable Output for RPn.............159
Oscillator System......................................................135
Output Compare x Module........................................193
Partitioned Output Pair, Complementary
PWM Mode........... ................. ...... ................. ....200
PLL............................................................................137
Remappable MUX Input for U1RX............................157
Reset System...................... ....... ...... ................. ...... ....89
Shared Po rt Struc ture. ........................... ................. ..155
Simplified Conceptual High-Speed PWM .................199
SPIx Module.......................................................... ....219
Timer2 /3 (32-Bit)......... ...... ...... ....... ................. ...... ....187
Type B Time r ..... ....... ...... ................. ................. ........185
Type C Timer..... ....... ...... ................. ...... ...... .............185
UART1......................................................................233
Watchdog Timer (WDT)............................................271
Brown-out Reset (BOR)......................................94, 267, 270
C
C Compilers
MPLAB XC Compilers.................. ...... ...... ....... ...... ....284
Clock Switching.................................................................146
Enabling....................................................................146
Sequence..................................................................146
Code Examples
Erasing a Program Memory Page.............................. 87
Initiating a Programming Sequence ........................... 88
Loading Write Buffers.......................... ....... .... .. .... .. .... 88
Port Write/Read........................................................ 156
PWRSAV Ins tructi on Syntax ....... ...... ....................... 147
Code Protection........................................................ 267, 273
CodeGuard Security......................................................... 267
Configuration Bits ............................................................. 267
Description................................................................ 268
Configurati o n R e g i ster Ma p... ..... ...... ...... ...... ..... .. ...... ...... . 267
Config uring Analog Port Pins............. ...... ................. ...... .. 156
CPUControl Register s................... ...... ...... ....... ...... ...... ...... 34
CPU Clockin g Sys te m........ ....... ...... ...... ...... ....... ...... ...... .. 136
PLL Config uration..................................................... 137
Selection................................................................... 136
Sources .................................................................... 136
Customer Change Notification Service............................. 392
Customer Notification Se r vice ......... ...... ...... ................... .. 392
Custome r Support. ...... ...... ................. ...... ................. ...... .. 392
D
DAC.................................................................................. 264
Output Range ................. ....... .. .. .... .. .. .. ....... .. .... .. .. .. .. 264
Data Accumulators and Adder/Subtracter.......................... 40
Data Space Write Saturation...................................... 42
Overflow and Saturation............................................. 40
Round Logic ............................................................... 41
Write Back.................................................................. 41
Data Addre ss Space............... ................. ....... ...... .............. 45
Alignment.................................................................... 45
Memory Map for dsPIC33FJ06GS101/102 Devices
with 256 Bytes of RAM....................................... 46
Memory Map for dsPIC33FJ06GS202 Device
with 1-Kbyte RAM............................................... 47
Memory Map for dsPIC33FJ16GS402/404/502/504
Devices with 2 -K b yte RAM.... ............. ...... ...... .... 48
Near Data Space........................................................ 45
Software Stack .................. ........................... .............. 73
Width .......................................................................... 45
Data Addressing
Overview..................................................................... 31
DC and AC Characteristics
Graphs and Tables................................................... 347
DC Characteristics.................................................... 288, 342
Doze Current (IDOZE)........................................ 294, 344
High Tempera ture........... ....... ...... ................. ...... ...... 334
I/O Pin Input Specifications ............. .... ......... .. .... .... .. 295
I/O Pin Outpu t Specifica tions....... ...... ....... ...... .. 297, 336
Idle Current (IIDLE)............................................ 292, 343
Operating Current (IDD) .................................... 290, 342
Operating MIPS vs. Voltage..................... 288, 334, 342
Power-Down Current (IPD)................................ 293, 335
Program Memory.............................................. 299, 337
Temperature and Voltage......................................... 334
Temperature and Voltage Specifications .................. 289
Thermal Operating Conditions .................................. 334
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 388 2008-2014 Microchip Technology Inc.
Demo/Development Boards, Evaluation and
Starter Kits... ...... ...... ................. ...... ................. ....... ..286
Development Support .......................................................283
Third-Party Tools ......................................................286
Doze Mode........................................................................148
DSP Engin e. ....... ...... ................. ...... ................. ................. ..38
Multiplier......................................................................40
E
Electrical Characteristics...................................................287
50 MIPS.......................... ...... ................. ................. ..341
AC.............................................................................338
AC Characteristics and
Timing Parameters....................................300, 345
BOR..........................................................................298
Equations
Device Operating Frequency ....................................136
FOSC Calculation.......................................................137
Maximum Row Write Tim e..........................................84
Minim u m Row Write Time............... ....... ...... ...... ....... ..84
Programming Time ................. ...... ....... ...... ...... ....... ....84
XT with PLL Mode Example......................................137
Errata ..................................................................................14
External Reset (EXTR)........................................................95
F
Fail-Safe Clock Monitor (FSCM).......................................146
Flash Pr ogram Memory.. ................. ................. ................. ..83
Control Reg i sters.......... ...... ................. ...... ...... ....... ....84
Operations ..................................................................84
Progra m ming Algorithm.......... ...... ................. .............87
RTSP Operation..........................................................84
Table Instructions........................................................83
Flexible Configuration.......................................................267
G
Guidel in e s for Ge tting Start ed wit h 16- Bit DSCs........ .........21
H
High-Speed 10-Bit Analog-to-Digital
Converter (ADC).......................................................239
High-Sp e ed Ana log Comparato r............. ....... ...... .............263
Digital L ogic ........... ....... ...... ...... ...... ....... ................. ..264
Input Range ............................ .. .... .. ....... .. .. .. .. .... .. .....264
Inter a ction with I/O Buffers............ ....... ...... ...... .........264
High-Sp eed PWM .. ...... ................. ...... ................. ...... .......197
Control Reg i sters.......... ...... ................. ...... ...... ....... ..200
High-Temperature Electrica l C h a r a cteri stics. .. ...... ...... ..... .3 3 3
I
I/O Ports........... ...... ...... ................. ................. ................. ..155
Paral l e l I/O (PIO)........ ................. ....... ................ .......155
Write/Read Timing ....................................................156
I2CControl Re g i sters.......... ................ ....... ...... ...... ....... ..227
Operating Modes ......................................................225
In-Circuit Debugger...........................................................272
In-Circuit Emulation...........................................................267
In-Circuit Serial Programming (ICSP) .......................267, 272
Input Capture ............................ .... .. .... .. .. ......... .. .... .. .. .......191
Control Reg i ster................ ...... ...... ....... ...... ...... ....... ..192
Input Change Notification....................................... .. .... .....156
Instruction Addressing Modes ............................................ 73
File Register Instructions............................................ 73
Fundamental Modes Supported .................. ......... .... .. 74
MAC Instru ctions.......... ...... ....... ...... ...... ...... ....... ........ 74
MCU Instru ction s......................... ...... ................. ...... ..73
Move and Accumulator Instructions ............................ 74
Other Ins tructions ........... ...... ....... ...... ................. ...... ..74
Instruction Set
Overview................................................................... 278
Summary .................................................................. 275
Instruction-Based Power-Sav in g Modes........................... 147
Idle............................................................................ 148
Sleep ........................................................................ 147
Interfacing Program and Data Memory Spaces.................. 78
Internal RC Oscillator
Use with WDT........................................................... 271
Inter net Address ........ ................. ................. ...... ............... 39 2
Interrupts
Alternate Interrupt Vector Table (AIVT)...................... 97
Control and Status Registers....................... ......... ....100
IECx.................................................................. 100
IFSx.................................................................. 100
INTCON1.......................................................... 100
INTCON2.......................................................... 100
INTTREG.......................................................... 100
IPCx.................................................................. 100
Interrupt Vector Table (IVT)........................................ 97
Reset Sequence.................................... .... ......... .... ....97
Setup Procedure s..... . ..... ........................... ............... 13 4
Initialization....................................................... 134
Interrupt Disable............................................... 134
Interrupt Service Routine.................................. 134
Trap Ser vice Routine................... ...... ....... ...... ..134
Interrupts Coincident with Power Save Instructions ......... 148
J
JTAG Boundary Scan Interf ace............................. ........... 267
JTAG Interface .................................................................. 272
M
Memory Organization . ........................................................ 43
Microc h i p In te rnet Web Site........ ....... ................ ....... ........ 392
Modulo Addressing............................................................. 75
Applicability................................................................. 76
Operation Example..................................................... 75
Start and End Address ............................................... 75
W Addres s Reg ister Selectio n............. ...... ............. .... 75
MPLAB Assembler, Lin k er, Librar ia n................. ............... 28 4
MPLAB ICD 3 In-Circuit Debugger.................. .... ......... .... 285
MPLAB PM3 Device Programmer.................................... 285
MPLAB REA L IC E In -Circui t Emulator Sy stem ................ 285
MPLAB X Integrated Development
Environ ment Sof twa re ............ ....... ...... ................. .... 28 3
MPLAB X SIM Software Simulator ................................... 285
MPLIB Obje ct Libraria n... ...... ...... ....... ...... ................. ...... .. 284
MPLINK Obje ct Linker............ ...... ....... ...... ...... ................. 284
O
Open-Drain Configuration................................................. 156
Oscillator Configuration .... .. .. .. .. .. ...................................... 135
Control Reg i sters.............. ............. ...... ...... ....... ...... .. 139
Outpu t Compare........ ....... ...... ................. ...... ................. .. 193
Modes....................................................................... 194
Operation Diagram ................................................... 194
2008-2014 Microchip Technology Inc. DS70000318G-page 389
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
P
Packaging.........................................................................351
Details.......................................................................353
Marking.....................................................................351
Peripheral Module Disable (PMD) ....................................148
Peripheral Pin Select (PPS)..............................................157
PICkit 3 In-Circuit Debugger/Programmer ........................285
Pinout I/O Descriptions (table)............................................19
Power-on Res e t (POR)............... ....... ...... ................. ...... ....94
Power-Saving Features ....................................................147
Clock Frequency and Switching ................................147
Power-up Timer (PWRT) .......... ...... ....... ...... ...... ....... ..........94
PPS Control Regis te r s....................... ...... ...... ...... ....... ......161
Selectable Input Sources..........................................158
Selectio n Ou tp u t Sources............ ...... ...... ....... ...... ....159
Program Address Space.....................................................43
Construction................................................................78
Data Access from Program Memory Using
Program Space Visibility.....................................81
Data Access from Program Memory Using
Table Instructions ...............................................80
Data Access from, Addre ss Ge n era tion............ ...... ....79
Memory Maps.............................................................43
Table Read Instructions
TBLRDH .............................................................80
TBLRDL..............................................................80
Visibility Operation......................................................81
Program Mem ory
Inter rupt Vecto r........... ...... ...... ................. ...................44
Organization................................................................44
Reset Vec tor................... ...... ................. ...... ...............44
R
Reference Clock Generation.............................................138
Register Maps
Analog Comparator Control for
dsPIC33FJ06GS202...........................................67
Analog Comparator Control for
dsPIC33FJ16GS503/504....................................67
Change Notification for dsPIC33FJ06GS101 .............51
Change Notification for dsPIC33FJ06GS102/202
and dsPIC33FJ16GS402/502........................... ..51
Change Notification for
dsPIC33FJ16GS404/504....................................51
CPU Core....................................................................50
High-Speed 10-Bit ADC for dsPIC33FJ06GS101.......63
High-Speed 10-Bit ADC for dsPIC33FJ06GS102.......63
High-Speed 10-Bit ADC for dsPIC33FJ06GS202.......64
High-Speed 10-Bit ADC for
dsPIC33FJ16GS402/404....................................64
High-Speed 10-Bit ADC for dsPIC33FJ16GS502.......65
High-Speed 10-Bit ADC for dsPIC33FJ16GS504.......66
High-Sp eed PWM... ...... ................. ...... ................. ......59
High-Speed PWM Generator 1. ..................................60
High-Speed PWM Gen erat or 2 for dsPIC33FJ06GS101/
202 and dsPIC33FJ16GSX02/X04.....................60
High-Speed PWM Generator 3 for
dsPIC33FJ16GSX02/X04...................................61
High-Speed PWM Gen erat or 4 for dsPIC33FJ06GS101
and dsPIC33FJ16GS50X ...................................61
I2C1 ............................................................................62
Input Capture for dsPIC33FJ06GS202.......................58
Input Capture for dsPIC33FJ16GSX02/X04...............59
Interrupt Controller for dsPIC33FJ06GS101...............52
Interrupt Controller for dsPIC33FJ06GS102 .............. 53
Interrupt Controller for dsPIC33FJ06GS202 .............. 54
Interrupt Controller for dsPIC33FJ16GS402/404 ....... 55
Interrupt Controller for dsPIC33FJ16GS502 .............. 56
Interrupt Controller for dsPIC33FJ16GS504 .............. 57
NVM............................................................................ 71
Output Compare for dsPIC33FJ06GS101/X02 .......... 59
Output Compare for dsPIC33FJ16GSX02
and dsPIC33FJ06GSX 04................................... 59
PMD for dsPI C3 3 FJ06GS101 ....... ................. ...... ...... 71
PMD for dsPI C3 3 FJ06GS102 ....... ................. ...... ...... 71
PMD for dsPI C3 3 FJ06GS202 ....... ................. ...... ...... 72
PMD for dsPIC33FJ16GS402/404 ............................. 72
PMD for dsPIC33FJ16GS502/504 ............................. 72
PORTA....................................................................... 70
PORTB for dsPIC33FJ06GS101................................ 70
PORTB for dsPIC33FJ06G S102/ 202
and dsPIC33FJ16GS4 02/404/502/504............... 70
PORTC for dsPIC33FJ1 6GS404/ 504......................... 70
PPS Input ................ ......... ..................... ............ ......... 6 8
PPS O u tpu t for dsPIC33 F J 0 6GS1 0 1 .... .. ...... .. ...... .. ... 68
PPS Output for dsPIC33FJ06G S 102/202
and dsPIC33FJ16GS4 02/502............................. 69
PPS Output for dsPIC33FJ16G S 404/504 .................. 69
SPI1............................................................................ 62
System Control........................................................... 71
Timers for dsPIC33FJ06G S101/X02..... ..................... 58
Timers for dsPIC33FJ16GSX02/X04.......................... 58
UART1........................................................................ 62
Registers
ACLKCON (Auxiliary Clock Divisor Control)............. 144
ADBASE (Analog-to-Digital Base)............................ 250
ADCON (Analog-to-Digital Control).......................... 247
ADCPC0 (Analog-to-Digital Convert Pair
Control 0)................... ...... ................. ...... ...... .... 251
ADCPC1 (Analog-to-Digital Convert Pair
Control 1)................... ...... ................. ...... ...... .... 254
ADCPC2 (Analog-to-Digital Convert Pair
Control 2)................... ...... ................. ...... ...... .... 257
ADCPC3 (Analog-to-Digital Convert Pair
Control 3)................... ...... ................. ...... ...... .... 260
ADPCFG (Analog-to-Digital Port Configuration)....... 250
ADSTAT ( Ana l o g -to-Digit a l Status)........ ...... ...... ...... 249
ALTDTRx (PWMx Alternate Dead-Time).................. 210
CLKDIV (Clock Divisor) ............................................ 141
CMPCONx (Comparator Control x).......................... 265
CMPDACx (Compa rator DAC x Control)................ .. 266
CORCON (Core Control).................................... 36, 101
DTRx (PWMx Dead-T ime)........................................ 210
FCLCONx (PWM x Fault Current-Limit Control)........ 214
I2CxCON (I2C x Con trol)................ ...... ............. ...... .. 228
I2CxMSK (I2 Cx Slave Mode Addr ess Mask)............ 232
I2CxSTAT (I2Cx Status)........................................... 230
ICxCON (Input Capture x Control)............................ 192
IEC0 (Interrupt Enable Control 0)........................... .. 112
IEC1 (Interrupt Enable Control 1)........................... .. 114
IEC3 (Interrupt Enable Control 3)........................... .. 115
IEC4 (Interrupt Enable Control 4)........................... .. 115
IEC5 (Interrupt Enable Control 5)........................... .. 116
IEC6 (Interrupt Enable Control 6)........................... .. 117
IEC7 (Interrupt Enable Control 7)........................... .. 118
IFS0 ( In terrupt Flag Statu s 0)............ ....................... 105
IFS1 ( In terrupt Flag Statu s 1)............ ....................... 107
IFS3 ( In terrupt Flag Statu s 3)............ ....................... 108
IFS4 ( In terrupt Flag Statu s 4)............ ....................... 108
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 390 2008-2014 Microchip Technology Inc.
IFS5 (Interrupt Flag Status 5) ...................................109
IFS6 (Interrupt Flag Status 6) ...................................110
IFS7 (Interrupt Flag Status 7) ...................................111
INTCON1 (Interrupt Control 1)..................................102
INTTREG (Interru pt Control and Status)...................133
IOCONx (PWMx I/O Co nt r o l)...... ............. ...... ...... .....212
IPC0 (Interrupt Prio r i ty Control 0) ... ....... ...... ...... .......119
IPC1 (Interrupt Prio r i ty Control 1) ... ....... ...... ...... .......120
IPC14 (Interrupt Priority Control 14) .........................125
IPC16 (Interrupt Priority Control 16) .........................125
IPC2 (Interrupt Prio r i ty Control 2) ... ....... ...... ...... .......121
IPC23 (Interrupt Priority Control 23) .........................126
IPC24 (Interrupt Priority Control 24) .........................127
IPC25 (Interrupt Priority Control 25) .........................128
IPC26 (Interrupt Priority Control 26) .........................129
IPC27 (Interrupt Priority Control 27) .........................130
IPC28 (Interrupt Priority Control 28) .........................131
IPC29 (Interrupt Priority Control 29) .........................132
IPC3 (Interrupt Prio r i ty Control 3) ... ....... ...... ...... .......122
IPC4 (Interrupt Prio r i ty Control 4) ... ....... ...... ...... .......123
IPC5 (Interrupt Prio r i ty Control 5) ... ....... ...... ...... .......124
IPC7 (Interrupt Prio r i ty Control 7) ... ....... ...... ...... .......124
LEBCONx (Leading-Edge Blanking Control) ............217
MDC (PWM Master Duty Cycle) ...............................204
NVMCON (Flash Memor y Con tr o l)........ ............ .........85
NVM KEY (N o n vo l a tile Memor y Key) .... ...... ...... .. ..... ...86
OCxC ON (O u tp u t Com p ar e x Control......... ...... ..... ...195
OSCCON (Oscillator Control)...................................139
OSCTUN (FRC Oscill a tor Tuning)........... ...... ...... .....143
PDCx (PWMx Generator Duty Cycle).......................207
PHASEx (PWMx Primary Phase -Shift)............ .........208
PLLFBD (PLL Feedback Divisor)..............................142
PMD1 (Peripheral Module Disable Control 1). ..........149
PMD2 (Peripheral Module Disable Control 2). ..........150
PMD3 (Peripheral Module Disable Control 3). ..........151
PMD4 (Peripheral Module Disable Control 4). ..........151
PMD6 (Peripheral Module Disable Control 6). ..........152
PMD7 (Peripheral Module Disable Control 7). ..........153
PTCON (PWM Time Base Control) ..........................201
PTCON2 (PWM Clock Divider Select)........... ...........203
PTPER (PWM Mast e r Tim e Base)......... ...... ...... .......203
PWMCAPx (Primary PW Mx Time
Base Captu r e )....... ...... ...... ...... ....... ...... .............218
PWMCONx (PWMx Control).....................................205
RCON (Reset Contr o l)............ ...... ....... ...... ...... ....... ....90
REFOCON (Reference Oscillator Control)................145
RPINR0 (Peripheral Pin Select Input 0)....................161
RPINR1 (Peripheral Pin Select Input 1)....................162
RPINR11 (Peripheral Pin Select Input 11)................165
RPINR18 (Peripheral Pin Select Input 18)................166
RPINR20 (Peripheral Pin Select Input 20)................167
RPINR21 (Peripheral Pin Select Input 21)................168
RPINR29 (Peripheral Pin Select Input 29)................169
RPINR3 (Peripheral Pin Select Input 3)....................163
RPINR30 (Peripheral Pin Select Input 30)................170
RPINR31 (Peripheral Pin Select Input 31)................171
RPINR32 (Peripheral Pin Select Input 32)................172
RPINR33 (Peripheral Pin Select Input 33)................173
RPINR34 (Peripheral Pin Select Input 34)................174
RPINR7 (Peripheral Pin Select Input 7)....................164
RPOR0 (Peripheral Pin Select Output 0)..................174
RPOR1 (Peripheral Pin Select Output 1).................. 175
RPOR10 (Peripheral Pin Select Output 10).............. 179
RPOR11 (Peripheral Pin Select Output 11).............. 180
RPOR12 (Peripheral Pin Select Output 12).............. 180
RPOR13 (Peripheral Pin Select Output 13).............. 181
RPOR14 (Peripheral Pin Select Output 14).............. 181
RPOR16 (Peripheral Pin Select Output 16).............. 182
RPOR17 (Peripheral Pin Select Output 17).............. 182
RPOR2 (Peripheral Pin Select Output 2).................. 175
RPOR3 (Peripheral Pin Select Output 3).................. 176
RPOR4 (Peripheral Pin Select Output 4).................. 176
RPOR5 (Peripheral Pin Select Output 5).................. 177
RPOR6 (Peripheral Pin Select Output 6).................. 177
RPOR7 (Peripheral Pin Select Output 7).................. 178
RPOR8 (Peripheral Pin Select Output 8).................. 178
RPOR9 (Peripheral Pin Select Output 9).................. 179
SDCx (PWMx Secondary Duty Cycle)...................... 207
SEVTCMP (PWM Special Event Compare) ............. 204
SPHASEx (PW Mx Sec ondary Phas e-Shift).............. 209
SPIxCON1 (SPIx Control 1)......................................221
SPIxCON2 (SPIx Control 2)......................................223
SPIxSTAT (SPIx Status and Control)....................... 220
SR (CPU STATUS)............................................. 34, 101
STRIGx (PWMx Secondary Trigger
Compare Valu e) ............. ................. ....... ...... .... 21 6
T1CON (Timer1 Con trol) ...... ....... ............ ....... ...... .... 184
TRGCONx (PWMx Trigger Control) ......................... 211
TRIGx (P WMx Primary Trigger
Compare Valu e) ............. ................. ....... ...... .... 21 6
TxCON (Timerx Control, x = 2)................................. 188
TyCON (Timery Control, y = 3)................................. 189
UxMODE (UAR Tx Mode)............................... ........... 234
UxSTA (UARTx Status and Control)......................... 236
Reset .................................................................................. 89
Configuration Mismatch.............................................. 95
Illegal Condition.................... .. ....... .. .. .. .. .. .. ....... .. .. .. .. .. 95
Illegal Op cod e......... ...... ...... ....... ...... ...... ...... ....... ..89, 95
Security................................................................. 89, 96
System........................................................................ 92
Trap Conflict...... ....... ...... ................. ...... ...... ....... ...... .. 95
Uninitialized W Register.................................. 89, 95, 96
Resets................................................................................. 89
Resources Required for Digital Phase-Shift
ZVT Converter................ ...... ................. ...... ............... 30
Revision History................................................................ 373
S
Serial Peripheral Interface (SPI)....................................... 219
Software RE SET In structio n ( SWR) ..... .. ...... .. ...... ..... .. .. ..... 95
Software Stack Pointer, Frame Pointer
CALL Stack Fr a me............. ....... ................ ....... ...... .... 73
Special Features of th e CPU................... ...... ...... ....... ...... 267
Symbols Used in Opcode Descriptions ............................ 276
T
Temperature and Voltage Specifications
AC..................................................................... 300, 338
Timer1............................................................................... 183
Timer2/3............................................................................ 185
16-Bit Operatio n ..... ................ ....... ................. ...... .... 186
32-Bit Operatio n ..... ................ ....... ................. ...... .... 186
2008-2014 Microchip Technology Inc. DS70000318G-page 391
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
Timing Diagrams
Analog-to-Digital Conversion per Input.....................329
Brown-out Situations...................................................94
External Clock...........................................................301
High-Sp eed PWMx ........................ ...... ................. ....311
High-Sp eed PWMx Fault ....................... ...... ....... ......311
I/O.............................................................................304
I2Cx Bus Data (Master Mode) ..................................324
I2Cx Bus Data (Slave Mode) ....................................326
I2Cx Bus Start/Stop Bits (Master Mode)...................324
I2Cx Bus Start/Stop Bits Slave Mode)......................326
Input Capture x (ICx).................................................309
OCx/PWMx...............................................................310
Output Compare x (OCx)..........................................309
Reset, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer .........................................305
SPIx Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1) ... ...... ....... ................. ..........315
SPIx Master Mode (Full-Duplex, CKE = 1,
CKP = x, CMP = 1) .................. ...... ...... ....... ......314
SPIx Master Mode (Half-Duplex,
Transmit Only, CKE = 0)........ ...... ...... ....... ...... ..312
SPIx Master Mode (Half-Duplex,
Transmit Only, CKE = 1)........ ...... ...... ....... ...... ..312
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) ...........................................322
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) ...........................................320
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) ...........................................316
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) ...........................................318
Syste m Rese t.................. ...... ................. ...... ...............93
Timer1 , 2 , 3 Exte rnal Clock................ ...... ....... ...... ....307
Timing Requirements
10-Bit, High-Speed ADC Requirements....................329
External Clock...................................................301, 345
I/O.............................................................................304
Input Capture x .................................. .... .. .... ....... .. ....309
Simple OCx/PWMx Mode.........................................345
SPIx Master Mode (CKE = 0) ...................................339
SPIx Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1) ... ...... ....... ................. ..........315
SPIx Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) ... ...... ....... ................. ..........314
SPIx Master Mode (Half-Duplex,
Transmit Only).... ...... ...... ................. ....... ...... ....313
SPIx Module Master Mode (CKE = 1).......................339
SPIx Module Slave Mode (CKE = 0).........................340
SPIx Module Slave Mode (CKE = 1).........................340
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) ...........................................323
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) ...........................................321
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) ...........................................317
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) ...........................................319
Timing Specifications
10-Bit High-Speed ADC Module. .............................. 328
Auxilia ry PLL Clock.................. ...... ...... ....... ...... ........ 302
Comparator Module................. .. .... .. .... ....... .. .. .... .. .... 330
DAC Module....... ...... ...... ....... ...... ...... ....... ...... .......... 330
DAC Output Buffer DC ........................ ....... ...... ...... .. 331
High-Speed PWMx Requirements............................ 311
I2Cx Bus Data Requirements (Master Mode)........... 325
I2Cx Bus Data Requirements (Slave Mode)............. 327
Output Compare x Requirements. ............................ 309
PLL Clock......................................................... 302, 338
Reset, Watchdog Timer, Oscillator Start -up Time r,
Power-up Timer and Brown-out Reset
Requirements................................................... 306
Simple OCx/PWM x Mode Requirements ................. 310
Timer1 External Clock Requirements....................... 307
Timer2 External Clock Requirements....................... 308
Timer3 External Clock Requirements....................... 308
U
Universal Asynchronous Receiver
Transmitter ( UAR T)................. ...... ................. .......... 233
Using the RCON Status Bits............................................... 96
V
Voltage Re gulator (On-Chip )..................... ....................... 270
W
Watchdog Timer (WDT)....................... .... .... ......... .... 267, 271
Programming Consider a tions............ ....... ...... ...... .... 271
Watchdog Timer Time-out Reset (WDTO) ......................... 95
WWW Address ......... ...... ...... ................. ........................... 39 2
WWW, On-Line Support..................................................... 14
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 392 2008-2014 Microchip Technology Inc.
NOTES:
2008-2014 Microchip Technology Inc. DS70000318G-page 393
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
THE MICROCHIP WEB SITE
Microc hip pro vides onl ine s upport v ia our W WW site at
www.microchip.com. Thi s web site is used as a mean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online dis cu ss io n gr oups, Microchip consul t an t
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminar s and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specif ied produ ct family or develo pment tool of interes t.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technic al suppo rt is avail able throug h the web si te
at: http://microchip.com/support
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 394 2008-2014 Microchip Technology Inc.
NOTES:
2008-2014 Microchip Technology Inc. DS70000318G-page 395
dsPIC33F J06GS101/X0 2 an d dsPIC33FJ16GSX02 /X04
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Architecture: 33 = 16-bit Digital Signal Controller
Flash Memory Family: FJ = Flash program memory, 3.3V
Product Group: GS1 = Switch Mode Power Supply (SMPS) family
GS2 = Switch Mode Power Supply (SMPS) family
GS4 = Switch Mode Power Supply (SMPS) family
GS5 = Switch Mode Power Supply (SMPS) family
Pin Count: 01 = 18-pin
02 = 28-pin
04 = 44-pin
Speed 50 = 50 MIPS
Temperature Range: I = -40C to+85C (Industrial)
E=-40C to+125C (Extended)
H=-40C to+150C (High)
Package: PT = Plastic Thin Quad Flatpack - 10x10x1 mm body (TQFP)
ML = Plastic Quad Flat, No Lead Package - 8x8 mm body (QFN)
MM = Plastic Quad Flat, No Lead Package - 6x6x0.9 mm body (QFN-S)
SO = Plastic Small Outline - Wide - 7.50 mm body (SOIC)
SP = Skinny Plastic Dual In-Line - 300 mil body (SPDIP)
TL = Very Thin Leadless Array - 6x6 mm body (VTLA)
Examples:
a) dsPIC33FJ06GS102-E/SP:
SMPS dsPIC33, 6-Kbyte program
memory, 28-pin, Extended
tempera t ur e, SPDIP package .
Microchip T rademark
Architecture
Flash Memory Family
Progra m Memory Size (K byte)
Product Group
Pin Coun t
Speed (if applicable)
Package
Pattern
dsPIC 33 FJ 06 GS1 02 T - 50 E / SP - XXX
Tape and Reel Flag (if applicable)
Temperature Range
dsPIC33FJ06GS101/X02 and dsPIC33 FJ 16GSX02/X04
DS70000318G-page 396 2008-2014 Microchip Technology Inc.
NOTES:
2008-2014 Microchip Technology Inc. DS70000318G-page 397
Information contained in this publication regarding device
applications a nd the lik e is provid ed only for your convenien ce
and may be supers ed ed by u pdates. I t is y our responsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PI C32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip T echnology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Em bedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology I nc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM ,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE , In - Circuit Serial
Programm ing, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PIC DEM .net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germ any II Gm bH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned here in are property of their
respective companies.
© 2008-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-63276-216-0
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its f amily of products is one of the most secure families of its kind on t he market t oday, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS70000318G-page 398 2008-2014 Microchip Technology Inc.
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Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los A n ge les
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-67 33
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7 000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5 511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9 588
Fax: 86-23-8980-9500
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2 460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5 533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2 829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5 300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7 252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohs iung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53 -63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-37664 00
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Germany - Pforzheim
Tel: 49-7231-42475 0
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-762528 6
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921- 5800
Fax: 44-118-921- 5820
Worldwide Sales and Service
03/25/14
