TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Available in 5-V, 4.85-V, and 3.3-V
Fixed-Output and Adjustable Versions
D
Very Low-Dropout Voltage ...Maximum of
32 mV at IO = 100 mA (TPS7150)
D
Very Low Quiescent Current – Independent
of Load . . . 285 µA Typ
D
Extremely Low Sleep-State Current
0.5 µA Max
D
2% Tolerance Over Specified Conditions
For Fixed-Output Versions
D
Output Current Range of 0 mA to 500 mA
D
TSSOP Package Option Offers Reduced
Component Height for Space-Critical
Applications
D
Power-Good (PG) Status Output
description
The TPS71xx integrated circuits are a family
of micropower low-dropout (LDO) voltage
regulators. An order of magnitude reduction in
dropout voltage and quiescent current over
conventional LDO performance is achieved by
replacing the typical pnp pass transistor with a
PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 32
mV at an output current of 100 mA for the TPS7150) and is directly proportional to the output current (see
Figure 1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very
low and remains independent of output loading (typically 285 µA over the full range of output current, 0 mA to
500 mA). These two key specifications yield a significant improvement in operating life for battery-powered
systems. The LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down
the regulator, reducing the quiescent current to 0.5 µA maximum at TJ = 25°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
NC – No internal connection
1
2
3
4
8
7
6
5
GND
EN
IN
IN
PG
SENSE†/FB‡
OUT
OUT
D OR P PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
GND
GND
NC
NC
EN
NC
IN
IN
IN
PG
NC
NC
FB‡
NC
SENSE†
OUT
OUT
NC
NC
PW PACKAGE
(TOP VIEW)
†SENSE – Fixed voltage options only
(TPS7133, TPS7148, and TPS7150)
‡FB – Adjustable version only (TPS7101)
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
0.1
0.05
00 0.05 0.1 0.15 0.2 0.25 0.3
Dropout Voltage – V
0.15
0.2
0.25
0.35 0.4 0.45 0.5
IO – Output Current – A
TA = 25°C
TPS7148
TPS7150
TPS7133
Figure 1. Dropout Voltage Versus Output Current
Power good (PG) reports low output voltage and can be used to implement a power-on reset or a low-battery
indicator.
The TPS71xx is offered in 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%
over line, load, and temperature ranges (3% for adjustable version). The TPS71xx family is available in PDIP
(8 pin), SO (8 pin), and TSSOP (20-pin) packages. The TSSOP has a maximum height of 1,2 mm.
AVAILABLE OPTIONS
TJ
OUTPUT VOLTAGE
(V) PACKAGED DEVICES CHIP FORM
T
JMIN TYP MAX SMALL OUTLINE
(D) PLASTIC DIP
(P) TSSOP
(PW) (Y)
4.9 5 5.1 TPS7150QD TPS7150QP TPS7150QPW TPS7150Y
4.75 4.85 4.95 TPS7148QD TPS7148QP TPS7148QPW TPS7148Y
–40°C to 125°C3.23 3.3 3.37 TPS7133QD TPS7133QP TPS7133QPW TPS7133Y
Adjustable†
1.2 V to 9.75 V TPS7101QD TPS7101QP TPS7101QPW TPS7101Y
†The D and PW packages are available taped and reeled. Add R suffix to device type (e.g., TPS7150QDR). The TPS7101Q is
programmable using an external resistor divider (see application information). The chip form is tested at 25°C.
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
†TPS7133, TPS7148, TPS7150 (fixed-voltage options)
‡Capacitor selection is nontrivial. See application information section
for details.
SENSE
PG
OUT
OUT
9
8
6
10
IN
IN
IN
EN
GND
321
20
15
14
13
VI
0.1 µF
PG
CSR
VO
10 µF
+
TPS71xx†
CO‡
Figure 2. Typical Application Configuration
TPS71xx chip information
These chips, when properly assembled, display characteristics similar to the TPS71xxQ. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
(6)
(4)
(3)
(7)
(2)
(1)
GND
FB¶
OUT
PG
IN
EN TPS71xx
80
92
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
(6)
(7)
(2)
(5) (4)
(3)
(1)
§SENSE – Fixed voltage options only (TPS7133, TPS7148,
and TPS7150)
¶FB – Adjustable version only (TPS7101)
BONDING PAD ASSIGNMENTS SENSE§
(5)
NOTE A: For most applications, OUT and SENSE should
be tied together as close as possible to the device;
for other implementations, refer to SENSE-pin
connection discussion in the Applications
Information section of this data sheet.
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
_
+
Vref = 1.178 V
OUT
SENSE‡/FB
EN
IN
GND
R1
R2
PG
_
+
TPS7101
TPS7133
TPS7148
TPS7150
DEVICE UNITR1 R2
0
420
726
756
∞
233
233
233
Ω
kΩ
kΩ
kΩ
RESISTOR DIVIDER OPTIONS
†Switch positions are shown with EN low (active).
‡For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to
SENSE-pin connection discussion in Applications Information section.
NOTE A: Resistors are nominal values only .
1.12 V
†††
MOS transistors
Bilpolar transistors
Diodes
Capacitors
Resistors
COMPONENT COUNT
464
41
4
17
76
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)§
Input voltage range¶, VI, PG, SENSE, EN –0.3 V to 11 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Tables 1 and 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
§Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
¶All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (see Figure 3)#
PACKAGE
T
A
≤ 25°CDERATING FACTOR T
A
= 70°C T
A
= 125°C
PACKAGE
A
POWER RATING ABOVE TA = 25°C
A
POWER RATING
A
POWER RATING
D725 mW 5.8 mW/°C464 mW 145 mW
D
P
||
725
mW
1175 mW
5.8
mW/ C
9.4 mW/°C
464
mW
752 mW
145
mW
235 mW
PW|| 700 mW 5.6 mW/°C448 mW 140 mW
DISSIPATION RATING TABLE 2 – CASE TEMPERATURE (see Figure 4)#
PACKAGE
T
C
≤ 25°CDERATING FACTOR T
C
= 70°C T
C
= 125°C
PACKAGE
C
POWER RATING ABOVE TC = 25°C
C
POWER RATING
C
POWER RATING
D
P
2188 mW
2738 mW
17.5 mW/°C
21 9 mW/°C
1400 mW
1752 mW
438 mW
548 mW
P
PW||
2738
m
W
4025 mW
21
.
9
m
W/°C
32.2 mW/°C
1752
m
W
2576 mW
548
m
W
805 mW
#Dissipation rating tables and figures are provided for maintenance of junction temperature at or below
absolute maximum temperature of 150°C. For guidelines on maintaining junction temperature within
recommended operating range, see the Thermal Information section.
|| Refer to Thermal Information section for detailed power dissipation considerations when using the TSSOP packages.
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 3
1200
800
400
025 50 75 100
– Maximum Continuous Dissipation – mW
DISSIPATION DERATING CURVE†
vs
FREE-AIR TEMPERATURE
125 150
1400
1000
600
200 PW and PWP
Package
RθJA = 178°C/W
PD
TA – Free-Air Temperature – °C
P Package
RθJA = 106°C/W
D Package
RθJA = 172°C/W
Figure 4
2400
1600
800
025 50 75 100
– Maximum Continuous Dissipation – mW
3200
4000
DISSIPATION DERATING CURVE†
vs
CASE TEMPERATURE
4800
125 150
4400
3600
2800
2000
1200
400
PW Package
RθJC = 31°C/W
PD
TC – Case Temperature – °C
D Package
RθJC = 57°C/W
P Package
RθJC = 46°C/W
†Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C.
For guidelines on maintaining junction temperature within recommended operating range, see the Thermal Information section.
recommended operating conditions
MIN MAX UNIT
‡
TPS7101Q 2.5 10
In
p
ut voltage VI‡
TPS7133Q 3.77 10
V
Input
voltage
,
V
I
‡
TPS7148Q 5.2 10
V
TPS7150Q 5.33 10
High-level input voltage at EN, VIH 2 V
Low-level input voltage at EN, VIL 0.5 V
Output current range, IO0 500 mA
Operating virtual junction temperature range, TJ–40 125 °C
‡Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the
maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To
calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load)
Because the TPS7101 is programmable, rDS(on) should be used to calculate VDO before applying the above equation. The equation for calculating
VDO from rDS(on) is given in Note 2 in the electrical characteristics table. The minimum value of 2.5 V is the absolute lower limit for the
recommended input voltage range for the TPS7101.
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at IO = 10 mA, EN = 0 V , CO = 4.7 µF/CSR† = 1 Ω, SENSE/FB shorted to OUT
(unless otherwise noted)
PARAMETER TEST CONDITIONS
‡
T
J
TPS7101Q, TPS7133Q
TPS7148Q, TPS7150Q UNIT
J
MIN TYP MAX
Ground current (active mode)
EN ≤ 0.5 V
,
V
I
= V
O
+ 1 V
,
25°C 285 350
µA
Ground
current
(active
mode)
EN
≤
0.5
V,
0 mA ≤ IO ≤ 500 mA
VI
VO
+
1
V,
–40°C to 125°C 460 µ
A
In
p
ut current (standby mode)
EN V
27V≤V≤10 V
25°C 0.5
µA
Input
current
(standby
mode)
EN
=
V
I,
2
.
7
V
≤
V
I
≤
10
V
–40°C to 125°C 2 µ
A
Out
p
ut current limit
VO=0
VI=10V
25°C 1.2 2
A
Output
current
limit
V
O =
0
,
V
I =
10
V
–40°C to 125°C 2
A
Pass-element leaka
g
e current in standb
y
EN V
27V≤V≤10 V
25°C 0.5
µA
gy
mode
EN
=
V
I,
2
.
7
V
≤
V
I
≤
10
V
–40°C to 125°C 1 µ
A
PG leakage current
Normal o
p
eration
VPG =10V
25°C 0.02 0.5
µA
PG
l
ea
k
age curren
t
Normal
operation
,
V
PG =
10
V
–40°C to 125°C 0.5 µ
A
Output voltage temperature coefficient –40°C to 125°C 61 75 ppm/°C
Thermal shutdown junction temperature 165 °C
EN logic high (standby mode)
2.5 V ≤ VI ≤ 6 V
40°Cto125°C
2
V
EN
l
og
i
c
hi
g
h
(
s
t
an
db
y mo
d
e
)
6 V ≤ VI ≤ 10 V –
40°C
to
125°C
2.7
V
EN logic low (active mode)
27V≤VI≤10 V
25°C 0.5
V
EN
l
og
i
c
l
ow
(
ac
ti
ve mo
d
e
)
2
.
7
V
≤
V
I
≤
10
V
–40°C to 125°C 0.5
V
EN hysteresis voltage 25°C 50 mV
EN input current
0V≤VI≤10 V
0V≤VI≤10 V
25°C–0.5 0.5
µA
EN
i
npu
t
curren
t
0
V
≤
V
I
≤
10
V
0
V
≤
V
I
≤
10
V
–40°C to 125°C–0.5 0.5 µ
A
Minimum VIfor active
p
ass element
25°C 2.05 2.5
V
Minimum
V
I
for
active
pass
element
–40°C to 125°C 2.5
V
Minimum VIfor valid PG
IPG = 300 µA
IPG = 300 µA
25°C 1.06 1.5
V
Minimum
V
I
for
valid
PG
I
PG =
300
µ
A
I
PG =
300
µ
A
–40°C to 125°C 1.9
V
†CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101 electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, FB
shorted to OUT at device leads (unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TJ
TPS7101Q
UNIT
PARAMETER
TEST
CONDITIONS‡
T
JMIN TYP MAX
UNIT
Reference voltage (measured at FB
VI = 3.5 V, IO = 10 mA 25°C 1.178 V
Reference
voltage
(measured
at
FB
with OUT connected to FB) 2.5 V ≤ VI ≤ 10 V,
See Note 1 5 mA ≤ IO ≤ 500 mA, –40°C to 125°C 1.143 1.213 V
Reference voltage temperature
coefficient –40°C to 125°C 61 75 ppm/°C
VI=24V
50 µA≤IO≤150 mA
25°C 0.7 1
V
I =
2
.
4
V
,
50
µ
A
≤
I
O
≤
150
mA
–40°C to 125°C 1
VI=24V
150 mA ≤ I
O
≤ 500 25°C 0.83 1.3
Pass-element series resistance
V
I =
2
.
4
V
,
O
mA –40°C to 125°C1.3
Ω
(see Note 2)
VI=29V
50 µA≤IO≤500 mA
25°C 0.52 0.85
Ω
V
I =
2
.
9
V
,
50
µ
A
≤
I
O
≤
500
mA
–40°C to 125°C 0.85
VI = 3.9 V, 50 µA ≤ IO ≤ 500 mA 25°C 0.32
VI = 5.9 V, 50 µA ≤ IO ≤ 500 mA 25°C 0.23
In
p
ut regulation
V
I
= 2.5 V to 10 V, 50
µ
A ≤ I
O
≤ 500 mA, 25°C 18
mV
Input
regulation
I,
See Note 1
µO,
–40°C to 125°C 25
mV
I
O
= 5 mA to 500 mA, 2.5 V ≤ V
I
≤ 10 V, 25°C 14
mV
Out
p
ut regulation
O,
See Note 1
I,
–40°C to 125°C 25
mV
Output
regulation
I
O
= 50
µ
A to 500 mA, 2.5 V ≤ V
I
≤ 10 V, 25°C 22
mV
Oµ,
See Note 1
I,
–40°C to 125°C 54
mV
IO=50µA
25°C 48 59
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 44
dB
Ripple
rejection
f
=
120
Hz
I
O
= 500 mA, 25°C 45 54
dB
O,
See Note 1 –40°C to 125°C 44
Output noise-spectral density f = 120 Hz 25°C 2 µV/√Hz
10 H ≤f≤100 kH
CO = 4.7 µF 25°C 95
Output noise voltage 10 Hz ≤ f ≤ 100 kHz,
CSR†=1Ω
CO = 10 µF 25°C 89 µVrms
CSR†
=
1
Ω
CO = 100 µF 25°C 74
PG trip-threshold voltage§VFB voltage decreasing from above VPG –40°C to 125°C 1.101 1.145 V
PG hysteresis voltage§Measured at VFB 25°C 12 mV
PG out
p
ut low voltage§
IPG = 400 µA
VI= 2 13 V
25°C 0.1 0.4
V
PG
ou
t
pu
t
l
ow vo
lt
age
§
I
PG =
400
µ
A
,
V
I =
2
.
13
V
–40°C to 125°C 0.4
V
FB in
p
ut current
25°C–10 0.1 10
nA
FB
input
current
–40°C to 125°C–20 20
nA
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously , pass element rDS(on) increases (see Figure 27) to a point such that the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
2. To calculate dropout voltage, use equation:
VDO = IO ⋅ rDS(on)
rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively . For other
programmed values, refer to Figure 26.
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7133 electrical characteristics at IO = 10 mA, VI = 4.3 V , EN = 0 V , CO = 4.7 µF/CSR† = 1 Ω, SENSE
shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TJ
TPS7133Q
UNIT
PARAMETER
TEST
CONDITIONS‡
T
JMIN TYP MAX
UNIT
Out
p
ut voltage
VI = 4.3 V, IO = 10 mA 25°C 3.3
V
Output
voltage
4.3 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 3.23 3.37
V
IO=10mA
VI= 3 23 V
25°C 4.5 7
I
O =
10
mA
,
V
I =
3
.
23
V
–40°C to 125°C 8
Dropout voltage
IO= 100 mA
VI= 3 23 V
25°C 47 60
mV
D
ropou
t
vo
lt
age
I
O =
100
mA
,
V
I =
3
.
23
V
–40°C to 125°C 80
mV
IO= 500 mA
VI= 3 23 V
25°C 235 300
I
O =
500
mA
,
V
I =
3
.
23
V
–40°C to 125°C 400
Pass element series resistance
(3.23 V – V
O
)/I
O
, V
I
= 3.23 V, 25°C 0.47 0.6
Ω
Pass
-
element
series
resistance
(O)O,
IO = 500 mA
I,
–40°C to 125°C 0.8
Ω
In
p
ut regulation
VI=43Vto10V
50 µA≤IO≤500 mA
25°C 20
mV
Input
regulation
V
I =
4
.
3
V
to
10
V
,
50
µ
A
≤
I
O
≤
500
mA
–40°C to 125°C 27
mV
IO=5mAto500mA
43V≤VI≤10 V
25°C 21 38
mV
Out
p
ut regulation
I
O =
5
mA
to
500
mA
,
4
.
3
V
≤
V
I
≤
10
V
–40°C to 125°C 75
mV
Output
regulation
IO=50µA to 500 mA
43V≤VI≤10 V
25°C 30 60
mV
I
O =
50
µ
A
to
500
mA
,
4
.
3
V
≤
V
I
≤
10
V
–40°C to 125°C 120
mV
IO=50µA
25°C 43 54
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 40
dB
Ripple
rejection
f
=
120
Hz
IO= 500 mA
25°C 39 49
dB
I
O =
500
mA
–40°C to 125°C 36
Output noise-spectral density f = 120 Hz 25°C 2 µV/√Hz
10 H ≤f≤100 kH
CO = 4.7 µF25°C 274
Output noise voltage 10 Hz ≤ f ≤ 100 kHz,
CSR
†=
1Ω
CO = 10 µF25°C 228 µVrms
CSR†
=
1
Ω
CO = 100 µF25°C 159
PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C 2.868 3 V
PG hysteresis voltage 25°C 35 mV
PG out
p
ut low voltage
IPG =1mA
VI=28V
25°C 0.22 0.4
V
PG
output
low
voltage
I
PG =
1
mA
,
V
I =
2
.
8
V
–40°C to 125°C 0.4
V
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7148 electrical characteristics at IO = 10 mA, VI = 5.85 V , EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, SENSE
shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TJ
TPS7148Q
UNIT
PARAMETER
TEST
CONDITIONS‡
T
JMIN TYP MAX
UNIT
Out
p
ut voltage
VI = 5.85 V, IO = 10 mA 25°C 4.85
V
Output
voltage
5.85 V ≤VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 4.75 4.95
V
IO=10mA
VI= 4 75 V
25°C 2.9 6
I
O =
10
mA
,
V
I =
4
.
75
V
–40°C to 125°C 8
Dropout voltage
IO= 100 mA
VI= 4 75 V
25°C 30 37
mV
D
ropou
t
vo
lt
age
I
O =
100
mA
,
V
I =
4
.
75
V
–40°C to 125°C 54
mV
IO= 500 mA
VI= 4 75 V
25°C 150 180
I
O =
500
mA
,
V
I =
4
.
75
V
–40°C to 125°C 250
Pass element series resistance
(4.75 V – V
O
)/I
O
, V
I
= 4.75 V, 25°C 0.32 0.35
Ω
Pass
-
element
series
resistance
(O)O,
IO = 500 mA
I,
–40°C to 125°C 0.52
Ω
In
p
ut regulation
VI=585Vto10V
50 µA≤IO≤500 mA
25°C 27
mV
Input
regulation
V
I =
5
.
85
V
to
10
V
,
50
µ
A
≤
I
O
≤
500
mA
–40°C to 125°C 37
mV
IO=5mAto500mA
585V≤VI≤10 V
25°C 12 42
mV
Out
p
ut regulation
I
O =
5
mA
to
500
mA
,
5
.
85
V
≤
V
I
≤
10
V
–40°C to 125°C 80
mV
Output
regulation
IO=50µA to 500 mA
585V≤VI≤10 V
25°C 42 60
mV
I
O =
50
µ
A
to
500
mA
,
5
.
85
V
≤
V
I
≤
10
V
–40°C to 125°C 130
mV
IO=50µA
25°C 42 53
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 39
dB
Ripple
rejection
f
=
120
Hz
IO= 500 mA
25°C 39 50
dB
I
O =
500
mA
–40°C to 125°C 35
Output noise-spectral density f = 120 Hz 25°C 2 µV/√Hz
10 H ≤f≤100 kH
CO = 4.7 µF25°C 410
Output noise voltage 10 Hz ≤ f ≤ 100 kHz,
CSR
†=
1Ω
CO = 10 µF25°C 328 µVrms
CSR†
=
1
Ω
CO = 100 µF25°C 212
PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C 4.5 4.7 V
PG hysteresis voltage 25°C 50 mV
PG output low voltage
IPG =12mA
VI= 4 12 V
25°C 0.2 0.4
V
PG
ou
t
pu
t
l
ow vo
lt
age
I
PG =
1
.
2
mA
,
V
I =
4
.
12
V
–40°C to 125°C 0.4
V
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7150 electrical characteristics at IO = 10 mA, VI = 6 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, SENSE
shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS‡
TJ
TPS7150Q
UNIT
PARAMETER
TEST
CONDITIONS‡
T
JMIN TYP MAX
UNIT
Out
p
ut voltage
VI = 6 V, IO = 10 mA 25°C 5
V
Output
voltage
6 V ≤VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 4.9 5.1
V
IO=10mA
VI= 4 88 V
25°C 2.9 6
I
O =
10
mA
,
V
I =
4
.
88
V
–40°C to 125°C 8
Dropout voltage
IO= 100 mA
VI= 4 88 V
25°C 27 32
mV
D
ropou
t
vo
lt
age
I
O =
100
mA
,
V
I =
4
.
88
V
–40°C to 125°C 47
mV
IO= 500 mA
VI= 4 88 V
25°C 146 170
I
O =
500
mA
,
V
I =
4
.
88
V
–40°C to 125°C 230
Pass element series resistance
(4.88 V – V
O
)/I
O
, V
I
= 4.88 V, 25°C 0.29 0.32
Ω
Pass
-
element
series
resistance
(O)O,
IO = 500 mA
I,
–40°C to 125°C 0.47
Ω
In
p
ut regulation
VI=6Vto10V
50 µA≤IO≤500 mA
25°C 25
mV
Input
regulation
V
I =
6
V
to
10
V
,
50
µ
A
≤
I
O
≤
500
mA
–40°C to 125°C 32
mV
IO=5mAto500mA
6V≤VI≤10 V
25°C 30 45
mV
Out
p
ut regulation
I
O =
5
mA
to
500
mA
,
6
V
≤
V
I
≤
10
V
–40°C to 125°C 86
mV
Output
regulation
IO=50µA to 500 mA
6V≤VI≤10 V
25°C 45 65
mV
I
O =
50
µ
A
to
500
mA
,
6
V
≤
V
I
≤
10
V
–40°C to 125°C 140
mV
IO=50µA
25°C 45 55
Ri
pp
le rejection
f = 120 Hz
I
O =
50
µ
A
–40°C to 125°C 40
dB
Ripple
rejection
f
=
120
Hz
IO= 500 mA
25°C 42 52
dB
I
O =
500
mA
–40°C to 125°C 36
Output noise-spectral density f = 120 Hz 25°C 2 µV/√Hz
10 H ≤f≤100 kH
CO = 4.7 µF25°C 430
Output noise voltage 10 Hz ≤ f ≤ 100 kHz,
CSR
†=
1Ω
CO = 10 µF25°C 345 µVrms
CSR†
=
1
Ω
CO = 100 µF25°C 220
PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C 4.55 4.75 V
PG hysteresis voltage 25°C 53 mV
PG out
p
ut low voltage
IPG =12mA
VI= 4 25 V
25°C 0.2 0.4
V
PG
output
low
voltage
I
PG =
1
.
2
mA
,
V
I =
4
.
25
V
–40°C to 125°C 0.4
V
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at IO = 10 mA, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, TJ = 25°C, SENSE/FB
shorted to OUT (unless otherwise noted)
PARAMETER TEST CONDITIONS
‡
TPS7101Y, TPS7133Y
TPS7148Y, TPS7150Y UNIT
MIN TYP MAX
Ground current (active mode) EN ≤ 0.5 V,
0 mA ≤ IO ≤ 500 mA VI = VO + 1 V, 285 µA
Output current limit VO = 0, VI = 10 V 1.2 A
PG leakage current Normal operation, VPG = 10 V 0.02 µA
Thermal shutdown junction temperature 165 °C
EN hysteresis voltage 50 mV
Minimum VI for active pass element 2.05 V
Minimum VI for valid PG IPG = 300 µA 1.06 V
PARAMETER
TEST CONDITIONS‡
TPS7101Y
UNIT
PARAMETER
TEST
CONDITIONS‡
MIN TYP MAX
UNIT
Reference voltage (measured at FB with OUT
connected to FB) VI = 3.5 V, IO = 10 mA 1.178 V
VI = 2.4 V, 50 µA ≤ IO ≤ 150 mA 0.7
VI = 2.4 V, 150 mA ≤ IO ≤ 500 mA 0.83
Pass-element series resistance (see Note 2) VI = 2.9 V, 50 µA ≤ IO ≤ 500 mA 0.52 Ω
VI = 3.9 V, 50 µA ≤ IO ≤ 500 mA 0.32
VI = 5.9 V, 50 µA ≤ IO ≤ 500 mA 0.23
Input regulation VI = 2.5 V to 10 V,
See Note 1 50 µA ≤ IO ≤ 500 mA, 18 mV
Out
p
ut regulation
2.5 V ≤ VI ≤ 10 V,
See Note 1 IO = 5 mA to 500 mA, 14 mV
Output
regulation
2.5 V ≤ VI ≤ 10 V,
See Note 1 IO = 50 µA to 500 mA, 22 mV
Ripple rejection VI = 3.5 V,
IO = 50 µAf = 120 Hz, 59 dB
Output noise-spectral density VI = 3.5 V, f = 120 Hz 2µV/√Hz
VI
=
3.5 V,
CO = 4.7 µF 95
Output noise voltage
VI
=
3
.
5
V
,
10 Hz ≤ f ≤ 100 kHz,
†
CO = 10 µF 89 µVrms
CSR
†
= 1 ΩCO = 100 µF 74
PG hysteresis voltage§VI = 3.5 V, Measured at VFB 12 mV
PG output low voltage§VI = 2.13 V, IPG = 400 µA 0.1 V
FB input current VI = 3.5 V VI = 3.5 V 0.1 nA
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously , pass element rDS(on) increases (see Figure 27) to a point such that the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
2. To calculate dropout voltage, use equation:
VDO = IO ⋅ rDS(on)
rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively . For other
programmed values, refer to Figure 26.
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at IO = 10 mA, EN = 0 V , CO = 4.7 µF/CSR† = 1 Ω, TJ = 25°C, SENSE shorted
to OUT (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS‡
TPS7133Y
UNIT
PARAMETER
TEST
CONDITIONS‡
MIN TYP MAX
UNIT
Output voltage VI = 4.3 V, IO = 10 mA 3.3 V
VI = 3.23 V, IO = 10 mA 0.02
Dropout voltage VI = 3.23 V, IO = 100 mA 47 mV
VI = 3.23 V, IO = 500 mA 235
Pass-element series resistance (3.23 V – VO)/IO,
IO = 500 mA VI = 3.23 V, 0.47 Ω
Out
p
ut regulation
4.3 V ≤ VI ≤ 10 V, IO = 5 mA to 500 mA 21 mV
Output
regulation
4.3 V ≤ VI ≤ 10 V, IO = 50 µA to 500 mA 30 mV
Ri
pp
le rejection
V
I
= 4.3 V, IO = 50 µA 54
dB
Ripple
rejection
I,
f = 120 Hz IO = 500 mA 49
dB
Output noise-spectral density VI = 4.3 V, f = 120 Hz 2µV/√Hz
VI
=
4.3 V,
CO = 4.7 µF274
Output noise voltage
VI
=
4
.
3
V
,
10 Hz ≤ f ≤ 100 kHz,
CSR†
CO = 10 µF228 µVrms
CSR
†
= 1 ΩCO = 100 µF159
PG hysteresis voltage VI = 4.3 V 35 mV
PG output low voltage VI = 2.8 V, IPG = 1 mA 0.22 V
PARAMETER
TEST CONDITIONS‡
TPS7148Y
UNIT
PARAMETER
TEST
CONDITIONS‡
MIN TYP MAX
UNIT
Output voltage VI = 5.85 V, IO = 10 mA 4.85 V
VI = 4.75 V, IO = 10 mA 0.08
Dropout voltage VI = 4.75 V, IO = 100 mA 30 mV
VI = 4.75 V, IO = 500 mA 150
Pass-element series resistance (4.75 V – VO)/IO,
IO = 500 mA VI = 4.75 V, 0.32 Ω
Out
p
ut regulation
5.85 V ≤ VI ≤ 10 V, IO = 5 mA to 500 mA 12 mV
Output
regulation
5.85 V ≤ VI ≤ 10 V, IO = 50 µA to 500 mA 42 mV
Ri
pp
le rejection
V
I
= 5.85 V, IO = 50 µA 53
dB
Ripple
rejection
I,
f = 120 Hz IO = 500 mA 50
dB
Output noise-spectral density VI = 5.85 V, f = 120 Hz 2µV/√Hz
VI
=
5.85 V,
CO = 4.7 µF410
Output noise voltage
VI
=
5
.
85
V
,
10 Hz ≤ f ≤ 100 kHz,
CSR†
CO = 10 µF328 µVrms
CSR
†
= 1 ΩCO = 100 µF212
PG hysteresis voltage VI = 5.85 V 50 mV
PG output low voltage VI = 4.12 V, IPG = 1.2 mA 0.2 0.4 V
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at IO = 10 mA, EN = 0 V , CO = 4.7 µF/CSR† = 1 Ω, TJ = 25°C, SENSE shorted
to OUT (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS‡
TPS7150Y
UNIT
PARAMETER
TEST
CONDITIONS‡
MIN TYP MAX
UNIT
Output voltage VI = 6 V, IO = 10 mA 5 V
VI = 4.88 V, IO = 10 mA 0.13
Dropout voltage VI = 4.88 V, IO = 100 mA 27 mV
VI = 4.88 V, IO = 500 µA 146
Pass-element series resistance (4.88 V – VO)/IO,
IO = 500 mA VI = 4.88 V, 0.29 Ω
Out
p
ut regulation
6 V ≤ VI ≤ 10 V, IO = 5 mA to 500 mA 30 mV
Output
regulation
6 V ≤ VI ≤ 10 V, IO = 50 µA to 500 mA 45 mV
Ri
pp
le rejection
V
I
= 6 V, IO = 50 µA 55
dB
Ripple
rejection
I,
f = 120 Hz IO = 500 mA 52
dB
Output noise-spectral density VI = 6 V, f = 120 Hz 2µV/√Hz
VI
=
6V,
CO = 4.7 µF430
Output noise voltage
VI
=
6
V
,
10 Hz ≤ f ≤ 100 kHz,
CSR†
CO = 10 µF345 µVrms
CSR
†
= 1 ΩCO = 100 µF220
PG hysteresis voltage VI = 6 V 53 mV
PG output low voltage VI = 4.25 V, PG = 1.2 mA 0.2 V
†CSR refers to the total series resistance, including the ESR of the capacitor , any series resistance added externally, and PWB trace resistance
to CO.
‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Output current 5
IQQuiescent current vs Input voltage 6
vs Free-air temperature 7
VDO Dropout voltage vs Output current 8
∆VDO Change in dropout voltage vs Free-air temperature 9
∆VOChange in output voltage vs Free-air temperature 10
VOOutput voltage vs Input voltage 11
∆VOChange in output voltage vs Input voltage 12
13
VO
Out
p
ut voltage
vs Out
p
ut current
14
V
O
Output
voltage
vs
Output
current
15
16
17
Ri
pp
le rejection
vs Frequency
18
Ripple
rejection
vs
Frequency
19
20
21
Out
p
ut s
p
ectral noise density
vs Frequency
22
Output
spectral
noise
density
vs
Frequency
23
24
rDS(on) Pass-element resistance vs Input voltage 25
RDivider resistance vs Free-air temperature 26
II(SENSE) SENSE pin current vs Free-air temperature 27
FB leakage current vs Free-air temperature 28
VI
Minimum input voltage for active-pass element vs Free-air temperature 29
V
IMinimum input voltage for valid PG vs Free-air temperature 30
II(EN) Input current (EN)vs Free-air temperature 31
Output voltage response from Enable (EN) 32
VPG Power-good (PG) voltage vs Output voltage 33
CSR
Com
p
ensation series resistance
vs Out
p
ut current
34
CSR
Compensation
series
resistance
vs
Output
current
35
CSR
Com
p
ensation series resistance
vs Added ceramic ca
p
acitance
36
CSR
Compensation
series
resistance
vs
Added
ceramic
capacitance
37
CSR
Com
p
ensation series resistance
vs Out
p
ut current
38
CSR
Compensation
series
resistance
vs
Output
current
39
CSR
Com
p
ensation series resistance
vs Added ceramic ca
p
acitance
40
CSR
Compensation
series
resistance
vs
Added
ceramic
capacitance
41
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
315
295
285
265 0 50 100 150 200 250 300
– Quiescent Current –
325
345
QUIESCENT CURRENT
vs
OUTPUT CURRENT
355
350 400 450 500
335
305
275
Aµ
TA = 25°C
IO – Output Current – mA
TPS71xx, VI = 10 V
TPS7150, VI = 6 V
TPS7133, VI = 4.3 V
TPS7148, VI = 5.85 V
IQ
Figure 6
200
150
50
00123456
250
350
400
78910
100
300
QUIESCENT CURRENT
vs
INPUT VOLTAGE
VI – Input Voltage – V
TPS7133
TPS7150
TPS7148
TA = 25°C
RL = 10 Ω
TPS7101 With VO
Programmed to 2.5 V
– Quiescent Current –Aµ
IQ
Figure 7
300
250
200
150
350
QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
400
–50 –25 0 25 50 75 100 125
VI = VO(nom) + 1 V
IO = 10 mA
– Quiesent Current –
IQAµ
TA – Free-Air Temperature – °C
TPS7148Q
Figure 8
0.25
0.2
0.1
0.05
0
0.15
0 50 100 150 200 250 300
0.3
350 400 450 500
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
TA = 25°C
TPS7148
TPS7150
Dropout Voltage – V
IO – Output Current – mA
TPS7133
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
Change in Dropout Voltage – mV
CHANGE IN DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
10
8
6
4
2
0
–2
–4
–6
–8
–10
–50 –25 0 25 50 75 100 125
IO = 100 mA
TA – Free-Air Temperature – °C
Figure 10
0
– Change in Output Voltage – mV
10
15
CHANGE IN OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
20
5
–5
–10
–20
–50 –25 0 25 50 75 100 125
VI = VO(nom) + 1 V
IO = 10 mA
VO
–15
TA – Free-Air Temperature – °C
∆
Figure 11
3
2
1
00123456
– Output Voltage – V
4
5
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
6
78910
TPS7133
TA = 25°C
RL = 10 ΩTPS7150
TPS7148
VO
VI – Input Voltage – V
TPS7101 With VO
Programmed to 2.5 V
Figure 12
0
4567
– Change In Output Voltage – mV
5
15
CHANGE IN OUTPUT VOLTAGE
vs
INPUT VOLTAGE
20
8910
10
–5
–10
–15
–20
TPS7133
TPS7150
TPS7148
TA = 25°C
RL = 10 Ω
VI – Input Voltage – V
∆VO
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 13
2.5
2.495
2.485
2.480 100 200 300
– Output Voltage – V
2.505
2.515
TPS7101Q
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
2.52
400 500
2.49
2.51
VO
IO – Output Current – mA
TA = 25°C
VO Programmed to 2.5 V
VI = 3.5 V
VI = 10 V
Figure 14
3.3
3.29
3.27
3.260 100 200 300
– Output Voltage – V
3.31
3.33
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.34
400 500
3.28
3.32
TPS7133Q
TA = 25°C
VI = 10 V
VI = 4.3 V
VO
IO – Output Current – mA
Figure 15
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
TPS7148Q
4.87
4.85
4.83
4.8 0 100 300
– Output Voltage – V
4.89
4.92
500
4.91
4.9
4.88
4.86
4.84
4.82
4.81
200 400
VO
IO – Output Current – mA
TA = 25°C
VI = 5.85 V
VI = 10 V
Figure 16
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
TPS7150Q
5.01
4.99
4.97
4.94 0 100 300
– Output Voltage – V
5.03
5.06
400 500
5.05
5.04
5.02
5
4.98
4.96
4.95
200
TA = 25°C
VI = 6 V
VI = 10 V
VO
IO – Output Current – mA
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 17
40
30
10
0
Ripple Rejection – dB
50
60
f – Frequency – Hz
TPS7101Q
RIPPLE REJECTION
vs
FREQUENCY
70
20
10 100 1K 10K 100K 1M 10M
RL = 500 Ω
RL = 10 Ω
CO = 4.7 µF (CSR = 1 Ω)
No Input Capacitance
VO Programmed to 2.5 V
RL = 100 kΩ
TA = 25°C
VI = 3.5 V
Figure 18
10
M
1 M100 k10 k1 k100
Ripple Rejection – dB
f – Frequency – Hz
RIPPLE REJECTION
vs
FREQUENCY
70
60
50
40
30
20
10
0
–1010
RL = 100 kΩ
RL = 500 Ω
RL = 10 Ω
TPS7133Q
CO = 4.7 µF (CSR = 1 Ω)
No Input Capacitance
TA = 25°C
VI = 3.5 V
Figure 19
10 M1 M100 k10 k1 k100
Ripple Rejection – dB
f – Frequency – Hz
RIPPLE REJECTION
vs
FREQUENCY
70
60
50
40
30
20
10
0
–1010
RL = 100 kΩ
RL = 500 Ω
TPS7148Q
RL = 10 Ω
CO = 4.7 µF (CSR = 1 Ω)
No Input Capacitance
TA = 25°C
VI = 3.5 V
Figure 20
10
M
1 M100 k10 k1 k100
Ripple Rejection – dB
f – Frequency – Hz
RIPPLE REJECTION
vs
FREQUENCY
70
60
50
40
30
20
10
010
RL = 100 kΩ
RL = 500 Ω
RL = 10 Ω
CO = 4.7 µF (CSR = 1 Ω)
No Input Capacitance
TPS7150Q
TA = 25°C
VI = 3.5 V
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 21
0.01
0.1
f – Frequency – Hz
TPS7101Q
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
1
10
10 102103104105
CO = 4.7 µF (CSR = 1 Ω)
CO = 100 µF (CSR = 1 Ω)
CO = 10 µF (CSR = 1 Ω)
TA = 25°C
No Input Capacitance
VI = 3.5 V
VO Programmed to 2.5 V
Output Spectral Noise Density –V/ Hzµ
Figure 22
10 f – Frequency – Hz
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
10
1
0.1
0.01
CO = 10 µF (CSR = 1 Ω)
CO = 100 µF (CSR = 1 Ω)
CO = 4.7 µF (CSR = 1 Ω)
TA = 25°C
No Input Capacitance
VI = 4.3 V
TPS7133Q
102103104105
Output Spectral Noise Density –V/ Hzµ
Figure 23
0.01
10 100 1 k 10 k 100 k
0.1
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
1
10
CO = 10 µF (CSR = 1 Ω)
CO = 4.7 µF (CSR = 1 Ω)
CO = 100 µF (CSR = 1 Ω)
f – Frequency – Hz
TPS7148Q
TA = 25°C
No Input Capacitance
VI = 5.85 V
Output Spectral Noise Density –V/ Hzµ
Figure 24
10 100 1 k 10 k 100 k
CO = 10 µF (CSR = 1 Ω)
CO = 4.7 µF (CSR = 1 Ω)
CO = 100 µF (CSR = 1 Ω)
f – Frequency – Hz
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
TPS7150Q
10
1
0.1
0.01
TA = 25°C
No Input Capacitance
VI = 6 V
Output Spectral Noise Density –V/ Hzµ
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 25
0.4
0.3
0.2
0.1 2457
– Pass-Element Resistance –
0.5
PASS-ELEMENT RESISTANCE
vs
INPUT VOLTAGE
0.6
910
368
TA = 25°C
VI(FB) = 1.12 V
rDS(on) Ω
VI – Input Voltage – V
1
0.9
0.8
0.7
1.1
IO = 500 mA
IO = 100 mA
Figure 26
0.8
0.6
0.5
0.4
1
1.1
DIVIDER RESISTANCE
vs
FREE-AIR TEMPERATURE
1.2
0.9
0.7
–50 –25 0 25 50 75 100 125
TPS7150
TPS7148
TPS7133
VI = VO(nom) + 1 V
VI(sense) = VO(nom)
Ω
TA – Free-Air Temperature – °C
R – Divider Resistance – M
Figure 27
5.2
4.8
4.6
4.4
–
Sense
Pin
C
u
rrent
–
5.6
5.8
FIXED-OUTPUT VERSIONS
SENSE PIN CURRENT
vs
FREE-AIR TEMPERATURE
6
5.4
5
–50 –25 0 25 50 75 100 125
VI = VO(nom) + 1 V
VI(sense) = VO(nom)
II(
sense
)Aµ
TA – Free-Air Temperature – °C
Figure 28
0.3
0.2
0.1
0
FB Leakage Current – nA
0.4
0.5
ADJUSTABLE VERSION
FB LEAKAGE CURRENT
vs
FREE-AIR TEMPERATURE
0.6
–50 –25 0 25 50 75 100 125
VFB = 2.5 V
TA – Free-Air Temperature – °C
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 29
2.03
2.01
2.08
2
– Minimum Input Voltage – V
2.06
2.04
2.07
MINIMUM INPUT VOLTAGE FOR ACTIVE
PASS ELEMENT
vs
FREE-AIR TEMPERATURE
2.1
2.09
2.05
2.02
–50 –25 0 25 50 75 100 125
ÁÁ
ÁÁ
VI
TA – Free-Air Temperature – °C
RL = 500 Ω
Figure 30
1.08
1.07
1.06
1.05
– Minimum Input Voltage – V
1.09
MINIMUM INPUT VOLTAGE FOR VALID
POWER GOOD (PG)
vs
FREE-AIR TEMPERATURE
1.1
–50 –25 0 25 50 75 100 125
ÁÁ
ÁÁ
VI
TA – Free-Air Temperature – °C
50
40
20
10
0
90
30
– Input Current – nA
70
60
80
EN INPUT CURRENT
vs
FREE-AIR TEMPERATURE
100
–40 –20 0 20 40 60 80 100 120 140
VI = VI(EN) = 10 V
II(EN)
TA – Free-Air Temperature – °C
Figure 31
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
– Output Voltage – V
OUTPUT VOLTAGE RESPONSE FROM
ENABLE (EN)
0
2
4
6
0 20 40 60 80 100 120 140
EN Voltage – V
VO
TA = 25°C
RL = 500 Ω
CO = 4.7 µF (ESR = 1Ω)
No Input Capacitance
VO(nom)
Time – µs
–2
Figure 32
POWER-GOOD (PG) VOLTAGE
vs
OUTPUT VOLTAGE
3
2
1
093 94 95 96
– Power-Good (PG) Voltage – V
4
6
97 98
TA = 25°C
PG Pulled Up to 5 V With 5 kΩ
VO – Output Voltage (VO as a percent of VO(nom)) – %
5
ÁÁ
ÁÁ
VPG
Figure 33
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 34
1
0.10 50 100 150 200 250 300
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
OUTPUT CURRENT
350 400 450 500
10
100
IO – Output Current – mA
Region of Instability
Region of Instability
VI = VO(nom) + 1 V
No Input Capacitance
CO = 4.7 µF
No Added Ceramic Capacitance
TA = 25°C
Compensation Series Resistance –Ω
CSR –
Figure 35
1
0.10 50 100 150 200 250 300 350 400 450 500
10
100
IO – Output Current – mA
Region of Instability
Region of Instability
VI = VO(nom) + 1 V
No Input Capacitance
CO = 4.7 µF + 0.5 µF of
Ceramic Capacitance
TA = 25°C
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
OUTPUT CURRENT
Compensation Series Resistance –ΩCSR –
Figure 36
1
0.10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
10
100
Ceramic Capacitance – µF
Region of Instability
Region of Instability
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
ADDED CERAMIC CAPACITANCE
VI = VO(nom) + 1 V
No Input Capacitance
IO= 100 mA
CO = 4.7 µF
TA = 25°C
Compensation Series Resistance –ΩCSR –
Figure 37
1
0.10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
10
100
Ceramic Capacitance – µF
Region of Instability
Region of Instability
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
ADDED CERAMIC CAPACITANCE
VI = VO(nom) + 1 V
No Input Capacitance
IO= 500 mA
CO = 4.7 µF
TA = 25°C
Compensation Series Resistance –ΩCSR –
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 38
1
0.10 50 100 150 200 250 300
TYPICAL REGIONS OF STABILITY†
COMPENSATION SERIES RESISTANCE
vs
OUTPUT CURRENT
350 400 450 500
10
100
IO – Output Current – mA
Region of Instability VI = VO(nom) + 1 V
No Input Capacitance
CO = 10 µF
No Ceramic Capacitance
TA = 25°C
Compensation Series Resistance –ΩCSR –
0.2
Figure 39
1
0.10 50 100 150 200 250 300
TYPICAL REGIONS OF STABILITY†
COMPENSATION SERIES RESISTANCE
vs
OUTPUT CURRENT
350 400 450 500
10
100
IO – Output Current – mA
Region of Instability
VI = VO(nom) + 1 V
No Input Capacitance
CO = 10 µF + 0.5 µF of
Added Ceramic Capacitance
TA = 25°C
Compensation Series Resistance –ΩCSR –
0.2
Figure 40
1
0.10 0.1 0.2 0.3 0.4 0.5 0.6
TYPICAL REGIONS OF STABILITY†
COMPENSATION SERIES RESISTANCE
vs
ADDED CERAMIC CAPACITANCE
0.7 0.8 0.9 1
10
100
Ceramic Capacitance – µF
Region of Instability
VI = VO(nom) + 1 V
No Input Capacitance
CO = 10 µF
IO = 100 mA
TA = 25°C
Compensation Series Resistance –ΩCSR –
0.2
Figure 41
1
0.10 0.1 0.2 0.3 0.4 0.5 0.6
TYPICAL REGIONS OF STABILITY†
COMPENSATION SERIES RESISTANCE
vs
ADDED CERAMIC CAPACITANCE
0.7 0.8 0.9 1
10
100
Ceramic Capacitance – µF
Region of Instability
VI = VO(nom) + 1 V
No Input Capacitance
CO = 10 µF
IO = 500 mA
TA = 25°C
Compensation Series Resistance –ΩCSR –
0.2
†CSR values below 0.1 Ω are not recommended.
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
IN
EN
OUT
SENSE +
GND CO
CSR
Ccer†RL
VI
†Ceramic capacitor
To Load
Figure 42. Test Circuit for Typical Regions of Stability (Figures 34 through 41)
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
The TPS71xx series of low-dropout (LDO) regulators is designed to overcome many of the shortcomings of
earlier-generation LDOs, while adding features such as a power-saving shutdown mode and a power-good
indicator. The TPS71xx family includes three fixed-output voltage regulators: the TPS7133 (3.3 V), the
TPS7148 (4.85 V), and the TPS7150 (5 V). The family also offers an adjustable device, the TPS7101 (adjustable
from 1.2 V to 9.75 V).
device operation
The TPS71xx, unlike many other LDOs, features very low quiescent currents that remain virtually constant even
with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directly
proportional to the load current through the regulator (IB = IC/β). Close examination of the data sheets reveals
that those devices are typically specified under near no-load conditions; actual operating currents are much
higher as evidenced by typical quiescent current versus load current curves. The TPS71xx uses a PMOS
transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents are low
and invariable over the full load range. The TPS71xx specifications reflect actual performance under load.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in β forces an increase in IB to maintain the load. During power up, this translates
to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,
it means rapid battery discharge when the voltage decays below the minimum required for regulation. The
TPS71xx quiescent current remains low even when the regulator drops out, eliminating both problems.
Included in the TPS71xx family is a 4.85-V regulator, the TPS7148. Designed specifically for 5-V cellular
systems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systems
specified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery pack
before the device drops out, adding crucial talk minutes between charges.
The TPS71xx family also features a shutdown mode that places the output in the high-impedance state
(essentially equal to the feedback-divider resistance) and reduces quiescent current to under 2 µA. If the
shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated
output voltage is reestablished in typically 120 µs.
minimum load requirements
The TPS71xx family is stable even at zero load; no minimum load is required for operation.
SENSE-pin connection
The SENSE pin of fixed-output devices must be connected to the regulator output for proper functioning of the
regulator . Normally , this connection should be as short as possible; however, the connection can be made near
a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to a
high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through
to the regulator output. Routing the SENSE connection to minimize/avoid noise pickup is essential. Adding an
RC network between SENSE and OUT to filter noise is not recommended because it can cause the regulator
to oscillate.
external capacitor requirements
An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 µF) improves load
transient response and noise rejection if the TPS71xx is located more than a few inches from the power supply .
A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients
with fast rise times are anticipated.
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
external capacitor requirements (continued)
As with most LDO regulators, the TPS71xx family requires an output capacitor for stability. A 10-µF
solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the
full load range (see Figure 43). Adding high-frequency ceramic or film capacitors (such as power-supply bypass
capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum
capacitor is less than 1.2 Ω over temperature. Where component height and/or mounting area is a problem,
physically smaller, 10-µF devices can be screened for ESR. Figures 34 through 41 show the stable regions of
operation using different values of output capacitance with various values of ceramic load capacitance.
In applications with little or no high-frequency bypass capacitance (< 0.2 µF), the output capacitance can be
reduced to 4.7 µF, provided ESR is maintained between the values shown in figures 34 through 41. Because
minimum capacitor ESR is seldom if ever specified, it may be necessary to add a 0.5-Ω to 1-Ω resistor in series
with the capacitor and limit ESR to 1.5 Ω maximum.
SENSE
PG
OUT
OUT
9
8
6
10
IN
IN
IN
EN
GND
321
20
15
14
13
VI
C1
0.1 µF
50 V
PG
ESR
VO
10 µF
+
TPS71xx†
CO
†TPS7133, TPS7148, TPS7150 (fixed-voltage options)
250 kΩ
Figure 43. Typical Application Circuit
programming the TPS7101 adjustable LDO regulator
Programming the adjustable regulators is accomplished using an external resistor divider as shown in
Figure 44. The equation governing the output voltage is:
VO
+
Vref
@ǒ
1
)
R1
R2
Ǔ
where
Vref = reference voltage, 1.178 V typ
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
programming the TPS7101 adjustable LDO regulator (continued)
Resistors R1 and R2 should be chosen for approximately 7-µA divider current. A recommended value for R2
is 169 kΩ with R1 adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherent
advantage and consume more power. Larger values of R1 and R2 should be avoided as leakage currents at
FB introduce an error. Solving equation 1 for R1 yields a more useful equation for choosing the appropriate
resistance:
R1
+ǒ
VO
Vref
*
1
Ǔ@
R2
OUTPUT
VOLTAGE R1 R2
2.5 V
3.3 V
3.6 V
4 V
5 V
6.4 V
UNIT
191
309
348
402
549
750
169
169
169
169
169
169
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VO
VIPG
OUT
FB
R1
R2
GND
EN
IN
<0.5V
>2.7 V
TPS7101
Power-Good
Indicator
0.1 µF250 kΩ
+
Figure 44. TPS7101 Adjustable LDO Regulator Programming
power-good indicator
The TPS71xx features a power-good (PG) output that can be used to monitor the status of the regulator. The
internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal
regulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires a pullup
resistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or as a low-battery
indicator . PG does not assert itself when the regulated output voltage falls outside the specified 2% tolerance,
but instead reports an output voltage low, relative to its nominal regulated value.
regulator protection
The TPS71xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the
input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output
to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS71xx also features internal current limiting and thermal protection. During normal operation, the
TPS71xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of
the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator
operation resumes.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS7101QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
TPS7101QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
TPS7101QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS7101QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS7101QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
TPS7101QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
TPS7101QPW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
TPS7101QPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
TPS7101QPWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI Samples Not Available
TPS7101QPWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS7101QPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS7133QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS7133QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS7133QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS7133QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS7133QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
TPS7133QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
TPS7133QPW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS7133QPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS7133QPWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI Samples Not Available
TPS7133QPWPLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI Samples Not Available
TPS7133QPWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS7133QPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS7148QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS7148QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS7148QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS7148QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS7148QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
TPS7148QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
TPS7148QPWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI Samples Not Available
TPS7150QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS7150QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS7150QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS7150QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS7150QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
TPS7150QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
TPS7150QPWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI Samples Not Available
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 3
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS7101QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS7101QPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS7133QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS7133QPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS7148QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS7150QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-May-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS7101QDR SOIC D 8 2500 346.0 346.0 29.0
TPS7101QPWR TSSOP PW 20 2000 346.0 346.0 33.0
TPS7133QDR SOIC D 8 2500 346.0 346.0 29.0
TPS7133QPWR TSSOP PW 20 2000 346.0 346.0 33.0
TPS7148QDR SOIC D 8 2500 346.0 346.0 29.0
TPS7150QDR SOIC D 8 2500 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-May-2011
Pack Materials-Page 2
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