ams Datasheet Page 1
[v1-00] 2016-Jul-19 Document Feedback
TSL210
640 × 1 Linear Sensor Array
The TSL210 Linear Sensor Array consists of five sections of
128 photodiodes, each with associated charge amplifier
circuitry, running from a common clock. These sections can be
connected to form a contiguous 640 × 1 pixel array. Device
pixels measure 120μm (H) by 70μm (W) with 125μm
center-to-center pixel spacing. Operation is simplified by
internal logic that requires only a serial input (SI1 through SI5)
for each section and a common clock for the five sections.
The device is intended for use in a wide variety of applications
including contact imaging, mark and code reading, bar-code
reading, edge detection and positioning, OCR, level detection,
and linear and rotational encoding.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of TSL210, 640x1 Linear Sensor Array
are listed below:
Figure 1:
Added Value of Using TSL210
•Wide Dynamic Range: 2000:1 (66dB)
•Output Referenced to Ground
•Low Image Lag: 0.5% Typical
•Operation to 5MHz
•Single 5V Supply
Benefits Features
• Provides High Density Pixel Count •640 x 1 Sensor-Element Organization
• Enables High Resolution Scanning •200 Dots-per-Inch (DPI) Sensor Pitch
• Enables Capacitive Threshold Sensing •High Linearity and Uniformity
• Provides Full Dynamic Range •Rail-to-Rail Output Swing
General Description
Page 2 ams Datasheet
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TSL210 − General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 2:
TSL210 Block Diagram
SI
tiB-821KLC Shift Register
Q128
Switch Control Logic
Pixel
2
Pixel
128
Pixel
3
Analog
Bus
Output
Amplier
Gain
Trim
Q3Q2Q1
VDD
RL
(External
330
Load)
AO
SO
GND
Integrator
Reset
_
+
Pixel 1
Sample/
Output
S1
S2
2
13
1
2
Page 4 ams Datasheet
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TSL210 − Pin Assignments
Figure 4:
Terminal Functions
Terminal I/O Description
No. Name
1V
DD
Supply voltage for both analog and digital circuits
2CLK I
Clock input for all sections. The clock controls the charge transfer,
pixel output, and reset.
3 SI1 I SI1 defines the start of the data out sequence for section 1.
4 AO1 O Analog output of section 1
5SO1 O
SO1 provides the signal to drive the SI2 input in serial mode or end of
data for section 1 in parallel mode
6 SI2 I SI2 defines the start of the data out sequence for section 2
7 AO2 O Analog output of section 2
8SO2 O
SO2 provides the signal to drive the SI3 input in serial mode or end of
data for section 2 in parallel mode
9 GND Ground (substrate). All voltages are referenced to the substrate.
10 SI3 I SI3 defines the start of the data out sequence for section 3
11 AO3 O Analog output of section 3
12 SO3 O SO3 provides the signal to drive the SI4 input in serial mode or end of
data for section 3 in parallel mode
13 SI4 I SI4 defines the start of the data out sequence for section 4
14 AO4 O Analog output of section 4
15 SO4 O SO4 provides the signal to drive the SI5 input in serial mode or end of
data for section 4 in parallel mode
16 SI5 I SI5 defines the start of the data out sequence for section 5
17 AO5 O Analog output of section 5
18 SO5 O SO5 provides the signal to drive the SI input of another device for
cascading or as an end of data indication
ams Datasheet Page 5
[v1-00] 2016-Jul-19 Document Feedback
TSL210 − Detailed Description
The device consists of five sections of 128 photodiodes
(called pixels - 640 total in the device) arranged in a linear array.
Each section has its own signal input and output lines, and all
five sections are connected to a common clock line. Light
energy impinging on a pixel generates photocurrent that is
then integrated by the active integration circuitry associated
with that pixel.
During the integration period, a sampling capacitor connects
to the output of the integrator through an analog switch. The
amount of charge accumulated at each pixel is directly
proportional to the light intensity on that pixel and the
integration time. The voltage output developed for each pixel
is according to the following relationship:
where:
•V
out
is the analog output voltage for white condition
•V
drk
is the analog output voltage for dark condition
•R
e
is the device responsivity for a given wavelength of
light given in V/(μJ/cm
2
)
•E
e
is the incident irradiance in μW/cm
2
•t
int
is integration time in seconds
The output and reset of the integrators in each section are
controlled by a 128-bit shift register and reset logic. An output
cycle is initiated by clocking in a logic 1 on SI. As the SI pulse is
clocked through the shift register, the charge stored on the
sampling capacitors of each pixel is sequentially connected to
a charge-coupled output amplifier that generates a voltage on
analog output AO (given above). After being read, the pixel
integrator is then reset, and the next integration period begins
for that pixel. On the 129
th
clock rising edge, the SO pulse is
clocked out on SO signifying the end of the read cycle. The
section is then ready for another read cycle. The SO of each
section can be connected to SI on the next section in the array
(Figure 13). SO can be used to signify the read is complete.
AO is driven by a source follower that requires an external
pulldown resistor (330Ω typical). The output is nominally 0V for
no light input, 2V for normal white-level, and 3.4V for saturation
light level. When the device is not in the output phase, AO is in
a high impedance state.
A 0.1μF bypass capacitor should be connected between V
DD
and ground as close as possible to the device.
Detailed Description
(EQ1)
V
out
V
drk
R
e
()E
e
()t
int
()+=
Page 6 ams Datasheet
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TSL210 − Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated under Electrical
Characteristics is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Figure 5:
Absolute Maximum Ratings
Symbol Parameter Min Max Unit
V
DD
Supply voltage range -0.3 6 V
V
I
Input voltage range -0.3 V
DD
+ 0.3 V
I
IK
Input clamp current (V
I
< 0 or V
I
> V
DD
)-20 20 mA
I
OK
Output clamp current (V
O
< 0 or V
O
> V
DD
)-25 25 mA
V
O
Voltage range applied to any output in the high
impedance or power-off state -0.3 V
DD
+ 0.3 V
I
O
Continuous output current (V
O
=0 to V
DD
)-25 25 mA
Continuous current through V
DD
or GND -100 100 mA
I
O
Analog output current range -25 25 mA
T
A
Operating free-air temperature range -25 85 °C
T
STRG
Storage temperature range -25 85 °C
Lead temperature on connection pad for 10 seconds 260 °C
ESD
HBM
ESD tolerance, human body model ±2000 V
Absolute Maximum Ratings
ams Datasheet Page 7
[v1-00] 2016-Jul-19 Document Feedback
TSL210 − Electrical Characteristics
All limits are guaranteed. The parameters with min and max
values are guaranteed with production tests or
SQC (Statistical Quality Control) methods.
Figure 6:
Recommended Operating Conditions (see Figure 10 and Figure 12)
Note(s):
1. SI must go low before the rising edge of the next clock pulse.
Figure 7:
Electrical Characteristics at f
clock
=200kHz, V
DD
=5V, T
A
=25°C, λ
p
= 640nm, t
int
=5ms,
R
L
= 330Ω, E
e
= 18μW/cm
2
(unless otherwise noted)
(3)
Symbol Parameter Min Nom Max Unit
V
DD
Supply voltage 4.5 5 5.5 V
V
I
Input voltage 0 V
DD
V
V
IH
High-level input voltage 2 V
DD
V
V
IL
Low-level input voltage 0 0.8 V
λ Wavelength of light source 400 1000 nm
f
clock
Clock frequency 5 5000 kHz
t
int
Sensor integration time, serial 0.128 100 ms
t
int
Sensor integration time, parallel 0.026 100 ms
C
L
Load capacitance 330 pF
R
L
Load resistance 300 4700 Ω
T
A
Operating free-air temperature 0 70 °C
Symbol Parameter Test
Conditions Min Typ Max Units
V
OUT
Analog output voltage
(white, average over 640 pixels) See note (2) 1.6 2 2.4 V
V
DRK
Analog output voltage
(dark, average over 640 pixels) E
e
=0 0 0.05 0.15 V
PRNU Pixel response nonuniformity See note (4) ±20 %
Nonlinearity of analog output
voltage See note (5) ±0.4% FS
Output noise voltage See note (6) 1mV
rms
R
e
Responsivity 16 22 28 V/(μJ/cm
2
)
Electrical Characteristics
Page 8 ams Datasheet
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TSL210 − Electrical Characteristics
Note(s):
2. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640nm.
3. Clock duty cycle is assumed to be 50%.
4. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated.
5. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
6. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
7. Minimum saturation exposure is calculated using the minimum Vsat, the maximum Vdrk, and the maximum Re.
8. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination.
9. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:|
SE Saturation exposure See note (7) 155 nJ/cm
2
V
SAT
Analog output saturation voltage 2.5 3.4 V
DSNU Dark signal nonuniformity All pixels,
E
e
=0
(8)
0.04 0.12 V
IL Image lag See note (9) 0.5 %
I
DD
Supply current 37 50 mA
I
IH
High-level input current V
I
=V
DD
10 μA
I
IL
Low-level input current V
I
=0 10 μA
V
OH
High level output voltage,
SO1-SO5
I
O
=50μA 44.95
V
I
O
=4mA 4.6
V
OL
Low level output voltage,
SO1-SO5
I
O
=50μA 0.01 0.1
V
I
O
=4mA 0.4
C
i(SI)
Input capacitance, SI 20 pF
C
i(CLK)
Input capacitance, CLK 50 pF
Symbol Parameter Test
Conditions Min Typ Max Units
IL V
out IL()
V
drk
–
V
out white()
V
drk
–
-------------------------------------------- 100×=
ams Datasheet Page 9
[v1-00] 2016-Jul-19 Document Feedback
TSL210 − Electrical Characteristics
Figure 8:
Timing Requirements (see Figure 10 and Figure 12)
Note(s):
1. Input pulses have the following characteristics: t
r
=6ns, t
f
=6ns.
2. SI must go low before the rising edge of the next clock pulse.
Figure 9:
Dynamic Characteristics over Recommended Ranges of Supply Voltage and Operating
Free-Air Temperature (see Figure 12)
Symbol Parameter Min Nom Max Units
t
su(SI)
Setup time, serial input
(1)
20 ns
t
h(SI)
Hold time, serial input
(1), (2)
0ns
t
w
Pulse duration, clock high or low 50 ns
t
r
, t
f
Input transition (rise and fall) time 0 500 ns
Symbol Parameter Test
Condition Min Typ Max Unit
t
s
Analog output settling time to ±1% C
L
=10pF 185 ns
Page 10 ams Datasheet
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TSL210 − Typical Operating Characteristics
Figure 10:
Timing Waveforms (each section)
Figure 11:
Operational Waveforms (each section)
Typical Operating
Characteristics
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
129 Clock Cycles
CLK
SI1
AO
Hi-Z
Hi-Z
50%
AO
SI
CLK
Pixel 128
ts
0 V
0 V
5 V
2.5 V
th(SI)
5 V
tsu(SI)
tw1 2 128 129
ts
Pixel 1
Page 12 ams Datasheet
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TSL210 − Application Information
Integration Time
The integration time of the linear array is the period during
which light is sampled and charge accumulates on each pixel’s
integrating capacitor. The flexibility to adjust the integration
period is a powerful and useful feature of the
ams TSL2xx linear array family. By changing the integration
time, a desired output voltage can be obtained on the output
pin while avoiding saturation for a wide range of light levels.
Each pixel of the linear array consists of a light-sensitive
photodiode. The photodiode converts light intensity to a
voltage. The voltage is sampled on the Sampling Capacitor by
closing switch S2 (position 1) (see Figure 2). Logic controls the
resetting of the Integrating Capacitor to zero by closing switch
S1 (position 2).
At SI input (Start Integration), pixel 1 is accessed. During this
event, S2 moves from position 1 (sampling) to position 3
(holding). This holds the sampled voltage for pixel 1. Switch S1
for pixel 1 is then moved to position 2. This resets (clears) the
voltage previously integrated for that pixel so that pixel 1 is now
ready to start a new integration cycle. When the next clock
period starts, the S1 switch is returned to position 1 to be ready
to start integrating again. S2 is returned to position 1 to start
sampling the next light integration. Then the next pixel starts
the same procedure. The integration time is the time from a
specific pixel read to the next time that pixel is read again. If
either the clock speed or the time between successive SI pulses
is changed, the integration time will vary. After the final (n
th
)
pixel in the array is read on the output, the output goes into a
high-impedance mode. A new SI pulse can occur on the (n+1)
clock causing a new cycle of integration/output to begin. Note
that the time between successive SI pulses must not exceed the
maximum integration time of 100ms.
The minimum integration time for any given array is determined
by time required to clock out all the pixels in the array and the
time to discharge the pixels. The time required to discharge the
pixels is a constant. Therefore, the minimum integration period
is simply a function of the clock frequency and the number of
pixels in the array. A slower clock speed increases the minimum
integration time and reduces the maximum light level for
saturation on the output. The minimum integration time shown
in this data sheet is based on the maximum clock frequency
of 5MHz.
Application Information
ams Datasheet Page 13
[v1-00] 2016-Jul-19 Document Feedback
TSL210 − Application Information
The minimum integration time can be calculated from the
equation:
where:
n is the number of pixels
In the case of the TSL210, the minimum integration time would
be:
It is important to note that not all pixels will have the same
integration time if the clock frequency is varied while data is
being output.
It is good practice on initial power up to run the clock (n+1)
times after the first SI pulse to clock out indeterminate data
from power up. After that, the SI pulse is valid from the time
following (n+1) clocks. The output will go into a
high-impedance state after the n+1 high clock edge. It is good
practice to leave the clock in a low state when inactive because
the SI pulse required to start a new cycle is a low-to-high
transition.
The integration time chosen is valid as long as it falls in the
range between the minimum and maximum limits for
integration time. If the amount of light incident on the array
during a given integration period produces a saturated output
(Max Voltage output), then the data is not accurate. If this
occurs, the integration period should be reduced until the
analog output voltage for each pixel falls below the saturation
level. The goal of reducing the period of time the light sampling
window is active is to lower the output voltage level to prevent
saturation. However, the integration time must still be greater
than or equal to the minimum integration period.
If the light intensity produces an output below desired signal
levels, the output voltage level can be increased by increasing
the integration period provided that the maximum integration
time is not exceeded. The maximum integration time is limited
by the length of time the integrating capacitors on the pixels
can hold their accumulated charge. The maximum integration
time should not exceed 100ms for accurate measurements.
Although the linear array is capable of running over a wide
range of operating frequencies up to a maximum of 5MHz, the
speed of the A/D converter used in the application is likely to
be the limiter for the maximum clock frequency. The voltage
output is available for the whole period of the clock, so the
setup and hold times required for the analog-to-digital
conversion must be less than the clock period.
(EQ2)
T
int min()
1
maximum clock frequency
-------------------------------------------------------------------------
n×=
T
int min()
200ns 640×128μs==
Page 14 ams Datasheet
Document Feedback [v1-00] 2016-Jul-19
TSL210 − Application Information
Figure 13:
Connection Diagrams
SERIAL
TSL210
1 VDD
2 CLK
3 SI1
4 AO1
5 SO1
6 SI2
7 AO2
8 SO2
9 GND
10 SI3
11 AO3
12 SO3
13 SI4
14 AO4
15 SO4
16 SI5
17 AO5
18 SO5
RL
330 Ω
PARALLEL
TSL210
1 VDD
2 CLK
3 SI1
4 AO1
5 SO1
6 SI2
7 AO2
8 SO2
9 GND
10 SI3
11 AO3
12 SO3
13 SI4
14 AO4
15 SO4
16 SI5
17 AO5
18 SO5
RL
330 Ω
Output 5
Output 4
Output 3
Output 2
Output 1
Output
Input
Input
ams Datasheet Page 15
[v1-00] 2016-Jul-19 Document Feedback
TSL210 − Package Mechanical Data
Figure 14:
TSL210 Mechanical Specifications
Note(s):
1. All linear dimensions are in inches (millimeters).
2. Pixel centers are located along the center line of the mounting holes.
3. Cover glass index of refraction is 1.52.
4. This drawing is subject to change without notice.
Package Mechanical Data
17 y 0.10 (2,54)
Pin 1 2 y j 0.090 (2,29)
TOP VIEW
Bonded Die Bypass Capacitor
Cover Glass 0.0272 (0,69)
CROSS SECTION
SIDE VIEW
SIDE VIEW
18 y j0.0272 (0,69)
0.0208 (0,53)
0.510 (12,95)
0.490 (12,45)
1.869 (47,46)
1.858 (47,20)
3.706 (94,125)
3.696 (93,875)
3.54 (89,92)
3.53 (89,66)
0.242 (6,15)
0.222 (5,64)
C
L
0.158 (4,01)
0.150 (3,81)
0.878 (22,30)
0.858 (21,80)
0.048 (1,22)
0.038 (0,97)
0.130 (3,30)
0.120 (3,05)
Pixel 640Pixel 1
Green
RoHS
Page 16 ams Datasheet
Document Feedback [v1-00] 2016-Jul-19
TSL210 − Ordering & Contact Information
Figure 15:
Ordering Information
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
Provide feedback about this document at:
www.ams.com/Document-Feedback
For further information and requests, e-mail us at:
ams_sales@ams.com
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
Ordering Code Type Delivery Form Delivery Quantity
TSL210 640x1 Array Tray 20 pcs/tray
Ordering & Contact Information
ams Datasheet Page 17
[v1-00] 2016-Jul-19 Document Feedback
TSL210 − RoHS Compliant & ams Green Statement
RoHS: The term RoHS compliant means that ams AG products
fully comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams AG knowledge and belief as of the
date that it is provided. ams AG bases its knowledge and belief
on information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams AG has taken and continues
to take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams AG
and ams AG suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
RoHS Compliant & ams Green
Statement
Page 18 ams Datasheet
Document Feedback [v1-00] 2016-Jul-19
TSL210 − Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The
material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of
the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied,
or by description regarding the information set forth herein.
ams AG reserves the right to change specifications and prices
at any time and without notice. Therefore, prior to designing
this product into a system, it is necessary to check with ams AG
for current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This product is provided by ams AG “AS IS”
and any express or implied warranties, including, but not
limited to the implied warranties of merchantability and fitness
for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
Copyrights & Disclaimer
ams Datasheet Page 19
[v1-00] 2016-Jul-19 Document Feedback
TSL210 − Document Status
Document Status Product Status Definition
Product Preview Pre-Development
Information in this datasheet is based on product ideas in
the planning phase of development. All specifications are
design goals without any warranty and are subject to
change without notice
Preliminary Datasheet Pre-Production
Information in this datasheet is based on products in the
design, validation or qualification phase of development.
The performance and parameters shown in this document
are preliminary without any warranty and are subject to
change without notice
Datasheet Production
Information in this datasheet is based on products in
ramp-up to full production or full production which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade
Datasheet (discontinued) Discontinued
Information in this datasheet is based on products which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and
should not be used for new designs
Document Status
Page 20 ams Datasheet
Document Feedback [v1-00] 2016-Jul-19
TSL210 − Revision Information
Note(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
Changes from 039D (2011-Aug) to current revision 1-00 (2016-Jul-19) Page
Content of TAOS datasheet was converted to latest ams design
Added Figure 1 1
Added Figure 15 16
Revision Information
ams Datasheet Page 21
[v1-00] 2016-Jul-19 Document Feedback
TSL210 − Content Guide
1 General Description
1 Key Benefits & Features
2Block Diagram
3 Pin Assignments
5 Detailed Description
6Absolute Maximum Ratings
7 Electrical Characteristics
10 Typical Characteristics
12 Application Information
12 Integration Time
15 Mechanical Information
16 Ordering & Contact Information
17 RoHS Compliant & ams Green Statement
18 Copyrights & Disclaimer
19 Document Status
20 Revision Information
Content Guide
