Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
JUNE 2009 REV. 1.1.1
GENERAL DESCRIPTION
The XR16M752/XR68M7521 (M752) is a high
performance dual universal asynchronous receiver
and transmitter (UART) with 64 byte TX and RX
FIFOs. The M752 operates from 1.62 to 3.63 volts. It
is pin-to-pin and software compatible to the
TL16C752B and SC16C752B, but with additional
features such as a programmable fractional baud rate
generator, automatic RS-485 half-duplex direction
control, infrared mode and 8X and 4X sampling rate.
The standard features include 16 selectable TX and
RX FIFO trigger levels, automatic hardware (RTS/
CTS) and software (Xon/Xoff) flow control, and a
complete modem interface. Onboard registers
provide the user with operational status and data
error flags. An internal loopback capability allows
system diagnostics. Each channel is independently
programmable for data rates up to 16 Mbps at 3.3V
with a 4X sampling rate. The XR68M752 has an
additional 16/68# pin to select between the Intel and
Motorola bus interface. The M752 is available in the
48-pin TQFP, 32-pin QFN and 49-pin STBGA
packages.
NOTE: 1 Covered by U.S. Patent #5,649,122
APPLICATIONS
•Portable Appliances
•Telecommunication Network Routers
•Ethernet Network Routers
•Cellular Data Devices
•Factory Automation and Process Controls
FEATURES
•1.62 to 3.6 Volt Operation
•Pin-to-pin and software compatible to TI’s
TL16C752B and Philips’ SC16C752B in the 48-
TQFP package
•Two independent UART channels
■Data rate of up to 16 Mbps at 3.3 V
■Data rate of up to 12.5 Mbps at 2.5 V
■Data rate of up to 8 Mbps at 1.8 V
■Fractional Baud Rate Generator
■Data sampling rates of 16X, 8X and 4X
■Transmit and Receive FIFOs of 64 bytes
■Programmable TX and RX FIFO Trigger Levels
■Automatic Hardware (RTS/CTS) Flow Control
■Automatic Software (Xon/Xoff) Flow Control
■Halt and Resume Transmission Control
■Automatic RS-485 Half-duplex Direction
Control Output via RTS#
■Wireless Infrared (IrDA 1.0) Encoder/Decoder
■Automatic sleep mode
■Full modem interface
•Crystal oscillator (up to 24MHz) or external clock
(up to 64MHz) input
•48-TQFP, 32-QFN and 49-STBGA packages
FIGURE 1. XR16M752 BLOCK DIAGRAM
XTAL1
XTAL2
Crystal Osc/Buffer
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
8-bit Data
Bus
Interface
UART Channel A
64 Byte TX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
1.62 to 3.63 Volt VCC
GND
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
UART Channel B
(same as Channel A)
A2:A0
D7:D0
CSA# (CS#)
CSB# (A3)
INTA (IRQ#)
INTB (NC)
IOW# (R/W#)
IOR# (NC)
Reset/Reset#
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
64 Byte RX FIFO
16/68#
FIGURE 2. PIN OUT ASSIGNMENT - TQFP AND QFN PACKAGES
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CSA#
CSB#
NC
XTAL1
XTAL2
IOW#
CDB#
GND
RXRDYB#
IOR#
DSRB#
RIB#
RTSB#
CTSB#
NC
RESET
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
INTA
INTB
A0
A1
A2
NC
D4
D3
D2
D1
D0
TXRDYA#
VCC
RIA#
CDA#
DSRA#
CTSA#
NC
XR16M752
48-pin TQFP
Intel Mode Only
32
31
30
29
1
2
3
4
5
6
7
8
24
23
22
21
20
19
11
12
13
14
15
16
9
10
D5
D6
D7
RXB
RXA
TXA
TXB
CSA#
CSB#
XTAL1
XTAL2
IOW#
GND
IOR#
RTSB#
CTSB#
RESET
RTSA#
INTA
INTB
A0
A1
A2
D4
D3
D2
D1
D0
VCC
CTSA#
XR16M752
32-pin QFN
Intel Mode Only
28
27
26
25
18
17
NC
NC
32
31
30
29
1
2
3
4
5
6
7
8
24
23
22
21
20
19
11
12
13
14
15
16
9
10
D5
D6
D7
RXB
RXA
TXA
TXB
CSA#
CSB#
XTAL1
XTAL2
IOW#
GND
IOR#
RTSB#
CTSB#
RESET
RTSA#
INTA
INTB
A0
A1
A2
D4
D3
D2
D1
D0
VCC
CTSA#
XR68M752
32-pin QFN
Intel Mode
28
27
26
25
18
17
NC
16/68#
VCC
32
31
30
29
1
2
3
4
5
6
7
8
24
23
22
21
20
19
11
12
13
14
15
16
9
10
D5
D6
D7
RXB
RXA
TXA
TXB
CS#
A3
XTAL1
XTAL2
R/W#
GND
NC
RTSB#
CTSB#
RESET#
RTSA#
IRQ#
NC
A0
A1
A2
D4
D3
D2
D1
D0
VCC
CTSA#
XR68M752
32-pin QFN
Motorola Mode
28
27
26
25
18
17
NC
16/68#
GND
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CSA#
CSB#
NC
XTAL1
XTAL2
IOW#
CDB#
GND
RXRDYB#
IOR#
DSRB#
RIB#
RTSB#
CTSB#
RESET
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
INTA
INTB
A0
A1
A2
D4
D3
D2
D1
D0
TXRDYA#
VCC
RIA#
CDA#
DSRA#
CTSA#
NC
XR68M752
48- pin TQFP
Intel Mode
NC
VCC
16 #/68
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CS#
A3
NC
XTAL1
XTAL2
R/W#
CDB#
GND
RXRDYB#
NC
DSRB#
RIB#
RTSB#
CTSB#
RESET#
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
IRQ#
NC
A0
A1
A2
D4
D3
D2
D1
D0
TXRDYA#
VCC
RIA#
CDA#
DSRA#
CTSA#
NC
XR68M752
48- pin TQFP
Motorola Mode
NC
GND
16 #/68
XR16M752/XR68M752
2
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
FIGURE 3. PIN OUT ASSIGNMENT - STBGA PACKAGE
1 2 3 4 5 6 7
A
B
C
D
E
F
G
Transparent Top View
A1 Corner
NC D3 D0 RIA# CTSA# RS485# DTRA#
D5 D4 D1 D2 VCC DSRA# RESET
D6 D7 RXB TXRDYA# CDA# OP2A# DTRB#
TXB RXA TXA TXRDYB# RTSA# INTA INTB
CSB# CSA# OP2B# RIB# RXRDYA# A0 A1
PWRSAVE IOW# CDB# RXRDYB# DSRB# CTSB# ENIR#
XTAL1 XTAL2 GND IOR# RTSB# 16/68# A2
ORDERING INFORMATION
PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE DEVICE STATUS
XR16M752IL32 32-pin QFN -40°C to +85°C Active
XR16M752IM48 48-Lead TQFP -40°C to +85°C Active
XR68M752IL32 32-pin QFN -40°C to +85°C Active
XR68M752IM48 48-Lead TQFP -40°C to +85°C Active
XR68M752IB49 49-pin STBGA -40°C to +85°C Active
XR16M752/XR68M752
3
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
XR16M752/XR68M752
4
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
PIN DESCRIPTIONS
Pin Description
NAME 32-QFN
PIN #
48-TQFP
PIN #
49-STBGA
PIN # TYPE DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
18
19
20
26
27
28
G7
E7
E6
IAddress data lines [2:0]. These 3 address lines select
one of the internal registers in UART channel A/B during
a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
2
1
32
31
30
29
28
27
3
2
1
48
47
46
45
44
C2
C1
B1
B2
A2
B4
B3
A3
I/O Data bus lines [7:0] (bidirectional).
IOR#
(NC)
14 19 G4 IWhen 16/68# pin is HIGH, the Intel bus interface is
selected and this input becomes read strobe (active low).
The falling edge instigates an internal read cycle and
retrieves the data byte from an internal register pointed
by the address lines [A2:A0], puts the data byte on the
data bus to allow the host processor to read it on the ris-
ing edge.
When 16/68# pin is LOW, the Motorola bus interface is
selected and this input is not used.
IOW#
(R/W#)
12 15 F2 IWhen 16/68# pin is HIGH, it selects Intel bus interface
and this input becomes write strobe (active low). The fall-
ing edge instigates the internal write cycle and the rising
edge transfers the data byte on the data bus to an inter-
nal register pointed by the address lines.
When 16/68# pin is LOW, the Motorola bus interface is
selected and this input becomes read (HIGH) and write
(LOW) signal.
CSA#
(CS#)
710 E2 IWhen 16/68# pin is HIGH, this input is chip select A
(active low) to enable channel A in the device.
When 16/68# pin is LOW, this input becomes the chip
select (active low) for the Motorola bus interface.
CSB#
(A3)
811 E1 IWhen 16/68# pin is HIGH, this input is chip select B
(active low) to enable channel B in the device.
When 16/68# pin is LOW, this input becomes address
line A3 which is used for channel selection in the Motor-
ola bus interface. Input logic 0 selects channel A and
logic 1 selects channel B.
XR16M752/XR68M752
5
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
INTA
(IRQ#)
22 30 D6 OWhen 16/68# pin is HIGH for Intel bus interface, this out-
put becomes channel A interrupt output. The output state
is defined by the user through the software setting of
MCR[3]. INTA is set to the active mode and OP2A# out-
put LOW when MCR[3] is set to a logic 1. INTA is set to
the three state mode and OP2A# to HIGH when MCR[3]
is set to a logic 0. See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, this
output becomes device interrupt output (active low, open
drain). An external pull-up resistor is required for proper
operation.
INTB
(NC)
21 29 D7 OWhen 16/68# pin is HIGH for Intel bus interface, this out-
put becomes channel B interrupt output. The output state
is defined by the user through the software setting of
MCR[3]. INTB is set to the active mode and OP2A# out-
put to LOW when MCR[3] is set to a logic 1. INTA is set to
the three state mode and OP2A# to HIGH when MCR[3]
is set to a logic 0. See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, this
output is not used.
TXRDYA# -43 C4 OUART channel A Transmitter Ready (active low). The
output provides the TX FIFO/THR status for transmit
channel A. See Table 3. If it is not used, leave it uncon-
nected.
RXRDYA# -31 E5 OUART channel A Receiver Ready (active low). This out-
put provides the RX FIFO/RHR status for receive channel
A. See Table 3. If it is not used, leave it unconnected.
TXRDYB# - 6 D4 OUART channel B Transmitter Ready (active low). The
output provides the TX FIFO/THR status for transmit
channel B. See Table 4. If it is not used, leave it uncon-
nected.
RXRDYB# -18 F4 OUART channel B Receiver Ready (active low). This out-
put provides the RX FIFO/RHR status for receive channel
B. See Table 3. If it is not used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA 5 7 D3 OUART channel A Transmit Data or infrared encoder data.
Standard transmit and receive interface is enabled when
MCR[6] = 0. In this mode, the TX signal will be HIGH dur-
ing reset or idle (no data). Infrared IrDA transmit and
receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is LOW. If it is not used, leave
it unconnected.
Pin Description
NAME 32-QFN
PIN #
48-TQFP
PIN #
49-STBGA
PIN # TYPE DESCRIPTION
XR16M752/XR68M752
6
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
RXA 4 5 D2 IUART channel A Receive Data or infrared receive data.
Normal receive data input must idle HIGH. The infrared
receiver pulses typically idles at LOW but can be inverted
by software control prior going in to the decoder, see
MCR[6]. If this pin is not used, tie it to VCC or pull it high
via a 100k ohm resistor.
RTSA# 23 33 D5 OUART channel A Request-to-Send (active low) or general
purpose output. This output must be asserted prior to
using auto RTS flow control, see EFR[6] and IER[6]. For
auto RS485 half-duplex direction control, see DLD[6].
CTSA# 25 38 A5 IUART channel A Clear-to-Send (active low) or general
purpose input. It can be used for auto CTS flow control,
see EFR[7] and IER[7]. This input should be connected to
VCC or GND when not used.
DTRA# -34 A7 OUART channel A Data-Terminal-Ready (active low) or
general purpose output. If it is not used, leave it uncon-
nected.
DSRA# -39 B6 IUART channel A Data-Set-Ready (active low) or general
purpose input. This input should be connected to VCC or
GND when not used.
CDA# -40 C5 IUART channel A Carrier-Detect (active low) or general
purpose input. This input should be connected to VCC or
GND when not used.
RIA# -41 A4 IUART channel A Ring-Indicator (active low) or general
purpose input. This input should be connected to VCC or
GND when not used.
OP2A# -32 C6 OOutput Port 2 Channel A - The output state is defined by
the user and through the software setting of MCR[3].
INTA is set to the active mode and OP2A# output LOW
when MCR[3] is set to a logic 1. INTA is set to the three
state mode and OP2A# output HIGH when MCR[3] is set
to a logic 0. See MCR[3]. If INTA is used, this output
should not be used as a general output else it will disturb
the INTA output functionality.
TXB 6 8 D1 OUART channel B Transmit Data or infrared encoder data.
Standard transmit and receive interface is enabled when
MCR[6] = 0. In this mode, the TX signal will be HIGH dur-
ing reset or idle (no data). Infrared IrDA transmit and
receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is LOW. If it is not used, leave
it unconnected.
RXB 3 4 C3 IUART channel B Receive Data or infrared receive data.
Normal receive data input must idle HIGH. The infrared
receiver pulses typically idles at logic 0 but can be
inverted by software control prior going in to the decoder,
see MCR[6]. If this pin is not used, tie it to VCC or pull it
high via a 100k ohm resistor.
Pin Description
NAME 32-QFN
PIN #
48-TQFP
PIN #
49-STBGA
PIN # TYPE DESCRIPTION
XR16M752/XR68M752
7
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
RTSB# 15 22 G5 OUART channel B Request-to-Send (active low) or general
purpose output. This port must be asserted prior to using
auto RTS flow control, see EFR[6] and IER[6]. For auto
RS485 half-duplex direction control, see DLD[6].
CTSB# 16 23 F6 IUART channel B Clear-to-Send (active low) or general
purpose input. It can be used for auto CTS flow control,
see EFR[7] and IER[7]. This input should be connected to
VCC or GND when not used.
DTRB# -35 C7 OUART channel B Data-Terminal-Ready (active low) or
general purpose output. If it is not used, leave it uncon-
nected.
DSRB# -20 F5 IUART channel B Data-Set-Ready (active low) or general
purpose input. This input should be connected to VCC or
GND when not used.
CDB# -16 F3 IUART channel B Carrier-Detect (active low) or general
purpose input. This input should be connected to VCC or
GND when not used.
RIB# -21 E4 IUART channel B Ring-Indicator (active low) or general
purpose input. This input should be connected to VCC or
GND when not used.
OP2B# - 9 E3 OOutput Port 2 Channel B - The output state is defined by
the user and through the software setting of MCR[3].
INTB is set to the active mode and OP2B# output LOW
when MCR[3] is set to a logic 1. INTB is set to the three
state mode and OP2B# output HIGH when MCR[3] is set
to a logic 0. See MCR[3]. If INTB is used, this output
should not be used as a general output else it will disturb
the INTB output functionality.
ANCILLARY SIGNALS
XTAL1 10 13 G1 ICrystal or external clock input.
XTAL2 11 14 G2 OCrystal or buffered clock output.
PwrSave - - F1 IPowerSave (active high, internal pull-down resistor). This
feature isolates the 752’s data bus interface from the host
preventing other bus activities that cause higher power
drain during sleep mode. See Sleep Mode with Auto
Wake-up and PowerSave Feature section for details.
16/68# 17 24 G6 IIntel or Motorola Bus Select (internal pull-up resistor).
This pin is not available for the XR16M752. This pin is
available for the XR68M752 only.
When 16/68# pin is HIGH, 16 or Intel Mode, the device
will operate in the Intel bus type of interface.
When 16/68# pin is LOW, 68 or Motorola mode, the
device will operate in the Motorola bus type of interface.
Pin Description
NAME 32-QFN
PIN #
48-TQFP
PIN #
49-STBGA
PIN # TYPE DESCRIPTION
XR16M752/XR68M752
8
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
RESET
(RESET#)
24 36 B7 IWhen 16/68# pin is HIGH for Intel bus interface, this input
becomes RESET (active high). When 16/68# pin is LOW
for Motorola bus interface, this input becomes RESET#
(active low).
A 40 ns minimum active pulse on this pin will reset the
internal registers and all outputs of channel A and B. The
UART transmitter output will be held HIGH, the receiver
input will be ignored and outputs are reset during reset
period (see Table 16).
EN485# - - A6 IAuto RS-485 half-duplex direction output enable for
channel A and B (active low, internal pull-up resistor).
Connect this pin to VCC or leave unconnected for normal
RTS# A/B function. Connect to GND for auto RS-485
half-duplex direction output via the RTS# A/B pins. The
Auto RS-485 half-duplex direction output control feature
can be disabled via DLD[6] after power-up. SEE ”AUTO
RS485 HALF-DUPLEX CONTROL” ON PAGE 18.
ENIR# - - F7 IIR mode enable for channel A and B (active low, internal
pull-up resistor). Connect this pin to VCC or leave uncon-
nected for normal TX and RX. Connect to GND for both
channel A and B to power up in the IR mode. The IR
mode can be disabled via DLD[7] after power-up. SEE
”INFRARED MODE” ON PAGE 20.
VCC 26 42 B5 Pwr 1.62V to 3.63V power supply.
GND 13 17 G3 Pwr Power supply common, ground.
GND Center Pad - - Pwr The center pad on the backside of the QFN package is
metallic and should be connected to GND on the PCB.
The thermal pad size on the PCB should be the approxi-
mate size of this center pad and should be solder mask
defined. The solder mask opening should be at least
0.0025" inwards from the edge of the PCB thermal pad.
NC 912, 25, 37 A1 No Connection.
Pin Description
NAME 32-QFN
PIN #
48-TQFP
PIN #
49-STBGA
PIN # TYPE DESCRIPTION
XR16M752/XR68M752
9
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
1.0 PRODUCT DESCRIPTION
The XR16M752/XR68M752 (M752) integrates the functions of 2 enhanced 16C550 Universal Asynchronous
Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device
configuration registers. The configuration registers set is 16550 UART compatible for control, status and data
transfer. Additionally, each UART channel has 64-bytes of transmit and receive FIFOs, automatic RTS/CTS
hardware flow control, automatic Xon/Xoff and special character software flow control, programmable transmit
and receive FIFO trigger levels, infrared encoder and decoder (IrDA ver 1.0), programmable fractional baud
rate generator with a prescaler of divide by 1 or 4, and data rate up to 16 Mbps with 4X sampling clock rate.
The XR16M752 is a 1.62V to 3.63V device. The M752 is fabricated with an advanced CMOS process.
Enhanced Features
The M752 DUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of
16 bytes in the industry standard 16C550. The M752 is designed to work with low supply voltage and high
performance data communication systems, that require fast data processing time. Increased performance is
realized in the M752 by the larger transmit and receive FIFOs, FIFO trigger level control and automatic flow
control mechanism. This allows the external processor to handle more networking tasks within a given time.
For example, the 16C550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses
a character length of 11 bits, including start/stop bits at 115.2 Kbps). This means the external CPU will have to
service the receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the M752, the data buffer will
not require unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional
time for other applications and reducing the overall UART interrupt servicing time. In addition, the
programmable FIFO level trigger interrupt and automatic hardware/software flow control is uniquely provided
for maximum data throughput performance especially when operating in a multi-channel system. The
combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and
reduces power consumption.
The M752 supports a half-duplex output direction control signaling pin, RTS# A/B, to enable and disable the
external RS-485 transceiver operation. It automatically switches the logic state of the output pin to the receive
state after the last stop-bit of the last character has been shifted out of the transmitter. After receiving, the logic
state of the output pin switches back to the transmit state when a data byte is loaded in the transmitter. The
auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has
to set DLD Bit-6 to “1”. This pin is HIGH for receive state and LOW for transmit state.
Data Rate
The M752 is capable of operation up to 16 Mbps at 3.3V with 4X internal sampling clock rate, 8 Mbps at 3.3V
with 8X sampling clock rate, and 4 Mbps at 3.3V with 16X internal sampling clock rate. The device can operate
with an external 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of up to 64 MHz on XTAL1
pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler bit for
data rates of up to 3.68 Mbps.
The rich feature set of the M752 is available through the internal registers. Automatic hardware/software flow
control, programmable transmit and receive FIFO trigger levels, programmable TX and RX baud rates, infrared
encoder/decoder interface, modem interface controls, and a sleep mode are all standard features.
Following a power on reset or an external reset, the M752 is software compatible with previous generation of
UARTs, 16C450, 16C550 and 16C2550.
XR16M752/XR68M752
10
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The XR16M752 data interface supports the Intel compatible types of CPUs while the
XR68M752 supports both the Intel and Motorola compatible data interfaces. No clock (oscillator nor external
clock) is required to operate a data bus transaction. Each bus cycle is asynchronous using CS#, IOR# and
IOW# signals. Both UART channels share the same data bus for host operations. The data bus
interconnections are shown in Figure 4.
FIGURE 4. XR16M752/XR68M752 DATA BUS INTERCONNECTIONS
VCC
VCC
OP2A#
DSRA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RIA#
CDA#
OP2B#
DSRB#
CTSB#
RTSB#
DTRB#
RXB
TXB
RIB#
CDB#
GND
A0
A1
A2
UART_CSA#
UART_CSB#
IOR#
IOW #
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSA#
CSB#
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW#
UART
Channel A
UART
Channel B
UART_INTB
UART_INTA
INTB
INTA
RXRDYA#
TXRDYA#
RXRDYA#
TXRDYA#
RXRDYB#
TXRDYB#
RXRDYB#
TXRDYB#
UART_RESET RESET
Serial Interface of
RS-232, RS-422
or RS-485
Serial Interface of
RS-232, RS-422
or RS-485
(no connect)
(no connect)
2.25 to 3.6 Volt VCC
VCC
OP2A#
DSRA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RIA#
CDA#
OP2B#
DSRB#
CTSB#
RTSB#
DTRB#
RXB
TXB
RIB#
CDB#
GND
A0
A1
A2
UART_CS#
A3
R/W#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSA#
CSB#
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW#
UART
Channel A
UART
Channel B
UART_IRQ#
INTB
INTA
RXRDYA#
TXRDYA#
RXRDYA#
TXRDYA#
RXRDYB#
TXRDYB#
RXRDYB#
TXRDYB#
RESET#
VCC
UART_RESET#
(no connect)
(no connect)
(no connect)
VCC
Intel Data Bus Interconnections
Motorola Data Bus Interconnections
Serial Interface of
RS-232, RS-422
or RS-485
Serial Interface of
RS-232, RS-422
or RS-485
XR16M752/XR68M752
11
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
2.2 Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device.
2.3 Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. During Intel Bus Mode (16/68# pin connected to VCC), a
logic 0 on chip select pins, CSA# or CSB#, allows the user to select UART channel A or B to configure, send
transmit data and/or unload receive data to/from the UART. Selecting both UARTs can be useful during power
up initialization to write to the same internal registers, but do not attempt to read from both UARTs
simultaneously. Individual channel select functions are shown in Table 1.
TABLE 1: CHANNEL A AND B SELECT IN 16 MODE
FUNCTION
1 1 UART de-selected
0 1 Channel A selected
1 0 Channel B selected
0 0 Channel A and B selected
During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the M752 decodes an
additional address, A3, to select one of the UART ports. The A3 address decode function is used only when in
the Motorola Bus Mode. See Table 2.
TABLE 2: CHANNEL A AND B SELECT IN 68 MODE
FUNCTION
1 N/A UART de-selected
0 0 Channel A selected
0 1 Channel B selected
2.4 Channel A and B Internal Registers
Each UART channel in the M752 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM/DLD), and a user accessible Scratchpad Register (SPR).
Beyond the general 16C550 features and capabilities, the M752 offers enhanced feature registers (EFR, Xon/
Xoff 1, Xon/Xoff 2, TCR, TLR and DLD) that provide automatic RTS and CTS hardware flow control, Xon/Xoff
software flow control, automatic RS-485 half-duplex direction output enable/disable, and programmable FIFO
trigger level control. All the register functions are discussed in full detail later in “Section 3.0, UART Internal
Registers” on page 24.
CSA# CSB#
CS# A3
XR16M752/XR68M752
12
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
2.5 DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the M752 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. In this mode, the M752
sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO
becomes empty. The following table shows their behavior. Also see Figures 20 through 25.
TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS FCR BIT-0=0
(FIFO DISABLED)FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY# A/B LOW = 1 byte.
HIGH = no data.
LOW = at least 1 byte in FIFO.
HIGH = FIFO empty.
HIGH to LOW transition when FIFO reaches the
trigger level, or time-out occurs.
LOW to HIGH transition when FIFO empties or
LSR[7] = 1.
TXRDY# A/B LOW = THR empty.
HIGH = byte in THR.
LOW = FIFO empty.
HIGH = at least 1 byte in FIFO.
LOW = FIFO is below the trigger level.
HIGH = FIFO is full.
2.6 INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 4 and 5 summarize the operating behavior for the transmitter and receiver. Also see Figures 20
through 25.
TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER
Auto RS485
Mode
FCR BIT-0 = 0
(FIFO DISABLED)FCR BIT-0 = 1 (FIFO ENABLED)
INTA/B Pin NO LOW = a byte in THR
HIGH = THR empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
INTA/B Pin YES LOW = a byte in THR
HIGH = transmitter empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or transmitter empty
TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
INTA/B Pin LOW = no data
HIGH = 1 byte
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
XR16M752/XR68M752
13
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
2.7 Crystal Oscillator or External Clock Input
The M752 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. Please note that the input XTAL1 is not
5V tolerant and so the maximum at the pin should be VCC. For programming details, see ““Section 2.8,
Programmable Baud Rate Generator with Fractional Divisor” on page 13.”
FIGURE 5. TYPICAL OSCILLATOR CONNECTIONS
C1
22-47 pF
C2
22-47 pF
Y1 1.8432 MHz
to
24 MHz
R1
0-120 Ω
(Optional)
R2
500 ΚΩ − 1 ΜΩ
XTAL1 XTAL2
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 5). The programmable Baud
Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. However, with an
external clock input on XTAL1 pin, it can extend its operation up to 64 MHz (16 Mbps serial data rate) at 3.3V
with an 4X sampling rate. For further reading on the oscillator circuit please see the Application Note DAN108
on the EXAR web site at http://www.exar.com.
2.8 Programmable Baud Rate Generator with Fractional Divisor
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to
obtain a 16X, 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter for
data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the
value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed
during initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor
and the DLD register provides the fractional part of the dvisior. The four lower bits of the DLD are used to select
a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator
Registers DLL, DLM and DLD provides the capability for selecting the operating data rate. Table 6 shows the
standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used
(MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 6. At 8X sampling rate, these
data rates would double and at 4X sampling rate, these data rates would quadruple. Also, when using 8X
sampling mode, the bit time will have a jitter of ± 1/16 whenever the DLD is non-zero and is an odd number.
XR16M752/XR68M752
14
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
When using 4X sampling mode, the bit time will have a jitter of ± 1/8 whenever DLD is non-zero, odd and not a
multiple of 4. When using a non-standard data rate crystal or external clock, the divisor value can be calculated
with the following equation(s):
Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8
DLL = TRUNC(Required Divisor) & 0xFF
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
The closest divisor that is obtainable in the M752 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
FIGURE 6. BAUD RATE GENERATOR
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL, DLM and DLD
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X or 8X or 4X
Sampling
Rate Clock
to Transmitter
and Receiver
To Other
Channel
Fractional Baud
Rate Generator
Logic
TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
Required
Output Data
Rate
DIVISOR FOR
16x Clock
(Decimal)
DIVISOR
OBTAINABLE IN
M752
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
DLD PROGRAM
VALUE (HEX)
DATA ERROR
RATE (%)
400 3750 3750 EA6 0 0
2400 625 625 271 0 0
4800 312.5 312 8/16 138 8 0
9600 156.25 156 4/16 09C 4 0
10000 150 150 096 0 0
19200 78.125 78 2/16 04E 2 0
25000 60 60 03C 0 0
28800 52.0833 52 1/16 034 10.04
38400 39.0625 39 1/16 027 1 0
50000 30 30 01E 0 0
57600 26.0417 26 1/16 01A 10.08
75000 20 20 014 0 0
100000 15 15 0 F 0 0
115200 13.0208 13 0 D 0 0.16
153600 9.7656 9 12/16 0 9 C 0.16
200000 7.5 7 8/16 0 7 8 0
225000 6.6667 6 11/16 0 6 B 0.31
230400 6.5104 6 8/16 0 6 8 0.16
250000 66 0 6 0 0
300000 55 0 5 0 0
400000 3.75 3 12/16 0 3 C 0
460800 3.2552 3 4/16 0 3 4 0.16
500000 33 0 3 0 0
750000 22 0 2 0 0
921600 1.6276 1 10/16 0 1 A 0.16
1000000 1.5 1 8/16 0 1 8 0
XR16M752/XR68M752
15
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
2.9 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X
internal clock. A bit time is 16 (8 if 8X or 4 if 4X) clock periods (see DLD[5:4]). The transmitter sends the start-
bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The
status of the FIFO and TSR are reported in the Line Status Register (LSR[6:5]).
XR16M752/XR68M752
16
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
2.9.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.9.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X or 8X or 4X
Clock
( DLD[5:4] )
2.9.3 Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit Data Shift Register
(TSR)
Transmit
Data Byte THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
Transmit
FIFO
16X or 8X or 4X Clock
( DLD[5:4] )
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.)
TXFIFO1
XR16M752/XR68M752
17
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
2.10 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD [5:4]) for timing. It
verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of
a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate. After 8 clocks
(or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is
sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same
manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are
immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4
word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR
interrupt is enabled by IER bit-0.
2.10.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X or 8X or 4X Clock
( DLD[5:4] )
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X or 4X Clock
( DLD[5:4] )
Error Tags
(64-sets)
Error Tags in
LSR bits 4:2
Receive Data Characters
FIFO
Trigger=16
Example
: - RX FIFO trigger level selected at 16 bytes
(See Note Below)
Data fills to
Halt Level
Data falls to
Resume Level
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills to the Halt Level
to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls to the Resume
Level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
64 bytes by 11-bit wide
FIFO
XR16M752/XR68M752
18
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
2.11 Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 11):
•Enable auto RTS flow control using EFR bit-6.
•The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
•Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.12 Auto RTS Halt and Resume
The RTS# pin will not be forced HIGH (RTS off) until the receive FIFO reaches the Halt Level (TCR[3:0]). The
RTS# pin will return LOW after the RX FIFO is unloaded to the Resume Level (TCR[7:4]). Under these
conditions, the M752 will continue to accept data if the remote UART continues to transmit data. It is the
responsibility of the user to ensure that the Halt Level is greater than the Resume Level. If interrupts are used,
it is recommended that Halt Level > RX Trigger Level > Resume Level. The Auto RTS function is initiated
when the RTS# output pin is asserted LOW (RTS On).
2.13 Auto RS485 Half-duplex Control
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by DLD
bit-6. When idle, the auto RS485 half-duplex direction control signal (RTS#) is LOW for receive mode. When
data is loaded into the THR for transmission, the RTS# output is automatically asserted HIGH prior to sending
the data. After the last stop bit of the last character that has been transmitted, the RTS# signal is automatically
de-asserted. This helps in turning around the transceiver to receive the remote station’s response. When the
host is ready to transmit next polling data packet, it only has to load data bytes to the transmit FIFO. The
transmitter automatically re-asserts RTS# (HIGH) output prior to sending the data. In addition to changing the
behavior of the RTS# output, this feature also changes the behavior of the transmit empty interrupt (see
Table 4). In the 49-pin STBGA package, this feature can be enabled by connecting the EN485# pin to GND. If
this feature is enabled by the EN485# pin, it can be disabled by DLD bit-6 after power-up.
XR16M752/XR68M752
19
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
2.14 Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 11):
•Enable auto CTS flow control using EFR bit-7.
If using the Auto CTS interrupt:
•Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as
the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-
asserted (LOW), indicating more data may be sent.
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION
RTSA# CTSB#
RXA TXB Transmitter
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Auto CTS
Monitor
RTSA#
TXB
RXA FIFO
CTSB#
Remote UART
UARTB
Local UART
UARTA
ON OFF ON
Suspend Restart
RTS High
Threshold
Data Starts
ON OFF ON
Assert RTS# to Begin
Transmission
1
2
3
4
5
6
7
Receive
Data RTS Low
Threshold
9
10
11
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Transmitter
Auto CTS
Monitor
RTSB#CTSA#
RXBTXA
INTA
(RXA FIFO
Interrupt)
RX FIFO
Trigger Level
RX FIFO
Trigger Level
8
12
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
XR16M752/XR68M752
20
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
2.15 Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 15), the M752 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the M752 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the M752 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the M752 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to 0x00. Following reset the user can
write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff
characters (See Table 15) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are
selected, the M752 compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control
mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the M752 automatically
sends the Xoff-1,2 via the serial TX output to the remote modem when the RX FIFO reaches the Halt Level
(TCR[3:0]). To clear this condition, the M752 will transmit the programmed Xon-1,2 characters as soon as RX
FIFO falls down to the Resume Level.
2.16 Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The M752 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will
be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal
Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison.
2.17 Infrared Mode
The M752 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGH-
pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See Figure 12 below.
The infrared encoder and decoder can be enabled by setting DLD register bit-7 to a ‘1’. When the infrared
feature is enabled, the transmit data output, TX, idles LOW. Likewise, the RX input also idles LOW, see
Figure 12. In the 49-pin STBGA package, this feature can be enabled upon power-up by connecting the
ENIR# pin of the STBGA package to GND. If the IR mode is enabled via the ENIR# pin, it can be disabled
after power-up via DLD bit-7.
The wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin. Each
time it senses a light pulse, it returns a logic 1 to the data bit stream.
XR16M752/XR68M752
21
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
Character
Data Bits
Start
Stop
0000 0
11 111
Bit Time
1/16 Clock Delay
IRdecoder
-
RX Data
Receive
IR Pulse
(RX pin)
Character
Data Bits
Start
Stop
0000 0
11 111
TX Data
Transmit
IR Pulse
(TX Pin)
Bit Time 1/2 Bit Time
3/16 Bit Time
IrEncoder-1
XR16M752/XR68M752
22
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
2.18 Sleep Mode with Wake-Up Indicator and PowerSave Feature
The M2751 supports low voltage system designs, hence, a sleep mode with auto wake-up and PowerSave
feature is included to reduce power consumption when the device is not actively used.
2.19 Sleep Mode with Auto Wake-Up
The M752 supports low voltage system designs, hence, a sleep mode is included to reduce its power
consumption when the chip is not actively used. In addition, there is a PowerSave Feature on the 49-pin
STBGA package that eliminates any unnecessary external buffer.
All of these conditions must be satisfied for the M752 to enter sleep mode:
■no interrupts pending for both channels of the M752 (ISR bit-0 = 1)
■sleep mode of both channels are enabled (IER bit-4 = 1)
■modem inputs are not toggling (MSR bits 0-3 = 0)
■RX input pins are idling HIGH
The M752 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for
no clock output as an indication that the device has entered the sleep mode.
The M752 resumes normal operation by any of the following:
■a receive data start bit transition (HIGH to LOW)
■a data byte is loaded to the transmitter, THR or FIFO
■a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the M752 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the M752 is awakened by the modem inputs, a
read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while
an interrupt is pending from channel A or B. The M752 will stay in the sleep mode of operation until it is
disabled by setting IER bit-4 to a logic 0.
If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and modem input lines remain steady when the
M752 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical
Characteristics on page 40. If the input lines are floating or are toggling while the M752 is in sleep mode, the
current can be up to 100 times more. If any of those signals are toggling or floating, then an external buffer
would be required to keep the address, data and control lines steady to achieve the low current.
2.19.1 PowerSave Feature (49-pin STBGA pacakge only)
The PowerSave Feature will eliminate the need for an external buffer by internally isolating the address, data
and control signals from other bus activities that could cause wasteful power drain. The M752 enters
PowerSave mode when pin F1 is connected to VCC and the M752 is in sleep mode (see Sleep Mode section
above).
Since PowerSave mode isolates the address, data and control signals, the device will wake-up by:
■a receive data start bit transition (HIGH to LOW)
■a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
The M752 will return to the PowerSave mode automatically after a read to the MSR (to reset the modem
inputs) and all interrupting conditions have been serviced and cleared. The 2751 will stay in the PowerSave
mode of operation until it is disabled by setting IER bit-4 to a logic 0 and/or the PowerSave pin is connected to
GND.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. The number of characters lost during the restart also depends on your
operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep
RX A/B inputs idling HIGH or “marking” condition during sleep mode to avoid receiving a “break” condition
upon the restart. This may occur when the external interface transceivers (RS-232, RS-485 or another type)
are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a
47k-100k ohm pull-up resistor on the RXA and RXB pins.
XR16M752/XR68M752
23
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
2.20 Internal Loopback
The M752 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX, RTS# and DTR# pins are held while the CTS#, DSR# CD# and RI# inputs are ignored.
Caution: the RX input pin must be held HIGH during loopback test else upon exiting the loopback test the
UART may detect and report a false “break” signal. Also, Auto RTS/CTS flow control is not supported during
internal loopback.
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B
TXA/TXB
RXA/RXB
Modem / General Purpose Control Logic
Internal Data Bus Lines and Control Signals
RTSA#/RTSB#
MCR bit-4=1
VCC
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB#
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
VCC
OP2A#/OP2B#
XR16M752/XR68M752
24
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
3.0 UART INTERNAL REGISTERS
Each of the UART channel in the M752 has its own set of configuration registers selected by address lines A0,
A1 and A2 with CSA# or CSB# selecting the channel. The complete register set is shown on Table 7 and
Table 8.
TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS
ADDRESSES REGISTER READ/WRITE COMMENTS
16C550 COMPATIBLE REGISTERS
0 0 0 RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only LCR[7] = 0
0 0 0 DLL - Divisor LSB Read/Write
LCR[7] = 1, LCR ≠ 0xBF
0 0 1 DLM - Divisor MSB Read/Write
0 1 0 DLD - Divisor Fractional Read/Write LCR[7] = 1, LCR ≠ 0xBF,
EFR[4] = 1
0 0 1 IER - Interrupt Enable Register Read/Write
LCR[7] = 0
0 1 0 ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
0 1 1 LCR - Line Control Register Read/Write
1 0 0 MCR - Modem Control Register Read/Write
LCR ≠ 0xBF
1 0 1 LSR - Line Status Register Read-only
1 1 0 MSR - Modem Status Register Read-only See Table 13
1 1 1 SPR - Scratch Pad Register Read/Write See Table 12
1 1 0 TCR - Transmission Control Register Read/Write See Table 13
1 1 1 TLR - Trigger Level Register Read/Write See Table 12
1 1 1 FIFO Rdy - FIFO Ready Register Read-only See Table 12
ENHANCED REGISTERS
0 1 0 EFR - Enhanced Function Register Read/Write
LCR = 0xBF
1 0 0 Xon-1 - Xon Character 1 Read/Write
1 0 1 Xon-2 - Xon Character 2 Read/Write
1 1 0 Xoff-1 - Xoff Character 1 Read/Write
1 1 1 Xoff-2 - Xoff Character 2 Read/Write
A2 A1 A0
XR16M752/XR68M752
25
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
.
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0
REG
NAME
READ/
WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
LCR[7]=0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 1 IER RD/WR 0/ 0/ 0/ 0/ Modem
Stat. Int.
Enable
RX Line
Stat. Int.
Enable
TX
Empty
Int
Enable
RX Data
Int.
Enable
CTS Int.
Enable
RTS Int.
Enable
Xoff Int.
Enable
Sleep
Mode
Enable
0 1 0 ISR RD FIFOs
Enabled
FIFOs
Enabled
0/ 0/ INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
INT
Source
Bit-5
INT
Source
Bit-4
0 1 0 FCR WR RX FIFO
Trigger
RX FIFO
Trigger
0/ 0/ DMA
Mode
Enable
TX FIFO
Reset
RX
FIFO
Reset
FIFOs
Enable
TX FIFO
Trigger
TX FIFO
Trigger
0 1 1 LCR RD/WR Divisor
Enable
Set TX
Break
Set Par-
ity
Even
Parity
Parity
Enable
Stop
Bits
Word
Length
Bit-1
Word
Length
Bit-0
1 0 0 MCR RD/WR 0/ 0/ 0/ Internal
Lopback
Enable
OP2#/
INT Out-
put
Enable
FIFO
Rdy
Enable
(OP1#)
RTS#
Output
Control
DTR#
Output
Control
LCR≠0xBF
Clock
Pres-
caler
Select
TCR and
TLR
ENable
XonAny
1 0 1 LSR RD RX FIFO
Global
Error
THR &
TSR
Empty
THR
Empty
RX
Break
RX
Framing
Error
RX
Parity
Error
RX
Over-
run
Error
RX Data
Ready
1 1 0 MSR RD CD#
Input
RI# Input DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS# See Table 13
1 1 1 SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 See Table 12
1 1 0 TCR RD/WR Resume
Bit-3
Resume
Bit-2
Resume
Bit-1
Resume
Bit-0
Halt
Bit-3
Halt
Bit-2
Halt
Bit-1
Halt
Bit-0 See Table 13
1 1 1 TLR RD/WR RX Trig
Bit-3
RX Trig
Bit-2
RX Trig
Bit-1
RX Trig
Bit-0
TX Trig
Bit-3
TX Trig
Bit-2
TX Trig
Bit-1
TX Trig
Bit-0 See Table 12
1 1 1 FIFO
Rdy
RD 0 0 RX FIFO
B Status
RX FIFO
A Status
0 0 TX FIFO
B Status
TX FIFO
A Status See Table 12
XR16M752/XR68M752
26
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
SEE ”RECEIVER” ON PAGE 17.
4.2 Transmit Holding Register (THR) - Write-Only
SEE ”TRANSMITTER” ON PAGE 15.
4.3 Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.3.1 IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
Baud Rate Generator Divisor
0 0 0 DLL RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7]=1
LCR≠0xBF
0 0 1 DLM RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 1 0 DLD RD/WR IR Mode Auto
RS485
Direction
Control
4X Mode 8X Mode Bit-3 Bit-2 Bit-1 Bit-0 LCR[7]=1
LCR≠0xBF
EFR[4]=1
Enhanced Registers
0 1 0 EFR RD/WR Auto
CTS
Enable
Auto RTS
Enable
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5],
DLD
Soft-
ware
Flow
Cntl
Bit-3
Soft-
ware
Flow
Cntl
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
LCR=0XBF
1 0 0 XON1 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
1 0 1 XON2 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
1 1 0 XOFF
1
RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
1 1 1 XOFF
2
RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0
REG
NAME
READ/
WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
XR16M752/XR68M752
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REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M752 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
•Logic 0 = Disable the receive data ready interrupt (default).
•Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-
FIFO mode or when spaces in the FIFO is above the programmed trigger level in the FIFO mode. If the THR is
empty when this bit is enabled, an interrupt will be generated.
•Logic 0 = Disable Transmit Ready interrupt (default).
•Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3, 4 or 7 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bit-7 is set if any character in the RX FIFO has a parity or framing error, or is
a break character. LSR[4:2] always show the error status for the received character available for reading from
the RX FIFO. If IER[2] = 1, an LSR interrupt will be generated as long as LSR[7] = 1, ie. the RX FIFO contains
at lease one character with an error.
•Logic 0 = Disable the receiver line status interrupt (default).
•Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
•Logic 0 = Disable the modem status register interrupt (default).
•Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
•Logic 0 = Disable Sleep Mode (default).
•Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
•Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
•Logic 1 = Enable the receive Xoff interrupt. See Software Flow Control section for details.
XR16M752/XR68M752
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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
•Logic 0 = Disable the RTS# interrupt (default).
•Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
•Logic 0 = Disable the CTS# interrupt (default).
•Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
4.4 Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 9, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1 Interrupt Generation:
•LSR is by any of the LSR bits 1, 2, 3, 4 and 7.
•RXRDY is by RX trigger level.
•RXRDY Time-out is by a 4-char plus 12 bits delay timer.
•TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).
•MSR is by any of the MSR bits 0, 1, 2 and 3.
•Receive Xoff/Special character is by detection of a Xoff or Special character.
•CTS# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.
•RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.
4.4.2 Interrupt Clearing:
•LSR interrupt is cleared by reading all characters with errors out of the RX FIFO.
•RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
•RXRDY Time-out interrupt is cleared by reading RHR.
•TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
•MSR interrupt is cleared by a read to the MSR register.
•Xoff interrupt is cleared when Xon character(s) is received.
•Special character interrupt is cleared by a read to ISR.
•RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
XR16M752/XR68M752
29
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
]
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY ISR REGISTER STATUS BITS SOURCE OF INTERRUPT
LEVEL BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
1 0 0 0 1 1 0 LSR (Receiver Line Status Register)
2 0 0 1 1 0 0 RXRDY (Receive Data Time-out)
3 0 0 0 1 0 0 RXRDY (Received Data Ready)
4 0 0 0 0 1 0 TXRDY (Transmit Ready)
5 0 0 0 0 0 0 MSR (Modem Status Register)
6 0 1 0 0 0 0 RXRDY (Received Xoff or Special character)
7 1 0 0 0 0 0 CTS#, RTS# change of state
- 0 0 0 0 0 1 None (default)
ISR[0]: Interrupt Status
•Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
•Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 9).
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is set when EFR[4] = 1 and IER[5] = 1. ISR bit-4 indicates that the receiver detected a data match of
the Xoff character(s). If this is an Xoff interrupt, it is cleared when XON is received. If it is a special character
interrupt, it is cleared by reading ISR.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR[4] = 1. ISR bit-5 indicates that the CTS# or RTS# has been de-asserted.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5 FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
•Logic 0 = Disable the transmit and receive FIFO (default).
•Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
XR16M752/XR68M752
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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•Logic 0 = No receive FIFO reset (default)
•Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•Logic 0 = No transmit FIFO reset (default).
•Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
•Logic 0 = Normal Operation (default).
•Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1)
(logic 0 = default, TX trigger level = 8)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of spaces in the FIFO is above the selected trigger level, or when it gets empty in case that the FIFO
did not get filled over the trigger level on last re-load. Table 10 shows the selections. The UART will issue a
transmit interrupt when the number of available spaces in the FIFO is less than the transmit trigger level.
Table 10 shows the selections.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level = 8)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO is greater than the receive trigger level or when a receive data
timeout occurs (see “Section 2.10, Receiver” on page 17).
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
BIT-7 BIT-6 BIT-5 BIT-4
RECEIVE
TRIGGER LEVEL
(CHARACTERS)
TRANSMIT
TRIGGER LEVEL
(SPACES)
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
8
16
56
60
8
16
32
56
FCR FCR FCR FCR
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REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
4.6 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
WORD LENGTH
0 0 5
0 1 6 (default)
1 0 7
1 1 8
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
WORD
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
05,6,7,8 1
1 5 1-1/2
16,7,8 2 (default)
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 11 for parity selection summary below.
•Logic 0 = No parity.
•Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format.
•Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
•Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
BIT-1 BIT-0
BIT-2
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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
•LCR BIT-5 = logic 0, parity is not forced (default).
•LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
•LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
TABLE 11: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3 PARITY SELECTION
X X 0 No parity
0 0 1 Odd parity
0 1 1 Even parity
1 0 1 Force parity to mark, “1”
1 1 1 Forced parity to space, “0”
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space", LOW state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
•Logic 0 = No TX break condition (default).
•Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL, DLM and DLD) enable.
•Logic 0 = Data registers are selected (default).
•Logic 1 = Divisor latch registers are selected.
4.7 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
•Logic 0 = Force DTR# output HIGH (default).
•Logic 1 = Force DTR# output LOW.
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. The RTS# pin can also be used for Auto RS485 Half-Duplex direction control enabled by FCTR bit-
3. If the modem interface is not used, this output may be used as a general purpose output.
•Logic 0 = Force RTS# HIGH (default).
•Logic 1 = Force RTS# LOW.
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REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
MCR[2]: OP1# / FIFO Rdy Enable
OP1# is not available as an output pin on the M752. But it is available for use during Internal Loopback Mode
(MCR[4] = 1). In the Internal Loopback Mode, this bit is used to write the state of the modem RI# interface
signal.
This bit is also used to select between the SPR, TLR and FIFO Rdy registers. All of these registers are
accessible at address offset 0x7 when LCR≠0xBF. However, LCR = 0xBF is required to access EFR.
TABLE 12: REGISTER AT ADDRESS OFFSET 0X7
EFR[4] MCR[6] MCR[4, 2] Register at Address Offset 0x7
0 X ≠’01’ Scratchpad Register (SPR)
1 0 ≠’01’ Scratchpad Register (SPR)
1 1 ≠’01’ Trigger Level Register (TLR)
X X =’01’ FIFO Ready Register (FIFO Rdy)
MCR[3]: OP2# Output / INT Output Enable
This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used
as a general purpose output.
•Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default).
•Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.
MCR[4]: Internal Loopback Enable
•Logic 0 = Disable loopback mode (default).
•Logic 1 = Enable local loopback mode, see loopback section and Figure 13.
MCR[5]: Xon-Any Enable (requires EFR bit-4=1 to write to this bit)
•Logic 0 = Disable Xon-Any function (default).
•Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the M752 is programmed to use the Xon/Xoff flow control.
MCR[6]: TCR and TLR Enable (requires EFR bit-4=1 to write to this bit)
This bit enables the TCR and TLR registers at address offset 0x6 and 0x7, respectively. See Table 12 above
for the correct register setting to access the TLR register. See Table 13 below for the setting to access the
TCR register.
•Logic 0 = Reserved (default).
•Logic 1 = Enable access to the TCR and TLR registers.
TABLE 13: REGISTER AT ADDRESS OFFSET 0X6
EFR[4] MCR[6] Register at Address Offset 0x6
0 X Modem Status Register (MSR)
1 0 Modem Status Register (MSR)
1 1 Trigger Control Register (TCR)
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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
MCR[7]: Clock Prescaler Select (requires EFR bit-4=1 to write to this bit)
•Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
•Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
4.8 Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
•Logic 0 = No data in receive holding register or FIFO (default).
•Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Error Flag
•Logic 0 = No overrun error (default).
•Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Tag
•Logic 0 = No parity error (default).
•Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
•Logic 0 = No framing error (default).
•Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[4]: Receive Break Error Tag
•Logic 0 = No break condition (default).
•Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte
is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0
concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set
when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
•Logic 0 = No FIFO error (default).
•Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.
4.9 Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem
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REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
changes state. These bits may be used for general purpose inputs when they are not used with modem
signals.
MSR[0]: Delta CTS# Input Flag
•Logic 0 = No change on CTS# input (default).
•Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
•Logic 0 = No change on DSR# input (default).
•Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
•Logic 0 = No change on RI# input (default).
•Logic 1 = The RI# input has changed from a LOW to HIGH, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
•Logic 0 = No change on CD# input (default).
•Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has
finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of
the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The
CTS# input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is
not used.
MSR[6]: RI Input Status
Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
4.10 Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle. There are also
two other registers (TLR and FIFO Rdy) that share the same address location as the Scratch Pad Register.
See Table 12.
4.11 Transmission Control Register (TCR) - Read/Write (requires EFR bit-4 = 1)
This register replaces MSR and is accessible only when MCR[6] = 1. This 8-bit register is used to store the RX
FIFO threshold levels to halt/resume transmission during hardware or software flow control.
TCR[3:0]: RX FIFO Halt Level
A value of 0-60 (decimal value of TCR[3:0] multiplied by 4) can be selected as the Halt Level. When the RX
FIFO is greater than or equal to this value, the RTS# output will be de-asserted if Auto RTS flow control is used
or the XOFF character(s) will be transmitted if Auto XON/XOFF flow control is used. It is recommended that
this value is greater than the RX Trigger Level.
TCR[7:4]: RX FIFO Resume Level
A value of 0-60 (decimal value of TCR[7:4] multiplied by 4) can be selected as the Resume Level. When the
RX FIFO is less than or equal to this value, the RTS# output will be re-asserted if Auto RTS flow control is used
or the XON character(s) will be transmitted if Auto XON/XOFF flow control is used. It is recommended that this
value is less than the RX Trigger Level.
4.12 Trigger Level Register (TLR) - Read/Write (requires EFR bit-4 = 1)
This register replaces SPR and is accessible under the conditions listed in Table 12. This 8-bit register is used
to store the RX and TX FIFO trigger levels used for interrupts.
TLR[3:0]: TX FIFO Trigger Level
A value of 4-60 (decimal value of TCR[3:0] multiplied by 4) can be selected as the TX FIFO Trigger Level.
When the number of available spaces in the TX FIFO is greater than or equal to this value, a Transmit Ready
interrupt is generated. For any non-zero value, TCR[3:0] will be used as the TX FIFO Trigger Level. If
TCR[3:0] = 0x0, then the TX FIFO Trigger Level is the value selected by FCR[5:4]. See Table 10.
TLR[7:4]: RX FIFO Trigger Level
A value of 4-60 (decimal value of TCR[7:4] multiplied by 4) can be selected as the RX FIFO Trigger Level.
When the number of characters received in the RX FIFO is greater than or equal to this value, a Receive Data
Ready interrupt is generated (a Receive Data Timeout interrupt is independent of the RX FIFO Trigger Level
and can be generated any time there is at least 1 byte in the RX FIFO and the RX input has been idle for the
timeout period described in “Section 2.10, Receiver” on page 17). For any non-zero value, TCR[7:4] will be
used as the RX FIFO Trigger Level. If TCR[7:4] = 0x0, then the RX FIFO Trigger Level is the value selected by
FCR[7:6]. See Table 10.
4.13 Baud Rate Generator Registers (DLL, DLM and DLD[3:0]) - Read/Write
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. SEE ”PROGRAMMABLE BAUD RATE GENERATOR
WITH FRACTIONAL DIVISOR” ON PAGE 13.
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 14 below.
TABLE 14: SAMPLING RATE SELECT
DLD[5] DLD[4] SAMPLING RATE
0 0 16X
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REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
DLD[6]: Auto RS-485 Direction Control
•Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
becomes empty and transmit shift register is shifting data out. The RTS# output can be used as a general
purpose output or for Auto RTS flow control.
•Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its
output logic state from HIGH to LOW one bit time after the last stop bit of the last character is shifted out.
Also, the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The
RTS# output pin will automatically return to a HIGH when a data byte is loaded into the TX FIFO. See
“Section 2.13, Auto RS485 Half-duplex Control” on page 18.
DLD[7]: Infrared Encoder/Decoder Enable
•Logic 0 = Enable the standard modem receive and transmit input/output interface (default).
•Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. While in this mode, the infrared TX output will be idling LOW. SEE ”INFRARED MODE” ON
PAGE 20.
4.14 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
0 1 8X
1 X 4X
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0 TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0 0 0 0 No TX and RX flow control (default and reset)
0 0 X X No transmit flow control
1 0 X X Transmit Xon1, Xoff1
0 1 X X Transmit Xon2, Xoff2
1 1 X X Transmit Xon1 and Xon2, Xoff1 and Xoff2
X X 0 0 No receive flow control
X X 1 0 Receiver compares Xon1, Xoff1
X X 0 1 Receiver compares Xon2, Xoff2
1 0 1 1 Transmit Xon1, Xoff1
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
TABLE 14: SAMPLING RATE SELECT
DLD[5] DLD[4] SAMPLING RATE
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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7, TCR,
TLR and DLD to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the
new values. This feature prevents legacy software from altering or overwriting the enhanced functions once
set. Normally, it is recommended to leave it enabled, logic 1.
•Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-
7, and DLD are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5,
MCR bits 5-7, and DLD are set to a logic 0 to be compatible with ST16C550 mode (default).
•Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
•Logic 0 = Special Character Detect Disabled (default).
•Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts HIGH at the programmed HALT level. RTS# will return LOW when FIFO data falls below the
programmed RESUME level. The RTS# output must be asserted (LOW) before the auto RTS can take effect.
RTS# pin will function as a general purpose output when hardware flow control is disabled.
•Logic 0 = Automatic RTS flow control is disabled (default).
•Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
•Logic 0 = Automatic CTS flow control is disabled (default).
•Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH.
Data transmission resumes when CTS# returns LOW.
4.14.1 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Table 8.
0 1 1 1 Transmit Xon2, Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
1 1 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0 0 1 1 No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0 TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B
DLM, DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up.
They do not reset when the Reset Pin is asserted.
DLD Bits 7-0 = 0x00
RHR Bits 7-0 = 0xXX
THR Bits 7-0 = 0xXX
IER Bits 7-0 = 0x00
FCR Bits 7-0 = 0x00
ISR Bits 7-0 = 0x01
LCR Bits 7-0 = 0x1D
MCR Bits 7-0 = 0x00
LSR Bits 7-0 = 0x60
MSR Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR Bits 7-0 = 0xFF. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
TCR Bits 7-0 = 0x0F
TLR Bits 7-0 = 0x00
FIFO Rdy Bits 7-0 = 0x03
EFR Bits 7-0 = 0x00
XON1 Bits 7-0 = 0x00. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
XON2 Bits 7-0 = 0x00. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
XOFF1 Bits 7-0 = 0x00. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
XOFF2 Bits 7-0 = 0x00. Only resets to these values during a power up. They do not
reset when the Reset Pin is asserted.
I/O SIGNALS
TX HIGH
OP2# HIGH
RTS# HIGH
DTR# HIGH
RXRDY# HIGH
TXRDY# LOW
INT Three-State Condition
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REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REGISTERS RESET STATE
RESET STATE
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5.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Power Supply Range 4 Volts
Voltage at Any Pin GND-0.3V to 4V
Operating Temperature -40o to +85oC
Storage Temperature -65o to +150oC
Package Dissipation 500 mW
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
Thermal Resistance (48-TQFP) theta-ja =59oC/W, theta-jc = 16oC/W
Thermal Resistance (32-QFN) theta-ja = 33oC/W, theta-jc = 22oC/W
DC ELECTRICAL CHARACTERISTICS
TA= -40o to +85oC, Vcc is 1.62V to 3.63V
SYMBOL PARAMETER
LIMITS
MIN MAX
LIMITS
MIN MAX
LIMITS
MIN MAX
UNITS CONDITIONS
VILCK Clock Input Low Level -0.3 0.3 -0.3 0.6 -0.3 0.6 V
VIHCK Clock Input High Level 1.4 VCC 1.8 VCC 2.4 VCC V
VIL Input Low Voltage -0.3 0.2 -0.3 0.5 -0.3 0.8 V
VIH Input High Voltage 1.4 VCC 1.8 VCC 2.0 VCC V
VOL Output Low Voltage
0.4
0.4
0.4 V
V
IOL = 4 mA
IOL = 2 mA
IOL = 1.5 mA
VOH Output High Voltage
1.4
1.8
2.0 V
V
IOH = -1 mA
IOH = -400 uA
IOH = -200 uA
IIL Input Low Leakage Current ±10 ±10 ±10 uA
IIH Input High Leakage Current ±10 ±10 ±10 uA
CIN Input Pin Capacitance 5 5 5 pF
ICC Power Supply Current 0.5 1 2 mA XTAL1 = 2 MHz
ISLEEP Sleep Current (16 Mode) 310 15 uA See Test 1
ISLEEP Sleep Current (68 Mode) 50 75 100 uA See Test 1
Test 1: The following inputs must remain steady at VCC or GND state to minimize Sleep current: A0-A2, D0-
D7, IOR#, IOW#, CSA# (CS# in 68 Mode), CSB# and all modem inputs. Also, RXA and RXB inputs must idle
HIGH while asleep. Floating inputs will result in sleep currents in the mA range.
1.8V 2.5V 3.3V
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REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
AC ELECTRICAL CHARACTERISTICS
Unless otherwise noted: TA=-40o to +85oC, Vcc=1.62 - 3.63V, 70 pF load where applicable
SYMBOL PARAMETER
LIMITS
1.8V ± 10%
MIN MAX
LIMITS
2.5V ± 10%
MIN MAX
LIMITS
3.3V ± 10%
MIN MAX
UNIT
XTAL1 UART Crystal Oscillator 24 24 24 MHz
ECLK External Clock 32 50 64 MHz
TECLK External Clock Time Period 15 10 7ns
TAS Address Setup Time (16 mode) 5 5 5 ns
TAH Address Hold Time (16 mode) 0 0 0 ns
TCS Chip Select Width (16 mode) 60 30 30 ns
TRD IOR# Strobe Width (16 mode) 60 30 30 ns
TDY Read Cycle Delay (16 mode) 60 30 30 ns
TRDV Data Access Time (16 mode) 55 25 25 ns
TDD Data Disable Time (16 mode) 020 020 010 ns
TWR IOW# Strobe Width (16 mode) 60 30 30 ns
TDY Write Cycle Delay (16 mode) 60 30 30 ns
TDS Data Setup Time (16 mode) 15 10 10 ns
TDH Data Hold Time (16 mode) 5 5 5 ns
TADS Address Setup (68 Mode) 5 5 5 ns
TADH Address Hold (68 Mode) 0 0 0 ns
TRWS R/W# Setup to CS# (68 Mode) 5 5 5 ns
TRDA Read Data Access (68 mode) 55 25 25 ns
TRDH Read Data Disable (68 mode) 20 20 10 ns
TWDS Write Data Setup (68 mode) 15 10 10 ns
TWDH Write Data Hold (68 Mode) 5 5 5 ns
TRWH CS# De-asserted to R/W# De-asserted (68
Mode)
5 5 5 ns
TCSL CS# Width (68 Mode) 60 30 30 ns
TCSD CS# Cycle Delay (68 Mode) 60 30 30 ns
TWDO Delay From IOW# To Output 50 50 50 ns
TMOD Delay To Set Interrupt From MODEM Input 50 50 50 ns
TRSI Delay To Reset Interrupt From IOR# 50 50 50 ns
TSSI Delay From Stop To Set Interrupt 1 1 1 Bclk
XR16M752/XR68M752
42
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
TRRI Delay From IOR# To Reset Interrupt 45 45 45 ns
TSI Delay From Stop To Interrupt 45 45 45 ns
TINT Delay From Initial INT Reset To Transmit Start 824 824 824 Bclk
TWRI Delay From IOW# To Reset Interrupt 45 45 45 ns
TSSR Delay From Stop To Set RXRDY# 1 1 1 Bclk
TRR Delay From IOR# To Reset RXRDY# 45 45 45 ns
TWT Delay From IOW# To Set TXRDY# 45 45 45 ns
TSRT Delay From Center of Start To Reset TXRDY# 8 8 8 Bclk
TRST Reset Pulse Width 40 40 40 ns
Bclk Baud Clock 16X or 8X or 4X of data rate Hz
FIGURE 14. CLOCK TIMING
External
Clock
TECH TECL
VIH
VIL
TECLK
AC ELECTRICAL CHARACTERISTICS
Unless otherwise noted: TA=-40o to +85oC, Vcc=1.62 - 3.63V, 70 pF load where applicable
SYMBOL PARAMETER
LIMITS
1.8V ± 10%
MIN MAX
LIMITS
2.5V ± 10%
MIN MAX
LIMITS
3.3V ± 10%
MIN MAX
UNIT
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B
IOW #
RTS#
DTR#
CD#
CTS#
DSR#
INT
IOR#
RI#
TWDO
TMOD TMOD
TRSI
TMOD
Active
Active
Change of state Change of state
Active Active Active
Change of state Change of state
Change of state
Active Active
FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING
TAS
TDD
TAH
TRD
TRDV
TDY
TDD
TRDV
TAH
TAS
TCS
Valid Address Valid Address
Valid Data Valid Data
A0-A2
CSA#/
CSB#
IOR#
D0-D7
RDTm
TCS
TRD
XR16M752/XR68M752
43
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING
16Write
TAS
TDH
TAH
TWR
TDS
TDY
TDH
TDS
TAH
TAS
TCS
Valid Address Valid Address
Valid Data Valid Data
A0-A2
CSA#/
CSB#
IOW#
D0-D7
TCS
TWR
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING
68Read
TADS
TRDH
TADHTCSL
TRDA
TCSD
TRWS
Valid Address Valid Address
Valid Data
A0-A2
CS#
R/W#
D0-D7
TRWH
Valid Data
XR16M752/XR68M752
44
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING
68Write
TADS TADHTCSL
TWDS
TCSD
TRWS
Valid Address Valid Address
Valid Data
A0-A2
CS#
R/W#
D0-D7
TRWH
Valid Data
TWDH
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
RX
RXRDY#
IOR#
INT
D0:D7
Start
Bit D0:D7
Stop
Bit D0:D7
TSSR
1 Byte
in RHR
Active
Data
Ready
Active
Data
Ready
Active
Data
Ready
1 Byte
in RHR
1 Byte
in RHR
TSSR TSSR
RXNFM
TRR TRR TRR
TSSR TSSR TSSR
(Reading data
out of RHR)
XR16M752/XR68M752
45
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
TX
TXRDY#
IOW#
INT*
D0:D7
Start
Bit D0:D7
Stop
Bit D0:D7
TWT
TXNonFIFO
TWT TWT
TWRI TWRI TWRI
TSRT TSRT TSRT
*INT is cleared when the ISR is read or when data is loaded into the THR.
ISR is read ISR is readISR is read
(Loading data
into THR)
IER[1]
enabled
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B
RX
RXRDY#
IOR#
INT
D0:D7
S
TSSR
RXINTDMA#
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
First Byte is
Received in
RX FIFO
D0:D7
SD0:D7TD0:D7
SD0:D7
S
TD0:D7
S
TTD0:D7
ST
Start
Bit
Stop
Bit
TRR
TRRI
TSSI
(Reading data out
of RX FIFO)
XR16M752/XR68M752
46
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B
RX
RXRDY#
IOR#
INT
D0:D7
S
TSSR
RXFIFODMA
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
D0:D7
SD0:D7TD0:D7
SD0:D7
S
TD0:D7
S
TTD0:D7
ST
Start
Bit
Stop
Bit
TRR
TRRI
TSSI
(Reading data out
of RX FIFO)
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
TX
TXRDY#
IOW#
INT*
TXDMA#
D0:D7
SD0:D7TD0:D7
SD0:D7
S
TD0:D7
S
TTD0:D7
ST
Start
Bit
Stop
Bit
TWRI
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level TX FIFO drops
below trigger level
Data in
TX FIFO
TX FIFO
Empty
TWT
TSRT
TX FIFO
Empty
T
TS
TSI
ISR is read
IER[1]
enabled
ISR is read
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
XR16M752/XR68M752
47
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
TX
TXRDY#
IOW#
INT*
D0:D7
S
TXDMA
D0:D7
SD0:D7
TD0:D7
SD0:D7S
TD0:D7
S
TTD0:D7ST
Start
Bit
Stop
Bit
TWRI
T
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
At least 1
empty location
in FIFO
TSRT
TX FIFO
Full
TWT
TSI
ISR Read ISR Read
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
IER[1]
enabled
XR16M752/XR68M752
48
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)
36 25
24
13
1
1
2
37
48
D
D
1
D
D
1
B
e
α
A
2
A
1
A
Seating
Plane
L
C
Note: The control dimension is the millimeter column
A0.039 0.047 1.00 1.20
A10.002 0.006 0.05 0.15
A20.037 0.041 0.95 1.05
B0.007 0.011 0.17 0.27
C0.004 0.008 0.09 0.20
D0.346 0.362 8.80 9.20
D10.272 0.280 6.90 7.10
e0.020 BSC 0.50 BSC
L0.018 0.030 0.45 0.75
a 0°7°0°7°
XR16M752/XR68M752
49
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm)
Note: the actual center pad
is metallic and the size (D2)
is device-dependent with a
typical tolerance of 0.3mm
Note: The control dimension is in millimeter.
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A0.031 0.039 0.80 1.00
A1 0.000 0.002 0.00 0.05
A3 0.006 0.010 0.15 0.25
D0.193 0.201 4.90 5.10
D2 0.138 0.150 3.50 3.80
b0.007 0.012 0.18 0.30
e0.0197 BSC 0.50 BSC
L0.012 0.020 0.35 0.45
k0.008 -0.20 -
XR16M752/XR68M752
50
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
PACKAGE DIMENSIONS (49 PIN SHRINK THIN BALL GRID ARRAY - 4 X 4mm)
B
A
E
D
C
A1 corner
F
G
13245
76
D1
D1D
D
e
b
A1
AA2
(A1 corner feature is mfger option)
Plane
Seating
Note: The control dimension is in millimeter.
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A0.035 0.046 0.88 1.18
A1 0.007 0.011 0.18 0.28
A2 0.028 0.035 0.70 0.90
D0.154 0.161 3.90 4.10
D1 0.118 BSC 3.00 BSC
b0.010 0.014 0.26 0.36
e0.020 BSC 0.50 BSC
XR16M752/XR68M752
51
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REVISION HISTORY
DATE REVISION DESCRIPTION
July 2006 P1.0.0 Preliminary Datasheet.
September 2006 1.0.0 Final Datasheet. Updated AC Electrical Characteristics.
May 2007 1.0.1 Corrected pin names pin out assignment for 48-pin TQFP package for XR68M752 in
Motorola mode. Added GND center pad for QFN package to pin description. Added
Motorola mode Read/Write timing waveforms. Updated QFN package dimensions
drawing to show minimum "k" parameter.
May 2007 1.0.2 Updated pin description table, correct pin # of RXA in QFN-32 package.
December 2007 1.1.0 Added 49-pin STBGA package with these additional pins - PwrSave, ENIR# and
EN485#.
June 2009 1.1.1 Corrected page 30 FCR[7:6] and FCR[5:4] default trigger levels.
52
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2008 EXAR Corporation
Datasheet June 2009.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
XR16M752/XR68M752
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
XR16M752/XR68M752
I
REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................ 1
APPLICATIONS .............................................................................................................................................. 1
FEATURES .................................................................................................................................................... 1
FIGURE 1. XR16M752 BLOCK DIAGRAM .......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT - TQFP AND QFN PACKAGES ....................................................................................................... 2
FIGURE 3. PIN OUT ASSIGNMENT - STBGA PACKAGE ...................................................................................................................... 3
ORDERING INFORMATION ............................................................................................................................... 3
PIN DESCRIPTIONS ........................................................................................................ 4
1.0 PRODUCT DESCRIPTION ...................................................................................................................... 9
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 10
2.1 CPU INTERFACE .............................................................................................................................................. 10
FIGURE 4. XR16M752/XR68M752 DATA BUS INTERCONNECTIONS ................................................................................................ 10
2.2 DEVICE RESET ................................................................................................................................................. 11
2.3 CHANNEL A AND B SELECTION .................................................................................................................... 11
TABLE 1: CHANNEL A AND B SELECT IN 16 MODE .......................................................................................................................... 11
TABLE 2: CHANNEL A AND B SELECT IN 68 MODE .......................................................................................................................... 11
2.4 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................. 11
2.5 DMA MODE ....................................................................................................................................................... 12
TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE ........................................................................................... 12
2.6 INTA AND INTB OUTPUTS............................................................................................................................... 12
TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER ...................................................................................................... 12
TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................. 12
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 13
FIGURE 5. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................... 13
2.8 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 13
FIGURE 6. BAUD RATE GENERATOR ............................................................................................................................................... 14
TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................... 15
2.9 TRANSMITTER.................................................................................................................................................. 15
2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 16
2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................... 16
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 16
2.9.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 16
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 16
2.10 RECEIVER ....................................................................................................................................................... 17
2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 17
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................... 17
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 18
2.11 AUTO RTS (HARDWARE) FLOW CONTROL................................................................................................ 18
2.12 AUTO RTS HALT AND RESUME .................................................................................................................. 18
2.13 AUTO RS485 HALF-DUPLEX CONTROL ..................................................................................................... 18
2.14 AUTO CTS FLOW CONTROL........................................................................................................................ 19
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 19
2.15 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 20
2.16 SPECIAL CHARACTER DETECT.................................................................................................................. 20
2.17 INFRARED MODE ........................................................................................................................................... 20
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 21
2.18 SLEEP MODE WITH WAKE-UP INDICATOR AND POWERSAVE FEATURE ........................................... 22
2.19 SLEEP MODE WITH AUTO WAKE-UP .......................................................................................................... 22
2.19.1 POWERSAVE FEATURE (49-PIN STBGA PACAKGE ONLY) ................................................................................. 22
2.20 INTERNAL LOOPBACK................................................................................................................................. 23
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 23
3.0 UART INTERNAL REGISTERS............................................................................................................. 24
TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS ...................................................................................... 24
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ......................................... 25
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 26
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 26
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 26
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 26
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 26
XR16M752/XR68M752
II
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 27
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 28
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 28
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 28
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 29
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 29
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 30
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 31
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 32
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE.. 32
TABLE 12: REGISTER AT ADDRESS OFFSET 0X7 ............................................................................................................................. 33
TABLE 13: REGISTER AT ADDRESS OFFSET 0X6 ............................................................................................................................. 33
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 34
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 34
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 36
4.11 TRANSMISSION CONTROL REGISTER (TCR) - READ/WRITE (REQUIRES EFR BIT-4 = 1)..................... 36
4.12 TRIGGER LEVEL REGISTER (TLR) - READ/WRITE (REQUIRES EFR BIT-4 = 1) ...................................... 36
4.13 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD[3:0]) - READ/WRITE................................ 36
TABLE 14: SAMPLING RATE SELECT ............................................................................................................................................... 36
4.14 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 37
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 37
4.14.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 38
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B ............................................................................................ 39
5.0 ELECTRICAL CHARACTERISTICS ...................................................................................................... 40
ABSOLUTE MAXIMUM RATINGS..................................................................................................................... 40
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) .............................................. 40
DC ELECTRICAL CHARACTERISTICS ............................................................................................................. 40
AC ELECTRICAL CHARACTERISTICS ............................................................................................................. 41
FIGURE 14. CLOCK TIMING............................................................................................................................................................. 42
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 43
FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING ................................................................................................................... 43
FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING.................................................................................................................. 44
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING .......................................................................................................... 44
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 45
FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING......................................................................................................... 45
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 46
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 46
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 47
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B............................ 47
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 48
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)................................................................................... 49
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm)................................................................................ 50
PACKAGE DIMENSIONS (49 PIN SHRINK THIN BALL GRID ARRAY - 4 X 4mm) ................................................. 51
REVISION HISTORY...................................................................................................................................... 52
