NCP115
www.onsemi.com
12
APPLICATIONS INFORMATION
General
The NCP115 is a high performance 300 mA Low Dropout
Linear Regulator. This device delivers very high PSRR
(over 70 dB at 1 kHz) and excellent dynamic performance
as load/line transients. In connection with very low
quiescent current this device is very suitable for various
battery powered applications such as tablets, cellular
phones, wireless and many others. The device is fully
protected in case of output overload, output short circuit
condition and overheating, assuring a very robust design.
Input Capacitor Selection (CIN)
It is recommended to connect at least a 1 mF Ceramic X5R
or X7R capacitor as close as possible to the IN pin of the
device. This capacitor will provide a low impedance path for
unwanted AC signals or noise modulated onto constant
input voltage. There is no requirement for the min. /max.
ESR of the input capacitor but it is recommended to use
ceramic capacitors for their low ESR and ESL. A good input
capacitor will limit the influence of input trace inductance
and source resistance during sudden load current changes.
Larger input capacitor may be necessary if fast and large
load transients are encountered in the application.
Output Decoupling (COUT)
The NCP115 requires an output capacitor connected as
close as possible to the output pin of the regulator. The
recommended capacitor value is 1 mF and X7R or X5R
dielectric due to its low capacitance variations over the
specified temperature range. The NCP115 is designed to
remain stable with minimum effective capacitance of
0.47 mF to account for changes with temperature, DC bias
and package size. Especially for small package size
capacitors such as 0402 the effective capacitance drops
rapidly with the applied DC bias.
There is no requirement for the minimum value of
Equivalent Series Resistance (ESR) for the COUT but the
maximum value of ESR should be less than 1.8 W. Larger
output capacitors and lower ESR could improve the load
transient response or high frequency PSRR. It is not
recommended to use tantalum capacitors on the output due
to their large ESR. The equivalent series resistance of
tantalum capacitors is also strongly dependent on the
temperature, increasing at low temperature.
Enable Operation
The NCP1 15 uses the EN pin to enable/disable its device
and to deactivate/activate the active discharge function.
If the EN pin voltage is <0.4 V the device is guaranteed to
be disabled. The pass transistor is turned−off so that there is
virtually no current flow between the IN and OUT. The
active dischar ge transistor is active so that the output voltage
VOUT is pulled to GND through a 100 W resistor. In the
disable state the device consumes as low as typ. 10 nA from
the VIN.
If the EN pin voltage >0.9 V the device is guaranteed to
be enabled. The NCP115 regulates the output voltage and
the active discharge transistor is turned−off.
The EN pin has internal pull−down current source with
typ. value of 300 nA which assures that the device is
turned−off when the EN pin is not connected. In the case
where the EN function isn’t required the EN should be tied
directly to IN.
Output Current Limit
Output Current is internally limited within the IC to a
typical 600 mA. The NCP115 will source this amount of
current measured with a voltage drops on the 90% of the
nominal VOUT. If the Output Voltage is directly shorted to
ground (VOUT = 0 V), the short circuit protection will limit
the output current to 630 mA (typ). The current limit and
short circuit protection will work properly over whole
temperature range and also input voltage range. There is no
limitation for the short circuit duration.
Thermal Shutdown
When the die temperature exceeds the Thermal Shutdown
threshold (TSD − 160°C typical), Thermal Shutdown event
is detected and the device is disabled. The IC will remain in
this state until the die temperature decreases below the
Thermal Shutdown Reset threshold (TSDU − 140°C typical).
Once the IC temperature falls below the 140°C the LDO is
enabled again. The thermal shutdown feature provides the
protection from a catastrophic device failure due to
accidental overheating. This protection is not intended to be
used as a substitute for proper heat sinking.
Power Dissipation
As power dissipated in the NCP115 increases, it might
become necessary to provide some thermal relief. The
maximum power dissipation supported by the device is
dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material, and the
ambient temperature affect the rate of junction temperature
rise for the part.
The maximum power dissipation the NCP115 can handle
is given by:
PD(MAX) +ƪ85°C*TAƫ
qJA
(eq. 1)
The power dissipated by the NCP115 for given
application conditions can be calculated from the following
equations:
PD[VINǒIGND@IOUTǓ)IOUTǒVIN *VOUTǓ(eq. 2)