MT9JBF25672AKZ-1G4D1 - Micron Technology, Inc.

DDR3 SDRAM VLP Mini-UDIMM

MT9JBF25672AKZ – 2GB

Features

•DDR3 functionality and operations supported as

defined in the component data sheet

•244-pin, unbuffered dual in-line, 82mm, very low

profile (17.9mm) memory module (VLP Mini-

UDIMM)

•Fast data transfer rates: PC3-12800, PC3-10600,

PC3-8500, or PC3-6400

•2GB (256 Meg x 72)

•VDD = 1.5V ±0.075V

•VDDSPD = +3.0V to +3.6V

•Supports ECC error detection and correction

•Nominal and dynamic on-die termination (ODT) for

data, strobe, and mask signals

•Single rank

•On-board I2C temperature sensor with integrated

serial presence-detect (SPD) EEPROM

•8 internal device banks

•Fixed burst chop (BC) of 4 and burst length (BL) of 8

via the mode register set (MRS)

•Selectable BC4 or BL8 on-the-fly (OTF)

•Gold edge contacts

•Halogen-free

•Fly-by topology

•Terminated control, command, and address bus

Figure 1: 244-Pin VLP Mini-UDIMM

Module height: 17.9mm (0.705in)

Options Marking

•Operating temperature

–Commercial (0°C ≤ TA ≤ +70°C) None

•Package

–244-pin halogen-free VLP Mini-

UDIMM

•Frequency/CAS latency

–1.25ns @ CL = 11 (DDR3-1600) -1G6

–1.5ns @ CL = 9 (DDR3-1333) -1G4

–1.87ns @ CL = 7 (DDR3-1066) -1G1

Table 1: Key Timing Parameters

Speed

Grade

Industry

Nomenclature

Data Rate (MT/s) tRCD

(ns)

tRP

(ns)

tRC

(ns)CL = 11 CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5

-1G6 PC3-12800 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125

-1G4 PC3-10600 –1333 1333 1066 1066 800 667 13.125 13.125 49.125

-1G1 PC3-8500 – – – 1066 1066 800 667 13.125 13.125 50.625

-1G0 PC3-8500 – – – 1066 –800 667 15 15 52.5

-80C PC3-6400 – – – – – 800 800 12.5 12.5 50

-80B PC3-6400 – – – – – 800 667 15 15 52.5

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Features

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Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing

Parameter 2GB

Refresh count 8K

Row address 32K A[14:0]

Device bank address 8 BA[2:0]

Device configuration 2Gb (256 Meg x 8)

Column address 1K A[9:0]

Module rank address 1 S0#

Table 3: Part Numbers and Timing Parameters – 2GB Modules

Base device: MT41J256M8,1 2Gb DDR3 SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

MT9JBF25672AKZ-1G6__ 2GB 256 Meg x 72 12.8 GB/s 1.25ns/1600 MT/s 11-11-11

MT9JBF25672AKZ-1G4__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 9-9-9

MT9JBF25672AKZ-1G1__ 2GB 256 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 7-7-7

Notes: 1. The data sheet for the base device can be found on Micron’s Web site.

2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.

Consult factory for current revision codes. Example: MT9JBF25672AKZ-1G4D1.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Features

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Pin Assignments and Descriptions

Table 4: Pin Assignments

244-Pin DDR3 Mini-UDIMM Front 244-Pin DDR3 Mini-UDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

1 VTT 31 DQ24 61 VDD 92 DQ40 123 VTT 153 DQ29 183 A3 214 DQ45

2 VREFDQ 32 DQ25 62 A2 93 DQ41 124 VSS 154 VSS 184 A1 215 VSS

3 VSS 33 VSS 63 VDD 94 VSS 125 DQ4 155 DM3 185 VDD 216 DM5

4 DQ0 34 DQS3# 64 CK1 95 DQS5# 126 DQ5 156 NC 186 CK0 217 NC

5 DQ1 35 DQS3 65 CK1# 96 DQS5 127 VSS 157 VSS 187 CK0# 218 VSS

6 VSS 36 VSS 66 VDD 97 VSS 128 DM0 158 DQ30 188 VDD 219 DQ46

7 DQS0# 37 DQ26 67 VREFCA 98 DQ42 129 NC 159 DQ31 189 VDD 220 DQ47

8 DQS0 38 DQ27 68 VDD 99 DQ43 130 VSS 160 VSS 190 EVENT# 221 VSS

9 VSS 39 VSS 69 NC 100 VSS 131 DQ6 161 CB4 191 A0 222 DQ52

10 DQ2 40 CB0 70 VDD 101 DQ48 132 DQ7 162 CB5 192 VDD 223 DQ53

11 DQ3 41 CB1 71 A10 102 DQ49 133 VSS 163 VSS 193 BA1 224 VSS

12 VSS 42 VSS 72 BA0 103 VSS 134 DQ12 164 DM8 194 VDD 225 DM6

13 DQ8 43 DQS8# 73 VDD 104 DQS6# 135 DQ13 165 NC 195 RAS# 226 NC

14 DQ9 44 DQS8 74 WE# 105 DQS6 136 VSS 166 VSS 196 CS0# 227 VSS

15 VSS 45 VSS 75 CAS# 106 VSS 137 DM1 167 CB6 197 VDD 228 DQ54

16 DQS1# 46 CB2 76 VDD 107 DQ50 138 NC 168 CB7 198 ODT0 229 DQ55

17 DQS1 47 CB3 77 NC 108 DQ51 139 VSS 169 VSS 199 A13 230 VSS

18 VSS 48 VSS 78 NC 109 VSS 140 DQ14 170 NC 200 VDD 231 DQ60

19 DQ10 49 NC 79 VDD 110 DQ56 141 DQ15 171 NC 201 NC 232 DQ61

20 DQ11 50 RESET# 80 NC 111 DQ57 142 VSS 172 NC 202 NC 233 VSS

21 VSS 51 CKE0 81 NC 112 VSS 143 DQ20 173 VDD 203 VSS 234 DM7

22 DQ16 52 VDD 82 VSS 113 DQS7# 144 DQ21 174 NC 204 DQ36 235 NC

23 DQ17 53 BA2 83 DQ32 114 DQS7 145 VSS 175 A14 205 DQ37 236 VSS

24 VSS 54 NC 84 DQ33 115 VSS 146 DM2 176 VDD 206 VSS 237 DQ62

25 DQS2# 55 VDD 85 VSS 116 DQ58 147 NC 177 A12 207 DM4 238 DQ63

26 DQS2 56 A11 86 DQS4# 117 DQ59 148 VSS 178 A9 208 NC 239 VSS

27 VSS 57 A7 87 DQS4 118 VSS 149 DQ22 179 VDD 209 VSS 240 VDDSPD

28 DQ18 58 VDD 88 VSS 119 SA0 150 DQ23 180 A8 210 DQ38 241 SA1

29 DQ19 59 A5 89 DQ34 120 SCL 151 VSS 181 A6 211 DQ39 242 SDA

30 VSS 60 A4 90 DQ35 121 SA2 152 DQ28 182 VDD 212 VSS 243 VSS

91 VSS 122 VTT 213 DQ44 244 VTT

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Pin Assignments and Descriptions

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Table 5: Pin Descriptions

Symbol Type Description

A[14:0] Input Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one loca-

tion out of the memory array in the respective bank. A10 is sampled during a PRE-

CHARGE command to determine whether the PRECHARGE applies to one bank (A10

LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be pre-

charged, the bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-

the-fly” during CAS commands. The address inputs also provide the op-code during the

mode register command set.

BA[2:0] Input Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register

(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.

CK0, CK0# Input Clock: CK and CK# are differential clock inputs. All control, command, and address in-

put signals are sampled on the crossing of the positive edge of CK and the negative

edge of CK#.

CKE0 Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM.

DM[8:0] Input Input data mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH, along with the input data, during a write access. DM is sam-

pled on both edges of DQS. Although the DM pins are input-only, the DM loading is

designed to match that of the DQ and DQS pins.

ODT0 Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-

mination resistance internal to the DRAM. When enabled in normal operation, ODT is

only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ig-

nored if disabled via the LOAD MODE command.

RAS#, CAS#,

WE#

Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being

entered.

RESET# Input

(LVCMOS)

Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiv-

er is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and DC LOW

≤ 0.2 × VDD.

S0# Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command

decoder.

SA[2:0] Input Serial address inputs: These pins are used to configure the temperature sensor/SPD

EEPROM address range on the I2C bus.

SCL Input Serial clock for temperature sensor/SPD EEPROM: SCL is used to synchronize com-

munication to and from the temperature sensor/SPD EEPROM.

CB[7:0] I/O Check bits: Data used for ECC.

DQ[63:0] I/O Data input/output: Bidirectional data bus.

DQS[8:0],

DQS#[8:0]

I/O Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-

aligned with read data. Input with write data. Center-aligned with write data.

SDA I/O Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out

of the temperature sensor/SPD EEPROM on the I2C bus.

EVENT# Output

(open drain)

Temperature event: The EVENT# pin is asserted by the temperature sensor when criti-

cal temperature thresholds have been exceeded.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Pin Assignments and Descriptions

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Table 5: Pin Descriptions (Continued)

Symbol Type Description

VDD Supply Power supply: 1.5V ±0.075V. The component VDD and VDDQ are connected to the mod-

ule VDD.

VDDSPD Supply Temperature sensor/SPD EEPROM power supply: +3.0V to +3.6V.

VREFCA Supply Reference voltage: Control, command, and address (VDD/2).

VREFDQ Supply Reference voltage: DQ, DM (VDD/2).

VSS Supply Ground.

VTT Supply Termination voltage: Used for control, command, and address (VDD/2).

NC –No connect: These pins are not connected on the module.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Pin Assignments and Descriptions

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DQ Map

Table 6: Component-to-Module DQ Map

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

U1 0 6 131 U2 0 18 28

1 1 5 1 21 144

2 3 11 2 23 150

3 5 126 3 17 23

4 2 10 4 22 149

5 4 125 5 16 22

6 7 132 6 19 29

7 0 4 7 20 143

U4 8 34 89 U5 0 50 107

9 37 205 1 53 223

10 39 211 2 55 229

11 33 84 3 49 102

12 38 210 4 54 228

13 32 83 5 48 101

14 35 90 6 51 108

15 36 204 7 52 222

U6 0 61 232 U7 0 45 214

1 62 237 1 46 219

2 56 110 2 40 92

3 59 117 3 43 99

4 60 231 4 44 213

5 63 238 5 47 220

6 57 111 6 41 93

7 58 116 7 42 98

U8 0 CB0 40 U9 0 29 153

1 CB1 41 1 30 158

2 CB2 46 2 24 31

3 CB3 47 3 27 38

4 CB4 161 4 28 152

5 CB5 162 5 31 159

6 CB6 167 6 25 32

7 CB7 168 7 26 37

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

DQ Map

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Table 6: Component-to-Module DQ Map (Continued)

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

U10 0 9 14

1 14 140

2 12 134

3 11 20

4 8 13

5 15 141

6 13 135

7 10 19

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

DQ Map

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Functional Block Diagram

Figure 2: Functional Block Diagram

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM CS# DQ DQS#

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM CS# DQ DQS#

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

U10

DM CS# DQ DQS#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM CS# DQ DQS#

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM CS# DQ DQS#

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM CS# DQ DQS#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM CS# DQ DQS#

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM CS# DQ DQS#

DQS0#

DQS0

DM0

S0#

DQS1#

DQS1

DM1

DQS2#

DQS2

DM2

DQS3#

DQS3

DM3

DQS4#

DQS4

DM4

DQS5#

DQS5

DM5

DQS6#

DQS6

DM6

DQS7#

DQS7

DM7

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DM CS# DQ DQS#

DQS8#

DQS8

DM8

BA[2:0]

A[14:0]

RAS#

CAS#

WE#

CKE0

ODT0

RESET#

BA[2:0]: DDR3 SDRAMs

A[14:0]: DDR3 SDRAMs

RAS#: DDR3 SDRAMs

CAS#: DDR3 SDRAMs

WE#: DDR3 SDRAMs

CKE0: DDR3 SDRAMs

ODT0: DDR3 SDRAMs

RESET#: DDR3 SDRAMs

DDR3 SDRAM X 9

CK0

CK0#

CK1

CK1#

VREFCA

VSS

DDR3 SDRAMs

VDD

DDR3 SDRAMs

VDDSPD SPD EEPROM

VTT

DDR3 SDRAMs

VREFDQ

Clock, control, command, and address line terminations:

CKE0, A[14:0],

RAS#, CAS#, WE#,

ODT0, BA[2:0], S0#

DDR3

SDRAM

VTT

CK#

DDR3

SDRAM

VDD

VSS

Temperature

sensor/

SPD EEPROM

A1 A2

SA0 SA1

SDA

SCL

EVT

EVENT#

SA2

Note: 1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor

that is tied to ground. It is used for the calibration of the component’s ODT and output

driver.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Functional Block Diagram

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General Description

DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod-

ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod-

ules use DDR architecture to achieve high-speed operation. DDR3 architecture is

essentially an 8n-prefetch architecture with an interface designed to transfer two data

words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM

module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the

internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-

fers at the I/O pins.

DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK

and CK# to capture commands, addresses, and control signals. Differential clocks and

data strobes ensure exceptional noise immunity for these signals and provide precise

crossing points to capture input signals.

Fly-By Topology

DDR3 modules use faster clock speeds than earlier DDR technologies, making signal

quality more important than ever. For improved signal quality, the clock, control, com-

mand, and address buses have been routed in a fly-by topology, where each clock,

control, command, and address pin on each DRAM is connected to a single trace and

terminated (rather than a tree structure, where the termination is off the module near

the connector). Inherent to fly-by topology, the timing skew between the clock and DQS

signals can be easily accounted for by using the write-leveling feature of DDR3.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

General Description

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Electrical Specifications

Stresses greater than those listed may cause permanent damage to the module. This is a

stress rating only, and functional operation of the module at these or any other condi-

tions outside those indicated in each device’s data sheet is not implied. Exposure to

absolute maximum rating conditions for extended periods may adversely affect reliability.

Table 7: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD VDD supply voltage relative to VSS –0.4 +1.975 V

VIN, VOUT Voltage on any pin relative to VSS –0.4 +1.975 V

Table 8: Operating Conditions

Symbol Parameter Min Nom Max Units Notes

VDD VDD supply voltage 1.425 1.5.64 1.575 V

VREFCA(DC) Input reference voltage command/address bus 0.49 × VDD 0.5 × VDD 0.51 × VDD V

VREFDQ(DC) I/O reference voltage DQ bus 0.49 × VDD 0.5 × VDD 0.51 × VDD V

IVTT Termination reference current from VTT –600 –+600 mA

VTT Termination reference voltage (DC) –

command/address bus

0.49 × VDD -

20mV

0.5 × VDD 0.51 × VDD +

20mV

V 1

IIInput leakage current;

Any input 0V ≤ VIN ≤ VDD; VREF in-

put 0V ≤ VIN ≤ 0.95V (All other pins

not under test = 0V)

Address

inputs,

RAS#,CAS#,

WE#, S#,

CKE, ODT,

BA, CK, CK#

–18 0 +18 µA

DM –2 0 +2

IOZ Output leakage current;

0V ≤ VOUT ≤ VDD; DQ and ODT are

disabled; ODT is HIGH

DQ, DQS,

DQS#

–5 0 +5 µA

IVREF VREF supply leakage current;

VREFDQ = VDD/2 or VREFCA = VDD/2

(All other pins not under test = 0V)

–9 0 +9 µA

TAModule ambient operating temperature 0 –+70 °C 2, 3

TCDDR3 SDRAM component case operating temper-

ature

0–+95 °C 2, 3, 4

Notes: 1. VTT termination voltage in excess of the stated limit will adversely affect the command

and address signals’ voltage margin and will reduce timing margins.

2. TA and TC are simultaneous requirements.

3. For further information, refer to technical note TN-00-08: “Thermal Applications,”

available on Micron’s Web site.

4. The refresh rate is required to double when 85°C < TC ≤ 95°C.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Electrical Specifications

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DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR3 component data sheets.

Component specifications are available on Micron’s Web site. Module speed grades cor-

relate with component speed grades, as shown below.

Table 9: Module and Component Speed Grades

DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades

Module Speed Grade Component Speed Grade

-1G6 -125

-1G4 -15E

-1G1 -187E

-1G0 -187

-80C -25E

-80B -25

Design Considerations

Simulations

Micron memory modules are designed to optimize signal integrity through carefully de-

signed terminations, controlled board impedances, routing topologies, trace length

matching, and decoupling. However, good signal integrity starts at the system level. Mi-

cron encourages designers to simulate the signal characteristics of the system’s memo-

ry bus to ensure adequate signal integrity of the entire memory system.

Power

Operating voltages are specified at the DRAM, not at the edge connector of the module.

Designers must account for any system voltage drops at anticipated power levels to en-

sure the required supply voltage is maintained.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Electrical Specifications

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IDD Specifications

Table 10: DDR3 IDD Specifications and Conditions – 2GB

Values are for the MT41J256M8 DDR3 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8)

component data sheet, Die Rev D

Parameter Symbol 1600 1333 1066 Units

Operating current 0: One bank ACTIVATE-to-PRECHARGE IDD0 TBD 810 720 mA

Operating current 1: One bank ACTIVATE-to-READ-to-PRE-

CHARGE

IDD1 TBD 1035 900 mA

Precharge power-down current: Slow exit IDD2P0 TBD 108 108 mA

Precharge power-down current: Fast exit IDD2P1 TBD 315 270 mA

Precharge quiet standby current IDD2Q TBD 585 495 mA

Precharge standby current IDD2N TBD 585 495 mA

Precharge standby ODT current IDD2NT TBD 765 675 mA

Active power-down current IDD3P TBD 405 360 mA

Active standby current IDD3N TBD 675 540 mA

Burst read operating current IDD4R TBD 1800 1440 mA

Burst write operating current IDD4W TBD 2160 1800 mA

Refresh current IDD5B TBD 2295 2205 mA

Self refresh temperature current: MAX TC = 85°C IDD6 TBD 81 81 mA

Self refresh temperature current (SRT-enabled): MAX TC =

95°C

IDD6ET TBD 108 108 mA

All banks interleaved read current IDD7 TBD 3285 2880 mA

Reset current IDD8 TBD 126 126 mA

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Electrical Specifications

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Temperature Sensor with Serial Presence-Detect EEPROM

The temperature from the integrated thermal sensor is monitored and converts into a

digital word via the I2C bus. System designers can use the user-programmable registers

to create a custom temperature-sensing solution based on system requirements. Pro-

gramming and configuration details comply with JEDEC standard No. 21-C page 4.7-1,

“Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor.”

Serial Presence-Detect EEPROM Operation

DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a

256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JE-

DEC standard JC-45, “Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM

Modules.” These bytes identify module-specific timing parameters, configuration infor-

mation, and physical attributes. User-specific information can be written into the

remaining 128 bytes of storage. READ/WRITE operations between the system (master)

and the EEPROM (slave) device occur via an I2C bus. Write protect (WP) is connected to

VSS, permanently disabling hardware write protect. For further information please refer

to Micron technical note TN-04-42, "Memory Module Serial Presence-Detect."

Table 11: Temperature Sensor with Serial Presence-Detect EEPROM Operating Conditions

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD +3.0 +3.6 V

Supply current: VDD = 3.3V IDD –+2.0 mA

Input high voltage: Logic 1; SCL, SDA VIH +1.45 VDDSPD + 1 V

Input low voltage: Logic 0; SCL, SDA VIL –+0.55 V

Output low voltage: IOUT = 2.1mA VOL –+0.4 V

Input current IIN –5.0 +5.0 µA

Temperature sensing range ––40 +125 °C

Temperature sensor accuracy (initial release) ––2.0 +2.0 °C

Temperature sensor accuracy (class B) ––1.0 +1.0 °C

Table 12: Sensor and EEPROM Serial Interface Timing

Parameter/Condition Symbol Min Max Units

Time bus must be free before a new transition can

start

tBUF 4.7 –µs

SDA fall time tF 20 300 ns

SDA rise time tR–1,000 ns

Data hold time tHD:DAT 200 900 ns

Start condition hold time tH:STA 4.0 –µs

Clock HIGH period tHIGH 4.0 50 µs

Clock LOW period tLOW 4.7 –µs

SCL clock frequency tSCL 10 100 kHz

Data setup time tSU:DAT 250 –ns

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

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Table 12: Sensor and EEPROM Serial Interface Timing (Continued)

Parameter/Condition Symbol Min Max Units

Start condition setup time tSU:STA 4.7 –µs

Stop condition setup time tSU:STO 4.0 –µs

EVENT# Pin

The temperature sensor also adds the EVENT# pin (open drain). Not used by the SPD

EEPROM, EVENT# is a temperature sensor output used to flag critical events that can

be set up in the sensor’s configuration register.

EVENT# has three defined modes of operation: interrupt mode, compare mode, and

critical temperature mode. The open-drain output of EVENT# under the three separate

operating modes is illustrated below. Event thresholds are programmed in the 0x01 reg-

ister using a hysteresis. The alarm window provides a comparison window, with upper

and lower limits set in the alarm upper boundary register and the alarm lower boun-

dary register, respectively. When the alarm window is enabled, EVENT# will trigger

whenever the temperature is outside the MIN or MAX values set by the user.

The interrupt mode enables software to reset EVENT# after a critical temperature thresh-

old has been detected. Threshold points are set in the configuration register by the user.

This mode triggers the critical temperature limit and both the MIN and MAX of the tem-

perature window.

The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by

the user and only returns to the logic HIGH state when the temperature falls below the

programmed thresholds.

Critical temperature mode triggers EVENT# only when the temperature has exceeded

the programmed critical trip point. When the critical trip point has been reached, the

temperature sensor goes into comparator mode, and the critical EVENT# cannot be

cleared through software.

SM Bus Slave Subaddress Decoding

The temperature sensor’s physical address differs from the SPD EEPROM’s physical ad-

dress: binary 0011 for A0, A1, A2, and RW#, where A2, A1, and A0 are the three slave

subaddress pins and the RW# bit is the READ/WRITE flag.

If the slave base address is fixed for the temperature sensor/SPD EEPROM, then the

pins set the subaddress bits of the slave address, enabling the devices to be located any-

where within the eight slave address locations. For example, they could be set from 30h

to 3Eh.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

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Figure 3: EVENT# Pin Functionality

Time

Temperature

Critical

Alarm window (MAX)

Alarm window (MIN)

EVENT#

interrupt mode

EVENT#

comparator mode

EVENT#

critical temperature only mode

Clears event

Hysteresis affects

these trip points

Table 13: Temperature Sensor Registers

Name Address Power-on Default

Pointer register Not applicable Undefined

Capability register 0x00 0x0001

Configuration register 0x01 0x0000

Alarm temperature upper boundary register 0x02 0x0000

Alarm temperature lower boundary register 0x03 0x0000

Critical temperature register 0x04 0x0000

Temperature register 0x05 Undefined

Pointer Register

The pointer register selects which of the 16-bit registers is being accessed in subsequent

READ and WRITE operations. This register is a write-only register.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

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Table 14: Pointer Register Bits 0–7

Bit

76543210

0 0 0 0 Register

select

Table 15: Pointer Register Bits 0–2 Descriptions

Bit

Register2 1 0

0 0 0 Capability register

0 0 1 Configuration register

0 1 0 Alarm temperature upper boundary register

0 1 1 Alarm temperature lower boundary register

1 0 0 Critical temperature register

1 0 1 Temperature register

Capability Register

The capability register indicates the features and functionality supported by the temper-

ature sensor. This register is a read-only register.

Table 16: Capability Register (Address: 0x00)

Bit

15 14 13 12 11 10 9 8

RFU RFU RFU RFU RFU RFU RFU RFU

Bit

76543210

RFU RFU RFU Temperature resolution Wider range Precision Has alarm

and critical

temperature

Table 17: Capability Register Bit Description

Bit Description

0 Basic capability

1: Has alarm and critical trip point capabilities

1 Accuracy

0: ±2°C over the active range and ±3°C over the monitor range

1: ±1°C over the active range and ±2°C over the monitor range

2 Wider range

0: Temperatures lower than 0°C are clamped to a binary value of 0

1: Temperatures below 0°C can be read

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Table 17: Capability Register Bit Description (Continued)

Bit Description

4:3 Temperature resolution

00: 0.5°C LSB

01: 0.25°C LSB

10: 0.125°C LSB

11: 0.0625°C LSB

15:5 0: Must be set to zero

Configuration Register

Table 18: Configuration Register (Address: 0x01)

Bit

15 14 13 12 11 10 9 8

RFU RFU RFU RFU RFU Hysteresis Shutdown

mode

Bit

76543210

Critical lock

bit

Alarm lock bit Clear event Event output

status

Event output

control

Critical event

only

Event polarity Event mode

Table 19: Configuration Register Bit Descriptions

Bit Description Notes

0 Event mode

0: Comparator mode

1: Interrupt mode

Event mode cannot be changed if either of the lock

bits is set.

1 EVENT# polarity

0: Active LOW

1: Active HIGH

EVENT# polarity cannot be changed if either of the

lock bits is set.

2 Critical event only

0: EVENT# trips on alarm or critical temperature event

1: EVENT# trips only if critical temperature is reached

3 Event output control

0: Event output disabled

1: Event output enabled

4 Event status

0: EVENT# has not been asserted by this device

1: EVENT# is being asserted due to an alarm window

or critical temperature condition

This is a read-only field in the register. The event caus-

ing the event can be determined from the read tem-

perature register.

5 Clear event

0: No effect

1: Clears the event when the temperature sensor is in

the interrupt mode

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Table 19: Configuration Register Bit Descriptions (Continued)

Bit Description Notes

6 Alarm window lock bit

0: Alarm trips are not locked and can be changed

1: Alarm trips are locked and cannot be changed

7 Critical trip lock bit

0: Critical trip is not locked and can be changed

1: Critical trip is locked and cannot be changed

8 Shutdown mode

0: Enabled

1: Shutdown

The shutdown mode is a power-saving mode that dis-

ables the temperature sensor.

10:9 Hysteresis enable

00: Disable

01: Enable at 1.5°C

10: Enable at 3°C

11: Enable at 6°C

When enabled, a hysteresis is applied to temperature

movement around the trip points (see Figure 4

(page 19)). As an example, if the hysteresis register

is enabled to a delta of 6°C, the preset trip points will

toggle when the temperature reaches the program-

med value. These values will reset when the tempera-

ture drops below the trip points minus the set

hysteresis level. In this case, this would be critical tem-

perature minus 6°C.

The hysteresis is applied to both the above alarm win-

dow and the below alarm window bits found in the

read-only temperature register (see Table 20

(page 19)). EVENT# is also affected by this register.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

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Figure 4: Hysteresis Applied to Temperature Around Trip Points

TH1

TL2

TH - Hyst3

TL - Hyst

Below window bit

Above window bit

Notes: 1. TH is the value set in the alarm temperature upper boundary trip register.

2. TL is the value set in the alarm temperature lower boundary trip register.

3. Hyst is the value set in the hysteresis bits of the configuration register.

Table 20: Hysteresis Applied to Alarm Window Bits in the Temperature Register

Condition

Below Alarm Window Bit Above Alarm Window Bit

Temperature

Gradient Critical Temperature

Temperature

Gradient Critical Temperature

Sets Falling TL - Hyst Rising TH

Clears Rising TLFalling TH - Hyst

Temperature Format

The temperature trip point registers and temperature readout register use a 2’s comple-

ment format to enable negative numbers. The least significant bit (LSB) is equal to

0.0625°C or 0.25°C, depending on which register is referenced. For example, assuming

an LSB of 0.0625°C:

•A value of 0x018C would equal 24.75°C

•A value of 0x06C0 would equal 108°C

•A value of 0x1E74 would equal –24.75°C

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

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Temperature Trip Point Registers

The upper and lower temperature boundary registers are used to set the maximum and

minimum values of the alarm window. LSB for these registers is 0.25°C. All RFU bits in

the register will always report zero.

Table 21: Alarm Temperature Lower Boundary Register (Address: 0x02)

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 MSB LSB RFU RFU

Alarm window upper boundary temperature

Table 22: Alarm Temperature Lower Boundary Register (Address: 0x03)

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 MSB LSB RFU RFU

Alarm window lower boundary temperature

Critical Temperature Register

The critical temperature register is used to set the maximum temperature above the

alarm window. The LSB for this register is 0.25°C. All RFU bits in the register will always

report zero.

Table 23: Critical Temperature Register (Address: 0x04)

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 MSB LSB RFU RFU

Critical temperature trip point

Temperature Register

The temperature register is a read-only register that provides the current temperature

detected by the temperature sensor. The LSB for this register is 0.0625°C with a resolu-

tion of 0.0625°C. The most significant bit (MSB) is 128°C in the readout section of this

The upper three bits of the register are used to monitor the trip points that are set in the

previous three registers.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

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Table 24: Temperature Register (Address: 0x05)

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Above

critical

trip

Above

alarm

window

Below

alarm

window

MSB LSB

Temperature

Table 25: Temperature Register Bit Descriptions

Bit Description

13 Below alarm window

0: Temperature is equal to or above the lower boundary

1: Temperature is below alarm window

14 Above alarm window

0: Temperature is equal to or below the upper boundary

1: Temperature is above alarm window

15 Above critical trip point

0: Temperature is below critical trip point

1: Temperature is above critical trip point

Serial Presence-Detect Data

For the latest serial presence-detect data, refer to Micron's SPD page:

www.micron.com/SPD.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

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Module Dimensions

Figure 5: 244-Pin DDR3 VLP MiniUDIMM

82.15 (3.234)

81.85 (3.222)

Front view

17.91 (0.705)

17.89 (0.704)

10.0 (0.394)

TYP

1.0 (0.039)

TYP

45° X4

1.0 (0.039) R

0.5 (0.02) R

1.8 (0.071) D

6.0 (0.236)

TYP

2.0 (0.079)

TYP

78.0 (3.071)

TYP

0.6 (0.024)

TYP

0.45 (0.018)

TYP

Pin 1 Pin 122

43.9 (1.73)

TYP

Back view

3.3 (0.13)

TYP

3.6 (0.142) TYP

33.6 (1.323)

TYP

38.4 (1.512)

TYP

3.2 (0.126)

TYP

3.80 (0.15)

MAX

1.1 (0.043)

0.9 (0.035)

Pin 244 Pin 123

U1 U2

U4 U5

U6 U7 U8 U9 U10

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM VLP Mini-UDIMM

Module Dimensions

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