128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
CY7C1338
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Ma y 5, 2000
Features
• Supports 117-MHz microprocessor cache systems with
zero wait states
• 128K by 32 com m on I/ O
• Fast clock-to-output times
—7.5 ns (117-MHz version)
• Two-bit wraparound counter supporting eit her in ter-
leaved or linear burst seque nce
• Separate processor and controller address strobes pro-
vide direct interface with the processor and ext ernal
cache controller
• Synchronous self-timed write
• Asy nchronous output enab le
•3.3V I/Os
• JEDEC-standard pinout
• 100-pi n TQFP packaging
• ZZ “sleep” mode
Functional Descri pti on
The CY7C1338 is a 3.3V, 128K by 32 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bi t on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access .
The CY7C1338 allows both interleaved and linear burst se-
quences, sele cted by t he M O DE input pin. A HI GH s elects an
interlea ved bu rst sequ ence, whil e a LOW sele cts a linear burs t
sequence. Burst acces ses can be initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the address advancement (ADV) input.
A synchr onous self -timed write mechanism is provi ded to si m-
plify the write interface. A synchronous chip enable input and
an asynchr onous output enable input provide easy control for
bank selection and output three-state control.
Selection Guide
7C1338-117 7C1338-100 7C1338-90 7C1338-50
Maximum Access Time (ns) 7.5 8.0 8.5 11.0
Maximum Operatin g Current (mA) 350 325 300 250
Maxim um Standby Curr ent (mA) 2.0 2.0 2.0 2.0
Intel and Pentium are registered trademarks of Intel Corporation.
CLK
ADV
ADSC
A[16:0]
GW
BWE
BW0
CE1
CE3
CE2
OE
ZZ
BURST
COUNTER
DQ[31:24]
BYTEWRITE
REGISTERS
ADDRESS
REGISTER
DQ
INPUT
REGISTERS
128K X 32
MEMORY
ARRAY
CLK
Q0
Q1
Q
D
CE
CE
CLR
SLEEP
CONTROL
DQ[23:16]
BYTEWRITE
REGISTERS
D Q
DQ
DQ[15:8]
BYTEWRITE
REGISTERS
DQ[7:0]
BYTEWRITE
REGISTERS
D Q
ENABLE
REGISTER
DQ
CE
CLK
32 32
17
15
15
17
(A0,A1)2
MODE
ADSP
Logic Block Diagram
DQ[31:0]
BW1
BW2
BW3
CY7C1338
2
Pin Configura tion
100-Lead TQFP
A5
A4
A3
A2
A1
A0
DNU
DNU
VSS
VDD
DNU
A10
A11
A12
A13
A14
A16
NC
DQ14
VDDQ
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
VDDQ
DQ9
DQ8
VSS
NC
VDD
DQ7
DQ6
VDDQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VDDQ
DQ1
DQ0
NC
NC
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
NC
VDD
NC
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
NC
A6
A7
CE1
CE2
BW3
BW2
BW1
BW0
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSP
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
BYTE0
BYTE2
A15
ADV
ADSC
ZZ
MODE
DNU
CY7C1338
BYTE1
DQ15
BYTE3
CY7C1338
3
Pin Des criptions
Pin Number Name I/O Description
85 ADSC Input-
Synchronous Address Strobe from Controller, samp led on the risin g edge of CLK. When asserted
LO W, A[16:0] is capture d in the address registers. A[1:0] are also loaded into the burs t
counter. When ADSP and ADSC are both asser ted, onl y ADSP is recognized.
84 ADSP Input-
Synchronous Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
LO W, A[16:0] is capture d in the address registers. A[1:0] are also loaded into the burs t
counter. When ADSP and ADSC ar e bot h asserted, onl y ADSP is r eco gnize d. ASDP
is i g no red w hen C E1 is deasserted HIGH.
36, 37 A[1:0] Input-
Synchronous A1, A0 Address Inputs . These inputs feed the on-chi p burst counter as the LSBs as
well as being used to access a par ticular memory location in the memory array.
49−44,
81–82,
99–100,
32–35
A[16:2] Input-
Synchronous Address Input s used in conj unction with A[1:0] to select one of the 64K address loca-
tions. Sampled at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled active,
and ADSP or ADSC is active LOW.
96–93 BW[3:0] Input-
Synchronous Byte Write Selec t Inputs, active LO W. Qualifi ed with BWE to conduct by te wri tes.
Sampled on the rising edge. BW0 controls DQ[7:0] an d DP0, BW1 controls DQ[15:8] and
DP1, BW2 controls DQ[23:16] and DP2, and BW3 controls DQ[31:24] and DP3. See Write
Cycle Descriptions t able for further details.
83 ADV Input-
Synchronous Adva nce Input used to adv ance the on-chi p address count er. When LO W the internal
bur st counter is adv a nced in a b urst s equen ce. Th e b urst seque nce is s elect ed using
the MODE input.
87 BWE Input-
Synchronous Byte Wri te Enab le I nput , activ e LO W. Samp led on t he ris ing edge of CLK. This si gn al
mus t be asserted LOW to conduct a byte write.
88 GW Input-
Synchronous Global Write I nput, active LOW. Sam pled on the risin g edge of CLK. This signal is
used to conduct a global write, independent of the stat e of BWE and BW[3:0]. Global
writes override byte writes.
89 CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device.
98 CE1Input-
Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE2 and CE3 to sel ect/desel ect the device . CE1 gates ADSP.
97 CE2Input-
Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in con-
junction with CE1 and CE3 to select/deselect the device.
92 CE3Input-
Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE1 and CE2 to select/deselect the d evice.
86 OE Input-
Asynchronous Output Enable, asynchronous input, active LOW . Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deas serted HIGH, I/ O pins are
three-stated, and act as input data pins.
64 ZZ Input-
Asynchronous Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power
standby mode in which all ot her inpu ts are i gnored, but the data in the memory array
is maint ained. Lea ving ZZ floating or NC will default the de vice into an acti ve stat e.
ZZ pin has an internal pull-down.
31 MODE -Mode Input. Sele cts the burst order of t he device. Tied HIGH sel ects the in terleaved
burst order. Pulled LOW selects the linear burst order. When left floating or NC, de-
faults to interl eaved burst order. Mode pin has an internal pull-up.
29–28,
25–22,
19–18,
13–12, 9–6,
3–2, 79–78,
75–72,
69–68,
63–62,
59–56,
53–52
DQ[31:0] I/O-
Synchronous Bidi rect ional Data I/O lines. As inpu ts, the y feed into an on-chip data regi ster that is
trigg ered b y the rising edge of CLK. As output s, t hey del iv er the dat a conta ined i n the
memory location speci fi ed by A[16:0] during the previ ous clock rise of the r ead cycle.
The direction of the pins is controlled by OE in conj unction with the internal contr ol
logic. When OE is asserted LO W, the pins behave as outputs. When HIGH, DQ[31:0]
and DP[3:0] are placed in a three-state condition. The outputs are automatically
three-stated when a WRITE cycle is detected.
15, 41, 65,
91 VDD P ower Suppl y Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
CY7C1338
4
Functional Overview
All synchrono us inp uts pass th rough inp ut regi sters con tr olle d
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 7.5 ns (11 7-MHz device).
The CY7C133 8 supports secondary cache in systems utilizin g
either a linear or interleaved burst sequence. The interleaved
burst ord er supports Pentium and i486 processors. The li near
burst sequence is suited for processors that utilize a linear
burst sequence. The burst order i s user select able, and is de-
termined by sampl ing the MODE input. Accesses can be ini ti -
ated with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is contr olled by the ADV input. A
two- bit on-ch ip wrap around burs t counter ca ptures the first ad-
dress in a burst sequence and automatically increments the
address for the r e st of the bur s t a cce ss .
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[3:0]) inputs. A Global Write
Enable (GW) overrides all by te write inpu ts and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed wri te ci rcuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchr onous Output Enable (OE) provide for easy bank se-
lection and output three-state control. ADSP is ignor ed if CE1
is HIGH.
Single Read Accesses
A single read access is i nitiated when the followi ng conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all as-
serted act ive, and (2) ADSP or ADSC is asserted LO W (if the
access is initiated by ADSC, the write inp uts must be de assert-
ed during this first cycle). The address presented to the ad-
dress input s is latched into the address register and the burst
count er/con trol logic and prese nted to th e memory core. If the
OE input is asserted LO W , the reque sted data will be a vailable
at the data outputs a maximum to tCDV after clock rise. ADSP
is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses pre-
sented are loaded into the address register and the burst
counter /cont rol l ogic and deliv e red to the RAM core . The writ e
inputs (GW, BWE, and BW[3:0]) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropr iate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW0 controls DQ[7:0], BW1 controls
DQ[15:8], BW 2 controls DQ[23:16], and BW3 controls DQ[31:24].
All I/Os are three-stated during a byte write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be three-stated prior to the
presentation of data to DQ[31:0]. As a safety precaution, the
data lines are three-stated once a wr ite cycle is detected, re-
gardless of the state of OE.
Single Wri te Accesses Initiat ed by AD SC
This write ac cess is init iated when the follow ing con diti ons are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the wri te input signals (GW, BWE, and BW[3:0])
indic ate a write access. ADSC is ignored if ADSP is active LOW .
The addres ses p resent ed ar e loaded into t he addres s r egiste r
and the burst count er/control l ogic and delivered to the RAM
core. The i nformation presented to DQ[31:0] will be written into
the speci fied address location. Byte writes ar e allo wed. During
b y te writes , BW0 cont rol s DQ[7:0], BW1 controls DQ [15:8], B W2
controls DQ[23:16], and BWS3 controls DQ[31:24]. All I/Os are
three- stat ed when a wri te is detect ed, e v en a byt e write . Si nce
this is a c ommon I/O de vice, the asyn chronous OE input signal
must be dea sserted an d the I/ Os must be three -stat ed prior to
the pr esentation of data to DQ[31:0]. As a saf ety preca ution, t he
data lines are three-stated once a wr ite cycle is detected, re-
gardless of the state of OE.
Burst Sequences
The CY7C1338 provides an on-chip 2-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0],
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LO W on MODE wi ll se lect a line ar bu rst se quenc e. A HI GH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default t o a interleaved
burst sequence.
17, 40, 67,
90 VSS Ground Ground for the I/O circuitry of the device. Should be connected to groun d of the
system.
5, 10, 21,
26, 55, 60,
71, 76
VSSQ Ground Ground for the device . Should be connect ed to ground of the system.
4, 11, 20,
27, 54, 61,
70, 77
VDDQ I/O Power
Supply Power supply for the I/O ci rcuitry. Should be connected to a 3.3V power supply.
1,14, 16, 30,
50–51, 66,
80
NC -No connects.
38, 39, 42,
43 DNU -Do not use pins. Should be left unconnect ed or tied LOW.
Pin Des criptions (continued)
Pin Number Name I/O Description
CY7C1338
5
Sleep Mode
The ZZ input pin is an asynchronous i nput. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Ac-
cesses pending when enteri ng the “sleep” mode are not con-
sidered valid nor is the completion of the operation guaran-
teed. The device must be deselected prior to entering the
“sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LO W. Leaving ZZ unconnected defaults the device int o an ac-
tive state.
Table 1. Counter Implementation for the Intel®
Pentium®/80486 Processor’s Sequence
First
Address Second
Address Third
Address Fourth
Address
AX + 1 , AxAX + 1, AxAX + 1 , AxAX + 1, Ax
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Table 2. Count er Implementation for a Linear Sequence
First
Address Second
Address Third
Address Fourth
Address
AX + 1 , AxAX + 1, AxAX + 1, AxAX + 1, Ax
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Chara cteristics
Parameter Description Test Conditions Min. Max. Unit
ICCZZ Snooze mode
standby current ZZ > VDD − 0.2V 10 mA
tZZS Device operation to
ZZ ZZ > VDD − 0.2V 2tCYC ns
tZZREC ZZ re c overy time ZZ < 0.2 V 2t CYC ns
CY7C1338
6
Cycle Description Table[1, 2, 3]
Cycle Description ADD
Used CE1CE3CE2ZZ ADSP ADSC ADV WE OE CLK DQ
Deselected Cyc le, P ower-down None H X X L X L X X X L-H High-Z
Deselected Cyc le, P ower-down None L X L L L X X X X L-H High-Z
Deselected Cyc le, P ower-down None L H X L L X X X X L-H High-Z
Deselected Cyc le, P ower-down None L X L L H L X X X L-H High-Z
Deselected Cyc le, P ower-down None X X X L H L X X X L-H High-Z
Snooze M ode, Power -down None X X X H X X X X X X High-Z
Read Cycle, Begin Burst External L L H L L X X X L L-H Q
Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z
Write Cycl e, Begin Burst External L L H L H L X L X L-H D
Read Cycle, Begin Burst External L L H L H L X H L L-H Q
Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z
Write Cycl e, Continue Burst Next X X X L H H L L X L-H D
Write Cycl e, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Curren t X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Curren t X X X L H H H H H L-H High-Z
Read Cycle, Suspend Burst Curren t H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Curren t H X X L X H H H H L-H High-Z
Write Cycl e, Suspend Burst Curren t X X X L H H H L X L-H D
Write Cycl e, Suspend Burst Curren t H X X L X H H L X L-H D
Notes:
1. X=”Don't Care,” 1=Logic HIGH, 0=Logic LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a “Don't Care” for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.
CY7C1338
7
Maximum Ratings
(Above which the useful l ife may be impaired. For user guide-
li nes, not tes ted.)
Storage Temperature ..... .................... ..........–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Supply Volt age on VDD Relativ e to GND..... ....... ....–0.5V to +4.6V
DC Voltag e Appli ed to Output s
in High Z State[5]...............................................–0.5V to V DD + 0.5V
DC Input Vol tage[5]........................................... –0.5V to VDD + 0.5V
Cu r re n t in to Outp ut s (L OW )... ............ ............ .......... .... 20 mA
Static Discharge Voltage..... ...... .. ......... ...... .. ......... ... >2001V
(per MIL- STD-883, Method 3015 )
Latch-Up Curr ent... .. ....... ...... .. .................... ....... .. .. . >200 mA
Notes:
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
6. TA i s the case temperatu re .
Wr i te C ycl e D escr i p ti o n s[1, 2, 3, 4]
Function GW BWE BW3BW2BW1BW0
Read 11XXXX
Read 101111
Write Byte 0 - DQ[7:0] 101110
Write Byte 1 - DQ[15:8] 101101
Write Bytes 1, 0 101100
Write Byte 2 - DQ[23:16] 101011
Write Bytes 2, 0 101010
Write Bytes 2, 1 101001
Write Bytes 2, 1, 0 101000
Write Byte 3 - DQ[31:24] 100111
Write Bytes 3, 0 100110
Write Bytes 3, 1 100101
Write Bytes 3, 1, 0 100100
Write Bytes 3, 2 100011
Write Bytes 3, 2, 0 100010
Write Bytes 3, 2, 1 100001
Write All Bytes 100000
Write All Bytes 0 XXXXX
Operating Range
Range Ambient
Temperature[6] VDD VDDQ
Com’l 0°C to +70°C3. 135V to 3.6V 2.375V to VDD
CY7C1338
8
Electrical Characteristics Ov er the Operating Range
P arameter Des cri ption Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V
VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA 2.0 V
VOL Output LOW Vo lt age VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V
VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA 0.7 V
VIH Input HIGH Vo ltage VDDQ = 3.3V 2.0 VDD +
0.3V V
VIH Input HIGH Vo ltage VDDQ = 2.5V 1.7 VDD +
0.3V V
VIL Input LOW Voltage[5] VDDQ = 3.3V –0.3 0.8 V
VIL Input LOW Voltage[5] VDDQ = 2.5V –0.3 0.7 V
IXInput Load C urrent
(except ZZ and MODE) GND ≤ VI ≤ VDDQ −11µA
Input Current of MODE Input = VSS –30 µA
Input = VDDQ 5µA
Input Current of ZZ Input = VSS –5µA
Input = VDDQ 30 µA
IOZ Output Leakage Current GND ≤ VI ≤ V DD, Output Disabled –55µA
IOS Output Short Circuit Current[7] VDD = Max., VOUT = GND –300 mA
IDD VDD Operating Supply Current VDD = Ma x., IOU T = 0 mA,
f = fMAX = 1/ tCYC 8.5-ns cycle, 117 MHz 350 mA
10-ns cycle, 100 MHz 32 5 mA
11-ns cycle, 90 MHz 300 mA
20-ns cycle, 50 MHz 250 mA
ISB1 Automatic CE Power-Down
Current—TTL Inputs Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL,
f = fMAX = 1/tCYC,
inputs swi tching
8.5-ns cycle, 117 MHz 125 mA
10-ns cycle, 100 MHz 11 0 mA
11-ns cycle, 90 MHz 100 mA
20-ns cycle, 50 MHz 90 mA
ISB2 Automatic CE Power-Down
Current — CMOS Inputs Max. VDD, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0, inputs static
All speeds 10 mA
ISB3 Automatic CE Power-Down
Current—CMOS Input s Ma x. VDD, Device Deselected,
VIN ≥ VDDQ– 0.3V or VIN ≤ 0.3V,
f = fMAX, inputs switching
8.5-ns cycle, 117 MHz 95 mA
10-ns cycle, 100 MHz 85 mA
11-ns cycle, 90 MHz 75 mA
20-ns cycle, 50 MHz 65 mA
ISB4 Automatic CE Power-Down Current
— CMOS Inputs Max. VDD, Device Deselected,
VIN ≥ V DD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
All speeds 30 mA
Note:
7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C1338
9
Capacitance[8]
Parameter Descripti on Test Condi tions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 5.0V 4pF
CI/O I/O Capacitance 4 pF
AC Test Loads and Waveforms
3.0V
GND
90%
10% 90%
10%
≤3.0 ns ≤3.0 ns
OUTPUT
R1=317Ω
R2=351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
ALL INPUT PULSES
OUTPUT
RL=50Ω
Z0=50Ω
VL=1.5V
3.3V
Switching Characteristics Over the Operating Range[9]
Parameter Description
-117 -100 -90 -50
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC Clo ck Cycle Ti m e 8. 5 10 11 20 ns
tCH Clock HIGH 3.0 4.0 4.5 4.5 ns
tCL Clock LOW 3.0 4.0 4.5 4.5 ns
tAS Address Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tAH Address Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tCDV Data Output Valid After CLK Rise 7.5 8.0 8.5 11. 0 ns
tDOH Data Output Hold After CLK Rise 2 .0 2.0 2.0 2.0 ns
tADS ADSP, ADSC Set-Up Bef ore CLK Rise 2.0 2.0 2.0 2.0 ns
tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 0.5 n s
tWES BWS[1:0], GW, BWE Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tWEH BWS[1:0], GW, BWE Hold Aft er CLK Rise 0.5 0.5 0.5 0.5 n s
tADVS ADV Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tADVH ADV Hold After CLK Ri s e 0 .5 0 .5 0.5 0.5 n s
tDS Data Input Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tCES Chip Enable Set-Up 2.0 2.0 2.0 2.0 ns
tCEH Ch ip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tCHZ Clock t o H igh-Z [10, 11] 3.5 3.5 3.5 3.5 ns
tCLZ Clock to Low-Z[10, 11] 0000ns
tEOHZ OE HIGH to Output High- Z[10, 12] 3.5 3.5 3.5 3.5 ns
tEOLZ OE LOW to Output Low-Z[10, 12] 0000ns
tEOV OE LOW to Output Valid 3.5 3. 5 3.5 3.5 ns
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
9. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capac itance. S hown i n (a) and (b) of A C test loads.
10. tCHZ, tCLZ, tEOHZ, and tEOLZ are s pecifi ed with a load capacit ance of 5 pF as i n part (b) of A C Test Loads. Transiti on is meas ured ± 200 mV from steady -state voltage .
11. At any given voltage and temperature, tCHZ (max) is l ess than tCLZ (min).
12. This parameter is sampled and not 100% tested.
CY7C1338
10
Timing Diagra m s
Write Cycle Timing[13, 14]
Notes:
13. WE is the combination of BWE, BW[3:0] and GW to define a write cycle (see Write Cycle Descriptions table).
14. WDx stands for Write Data to Address X.
ADSP
CLK
ADSC
ADV
ADD
CE
1
OE
GW
WE
CE
2
CE
3
1a
Data-
In
tCYC
tCH
tCL
tADS
tADH
tADS tADH
tADVS tADVH
WD1 WD2 WD3
tAH
tAS
tWS tWH tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
2b 3a
1a
Single Write Burst Write Unselected
ADSP ig nored with C E1 inactive
CE1 masks ADSP
= D ON ’T CARE
= UNDEFINED
Pipelined Write
2a 2c 2d
tDH
tDS
High-Z
High-Z
Unselected with CE2
ADV M u st Be Inactive for ADSP Write
ADSC initiated write
CY7C1338
11
Read Cycle Timing[13, 15]
Note:
15. RDx stands for Read Data from Address X.
Timing Diagra m s (continued)
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
2a 2c
1a
Data Out
tCYC tCH
tCL
tADS tADH
tADS
tADH
tADVS
tADVH
RD1 RD2 RD3
tAH
tAS
tWS tWH
tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
tCDV
tEOV
2b 2c 2d 3a
1a
tOEHZ tDOH
tCLZ tCHZ
Singl e Read Burst Read Unselected
ADSP ignored with CE1 i nactive
Suspend Burst
CE1 masks ADSP
= DON’T CARE = UNDEFINED
Pipel ined Read
ADSC initiated read
Unselected with CE2
CY7C1338
12
Read/W rite Cycl e Timing
Timing Diagra m s (continued)
A
tAH
tAS
WE is the combination of BWE, BWS[1:0], and GW to define a write cycle (see Write Cycle Descriptions table).
tCLZ
tCHZ
CE is the combi nation of CE2 and CE3. All chip selects need to be active in order to select
the devic e. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Dat a-i n X,
tDOH
CLK
ADD
WE
CE1
Data
BCD
ADSP
ADSC
ADV
CE
OE
Q(A) Q(B) Q
(B+1) Q
(B+2) Q
(B+3) Q(B) D(C) D
(C+1) D
(C+2) D
(C+3) Q(D)
tCYC
tCH tCL
tADS tADH
tADS tADH
tADVH
tADVS
tCEH
tCEH
tCES
tCES
tWEH
tWES
tCDV
Dev ic e or igin ally
deselected
ADSP ignored
with CE1 HI GH
tEOHZ
Qx stands for Data-out X.
In/Out
CY7C1338
13
Timing Diagra m s (continued)
In/Out
A
tAS
= DON’T CARE = UNDEFINED
WE is th e combination of BWE, BW[1:0], and GW to defi ne a write cycle (see Writ e Cycle Descriptions tabl e).
tCLZ
tCHZ
CE is the co mb ination of CE2 and CE3. All chip sel ects need to be active in orde r to sel ect
the device. RAx stands for Read Address X, WAx st ands for Write Address X, Dx stands for Data-in X,
tDOH
CLK
ADD
WE
CE1
Data
B
ADSP
ADSC
ADV
CE
OE
Q(A) Q(B) Q(D) D(C)
D (E) D (F) D (G)
tCYC
tCH tCL
tADS tADH
tCEH
tCES
tWEH
tWES
tCDV
Pipeline Timing
Device originally
deselected
ADSP ignored
with CE1 HIGH
Qx stands for Data-out X.
CD
Q(C)
EFGH
D (H)
CY7C1338
14
Timing Diagra m s (continued)
OE
three-state
I/Os
tEOHZ tEOV
tEOLZ
OE Switchi ng Waveforms
CY7C1338
15
Note:
16. Device must be deselected when entering ZZ mode. See Cycle Description table for all possible signal conditions to deselect the device.
17. I/Os are in three-state when exiting ZZ sleep mode.
Timing Diagra m s (continued)
ADSP
CLK
ADSC
CE1
CE3
LOW
HIGH
ZZ tZZS
tZZREC
ICC ICC(active)
Three-state
I/Os
ZZ Mode Timing [16, 17]
CE2
ICCZZ
HIGH
CY7C1338
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so i ndemnifies Cypress Semiconductor agains t all charges.
Document #: 38-00722-B
Ordering Information
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
117 CY7C1338-117AC A1 01 100-Lead Thin Quad Fl at Pack Commercial
100 CY7C1338-100AC A1 01 100-Lead Thin Quad Fl at Pack
90 CY7C1338-90AC A101 100-Lead Thin Quad Fl at Pack
50 CY7C1338-50AC A101 100-Lead Thin Quad Fl at Pack
Package D i ag ra m
100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) A101
51-85050-A
