1
LTC1326/LTC1326-2.5
132625fc
TYPICAL APPLICATIO
U
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
Micropower Precision
Triple Supply Monitors
RST Output Voltage vs Supply Voltage (LTC1326-2.5)
Simultaneously Monitors Three Supplies
LTC1326: 5V, 3.3V and ADJ
LTC1326-2.5: 2.5V, 3.3V and ADJ
Guaranteed Threshold Accuracy: ±0.75%
Low Supply Current: 20µA
Internal Reset Time Delay: 200ms
Manual Push-Button Reset Input
Active Low and Active High Reset Outputs
Active Low “Soft” Reset Output
Power Supply Glitch Immunity
Guaranteed RESET for V
CC3
1V or V
CC5
1V
or V
CC25
1V
8-Pin SO and MSOP Packages
The LTC
®
1326/LTC1326-2.5 are triple supply monitors
intended for systems with multiple supply voltages. They
provide micropower operation, small size and high accu-
racy supply monitoring.
Tight 0.75% threshold accuracy and glitch immunity
ensure reliable reset operation without false triggering.
The 20µA typical supply current makes the LTC1326/
LTC1326-2.5 ideal for power-conscious systems.
The RST output is guaranteed to be in the correct state for
V
CC3
,
V
CC5
or V
CC25
down to 1V. The LTC1326/LTC1326-2.5
can be configured to monitor one, two or three inputs,
depending on system requirements.
A manual push-button reset input provides the ability to
generate a very narrow “soft” reset pulse (100µs typ) or a
200ms reset pulse equivalent to a power-on reset. Both
SRST and RST outputs are open-drain and can be OR-tied
with other reset sources.
Desktop Computers
Notebook Computers
Intelligent Instruments
Portable Battery-Powered Equipment
VCC3 (V)
0
2.0
2.5
3.5
1.5 2.5
1326/2.5 TA02
1.5
1.0
0.5 1.0 2.0 3.0 3.5
0.5
0
3.0
RST OUTPUT VOLTAGE (V)
VCC25 = VCCA = VCC3
4.7k PULL-UP FROM RST TO VCC3
TA = 25°C
PUSH-BUTTON
RESET
1326/2.5 TA01
V
CC3
V
CC25
0.1µF
V
CCA
GND
RST
PBR SRST
LTC1326-2.5
V
CORE
3.3V
2.5V
DC/DC
CONVERTER
SYSTEM
LOGIC
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 4843302.
2
LTC1326/LTC1326-2.5
132625fc
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
IS
Terminal Voltage
V
CC3
, V
CC5
, V
CC25
, V
CCA
......................... 0.5V to 7V
RST, SRST ............................................ 0.5V to 7V
RST ...................................... 0.5V to (V
CC3
+ 0.3V)
PBR .......................................................... 7V to 7V
Operating Temperature Range
LTC1326C/LTC1326C-2.5....................... 0°C to 70°C
LTC1326I/LTC1326I-2.5 ..................... 40°C to 85°C
Storage Temperature Range ................ 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
WU
U
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
1326
1326I
LTBA
LTUH
LTC1326CS8
LTC1326IS8
LTC1326CMS8
LTC1326IMS8
MS8 PART NUMBER
LTC1326CS8-2.5
LTC1326IS8-2.5
LTC1326CMS8-2.5
LTC1326IMS8-2.5
132625
326I25
LTEK
LTUJ
Consult factory for parts specified with wider operating temperature ranges.
1
2
3
4
8
7
6
5
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
VCC3
VCC5
VCCA
GND
PBR
SRST
RST
RST
T
JMAX
= 125°C, θ
JA
= 150°C/W
1
2
3
4
VCC3
VCC5
VCCA
GND
8
7
6
5
PBR
SRST
RST
RST
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
T
JMAX
= 125°C, θ
JA
= 250°C/W
1
2
3
4
8
7
6
5
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
V
CC3
V
CC25
V
CCA
GND
PBR
SRST
RST
RST
T
JMAX
= 125°C, θ
JA
= 150°C/W
1
2
3
4
V
CC3
V
CC25
V
CCA
GND
8
7
6
5
PBR
SRST
RST
RST
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
T
JMAX
= 125°C, θ
JA
= 250°C/W
ORDER PART NUMBER S8 PART NUMBER
ORDER PART NUMBER MS8 PART NUMBER ORDER PART NUMBER S8 PART NUMBER
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
(Notes 1, 2)
3
LTC1326/LTC1326-2.5
132625fc
V
RT3
Reset Threshold V
CC3
0°C T
A
70°C3.094 3.118 3.135 V
–40°C T
A
85°C3.052 3.118 3.143 V
V
RT5
Reset Threshold V
CC5
(LTC1326) 0°C T
A
70°C4.687 4.725 4.750 V
–40°C T
A
85°C4.625 4.725 4.762 V
V
RT25
Reset Threshold V
CC25
(LTC1326-2.5) 0°C T
A
70°C2.344 2.363 2.375 V
–40°C T
A
85°C2.312 2.363 2.381 V
V
RTA
Reset Threshold V
CCA
0°C T
A
70°C0.992 1.000 1.007 V
–40°C T
A
85°C0.980 1.000 1.007 V
V
CC
V
CC3
Operating Voltage RST in Correct Logic State 17V
I
VCC3
V
CC3
Supply Current PBR = V
CC3
20 40 µA
I
VCC5
V
CC5
Input Current (LTC1326) V
CC5
= 5V 410 µA
I
VCC25
V
CC25
Input Current (LTC1326-2.5) V
CC25
= 2.5V 2.8 7 µA
I
VCCA
V
CCA
Input Current V
CCA
= 1V –15 0 15 nA
t
RST
Reset Pulse Width RST Low with 10k Pull-Up to V
CC3
0°C T
A
70°C140 200 280 ms
–40°C T
A
85°C140 200 300 ms
t
SRST
Soft Reset Pulse Width SRST Low with 10k Pull-Up to V
CC3
50 100 200 µs
t
UV
V
CC
Undervoltage Detect to RST V
CC25
, V
CC3
or V
CCA
Less Than Reset 13 µs
Threshold V
RT
by More Than 1%
I
PBR
PBR Pull-Up Current PBR = 0V
0°C T
A
70°C3710 µA
–40°C T
A
85°C3715 µA
V
IL
PBR, RST Input Low Voltage 0.8 V
V
IH
PBR, RST Input High Voltage 2V
t
PW
PBR Min Pulse Width 40 ns
t
DB
PBR Debounce Deassertion of PBR Input to SRST 20 35 ms
Output (PBR Pulse Width = 1µs)
t
PB
PBR Assertion Time for Transition PBR Held Less Than V
IL
from Soft to Hard Reset Mode 0°C T
A
70°C1.4 2.0 2.8 s
–40°C T
A
85°C1.4 2.0 3.0 s
V
OL
RST Output Voltage Low I
SINK
= 5mA 0.15 0.4 V
I
SINK
= 100µA, V
CC3
= 1V, V
CC5
= 0V 0.05 0.4 V
0°C T
A
70°CV
CC3
= 0V, V
CC5
= 1V 0.05 0.4 V
V
CC3
= 1V, V
CC5
= 1V 0.05 0.4 V
I
SINK
= 100µA, V
CC3
= 1.1V, V
CC5
= 0V 0.05 0.4 V
–40°C T
A
85°CV
CC3
= 0V, V
CC5
= 1.1V 0.05 0.4 V
V
CC3
= 1.1V, V
CC5
= 1.1V 0.05 0.4 V
I
SINK
= 100µA, V
CC3
= 1V, V
CC25
= 0V 0.05 0.4 V
0°C T
A
70°CV
CC3
= 0V, V
CC25
= 1V 0.05 0.4 V
V
CC3
= 1V, V
CC25
= 1V 0.05 0.4 V
I
SINK
= 100µA, V
CC3
= 1.1V, V
CC25
= 0V 0.05 0.4 V
–40°C T
A
85°CV
CC3
= 0V, V
CC25
= 1.1V 0.05 0.4 V
V
CC3
= 1.1V, V
CC25
= 1.1V 0.05 0.4 V
SRST Output Voltage Low I
SINK
= 2.5mA 0.15 0.4 V
RST Output Voltage Low I
SINK
= 2.5mA 0.15 0.4 V
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC3 = 3.3V, VCC5 = 5V (for LTC1326),VCC25 = 2.5V (for LTC1326-2.5),
VCCA = VCC3, TA = 25°C unless otherwise noted.
4
LTC1326/LTC1326-2.5
132625fc
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OH
RST Output Voltage High (Note 3) I
SOURCE
= 1µAV
CC3
– 1 V
SRST Output Voltage High (Note 3) I
SOURCE
= 1µAV
CC3
– 1 V
RST Output Voltage High I
SOURCE
= 600µAV
CC3
– 1 V
t
PHL
Prop Delay RST to RST C
RST
= 20pF 25 ns
High Input to Low Output
t
PLH
Prop Delay RST to RST C
RST
= 20pF 45 ns
Low Input to High Output
V
OVR
V
CC5
Reset Override Voltage Override V
CC5
Ability to Assert RST (Note 4) V
CC3
±0.025 V
Note 3: The output pins SRST and RST have weak internal pull-ups to
V
CC3
of 6µA typ. However, external pull-up resistors may be used when
faster rise times are required.
Note 4: The V
CC5
reset override voltage is valid for an operating range less
than approximately 4.15V. Above this point the override is turned off and
the V
CC5
pin functions normally.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
15
IVCC3 (µA)
16
18
19
20
25
22
1326/2.5 G01
17
23
24
21
–60 –20 20 40
–40 0 60 80 100
IVCC3 vs Temperature
TEMPERATURE (°C)
2.50
IVCC25 (µA)
2.55
2.65
2.70
2.75
3.00
2.85
1326/2.5 G03
2.60
2.90
2.95
2.80
–60 –20 20 40
–40 0 60 80 100
IVCC25 vs Temperature
(LTC1326-2.5)
TEMPERATURE (°C)
IVCC5 (µA)
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
1326/2.5 G02
–60 –20 20 40
–40 0 60 80 100
IVCC5 vs Temperature
(LTC1326)
The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. LTC1326 Only VCC3 = 3.3V, VCC5 = 5V, VCCA = VCC3, TA = 25°C unless
otherwise noted.
5
LTC1326/LTC1326-2.5
132625fc
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
–60
V
CC25
THRESHOLD VOLTAGE, V
RT25
(V)
2.375
2.370
2.365
2.360
2.355
2.350
–20 20 40
1326/2.5 G10
–40 0 60 80 100
VCC25 Threshold Voltage
vs Temperature (LTC1326-2.5)
TEMPERATURE (°C)
–60
VCCA THRESHOLD VOLTAGE, VRTA (V)
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
–20 20 40
1326/2.5 G12
–40 0 60 80 100
VCCA Threshold Voltage
vs Temperature
VCC3 Threshold Voltage
vs Temperature
TEMPERATURE (°C)
–60
VCC3 THRESHOLD VOLTAGE, VRT3 (V)
60
1326/2.5 G11
–20 20
–40 80
0 40 100
3.135
3.130
3.125
3.120
3.115
3.110
3.105
3.100
VCCA Transient Immunity
V
CCA
RESET COMPARATOR OVERDRIVE (V)
0.001
20
TRANSIENT DURATION (µs)
30
40
0.01 0.1 1
1326/2.5 G07
10
0
25
35
15
5
RESET OCCURS
ABOVE CURVE
T
A
= 25°C
VCC3 RESET COMPARATOR OVERDRIVE (V)
0.001
20
TRANSIENT DURATION (µs)
30
40
0.01 0.1 1
1326/2.5 G08
10
0
25
35
15
5
RESET OCCURS
ABOVE CURVE
TA = 25°C
VCC3 Transient Immunity
TEMPERATURE (°C)
–60
VCC5 THRESHOLD VOLTAGE, VRT5 (V)
4.750
4.745
4.740
4.735
4.730
4.725
4.720
4.715
4.710
4.705
4.700
–20 20 40
1326/2.5 G09
–40 0 60 80 100
VCC5 Threshold Voltage
vs Temperature (LTC1326)
VCC5 Transient Immunity
(LTC1326)
VCC5 RESET COMPARATOR OVERDRIVE (V)
0.001
20
TRANSIENT DURATION (µs)
25
30
35
40
0.01 0.1 1
1326/2.5 G05
15
10
5
0
45
50
RESET OCCURS
ABOVE CURVE
TA = 25°C
VCCA Input Current vs Input Voltage
INPUT VOLTAGE (V)
0.8
–3
INPUT CURRENT (nA)
–2
–1
0
1
0.9 1.0 1.1 1.2
1326/2.5 G04
2
3
0.85 0.95 1.05 1.15
TA = 25°C
VCC25 Transient Immunity
(LTC1326-2.5)
V
CC25
RESET COMPARATOR OVERDRIVE (V)
0.001
TRANSIENT DURATION (µs)
0.01 0.1 1
1326/2.5 G06
45
40
35
30
25
20
15
10
5
0
RESET OCCURS
ABOVE CURVE
T
A
= 25°C
6
LTC1326/LTC1326-2.5
132625fc
RST (Pin 6): Reset Logic Output. Active low, open-drain
logic output with weak pull-up to V
CC3
. Can be pulled up
greater than V
CC3
when interfacing to 5V logic. Asserted
when one or more of the supplies are below trip
thresholds and held for 200ms after all supplies become
valid. Also asserted after PBR is held low for more than
2 seconds and for an additional 200ms after PBR is
released.
SRST (Pin 7): Soft Reset. Active low, open-drain logic
output with weak pull-up to V
CC3
. Can be pulled up
greater than V
CC3
when interfacing to 5V logic. Asserted
for 100µs after PBR is held low for less than 2 seconds
and released.
PBR (Pin 8): Push-Button Reset. Active low logic input
with weak pull-up to V
CC3
. Can be pulled up greater than
V
CC3
when interfacing to 5V logic. When asserted for less
than 2 seconds, outputs a soft reset 100µs pulse on the
SRST pin. When PBR is asserted for greater than 2
seconds, the RST output is forced low and remains low
until 200ms after PBR is released.
V
CC3
(Pin 1): 3.3V Sense Input and Power Supply Pin for
the IC. Bypass to ground with 0.1µF ceramic capacitor.
V
CC5
(Pin 2) (LTC1326): 5V Sense Input. Used as gate
drive for the RST output FET when the voltage on V
CC3
is
less than the voltage on V
CC5
. If unused, it can be tied to
V
CC3
(see Dual and Single Supply Monitor Operation in
the Applications Information section).
V
CC25
(Pin 2) (LTC1326-2.5): 2.5V Sense Input. Used as
gate drive for RST output FET when the voltage on V
CC3
is less than the voltage on V
CC25
. If unused, it can be tied
to V
CC3
.
V
CCA
(Pin 3): 1V Sense, High Impedance Input. Can be
used as a logic input with a 1V threshold. If unused, it can
be tied to either V
CC3
or V
CC25
.
GND (Pin 4): Ground.
RST (Pin 5): Reset Logic Output. Active high CMOS logic
output, drives high to V
CC3
, buffered complement of RST.
An external pull-down on the RST pin will drive this pin
high.
PIN FUNCTIONS
UUU
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Reset Pulse Width
vs Temperature
PBR Assertion Time to Reset
vs Temperature
“Soft” Reset Pulse Width
vs Temperature
TEMPERATURE (°C)
210
215
220
1326/2.5 G13
205
200
195
190
RESET PULSE WIDTH, tRST (ms)
225
–60 –20 20 40
–40 0 60 80 100
TEMPERATURE (°C)
105.0
107.5
110.0
1326/2.5 G14
102.5
100.0
97.5
95.0
SOFT RESET PULSE WIDTH, t
SRST
(µs)
112.5
–60 –20 20 40
–40 0 60 80 100
TEMPERATURE (°C)
2.10
2.15
2.20
1326/2.5 G15
2.05
2.00
1.95
1.90
PBR ASSERTION TIME TO RESET, tPB (SEC)
2.25
–60 –20 20 40
–40 0 60 80 100
7
LTC1326/LTC1326-2.5
132625fc
BLOCK DIAGRA S
W
LTC1326
+
+
+
+
+
25mV
V
CC3
V
CC3
INTERNAL
4.15V
V
CC3
SOFT RESET
RESET
25mV
3V
CCA
1V
CC3
2V
CC5
8PBR
7µA
6µA
6µA
7 SRST
4GND REF
PBR
TIMER
200ms
RESET
GENERATOR
V
CC3
6 RST
5
V
CC3
RST
1326 BD
V
CC3
+
V
CC3
V
CC5
POWER
DETECT/
GATE DRIVE
TO POWER
DETECT
LTC1326-2.5
+
+
VCC3
INTERNAL
VCC3
SOFT RESET
RESET
TO POWER
DETECT
VCC3
VCC25
3VCCA
1VCC3
2VCC25
8PBR
7µA
6µA
6µA
7 SRST
4GND REF
PBR
TIMER
200ms
RESET
GENERATOR
POWER
DETECT/
GATE DRIVE
VCC3
6 RST
5
VCC3
RST
1326-2.5 BD
VCC3
+
8
LTC1326/LTC1326-2.5
132625fc
The three internal precision voltage comparators have
response times that are typically 13µs. This slow re-
sponse time helps prevent mistriggering due to tran-
sients on each of the V
CC
inputs. The part’s ability to
suppress transients can be improved by bypassing each
of the V
CC
inputs with a 0.1µF capacitor to ground.
Push-Button Reset
The parts provide a push-button reset input pin. The PBR
input has an internal pull-up current source to V
CC3
. If the
PBR pin is not used it can be left floating.
When the PBR is pulled low for less than t
PB
(2 sec), a
narrow (100µs typ) soft reset pulse is generated on the
SRST output pin after the button is released. The push-
button circuitry contains an internal debounce counter
which delays the output of the soft reset pulse by typically
20ms. This pin can be OR-tied to the RST pin and issue
what is called a “soft” reset. The SRST thereby resets the
microprocessor without interrupting the DRAM refresh
cycle. In this manner DRAM information remains undis-
turbed. Alternatively, SRST may be monitored by the
processor to initiate a software-controlled reset.
When the PBR pin is held low for longer than t
PB
( 2 sec),
a standard reset is generated on the RST and RST pins.
Once the 2 second period has elapsed, a reset signal is
produced by the push-button logic, thereby clearing the
reset counter. Once the button is released, the reset
counter begins counting the reset period (200ms nomi-
nal). Consequently, the reset outputs remain asserted for
approximately 200ms after the button is released.
TI I G DIAGRA S
WW
U
APPLICATIO S I FOR ATIO
WUUU
Operation
The LTC1326/LTC1326-2.5 are micropower, high accu-
racy triple supply monitoring circuits. The parts have two
basic functions: generation of a reset when power sup-
plies are out of range, and generation of reset or a “soft”
reset when the PBR pin is pulled low.
Supply Monitoring
All three V
CC
inputs must be above predetermined
thresholds for 200ms before the reset output is released.
The parts will assert reset during power-up, power-down
and brownout conditions on any one or more of the V
CC
inputs.
On power-up, either the V
CC5
or V
CC3
pin on the LTC1326,
or the V
CC25
or V
CC3
pin on the LTC1326-2.5, can power
the drive circuits for the RST pin. This ensures that RST
will be low when V
CC5
, V
CC25
or V
CC3
reaches 1V. As long
as any one of the V
CC
inputs is below its predetermined
threshold, RST will stay a logic low. Once all of the V
CC
inputs rise above their thresholds, an internal timer is
started and RST is released after 200ms. The RST pin
outputs the inverted state of what is seen on RST pin.
RST is reasserted whenever any one of the V
CC
inputs
drops below its predetermined threshold and remains
asserted until 200ms after all of the V
CC
inputs are above
their thresholds.
On power-down, once any of the V
CC
inputs drop below
its threshold, RST is held at a logic low. A logic low of 0.4V
is guaranteed until V
CC3
and V
CC5
on the LTC1326 or V
CC3
and V
CC25
on the LTC1326-2.5 drop below 1V.
Push-Button Reset Function Timing
t < t
PB
t
PB
t
RST
t
DB
t
SRST
1326/2.5 TD02
PBR
RST
SRST
t
RST
1326/2.5 TD01
V
RTX
V
CCX
RST
VCC Monitor Timing
9
LTC1326/LTC1326-2.5
132625fc
During a supply induced reset condition, the ability of the
PBR pin to force a soft reset condition on the SRST pin
is disabled. In other words SRST will remain high. If the
PBR pin is held low, both during and after a supply
induced reset (low RST), the RST pin will remain low until
200ms after the PBR goes high.
Power Detect/Gate Drive
The LTC1326/LTC1326-2.5 for the most part are powered
internally from the V
CC3
pin. The exception is at the gate
drive of the output FET on the RST pin. On the input to this
FET is power detection circuitry used to detect and drive
the gate from either the 3.3V input pin (V
CC3
) or the 5V
input pin (V
CC5
) on the LTC1326 or the 2.5V input pin
(V
CC25
) on the LTC1326-2.5. The gate drive is derived
from the pin with the highest potential. This ensures the
part pulls the RST pin low as soon as either input pin is
1V.
Dual and Single Supply Monitor Operation
The V
CC3
, V
CC5
and V
CCA
inputs may be individually
disabled by the following override techniques which allow
the LTC1326 or LTC1326-2.5 to be used as a dual or single
supply monitor.
LTC1326 Override Functions
The V
CCA
pin, if unused, can be tied to either V
CC3
or V
CC5
.
This is an obvious solution since the trip points for V
CC3
and V
CC5
will always be greater than the trip point for V
CCA
.
The V
CC5
input trip point is disabled if its voltage is equal
to the voltage on V
CC3
±25mV and the voltage on V
CC5
is
less than 4.15V. In this manner, the part will behave as a
3.3V monitor and the V
CC5
reset will be disabled.
The V
CC5
trip point is reenabled when the voltage on V
CC5
is equal to the voltage on V
CC3
±25mV and the two inputs
are greater than approximately 4.15V. In this manner, the
LTC1326 can function as a 5V monitor with the 3.3V
monitor disabled.
When monitoring either 3.3V or 5V with V
CC3
strapped to
V
CC5
(see Figure 1), the LTC1326 determines which is the
appropriate range. The LTC1326 handles this situation as
shown in Figure 2. Above 1V and below V
RT3
, RST is held
low. From V
RT3
to approximately 4.15V, the LTC1326
assumes 3.3V supply monitoring and RST is deasserted.
Above approximately 4.15V, the LTC1326 operates as a 5V
monitor. In most systems, the 5V supply will pass through
the 3.1V to 4.15V region in <200ms during power-up, and
the RST output will behave as desired. Table 1 summarizes
the state of RST and RST at various operating voltages
with V
CC3
= V
CC5
.
APPLICATIO S I FOR ATIO
WUUU
Table 1. Override Truth Table (VCC3 = VCC5)
INPUTS (V
CC3
= V
CC5
= V
CC
) RST RST
0V V
CC
1V
1V V
CC
V
RT3
01
V
RT3
V
CC
4.15V 1 0
4.15V V
CC
V
RT5
01
V
RT5
V
CC
10
Figure 2. RST Voltage vs Supply Voltage
1
2
3
4
8
7
6
5
VCC3
VCC5
VCCA
GND
PBR
SRST
RST
RST
LTC1326
SYSTEM RESET
R2
1326/2.5 F01
R1
ADJUSTABLE
SUPPLY
3.3V OR
5V
4.7k
Figure 1
SUPPLY VOLTAGE (V)
0
RST OUTPUT VOLTAGE (V)
3
4
5
4
1326/2.5 F02
2
1
01235
V
CC3
= V
CC5
= V
CCA
= 0V TO 5V
4.7k PULL-UP FROM RST TO V
CC3
10
LTC1326/LTC1326-2.5
132625fc
Figure 3 contains a simple circuit for 5V systems that can’t
risk the RST output going high in the 3.1V to 4.15V range
(possibly due to very slow rise time on the 5V supply).
Diode D1 powers the LTC1326 while dropping 0.6V from
the V
CC5
pin to the V
CC3
pin. This prevents the part’s
internal override circuit from being activated. Without the
override circuit active, the RST pin stays low until V
CC5
reaches V
RT5
4.725V (See Figure 4).
LTC1326-2.5 Override Functions
The V
CCA
pin, if unused, can be tied to either V
CC3
or V
CC25
.
This is an obvious solution since the trip points for V
CC3
and V
CC25
will always be greater than the trip point for
V
CCA
. Likewise, the V
CC25
, if unused, can be tied to V
CC3
.
V
CC3
must always be used. Tying V
CC3
to V
CC25
and
operating off of a 2.5V supply will result in the continuous
assertion of RST.
Extending ESD Tolerance on the PBR Input Pin
The PBR pin is susceptible to ESD since it may be brought
out to a front panel in normal applications. The ESD
tolerance of this pin can be increased by adding a resistor
in series with the PBR pin. A 10k resistor can increase the
ESD tolerance of the PBR pin to approximately 10kV. The
PBR’s internal pull-up current of 7µA typical means there
is only 70mV (150mV max) dropped across the resistor.
See Figure 5.
APPLICATIO S I FOR ATIO
WUUU
PUSH-BUTTON
RESET
1
2
3
4
8
7
6
5
VCC3
VCC25
VCCA
GND
PBR
SRST
RST
RST
LTC1326-2.5
3.3V
SYSTEM RESET
2.5V
R2
R1
1326/2.5 F05
ADJUSTABLE SUPPLY
OR DC/DC FEEDBACK
DIVIDER
10k*
*OPTIONAL RESISTOR EXTENDS ESD TOLERANCE OF PBR INPUT TO APPROXIMATELY 10kV
Figure 5. Triple Supply Monitor (3.3V, 2.5V
and Adjustable) with Extended ESD Tolerance
1
2
3
4
8
7
6
5
VCC3
VCC5
VCCA
GND
PBR
SRST
RST
RST
LTC1326
SYSTEM RESET
1326/2.5 F03
5V
0.1µF
4.7k
D1*
*MMBD914 OR EQUIVALENT
V
CC5
(V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
RST OUTPUT VOLTAGE (V)
1326/2.5 F04
5
4
3
2
1
0
V
CC5
= V
CCA
= 0V TO 5V
4.7k PULL-UP FROM RST TO V
CC5
T
A
= 25°C
Figure 3. LTC1326 Monitoring a Single 5V Supply.
D1 Used to Avoid RST High Near 3.3V to 4V (See
Figure 2).
Figure 4. RST Output Voltage
Characteristics of the Circuit in Figure 3
11
LTC1326/LTC1326-2.5
132625fc
TYPICAL APPLICATIONS N
U
Triple Supply Monitor (3.3V, 5V and Adjustable)
1
2
3
4
8
7
6
5
V
CC3
V
CC5
V
CCA
GND
PBR
SRST
RST
RST
LTC1326
3.3V
SYSTEM RESET
5V
R2
R1
1326/2.5 TA03
ADJUSTABLE SUPPLY
OR DC/DC FEEDBACK
DIVIDER
Dual Supply Monitor (3.3V or 5V Plus Adj)
REFER TO LTC1326 OVERRIDE FUNCTIONS IN
THE APPLICATIONS INFORMATION SECTION.
1
2
3
4
8
7
6
5
V
CC3
V
CC5
V
CCA
GND
PBR
SRST
RST
RST
LTC1326
SYSTEM RESET
R2
1326/2.5 F01
R1
ADJUSTABLE
SUPPLY
3.3V OR
5V
4.7k
1
2
3
4
8
7
6
5
VCC3
VCC25
VCCA
GND
PBR
SRST
RST
RST
LTC1326-2.5
SYSTEM RESET
R2
1326/2.5 TA07
R1
ADJUSTABLE
SUPPLY
3.3V
4.7k
Dual Supply Monitor (3.3V Plus Adj)
Dual Supply Monitor (3.3V and 5V, Defeat VCCA Input)
1
2
3
4
8
7
6
5
V
CC3
V
CC5
V
CCA
GND
PBR
SRST
RST
RST
LTC1326
3.3V
SYSTEM RESET
5V
1326/2.5 TA05
12
LTC1326/LTC1326-2.5
132625fc
TYPICAL APPLICATIONS N
U
SRST Tied to RST and OR-Tying Other Sources to RST to
Generate Reset and Reset
Using VCCA Tied to DC/DC Feedback Divider
1
2
3
4
8
7
6
5
LTC1326
3.3V
SYSTEM
RESET
5V
22.1k
1%
1326/2.5 TA09
35.7k
1%
LTC1435
ADJUSTABLE
RESET TRIP
THRESHOLD 2.74V
2.9V
2.8k
1%
6
V
OSENSE
V
CC3
V
CC5
V
CCA
GND
PBR
SRST
RST
RST
Using the Short Pulse Width, Push-Button Soft Reset Feature
to Initiate Hard Reset
1
2
3
4
8
7
6
5
V
CC3
V
CC25
V
CCA
GND
PBR
SRST
RST
RST
LTC1326-2.5
3.3V
RESET
2.5V
PBR
20ms
RST
1326/2.5 TA11
200ms
40ns t
P
10µs
4.7k
SRST
6µA
6µA
3.3V
LTC1326/
LTC1326-2.5
PUSHBUTTON
RESET
RESET
1326/2.5 TA08
OTHER OPEN DRAIN
RESET SOURCES
OR-TIED TO RESET
7
8
PBR
RST
RST
VCC3
6
5
13
LTC1326/LTC1326-2.5
132625fc
TYPICAL APPLICATIONS N
U
Monitoring a Negative Supply
1
2
3
4
8
7
6
5
V
CC3
V
CC5
V
CCA
GND
PBR
SRST
RST
RST
LTC1326
5V
–5V
3.3V
C2
0.1µFSYSTEM RESET
1326/2.5 TA12
R1
150k
1%
R3
100k
1%
V
CCA
R2
150k
1%
R4
392k
1%
C1
0.1µF
Q1
2N3906
Q3
2N3904
Q2
2N3906
R4 (100k)(0.98)(V
TRIP
+ 0.55)(–1)
1
2
3
4
8
7
6
5
V
CC3
V
CC25
V
CCA
GND
PBR
SRST
RST
RST
LTC1326-2.5
2.5V
SYSTEM RESET
R2
1326/2.5 TA13
R1
ADJUSTABLE
SUPPLY
3.3V
100k
Reset Valid for VCC3 Down to 0V
VCC3 (V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
RST OUTPUT VOLTAGE (V)
1326/2.5 TA13a
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
VCC3 = VCC25 = VCCA
TA = 25°C
RST OUTPUT WITH
100k PULL-UP TO VCC3
RST OUTPUT
WITHOUT
100k PULL-UP.
10M LOAD TO GND
SUPPLY V
TRIP
R4
5V 4.6V 392k
3.3V 3V 237k
12V 10.8V 1M
14
LTC1326/LTC1326-2.5
132625fc
PACKAGE DESCRIPTIO
U
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
MSOP (MS8) 0204
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.127 ± 0.076
(.005 ± .003)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.90 ± 0.152
(.193 ± .006)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
15
LTC1326/LTC1326-2.5
132625fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
U
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
16
LTC1326/LTC1326-2.5
132625fc
© LINEAR TECHNOLOGY CORPORATION 2006
LT 1006 REV C • PRINTED IN THE USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear-tech.com
Triple Supply Monitor with 3.3V and 5V System Resets
V
CC3
V
CC5
V
CCA
GND
PBR
SRST
RST
RST
LTC1326
3.3V
TO 3.3V
SYSTEM RESET
10k10k
TO 5V
SYSTEM RESET
Q1
2N7002
5V
R2
R1
1326/2.5 TA14
ADJUSTABLE SUPPLY
OR DC/DC FEEDBACK
DIVIDER
PART NUMBER DESCRIPTION COMMENTS
LTC690 5V Supply Monitor, Watchdog Timer and Battery Backup 4.65V Threshold
LTC694-3.3 3.3V Supply Monitor, Watchdog Timer and Battery Backup 2.9V Threshold
LTC699 5V Supply Monitor and Watchdog Timer 4.65V Threshold
LTC1232 5V Supply Monitor, Watchdog Timer and Push-Button Reset 4.37V/4.62V Threshold
LTC1443/LTC1444/ Micropower Quad Comparators with 1% Reference LTC1443 has 1.182V Reference, LTC1444/LTC1445
LTC1445 have 1.221V Reference and Adjustable Hysteresis
LTC1536 Precision Triple Supply Monitor for PCI Applications Meets PCI t
FAIL
Timing Specifications
LTC1540 Nanopower Comparator with 2% Reference 1.182V Reference, 300nA Supply Current, 8-Pin MSOP
LTC1726-2.5 Micropower Triple Supply Monitor for 2.5V, 3.3V and ADJ Adjustable RESET and Watchdog Time Outs
LTC1726-5 Micropower Triple Supply Monitor for 5V, 3.3V and ADJ Adjustable RESET and Watchdog Time Outs
LTC1727-2.5 Micropower Triple Supply Monitor with Individual Outputs 2.338V, 3.086V, 1V Thresholds (±1.5%) 2.5, 3.3V, ADJ
LTC1727-5 Micropower Triple Supply Monitor with Individual Outputs 4.675V, 3.086V, 1V Thresholds (±1.5%) 5V, 3.3V, ADJ
LTC1728-1.8 Micropower Triple Supply Monitor in 5-Pin SOT-23 Package 2.805V, 1.683V,1V Thresholds (±1.5%) 3V, 1.8V, ADJ
LTC1728-2.5 Micropower Triple Supply Monitor in 5-Pin SOT-23 Package 2.338V, 3.086V, 1V Thresholds (±1.5%) 2.5, 3.3V, ADJ
LTC1728-5 Micropower Triple Supply Monitor in 5-Pin SOT-23 Package 4.675V, 3.086V, 1V Thresholds (±1.5%) 5V, 3.3V, ADJ
LTC1985-1.8 Micropower Triple Supply Monitor for 3V, 1.8V and ADJ Push-Pull RESET Output, SOT-23
LTC2900 Programmable Quad Supply Monitor Adjustable Reset, 10-Lead MSOP and 3mm × 3mm 10-Lead
DFN Package
LTC2901 Programmable Quad Supply Monitor Adjustable Reset and Watchdog Timer, 16-Lead SSOP Package
LTC2902 Programmable Quad Supply Monitor Adjustable Reset and Tolerance, 16-Lead SSOP Package,
Margining Functions
LTC2903 Precision Quad Supply Monitor 6-Lead SOT-23 Package, Ultralow Voltage Reset
LTC2904/LTC3905 3-State Programmable Precision Dual Supply Monitor Adjustable Tolerance and Reset Timer, 8-Lead SOT-23 Package
LTC2906/LTC2907 Precision Dual Supply Monitor 1-Selectable and 1 Adjustable Separate V
CC
Pin, RST/RST Outputs/Adjustable Reset Timer
LTC2908 Precision Six Supply Monitor (4 Fixed and 2 Adjustable) 8-Lead SOT-23 and DDB Packages
RELATED PARTS
TYPICAL APPLICATIO
U