© 2006 Microchip Technology Inc. DS39605D
PIC18F1220/1320
Data Sheet
18/20/28-Pin High-Performance,
Enhanced Flash Microcontrollers
with 10-bit A/D and nanoWatt Technology
DS39605D-page ii © 2006 Microchip Technology Inc.
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The Microchip name and logo, the Microchip logo, Accur on,
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© 2006, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
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intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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© 2006 Microchip Technology Inc. DS39605D-page 1
Low-Power Features:
Power Managed modes:
- Run: CPU on, pe ripherals on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
Pow er Consumption modes :
- PRI_RUN: 150 μA, 1 MHz, 2V
- PRI_IDLE: 37 μA, 1 MHz, 2V
- SEC_RUN: 14 μA, 32 kHz, 2V
- SEC_IDLE: 5.8 μA, 32 kHz, 2V
- RC_RUN: 110 μA, 1 MHz, 2V
- RC_IDLE: 52 μA, 1 MHz, 2V
- Sleep: 0.1 μA, 1 MHz, 2V
Timer1 Oscillator: 1.1 μA, 32 kHz, 2V
Watchdog Timer: 2.1 μA
Two-Speed Os ci ll ator Start-up
Oscillators:
Four Crystal modes:
- LP, XT, HS: up to 25 MHz
- HSPLL: 4-10 MHz (16-40 MHz internal)
Two External RC modes, up to 4 MHz
Two External Clock modes, up to 40 MHz
Internal oscillator block:
- 8 user-selectable frequencies: 31 kHz, 125 kHz,
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MH z
- 125 kHz to 8 MHz calibrated to 1%
- Two modes select one or two I/O pins
- OSCTUNEAllows user to shift frequency
Secondary oscillator using Timer1 @ 32 kHz
Fail-Safe Clock Monitor
- Allows for safe shutdown if peripheral clock stops
Peripheral Highl ight s:
High current sink/source 25 mA/25 mA
Three extern al inte rrup t s
Enhanced Capture/Compare/PWM (ECCP) module:
- One, two or four PWM outputs
- Selectab le pol ari ty
- Programmable dead time
- Auto-Shutdown and Auto-Restart
- Capture is 16-bit, max resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max resolution 100 ns (TCY)
Compa t ib le 10-b it, up to 13-chan nel Analog -to-
Digital Converter module (A/D) with programmable
acquisition time
Enhanced USART module:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-Wake-up on Start bit
- Auto-Baud Detect
Special Microcontroller Features:
100,000 eras e/w ri te cy cl e Enhan ced Flash
program memory typical
1,000,000 erase/write cycle Data EEPROM
memory typical
Flash/Data EEPROM Retention: > 40 years
Self-programmable under software control
Priority levels for interrupts
8 x 8 Single-Cycle Hardware Multiplier
Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
- 2% stability over VDD and Temperature
Single-supply 5V In-Circuit Serial Programming™
(ICSP™) via two pins
In-Circuit Debug (ICD) via two pins
Wide operating voltage range: 2.0V to 5.5V
Device
Program Memory Data Memory
I/O 10-bit
A/D (ch) ECCP
(PWM) EUSART Timers
8/16-bit
Flash
(bytes) # Sing le-Word
Instructions SRAM
(bytes) EEPROM
(bytes)
PIC18F1220 4K 2048 256 256 16 7 1 Y 1/3
PIC18F1320 8K 4096 256 256 16 7 1 Y 1/3
18/20/28-Pin High-Performance, Enhanced Flash MCUs
with 10-bit A/D and nanoWatt Technology
PIC18F1220/1320
PIC18F1220/1320
DS39605D-page 2 © 2006 Microchip Technology Inc.
Pin Diagrams
RB3/CCP1/P1A
RB2/P1B/INT2
OSC1/CLKI/RA7
OSC2/CLKO/RA6
VDD/AVDD
RB7/PGD/T1OSI/
RB6/PGC/T1OSO/
RB5/PGM/KBI1
RB4/AN6/RX/
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
MCLR/VPP/RA5
VSS/AVSS
RA2/AN2/VREF-
RA3/AN3/VREF+
RB0/AN4/INT0
RB1/AN5/TX/
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PIC18F1X20
18-Pin PDIP, SOIC
RB3/CCP1/P1A
RB2/P1B/INT2
OSC1/CLKI/RA7
OSC2/CLKO/RA6
VDD
RB7/PGD/T1OSI/
RB6/PGC/T1OSO/
RB5/PGM/KBI1
RB4/AN6/RX/
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
MCLR/VPP/RA5
VSS
RA2/AN2/VREF-
RA3/AN3/VREF+
RB0/AN4/INT0
RB1/AN5/TX/
1
2
3
4
5
7
8
9
10
20
19
18
17
16
14
13
12
11
PIC18F1X20
AVDDAVSS 615
20-Pin SSOP
28-Pin QFN
16
2
RA0/AN0
NC
RA4/T0CKI
MCLR/VPP/RA5
NC
AVSS
NC
RA2/AN2/VREF-
RA3/AN3/VREF+
RA1/AN1/LVDIN
OSC1/CLKI/RA7
OSC2/CLKO/RA6
VDD
NC
AVDD
RB7/PGD/T1OSI/P1D/KBI3
RB6/PGC/T1OSO/T13CKI/P1C/KBI2
NC
RB5/PGM/KBI1
7
PIC18F1X20
1
3
6
5
4
15
21
19
20
17
18
22
28
26
27
23
24
25
14
8
10
9
13
12
11
VSS
NC
NC
RB2/P1B/INT2
RB0/AN4/INT0
RB1/AN5/TX/CK/INT1
NC
RB4/AN6/RX/DT/KBI0 RB3/CCP1/P1A
T13CKI/P1C/KBI2
P1D/KBI3
CK/INT1 DT/KBI0
P1D/KBI3
T13CKI/P1C/KBI2
CK/INT1 DT/KBI0
© 2006 Microchip Technology Inc. DS39605D-page 3
PIC18F1220/1320
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Oscillator Configurations............................................................................................................................................................ 11
3.0 Power Managed Modes ............................. ..... .. .. .... .. .. .. .. ..... .... .. .. .. .. .. .. ....... .. .. .. .. .... .. ..... .. .. .. ...................................................... 19
4.0 Reset.......................................................................................................................................................................................... 33
5.0 Memory O rganization................................................................................................................................................................. 41
6.0 Flash Pro g ram Memory............................ ............................ ........................... ........................................................................... 57
7.0 Data EEPR OM Mem o ry.... ............... ........................... ............................ ........................... ........................................................ 67
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 71
9.0 Interrupts.................................................................................................................................................................................... 73
10.0 I/O Ports.............. ................................. ........................... ............................ ............................................................................... 87
11.0 Tim er0 Module ........................................................................................................................................................................... 99
12.0 Tim er1 Module ......................................................................................................................................................................... 103
13.0 Tim er2 Module ......................................................................................................................................................................... 109
14.0 Tim er3 Module ......................................................................................................................................................................... 111
15.0 Enhanc ed Capture/Com pare/PW M (ECCP) Module................................................................................................................ 115
16.0 Enhanced Addressable Universal Synchronous Asynchronous Receiver T ransm itter (EUS ART). . ........................................ 131
17.0 10-Bit Analog-to-Digital Converter (A/D) Module ................................. ........... .... .... ........... ...... .... ............................................ 155
18.0 Low-V oltage Detect.................................................................................................................................................................. 165
19.0 Specia l Features of the CPU.................... ............................ ..................... ............................................................................... 171
20.0 Instruction Set Summary.......................................................................................................................................................... 191
21.0 Development Support............................................................................................................................................................... 233
22.0 Electrical Characteristics.......................................................................................................................................................... 239
23.0 DC and AC Characteristics Graphs and Tables................................... ......... .... .... .. ......... .... .... .... .. .......................................... 269
24.0 Packagin g In fo rmation.............................. ..................... ............................ ............................................................................... 287
Appendix A: Revision History . ............................................................................................................................................................ 293
Appendix B: Device Differences ........................................................................................................................................................ 293
Appendix C: Conversion Considerations .......................... .... .. ....... .... .. .... .. .... ....... .. .... .. .... .. ....... .... .. .................................................. 294
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 294
Appendix E: Migration from Mid-Range to Enhanced Devices............................... .... .... .... ........... .... .... ......... ................................... 295
Appendix F: Migration from High-End to Enhanced Devices.............................. .... .... .. .... .. ....... .... .... .. .... .......................................... 295
Index .................................................................................................................................................................................................. 297
On-Line Support................ .... .... .. .... ....... .... .... .. .... ......... .. .... .... .. ......... .. .... .... .. ......... .... .. .... ................................................................. 305
Systems Information and Upgrade Hot Line...................................................................................................................................... 305
Reader Response.............................................................................................................................................................................. 306
PIC18F1220/1320 Product Identification System .............................. .... .... .... ......... .... .. .... ......... .... .... ................................................ 307
PIC18F1220/1320
DS39605D-page 4 © 2006 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
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© 2006 Microchip Technology Inc. DS39605D-page 5
PIC18F1220/1320
1.0 DEVICE OVERVIEW
This do cu me n t conta i ns dev ic e spec if i c in f orm at i on fo r
the following devices:
This family offers the advantages of all P IC18 m i crocon-
troll ers – namel y, high compu tationa l perfor manc e at an
economical price – with the addition of high endurance
Enhanced Flash program memory. On top of these fea-
tures, the PIC18F1220/1320 family introduces design
enhancements that make these microcontrollers a logical
choice for many high-performance, power sensitive
applications.
1.1 New Core Features
1.1.1 nanoWatt TECHNOLOGY
All of the devices in the PIC18F1220/1320 family incor-
porate a range of features that can significantly reduce
power consump tion during operation. Key items include:
Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
Multiple Idle Modes: The controller can also run
with its CPU core disabled, but the peripherals are
still active. In these states, power consumption can
be reduced even further, to as little as 4% of normal
operation requirements.
On-the-fly Mode Switching: The power managed
modes are invoked by user code during operation,
allowing the user to incorporate power-saving ideas
into their appl ic atio n’s softw are desig n.
Lower Consumption in Key Modules: The power
requirements for both Timer1 and the Watchdog
Timer have been reduced by up to 80%, with typical
values of 1.1 and 2.1 μA, respectively.
1.1.2 MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F1220/1320 family offer
nine different oscillator options, allowing users a wide
range of choices in developing application hardware.
These include:
Four Crystal modes, using crystals or ceramic
resonators.
Two External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output), or one pin (oscillator input, with the
second pin reassigned as general I/O).
Two External RC Oscillator modes, with the same
pin options as the External Clock modes.
An internal oscillator block, which provides an
8 M Hz clock (±2% accuracy) and an INTRC source
(approximately 31 kHz, stable over temperature and
VDD), as well as a range of 6 user-selectable clock
frequencies (from 125 kHz to 4 MHz) for a total of
8 c lock frequencies.
Besides its availability as a clock source, the internal
oscill ato r blo ck pro vid es a s t ab le re ference sourc e th at
gives the family additional features for robust
operation:
Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock fail-
ure occurs, the controller is switched to the internal
oscillator block, allowing for continued low-speed
operation, or a safe application shut down.
Two-Speed S tart-up: This option allows the internal
oscillator to serve as the clock source from Power-
on Reset, or wake-up from Sleep mode, until the
primary clock source is available. This allows for
code execution during what would otherwise be the
clock start-up interval and can even allow an appli-
cation to perform routine background activities and
return to Sleep without returning to full power
operation.
1.2 Other Special Features
Memory Endurance: The Enhanced Flash cells for
both program memory and data EEPROM are rated
to last for many thousands of erase/write cycles –
up to 100,000 for program memory and 1,000,000
for EEPROM. Data retention without refresh is
conservatively estimated to be greater than
40 years.
Self-programmability: These devices can write to
their own program memory spaces under internal
software control. By using a bootloader routine
located in the protected Boot Bloc k at the top of pro-
gram memory, it becomes possible to create an
application that can update itself in the field.
Enhanced CCP module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers. Other
features include auto-shutdown, for disabling PWM
outputs on interrupt or other select conditions and
auto-restart, to reactiv ate outpu ts once the condi tio n
has cle are d.
Enhanced USART: This serial communication
module features automatic wake-up on Start bit and
automat ic baud rate dete ction a nd supp orts RS-23 2,
RS-485 and LIN 1.2 protocols, making it ideally
suited for use in Local Interconnect Network (LIN)
bus applic ations.
10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduce code overhead.
Extended Watchdog Timer (WDT): This enhanced
version incorporates a 16-bit prescaler, allowing a
time-out range from 4 ms to over 2 minutes that is
stable across operating voltage and temperature.
PIC18F1220 PIC18F1320
PIC18F1220/1320
DS39605D-page 6 © 2006 Microchip Technology Inc.
1.3 Details on Indivi dual Family
Members
Devices in the PIC18F1220/1320 family are available
in 18-pin , 20-pin and 28 -pin pack ages. A block dia gram
for this device family is shown in Figure 1-1.
The devices are differentiated from each other only in
the amount of on-chip Flash program memory
(4 Kbytes for the PIC18F1220 device, 8 Kbytes for the
PIC18F1320 device). These and other features are
summa riz ed in Table 1-1.
A block diagram of the PIC18F1220/1320 device
architecture is provided in Figure 1-1. The pinouts for
this device family are listed in Table 1-2.
TABLE 1-1: DEVICE FEATURES
Features PIC18F1220 PIC18F1320
Operating Frequency DC – 40 MHz DC – 40 MHz
Program Memo ry (Bytes ) 4096 8192
Program Memo ry (Instructions) 2048 4096
Data Me mo ry (Byte s) 256 256
Data EEPROM Memory (Bytes) 256 256
Interrupt Sources 15 15
I/O Ports Ports A, B Ports A, B
Timers 4 4
Enhanced Capture/Compare/PWM Modules 1 1
Serial Communications Enhanced USART Enhanced USART
10-bit Analog-to-Digital Module 7 input channels 7 input channels
Resets (and Delays)
POR, BOR,
RESET Instruction, Stack Full,
St ack U nde rflo w (PWRT, OST),
MCLR (optional), WDT
POR, BOR,
RESET Instruction, Stack Full ,
Stack Underf low (PW RT, OST),
MCLR (optional), WDT
Programmab le Low-Voltage Dete ct Yes Yes
Programmab le Brown-o ut Rese t Yes Yes
Instruction Set 75 Instructions 75 Instructions
Packages
18-pin SDIP
18-pin SOIC
20-pin SSOP
28-pin QFN
18-pin SDIP
18-pin SOIC
20-pin S SOP
28-pin QFN
© 2006 Microchip Technology Inc. DS39605D-page 7
PIC18F1220/1320
FIGURE 1-1: PIC18F1220/1320 BLOCK DIAGRAM
Instruction
Decode &
Control
PORTA
PORTB
RA4/T0CKI
MCLR/VPP/RA5(1)
Enhanced
Timer0 Timer1 Timer2
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1/LVDIN
RA0/AN0
Data Latch
Data RAM
Address Latch
Address<12>
12(2)
BSR FSR0
FSR1
FSR2
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
WREG
8
BIT OP 8
8
ALU<8>
8
Address Latch
(8 Kbytes)
Data Latch
20
21
21
16
8
8
8
inc/dec logic
21 8
Data Bus<8>
8
Instruction
12
3
ROM Latch
Timer3
Bank0, F
PCLATU
PCU
OSC2/CLKO/RA6(2)
USART
8
Register
Table Latch
Table Pointer <2>
inc/dec
logic
RB0/AN4/INT0
RB4/AN6/RX/DT/KBI0
RB1/AN5/TX/CK/INT1
RB2/P1B/INT2
RB3/CCP1/P1A
RB5/PGM/KBI1
RB6/PGC/T1OSO/
RB7/PGD/T1OSI/
OSC2/CLKI/RA7(2)
Decode
Power-up
Timer
Power-on
Reset
Watchdog
Timer
VDD, VSS
Brown-out
Reset
Precision
Reference
Voltage
Low-Voltage
Programming
In-Circuit
Debugger
Oscillator
Start-up Timer
Timing
Generation
OSC1
(2)
OSC2
(2)
T1OSI
T1OSO
INTRC
Oscillator
Fail-Safe
Clock Monitor
Note 1: RA5 is availabl e only when the MCLR Reset is disabled.
2: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital
I/O. Refer to Section 2.0 “Oscillato r Config ura tions for additional information.
8
CCP
Enhanced
T13CKI/P1C/KBI2
Program Memory
(4 Kbytes)
PIC18F1220
PIC18F1320
A/D Converter
Data EEPROM
P1D/KBI3
MCLR
(1)
PIC18F1220/1320
DS39605D-page 8 © 2006 Microchip Technology Inc.
TABLE 1-2: PIC18F1220/1320 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Numbe r Pin
Type Buffer
Type Description
PDIP/
SOIC SSOP QFN
MCLR/VPP/RA5
MCLR
VPP
RA5
441I
P
I
ST
ST
Master Cl ear (input) or pr og ramming voltage (input ) .
Master Clear (Reset) input. This pin is an active-low
Reset to the dev ic e.
Programm ing voltage input.
Digital in put.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
16 18 21 I
I
I/O
ST
CMOS
ST
Oscillator crystal or ex te rn al cl ock input.
Oscillat or crystal input o r ex te rnal cloc k source
input. ST bu ffer whe n configur ed in R C m ode,
CMOS ot h erwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
15 17 20 O
O
I/O
ST
Oscillat or cr ystal or clock ou tp ut .
Oscillat or cr ystal output. C onnects to crys tal or
resonator in Crystal Oscillator mode.
In RC, EC and INTRC modes, OSC2 pin outputs
CLKO , wh ic h has 1/4 the fre quency of O SC 1 and
denote s in st ru ct i on cycle rat e.
General purpose I/O pin.
PORTA is a bidi r ec tion al I/O port.
RA0/AN0
RA0
AN0
1126
I/O
IST
Analog Digital I/O.
Analog inp ut 0.
RA1/AN1/LVDIN
RA1
AN1
LVDIN
2227
I/O
I
I
ST
Analog
Analog
Digital I/O.
Analog input 1.
Low-Voltage Detect input.
RA2/AN2/VREF-
RA2
AN2
VREF-
677
I/O
I
I
ST
Analog
Analog
Digital I/O.
Analog input 2.
A/D refer ence voltage (lo w) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
788
I/O
I
I
ST
Analog
Analog
Digit al I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
T0CKI
3328
I/O
IST/OD
ST Digital I/O. Open-drain when configured as output.
Time r0 ext ernal cloc k input.
RA5 See the MCLR/VPP/RA5 pin.
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See th e O SC 1/CLKI/RA7 pin.
Legend: TTL = TTL compat ibl e i npu t CMOS = CMOS co m patible i nput or output
ST = Schmitt Trigger input with CMOS levels I = Input
O=Output P =Power
OD = Open-dr ai n ( no P di ode to VDD)
© 2006 Microchip Technology Inc. DS39605D-page 9
PIC18F1220/1320
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN4/INT0
RB0
AN4
INT0
899
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog inp ut 4.
External interrupt 0.
RB1/AN5/TX/CK/INT1
RB1
AN5
TX
CK
INT1
91010
I/O
I
O
I/O
I
TTL
Analog
ST
ST
Digital I/O.
Analog inp ut 5.
EUSART asy nc hr onous trans m it.
EUSART synchronous clock (see related R X/ D T) .
External interrupt 1.
RB2/P1B/INT2
RB2
P1B
INT2
17 19 23 I/O
O
I
TTL
ST
Digital I/O.
Enhanced CCP1 / PW M ou tp ut.
External interrupt 2.
RB3/CCP1/P1A
RB3
CCP1
P1A
18 20 24 I/O
I/O
O
TTL
ST
Digital I/O.
Capture 1 in put/Compare 1 output/P WM 1 outpu t.
Enhanced CCP1 / PW M ou tp ut.
RB4/AN6/RX/DT/KBI0
RB4
AN6
RX
DT
KBI0
10 11 12 I/O
I
I
I/O
I
TTL
Analog
ST
ST
TTL
Digital I/O.
Analog inp ut 6.
EUSART asynchrono us rec ei ve .
EUSART syn chronous data (see related TX/CK).
Interru pt-on-change pin.
RB5/PGM/KBI1
RB5
PGM
KBI1
11 12 13 I/O
I/O
I
TTL
ST
TTL
Digital I/O.
Low-Volt age ICSP Programming enable pin.
Interru pt-on-change pin.
RB6/PGC/T1OSO/
T13CKI/P1C/KBI2
RB6
PGC
T1OSO
T13CKI
P1C
KBI2
12 13 15
I/O
I/O
O
I
O
I
TTL
ST
ST
TTL
Digital I/O.
In-Circuit Debugger and ICSP prog ramming clock pin.
Timer1 osci l lator output.
Ti mer1/T imer3 external clock output.
Enhanced CCP1 / PW M ou tp ut.
Interru pt-on-change pin.
RB7/PGD/T1OSI/
P1D/KBI3
RB7
PGD
T1OSI
P1D
KBI3
13 14 16
I/O
I/O
I
O
I
TTL
ST
CMOS
TTL
Digital I/O.
In-Ci rcuit Debugger and I CS P programming data pin.
T imer1 oscillator input.
Enhanced CCP1 / PW M ou tp ut.
Interru pt-on-change pin.
VSS 5 5, 6 3, 5 P Ground reference for logic and I/O pins.
VDD 14 15, 16 1 7, 19 P Positive supply for logic and I/O pins.
NC 18 No connect.
TABLE 1-2: PIC18F1220/1320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Numbe r Pin
Type Buffer
Type Description
PDIP/
SOIC SSOP QFN
Legend: TTL = TTL compat ibl e i npu t CMOS = CMOS co m patible i nput or output
ST = Schmitt Trigger input with CMOS levels I = Input
O=Output P =Power
OD = Open-dr ai n ( no P di ode to VDD)
PIC18F1220/1320
DS39605D-page 10 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS39605D-page 11
PIC18F1220/1320
2.0 OSCILLATOR
CONFIGURATIONS
2.1 Oscillator Types
The PIC18F1220 and PIC18F1320 devices can be
operated in ten dif ferent osci llator modes. The user can
program the configuration bits, FOSC3:FOSC0, in
Configuration Register 1H to select one of these ten
modes:
1. LP Low-Power Crystal
2. XT Crystal/Resonator
3. HS High-Speed Crystal/Resonator
4. HSPLL High-Speed Crystal/Resonator
with PLL enabled
5. RC External Resistor/Capacitor with
FOSC/4 output on RA6
6. RCIO Extern al Resi st or/C apacito r with
I/O on RA 6
7. INTIO1 Intern al Osci ll ator with F OSC/4
output on RA6 and I/O on RA7
8. INTIO2 Internal O scil lat or with I/O on RA6
and RA7
9. EC Extern al Cloc k with FOSC/4 output
10. ECIO External Clock with I/O on RA6
2.2 Crystal Oscill a tor/Ceramic
Resonators
In XT, LP, HS or HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
The oscillator design requires the use of a parallel cut
crystal.
FIGURE 2-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)
T ABLE 2-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Note: Use of a series cut crystal may give a
frequency out of the crystal manufacturer’s
specifications.
Typi cal C apacitor Values Used:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
56 pF
47 pF
33 pF
56 pF
47 pF
33 pF
HS 8.0 MHz
16.0 MHz 27 pF
22 pF 27 pF
22 pF
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
Dif ferent cap acitor values may be required to prod uce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following Table 2-2 for additional
information.
Reson ators U sed :
455 kHz 4.0 MHz
2.0 MHz 8.0 MHz
16.0 MHz
Note 1: See Table 2-1 and Table 2-2 for initial
value s of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cu t crystals.
3: RF varies with the oscillator mode chosen.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
Sleep
To
Logic
PIC18FXXXX
RS(2)
Internal
PIC18F1220/1320
DS39605D-page 12 © 2006 Microchip Technology Inc.
TABLE 2-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-2.
FIGURE 2-2: EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
2.3 HSPLL
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
crystal oscillator circuit, or to clock the device up to its
highest rated frequency from a crystal oscillator. This
may be useful for customers who are concerned with
EMI due to high-frequency crystals.
The HSPL L mode make s use of the HS mode oscil lator
for freque ncies u p to 10 MH z. A PLL t hen multipl ies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz.
The PLL is enabled only when the oscillator configura-
tion bits are programmed for HSPLL mode. If
programmed for any other mode, the PLL is not
enabled.
FIGURE 2-3: PLL BLOCK DIAGRAM
Osc Type Crystal
Freq
Typical Cap acitor V al ues
Tested:
C1 C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 1 MHz 33 pF 33 pF
4 MHz 27 pF 27 pF
HS 4 MHz 27 pF 27 pF
8 MHz 22 pF 22 pF
20 MHz 15 pF 15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below fo r ba si c start-up and operat ion. These values
are not optimized.
Dif ferent capa citor values may be require d to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information. Cryst a ls Us ed:
32 kHz 4 MHz
200 kHz 8 MHz
1 MHz 20 MH z
Note 1: Higher capacitance increases the stability
of oscillator , but also increases the st art-up
time.
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: RS may be required to avoid overdriving
crystals with low dr iv e lev el spe ci fic ati on.
5: Always veri fy os ci lla tor pe rform an ce ov er
the VDD and temperature range that is
expected for the application.
OSC1
OSC2
Open
Clock from
Ext. System PIC18FXXXX
(HS Mode)
MUX
VCO
Loop
Filter
Crystal
Osc
OSC2
OSC1
PLL Enable
FIN
FOUT
SYSCLK
Phase
Comparator
HS Oscillator Enable
÷4
(from Configuration Register 1H)
© 2006 Microchip Technology Inc. DS39605D-page 13
PIC18F1220/1320
2.4 External Clock Input
The EC and ECIO Oscilla tor modes require an externa l
clock source to be conn ected to the OSC1 pi n. There is
no oscillator start-up time required after a Power-on
Reset, or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be u sed fo r te st pu rpos es , o r to s yn chroni ze oth er
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-4: EXTER NAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)
The ECIO O sc illator mode func ti ons li ke t he EC m od e,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.
FIGURE 2-5: EXTER NAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
2.5 RC Oscillator
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) val-
ues and the operating temperature. In addition to this,
the oscil lator frequen cy will vary from unit to unit due to
normal manufacturing variation. Furthermore, the dif-
ference in lead frame capacitance between package
types will also affect the oscillation frequency, espe-
cially for low CEXT values. The user also needs to take
into account variation, due to tolerance of external
R and C components used. Figure 2-6 shows how the
R/C combination is connected.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be us ed fo r te st purposes, o r to s ync hro niz e oth er
logic.
FIGURE 2-6: RC OSCILLATOR MODE
The RCIO Oscillator mode (Figure 2-7) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 2-7: RCIO OSCILLATOR MODE
OSC1/CLKI
OSC2/CLKO
FOSC/4
Clock from
Ext. System PIC18FXXXX
OSC1/CLKI
I/O (OSC2)
RA6
Clock from
Ext. System PIC18FXXXX
OSC2/CLKO
CEXT
REXT
PIC18FXXXX
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 kΩ REXT 100 kΩ
CEXT > 20 pF
CEXT
REXT
PIC18FXXXX
OSC1 Internal
Clock
VDD
VSS
Recommended values: 3 kΩ REXT 100 kΩ
CEXT > 20 pF
I/O (OSC2)
RA6
PIC18F1220/1320
DS39605D-page 14 © 2006 Microchip Technology Inc.
2.6 Internal Oscillator Block
The PIC18F1220/1320 devices include an internal
oscillator block, which generates two different clock
signals; either can be used as the system’s clock
source. This can eliminate the need for external
osci llator circui ts on the OSC1 and/o r OSC2 pins .
The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the system clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 125 kHz to 4 MHz. The
INTOSC output is enabled when a system clock
frequency from 125 kHz to 8 MHz is selected.
The other clock source is the internal RC oscillator
(INTRC), which provides a 31 kHz output. The INTRC
oscillator is enabled by selecting the internal oscillator
block as the system clock source, or when any of the
following are enabled:
Power-up Timer
Fail-Safe Clock Monitor
Watchdog Timer
Two-Speed S t a r t-up
These features are discussed in greater detail in
Section 19.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (Register 2-2).
2.6.1 INTIO MODES
Using the internal oscillator as the clock source can
elimin ate the ne ed for up t o two extern al oscil lator pins ,
which can then be used for digital I/O. Two distinct
configurations are available:
In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 fu nc tio ns as RA 7 fo r dig it a l in put and
output.
In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
2.6.2 INTRC OUTPUT FREQUENCY
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz
(see Table 22-6). This changes the frequency of the
INTRC source from its nominal 31.25 kHz. Peripherals
and features that depend on the INTRC source will be
affected by this shift in frequency.
Once set during factory calibration, the INTRC
frequency will remain within ±2% as temperature and
VDD change across their full specified operating
ranges.
2.6.3 OSCTUNE REGISTER
The internal oscillator’s output has been calibrated at
the factory, but can be adjusted in the user’s applica-
tion . Thi s is do ne by writi ng to the OSCTUN E regi ster
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
When the O SC TUN E reg is ter is mo di fied , the IN T O SC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
frequency within 8 clock cycles (approximately
8*32μs = 256 μs). The INTOSC clock will stabilize
within 1 ms. Code exec ution c ontinues during th is shift.
There is no indication that the shift has occurred.
Operation of features that depend on the INTRC clock
source frequency, such as the WDT, Fail-Safe Clock
Monitor and peripherals, will also be affected by the
change in freq uency.
© 2006 Microchip Technology Inc. DS39605D-page 15
PIC18F1220/1320
REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER
2.7 Clock Sources and Oscillator
Switching
Like previous PIC18 devices, the PIC18F1220/1320
devices include a feature that allows the system clock
source to be switched from the main oscillator to an
alternate low-frequency clock source. PIC18F1220/
1320 devices offer two alternate clock sources. When
enabled, these give additional options for switching to
the various power managed operating modes.
Essentially, there are three clock sources for these
devices:
Primary oscillators
Secondary oscillators
Internal oscillator block
The primary oscillators include the External Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The par ticula r mode is defin ed on POR by the content s
of Configuration Register 1H. The details of these
modes are covered earlier in this chapter.
The secondary oscillat ors are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power managed mode.
PIC18F1220/1320 devices offer only the Timer1
oscill ator as a seconda ry oscilla tor . This oscill ator , in all
power managed modes, is often the time base for
function s suc h as a real-time clock.
Most often, a 32.768 kHz watch crystal is connected
between the RB6/T1OSO and RB7/T1OSI pins. Like
the LP mode oscillator circuit, loading capacitors are
also connected from each pin to ground. These pins
are also used during ICSP operations.
The Timer1 oscillator is discussed in greater detail in
Section 12.2 “Timer1 Oscillator”.
In additio n to being a primary clock source, the internal
oscillator block is available as a power managed
mode cl oc k s ourc e. The INTRC source is also us ed as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.
The clock sources for the PIC18F1220/1320 devices
are shown in Figure 2-8. See Section 12.0 “Timer1
Module” for furth er details of the T imer1 osci llator . See
Section 19.1 “Configuration Bits” for configuration
register details.
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TUN5 TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0
bit 5-0 TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
000001
000000 = Center frequency. Oscillator module is running at the calibrated frequency.
111111
100000 = Minimum frequency
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 16 © 2006 Microchip Technology Inc.
2.7.1 OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-2) controls several
aspects of the system clock’s operation, both in full
power operation and in power managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source that is used when the device is operating in
power managed modes. The available clock sources are
the primary cl ock (defined in Configuration Register 1H),
the secondary clock (Timer1 oscillator) and the internal
oscillator block. The clock selection has no effect until a
SLEEP instruction is executed and the device enters a
power managed mode of operation. The SCS bits are
cleared on all forms of Reset.
The Inter nal Oscillator Select bit s, IRCF2:IRCF0, select
the freque ncy o utput o f the in ternal o scill ator bl ock th at
is use d to driv e th e sys tem cl ock. The c hoi ces a re t he
INTRC source, the INTOSC source (8 MHz), or one of
the six frequencies derived from the INTOSC
postscaler (125 kHz to 4 MHz). If the internal oscillator
block is supplying the system clock, changing the
states of these bits will have an immediate change on
the internal oscillator’s output.
The OSTS, IO FS an d T1 R UN bits indic ate whic h cl oc k
source is currently providing the system clock. The
OSTS indicates that the Oscillator Start-up Timer has
timed ou t and the prima ry clock i s providin g the system
clock in Primary Clock modes. The IOFS bit indicates
when the internal oscillator block has stabilized and is
providing the system clock in RC Clock modes or
during Two-Speed Start-ups. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is
provi ding th e syste m cloc k in Seco ndary Clock mo des.
In power managed modes, only one of these three bits
will be set at any time. If none of these bits are set, the
INTRC is providing the system clock, or the internal
oscillator block has just started and is not yet stable.
The IDLEN bit controls the selective shutdown of the
controller ’s CPU in power managed modes. The uses
of these bits are discussed in more detail in
Section 3.0 “Power Managed Modes”.
FIGURE 2-8: PIC18F1220/1320 CLOCK DIAGRAM
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
T imer 1 oscilla tor is enable d by setting the
T1OSCEN bit in the T ime r1 Control re gis-
ter (T1CON<3>). If the Timer1 oscillator
is not en abl ed, then any at tem pt to se lec t
a secondary clock source when
executing a SLEEP instruction will be
ignored.
2: It is recommended that the Timer1 oscil-
lator be operating and stable before exe-
cuting the SLEEP instruction or a very
long delay may occur while the Timer1
oscillator starts.
PIC18F1220/1320
4 x PLL
CONFIG1H<3:0>
Secondary Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source Option
for Other Modules
OSC1
OSC2
Sleep
Primary Oscillator
HSPLL
LP, XT, HS, RC, EC
T1OSC
CPU
Peripherals
IDLEN
Postscaler
MUX
MUX
8
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
OSCCON<6:4>
111
110
101
100
011
010
001
000
31 kHz
INTRC
Source
Internal
Oscillator
Block
WDT, FSCM
8 MHz
Internal Oscillator
(INTOSC)
OSCCON<6:4>
Clock
Control OSCCON<1:0>
© 2006 Microchip Technology Inc. DS39605D-page 17
PIC18F1220/1320
REGISTER 2-2: OSCCON REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0
IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0
bit 7 bit 0
bit 7 IDLEN: Idle Enable bits
1 = Idle mode enabled; CPU core is not clocked in power managed modes
0 = Run mode enabled; CPU core is c lock ed in Run modes, but not Sle ep mode
bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111 = 8 MHz (8 MHz source drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (INTRC source drives clock directly)
bit 3 OSTS: Oscillator Start-up Time-out Status bit
1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2 IOFS: INTOSC Frequency Stable bit
1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable
bit 1-0 SCS1:SCS0: System Clock Select bits
1x = Internal oscillator block (RC modes)
01 = Timer1 oscillator (Secondary modes)
00 = Primary oscillator (Sleep and PRI_IDLE modes)
Note 1: Depends on state of the IESO bit in Configuration Register 1H.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 18 © 2006 Microchip Technology Inc.
2.7.2 OSCILLA TOR TR ANSIT ION S
The PIC18F1220/1320 devices contain circuitry to
prevent clocking “glitches” when switching between
clock sources. A short pause in the system clock
occurs during the clo ck switch. Th e length of thi s pause
is between 8 and 9 clock periods of the new clock
source. This ensures that the new clock source is
stable and that its pulse width will not be less than the
shortest pulse width of the two clock sources.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power Managed Modes”.
2.8 Effects of Power Managed Modes
on the Various Clock Sources
When the device executes a SLEEP instruction, the
system is switched to one of the power managed
modes, depending on the state of the IDLEN and
SCS1:SCS0 bits of the OSCCON register. See
Section 3.0 “Power Managed Modes” for details.
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if us ed by th e oscillat or) will stop oscil lating.
In Secondary Clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the system clock. The Timer1 oscillator may
also run in all power managed modes if required to
clock Timer1 or Timer3.
In Internal Oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the system clock
source. The INTRC output can be used directly to
provide the system clock and may be enabled to
support various special features, regardless of the
power managed mode (see Section 19.2 “Watchdog
Time r (WDT)” thro ugh Sect ion 19.4 “Fail-Sa fe Clock
Monitor”). The INT OSC out put at 8 MH z may be used
directly to clock the system, or may be divided down
first. The INT OSC output is disabl ed if the system cl ock
is provided directly from the INTRC output.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current cons umed during Sl eep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a real-
time cl ock. Ot her fea tures may be operat ing that d o not
require a system clock source (i.e., INTn pins, A/D
conversions and others).
2.9 Power-up Delays
Power-up delays are controlled by two timers, so that
no exte rna l Reset circuitry is re qui red fo r m os t a ppl ic a-
tions. The delays ensure that the device is kept in
Reset until the device powe r supply i s stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Sections 4.1 through 4.5.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 22-8) if enabled in Configuration Register 2L.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms following
the HS mode OST delay, so the PLL can lock to the
inco mi ng cl ock frequ enc y.
There is a delay of 5 to 10 μs following POR while the
controller becomes ready to execute instructions. This
delay runs concurrently with any other delays. This
may be the onl y delay that oc cu rs wh en any o f the EC ,
RC or INTIO modes are used as the primary clock
source.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode OSC1 Pin OSC2 Pin
RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output)
RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6
ECIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
LP, XT and HS Feedback inverter disabled at quiescent
voltage level Feedback inverter disabled at quiescent
voltage level
Note: See Table 4-1 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
© 2006 Microchip Technology Inc. DS39605D-page 19
PIC18F1220/1320
3.0 POWER MANAGED MODES
The PIC 18F122 0/1320 devic es o ffe r a tot al o f six oper-
ating modes for more efficient power management
(see Table 3-1). These provide a variety of options for
selective power conservation in applications where
resources may be limited (i.e., battery powered
devices).
There are three categories of power managed modes:
Sleep mode
Idle mo des
Run modes
These categories define which portions of the device
are clo cked and some times , what sp eed. The Ru n and
Idle modes may use any of the three available clock
sources (primary, secondary or INTOSC multiplexer);
the Sleep mode does not use a clock source.
The clock switching feature offered in other PIC18
devices (i.e., using the Timer1 oscillator in place of the
primary oscillator) and the Sleep mode offered by all
PICmicro® devices (where all system clocks are
stopped) are both offered in the PIC18F1220/1320
devices (SEC_RUN and Sleep modes, respectively).
However, additional power managed modes are avail-
able tha t allow t he user grea ter flexib ility in d eterminin g
what portions of the device are operating. The power
managed modes are event driven; that is, some
specific event must occur for the device to enter or
(more particularly) exit these operating modes.
For PIC18F1220/1320 devices, the power managed
modes are invoked by using the existing SLEEP
instruction. All modes exit to PRI_RUN mode when trig-
gered by an interrupt, a Reset or a WDT time-out
(PRI_RUN mode is the normal full power execution
mode; the C PU and peri phe rals are cl ock ed by the p ri-
mary oscillator source). In addition, power managed
Run modes may also exit to Sleep mode, or their
corresponding Idle mode.
3.1 Selecting Power Managed Modes
Selecting a power managed mode requires deciding if
the CPU is to be clocked or not and selecting a clock
source. The IDLEN bit controls CPU cloc king, while the
SCS1:SCS0 bits select a clock source. The individual
modes, bit settings, clock sources and affected
modules are summarized in Table 3-1.
3.1.1 CLOCK SOURCES
The clock source is selected by setting the SCS bits of
the OSCCON register (Register 2-2). Three clock
sources are available for use in power managed Idle
modes: the primary clock (as configured in Configuration
Register 1H), the secondary clock (Timer1 oscillator)
and the internal oscillator block. The secondary and
internal oscillator block sources are available for the
power managed modes (PRI_RUN mode is the normal
full power execution mode; the CPU and peripherals are
clocked by the primary os cilla to r source).
TABLE 3-1: POWER MANAGED MODES
Mode
OSCCON Bits Module Clocking
Available Clock and Oscillator Source
IDLEN
<7> SCS1:SCS0
<1:0> CPU Peripherals
Sleep 000 Off Off None – All clocks are disabled
PRI_RUN 000Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC(1)
This is the normal full pow er execution mode.
SEC_RUN 001Clocked Clocked Secondary – Timer1 Oscillator
RC_RUN 01xClocked Clocked Internal Oscillator Block(1)
PRI_IDLE 100 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE 101 Off Clocked Secondary – Timer1 Oscillator
RC_IDLE 11x Off Clocked Internal Oscillator Block(1)
Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
PIC18F1220/1320
DS39605D-page 20 © 2006 Microchip Technology Inc.
3.1.2 ENTERING POWER MANAGED
MODES
In general, entry, exit and switching between power
managed clock sources requires clock source
switching. In each case, the sequence of events is the
same.
Any change in the power managed mode begins with
loading the OSCCON register and executing a SLEEP
instruction. The SCS1:SCS0 bits select one of three
power managed clock sources; the primary clock (as
defined in Configuration Register 1H), the secondary
clock (the Timer1 oscillator) and the internal oscillator
block (use d in RC modes) . Modi fyi ng th e SCS bi ts will
have no effect until a SLEEP instruction is executed.
Entry to the power managed mode is triggered by the
execution of a SLEEP instruction.
Figure 3-5 shows how the system is clocked while
switching from the primary clock to the Timer1 oscilla-
tor. When the SLEEP instruction is executed, clocks to
the device are stopped at the beginning of the next
instruction cycle. Eight clock cycles from the new clock
source are counted to synchronize with the new clock
source. After eight clock pulses from the new clock
source are counted, clocks from the new clock source
resume clocking the system. The actual length of the
paus e is betwe en eight and nine cl ock peri ods from th e
new clock source. This ensures that the new clock
source is stab le a nd th at its puls e w idth will no t be l es s
than the shortest pulse width of the two clock sources.
Three bi t s in dicat e the current cloc k so urce: OSTS an d
IOFS in the OSCCON register and T1RUN in the
T1CON re gister. Only one of the se bit s will be se t while
in a power managed mode. When the OSTS bit is set,
the primary clock is providing the system clock. When
the IOFS bit is set, the INTOSC output is providing a
stable 8 MHz clock source and is providing the system
clock. When the T1RUN bit is set, th e Timer1 oscillator
is providing the system clock. If none of these bits are
set, then either the INTRC clock source is clocking the
system, or the INTOSC source is not yet stable.
If the internal oscillator block is configured as the pri-
mary clock source in Configuration Register 1H, then
both the OSTS and IOFS bits may be set when in
PRI_RUN or PRI_IDLE modes. This indicates that the
primary clock (INTOSC output) is generating a stable
8 MHz output. Entering an RC power managed mode
(same frequency) would clear the OSTS bit.
3.1. 3 MULTIPLE SLEEP COMMANDS
The power managed mode that is invoked with the
SLEEP instruction is determined by the settings of the
IDLEN and SCS bits at the time the instruction is exe-
cuted. If another SLEEP instruction is executed, the
device will enter the power managed mode specified b y
these same bits at that time. If the bits have changed,
the device will enter the new power managed mode
specified by the new bit settings.
3.1.4 COMPARISONS BETWEEN RUN
AND IDLE MODES
Clock source selection for the Run modes is identical to
the corresponding Idle modes. When a SLEEP instruc-
tion is executed, the SCS bits in the OSCCON register
are used to switch to a different clock source. As a
result, i f the re i s a ch ange of cloc k s ource at the time a
SLEEP instruction is executed, a clock switch will occu r.
In Idle modes, the CPU is not clocked and is not run-
ning. In Run modes, the C PU i s cl oc ked a nd ex ecuting
code. This difference modifies the operation of the
WDT when it times ou t. I n Id le mo des , a WDT tim e-o ut
results in a wake from power managed modes. In Run
modes, a WDT time-out results in a WDT Reset (see
Table 3-2).
During a wake-up from an Idle mode, the CPU starts
executing code by entering the corresponding Run
mode unt il the prima ry clock becomes read y. When the
primary cloc k bec omes ready, the cloc k so urce i s aut o-
matica lly switched to the prim ary clock. The I DLEN and
SCS bit s are un ch ang ed duri ng a nd af ter th e w ake-u p.
Figur e 3-2 shows how the system is clocked during the
clock source switch. The example assumes the device
was in SEC_IDLE or SEC_RUN mode when a wake is
triggered (the primary clock was configured in HSPLL
mode).
Note 1: Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
2: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode; executing a SLEEP instruction is
simply a tri gger to place th e controller in to
a power managed mode selected by the
OSCCON register, one of which is Sleep
mode.
© 2006 Microchip Technology Inc. DS39605D-page 21
PIC18F1220/1320
3.2 Sleep Mode
The power managed Sleep mode in the PIC18F1220/
1320 devices is identical to that offered in all other
PICmicro microcontrollers. It is entered by clearing the
IDLEN and SCS1:SCS0 bits (this is the Reset state)
and executing the SLEEP instr uctio n. T his shuts down
the primary oscillator and the OSTS bit is cleared (see
Figure 3-1).
When a wake even t occurs i n Sleep mo de (by int errupt,
Reset or WD T time-out), the sy stem wi ll not be cloc ked
until the primary clock source becomes ready (see
Figure 3-2), or it will be clocked from the internal
oscillator block if either the Two-Speed Start-up or the
Fail-Safe Clock Moni tor are enabled (see Section 19.0
“Special Features of the CPU”). In either case, the
OSTS bit is set whe n the primary c loc k is pro vi din g th e
system clocks. The IDLEN and SCS bits are not
affec ted by the wake-up.
3.3 Idle Modes
The IDLEN bit allows the microc ontroller ’s CPU to be
selectively shut down while the peripherals continue to
operat e. Clearing ID LEN allows the C PU to be cl ocked.
Setting IDLEN disables clocks to the CPU, effectively
stopping program execution (see Register 2-2). The
peripherals continue to be clocked regardless of the
setting of the IDLEN bit.
There is one exception to how the IDLEN bit functions.
When all the low-power OSCCON bits are cleared
(IDLEN:SCS1:SCS0 = 000), the device enters Sleep
mode upon the execution of th e SLEEP instruction. This
is both the Reset state of the OSCCON register and the
setting that selects Sleep mode. This maintains
compatibility with other PICmicro devices that do not
offer power managed modes.
If the Idle Enab le bit, IDLEN (OSCCON<7>), i s set to a
1’ when a SLEEP instruction is executed, the
peripherals will be clocked from the clock source
select ed using the SCS1:SCS0 bit s; however, the CPU
will not be clocked. Since the CPU is not executing
instructions, the only exits from any of the Idle modes
are by interrupt, WDT time-out or a Reset.
When a wake event occurs, CPU execution is delayed
approxi mately 10 μs whil e it becomes ready to e xecute
code. When the CPU begins executing code, it is
clocked by the same clock source as was selected in
the power managed mode (i.e., when waking from
RC_IDLE mode, the internal oscillator block will clock
the CPU an d periphe rals until the primary c lock so urce
becomes ready – this is essentially RC_RUN mode).
This continues until the primary clock source becomes
ready. When the primary clock becomes ready, the
OSTS bit is set and the system clock source is
switched to the primary clock (see Figure 3-4). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to full power
operation.
TABLE 3-2: COMPARISON BETWEEN POWER MANAGED MODES
Power
Managed
Mode CPU is Clocked by ... WDT Time-out
causes a ... Peripherals are
Clocked by ...
Clock during Wake-up
(while primary becomes
ready)
Sleep Not clocked (not running) Wake-up Not clocked None or INTOSC multiplexer
if Two-Speed Start-up or
Fail-Sa fe Cl ock Monitor are
enabled
Any Idle mode Not clocked (not running) Wake-up Primary, Secondary or
INTOSC multiplexer Unchanged from Idle mode
(CPU operates as in
corresponding Run mode)
Any Run mode Primary or secondary
clocks or INTOSC
multiplexer
Reset Primary or secondary
clocks or INTOSC
multiplexer
Unchanged from Run mode
PIC18F1220/1320
DS39605D-page 22 © 2006 Microchip Technology Inc.
FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE
FIGURE 3-2: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q4Q3Q2
OSC1
Peripheral
Sleep
Program
Q1Q1
Counter
Clock
CPU
Clock
PC + 2PC
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1 Q2 Q3 Q4 Q1 Q2
Clock
Counter PC + 8
PC + 6
Q1 Q2 Q3 Q4
Wake Event
Note 1: TOST = 1024 TOSC; T PLL = 2 ms (approx). Thes e intervals are not shown to scale.
TOST(1) TPLL(1)
OSTS bit Set
PC + 4
PC + 2
© 2006 Microchip Technology Inc. DS39605D-page 23
PIC18F1220/1320
3.3.1 PRI_IDLE MODE
This mode is unique among the three Low-Power Idle
modes, in that it does not disable the primary system
clock. For timing sensitive applications, this allows for
the faste st resump tion of device op eration with its more
accur ate prima ry clock sou rce, sinc e the clock s ource
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered by setting the IDLEN bit,
clearing the SCS bits and executing a SLEEP instruc-
tion. Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified in Configuration Register 1H. The OSTS bit
remains set in PRI_IDLE mode (see Figure 3-3).
When a wake event occurs, the CPU is clocked from
the primary clock source. A delay of approximately
10 μs is required between the wake event and code
execution starts. This is required to allow the CPU to
becom e re ady to exec ute inst ruct ion s. Af ter t he wa ke-
up, the O STS bit rem ains se t. The IDLE N and SCS bit s
are not affected by the wake-up (see Figure 3-4).
FIGURE 3-3: TRANSITION TIMING TO PRI_IDLE MODE
FIGURE 3-4: TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE
Q1
Peripheral
Program PC PC + 2
OSC1
Q3 Q4 Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program PC
CPU Clock
PC + 2
Q1 Q3 Q4
Clock
Counter
Q2
Wake Eve nt
CPU Start-up Delay
PIC18F1220/1320
DS39605D-page 24 © 2006 Microchip Technology Inc.
3.3.2 SEC_ID LE MODE
In SEC_IDLE mode, the CPU is disabled, but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered by setting the Idle bit,
modifying bits, SCS1:SCS0 = 01 and executing a
SLEEP instruction. When the clock source is switched
(see Figure 3-5) to the Timer1 oscillator, the primary
oscill ator is shut do wn, th e OSTS bit is cleared and the
T1RUN bit is set.
When a w ake event o ccurs, the pe ripherals contin ue to
be clocked from the Timer1 oscillator. After a 10 μs
delay following the wake event, the CPU begins exe-
cuting code, being clocked by the Timer1 osci llator . The
microcontroller operates in SEC_RUN mode until the
primary clock becomes ready. When the primary clock
become s ready , a clock switchback to the p rimary clock
occurs (see Figure 3-6). When the cloc k swit ch is com -
plete, the T1RUN bit is cleared, the OSTS bit is set and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up.
The Timer1 oscillator continues to run.
FIGURE 3-5: TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE
FIGURE 3-6: TIMING TRA NSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)
Note: The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
unti l th e os cilla tor has s tarte d; i n su ch sit -
uations, initial oscillator operation is far
from stable and unpredictable operation
may re sult.
Q4Q3Q2
OSC1
Peripheral
Program
Q1
T1OSI
Q1
Counter
Clock
CPU
Clock
PC + 2PC
12345678
Clock Transi tion
Q1 Q3 Q4
OSC1
Peripheral
Program PC PC + 2
T1OSI
PLL Clock
Q1
PC + 6
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 4
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake from Interrupt Event
TPLL(1)
12345678
Clock Transition
OSTS bit Set
TOST(1)
© 2006 Microchip Technology Inc. DS39605D-page 25
PIC18F1220/1320
3.3.3 RC_IDLE MODE
In RC_ID LE mode, the CPU is di sabled, but the periph-
erals co nti nue to b e c loc ke d fro m the internal oscilla tor
block using the INTOSC multiplexer. This mode allows
for cont rollable power c onservation during Idle periods.
This mode is entered by setting the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits be for e ex ecut in g the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer
(see Figure 3-7), the primary oscillator is shut down
and the OSTS bit is cleared.
If the IRCF bits are set to a non-zero value (thus,
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable, in about
1 ms. Clocks to the peripherals continue while the
INTOSC source stabilizes. If the IRCF bits were
previously at a non-zero value before the SLEEP
instruction was executed and the INTOSC source was
already st ab le, the IO FS bi t will rema in s et. If th e IRCF
bits are all cl ear, the INTOSC o utput is n ot enable d and
the IOFS bit will remai n clear; there will be no indicatio n
of the current clock source.
When a w ake event o ccurs, the pe ripherals contin ue to
be clocked fro m the INT OSC mu lti ple xe r. After a 10 μs
delay following the wake event, the CPU begins exe-
cuting co de, bein g clock ed by the INTOSC multi plexe r.
The microcontroller operates in RC_RUN mode until
the primary clock becomes ready. When the primary
clock becomes ready , a clock switchback to the primary
clock occurs (see F igure 3-8). W hen the clock sw itch is
complete, the IOFS bit is cleared, the OSTS bit is set
and the primary clock is providing the system clock.
The ID LEN a nd SC S b it s a re not affec ted by t he wake-
up. The INTRC source will continue to run if either the
WDT or the Fail-Safe Clock Monitor is enabled.
FIGURE 3-7: TIMING TRANSITION TO RC_IDLE MODE
FIGURE 3-8: TIMING TRANSITION FOR W AKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)
Q4Q3Q2
OSC1
Peripheral
Program
Q1
INTRC
Q1
Counter
Clock
CPU
Clock
PC + 2PC
12345678
Clock Transition
Q1 Q3 Q4
OSC1
Peripheral
Program PC PC + 2
INTOSC
PLL Clock
Q1
PC + 6
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 4
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake from Interrupt Event
TOST(1) TPLL(1)
12345678
Clock Transition
OSTS bit Set
Multiplexer
Q4
PIC18F1220/1320
DS39605D-page 26 © 2006 Microchip Technology Inc.
3.4 Run Modes
If the IDLEN bit is clear when a SLEEP instruction is
executed, the CPU and peripherals are both clocked
from the source selected using the SCS1:SCS0 bits.
While t hese operating mo des may not af ford the power
conservation of Idle or Sleep modes, they do allow the
device to continue executing instructions by using a
lower frequency clock source. RC_RUN mode also
offers the possibility of executing code at a frequency
great er than the primary cloc k .
Wake-up from a power managed Run mode can be
triggered by an interrupt, or any Reset, to return to full
power o pera tio n. As the CPU i s exec uti ng c od e in Run
modes, several additional exits from Run modes are
possib le. They inclu de exit to Sleep mode , exit to a cor-
responding Idle mode and exit by executing a RESET
instruction. While the device is in any of the power
managed Run modes, a WDT time-out will result in a
WDT R eset.
3.4.1 PRI_RUN MODE
The PRI_RUN mode is the normal full power execution
mode. If the SLEEP instruction is never executed, the
microc ontroller opera tes in this mode (a SLEEP instruc-
tion is executed to enter all other power managed
modes). All other power managed modes exit to
PRI_RUN mode when an interrupt or WDT time-out
occur.
There is no entry to PRI_RUN mode. The OSTS bit is
set. The IOFS bit may be set if the internal oscillator
block is the primary clock source (see Section 2.7.1
“Oscillator Control Register”).
3.4.2 SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clock ed from the T imer1 os cillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.
SEC_RUN mode is entered by clearing the IDLEN bit,
setting SCS1:SCS0 = 01 and executing a SLEEP
instr ucti on. Th e syste m clock source is switched to the
Timer1 oscillator (see Figure 3-9), the primary oscilla-
tor is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
When a wake event occurs, the peripherals and CPU
continue to be clocked from the Timer1 oscillator while
the primary clock is started. When the primary clock
become s ready , a clock switchback to the p rimary clock
occurs (see Figure 3-6). When the cloc k swit ch is com -
plete, the T1RUN bit is cleared, the OSTS bit is set and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up.
The Timer1 oscillator continues to run.
Firmware can force an exit from SEC_RUN mode. By
clearing the T1OSCEN bit (T1CON<3>), an exit from
SEC_RUN back to normal full power operation is trig-
gered. The Timer1 oscillator will continue to run and
provide the system clock, even though the T1OSCEN
bit is cleared. The primary clock is started. When the
primary clock becomes ready , a clock switchback to the
primary clock occurs (see Figure 3-6). When the clock
switch i s compl ete, the T imer1 oscil lator is disabled, the
T1RUN bit is cleared, the OSTS bit is set and the pri-
mary clock is providing the system clock. The IDLEN
and SCS bits are not affected by the wake-up.
FIGURE 3-9: TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE
Note: The Timer1 oscillator should already be
running pri or to entering SEC_RUN mod e.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, system clocks will be delayed
until the oscillator has started; in such
situations, initial oscillator operation is far
from stable and unpredictable operation
may re sult.
Q4Q3Q2
OSC1
Peripheral
Program
Q1
T1OSI
Q1
Counter
Clock
CPU
Clock
PC + 2PC
12345678
Clock Transition
Q4Q3
Q2 Q1 Q3
Q2
PC + 2
© 2006 Microchip Technology Inc. DS39605D-page 27
PIC18F1220/1320
3.4.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer and the primary clock is shut
down. When using the INTRC source, this mode pro-
vides the best power conservation of all the Run
modes, while still executing code. It works well for user
applic ations whic h are n ot highly tim ing sens itive, or d o
not requ ire high-speed clocks at all times.
If the primary clock source is the internal oscillator
block (ei ther of the INTIO1 or INTIO 2 oscill ators), there
are no distinguishable differences between PRI_RUN
and RC_RUN modes during execution. However, a
clock switch delay will occur during entry to and exit
from RC_RUN mode. Therefore, if the primary clock
source is the internal oscillator block, the use of
RC_RUN mode is not recommended.
This m ode i s e nte red by c lea rin g th e ID LEN b it, se ttin g
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The IRCF bits may select the clock
frequency before the SLEEP instruction is executed.
When the clock source is switched to the INTOSC
multiplexer (see Figure 3-10), the primary oscillator is
shut down and the OSTS bit is cleared.
The IRCF bits may be modified at any time to immedi-
ately change the system clock speed. Executing a
SLEEP instruction is not required to select a new clock
frequency from the INTOSC multiplexer.
If the IRCF bits are all clear, the INTOSC output is not
enabled and the IOFS bit wi ll remain clear; t here will b e
no indication of the current clock source. The INTRC
source is providing the system clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output bec omes st able. Cloc ks to
the system continue while the INTOSC source
stabilizes, in approximately 1 ms.
If the IRCF bits were previously at a non-zero value
before the SLEEP instruction was executed and the
INTOSC source was already stable, the IOFS bit will
remain set.
When a wa ke event occurs, the system conti nues to be
clock ed from the INT OSC multi plexer whi le the prim ary
clock is started. When the primary clock becomes
ready, a clock switch to the primary clock occurs (see
Figure 3-8). When the clock switch is complete, the
IOFS bit is c leared, the O STS bit is se t and the prim ary
clock is providing the system clock. The IDLEN and
SCS bits are not affected by the wake-up. The INTRC
source will continue to run if either the WDT or the
Fail- Safe Cloc k Mo nito r is enab led .
FIGURE 3-10: TIMING TRA NSITION TO RC_RUN MODE
Note: Cau tio n s hou ld be u se d w he n m odi fy ing a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
Q3Q2Q1
OSC1
Peripheral
Program
Q4
INTRC
Q4
Counter
Clock
CPU
Clock
PC + 2PC
12345678
Clock Transition
Q3Q2Q1 Q4 Q2Q1 Q3
PC + 4
PIC18F1220/1320
DS39605D-page 28 © 2006 Microchip Technology Inc.
3.4.4 EXIT TO IDLE MODE
An exit from a power managed Run mode to its
corresponding Idle mode is executed by setting the
IDLEN bit and executing a SLEEP instruction. The CPU
is halted at the beginning of the instructi on following the
SLEEP instruction. There are no changes to any of the
clock source status bits (OSTS, IOFS or T1RUN).
While th e CPU is halte d, the periphe rals c ontin ue to b e
clocked from the previously selected clock source.
3.4.5 EXIT TO SLEEP MODE
An exit from a power managed Run mode to Sleep
mode is executed by clearing the IDLEN and
SCS1:SCS0 bits and executing a SLEEP instruction.
The code is no different than the method used to invoke
Sleep mode from the normal operating (full power)
mode.
The primary clock and internal oscillator block are
disabled. The INTRC will continue to operate if the
WDT is enabled. The Timer1 oscillator will continue to
run, if enabled in the T1CON register (Register 12-1).
All clock source status bits are cleared (OSTS, IOFS
and T1RUN).
3.5 Wake from Power Managed Modes
An exit from any of the power managed modes is trig-
gered by an interrupt, a Reset or a WDT time-out. This
section discusses the triggers that cause exits from
power managed modes. The clocking subsystem
actions are discussed in each of the power managed
modes (see Sections 3.2 through 3.4).
Device behavior during Low-Power mode exits is
summa riz ed in Table 3-3.
3.5. 1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit a power managed mode and resume full
power operation. To enable this functionality, an inter-
rupt sou r ce mu st be e nab led by setti ng it s en able bit in
one of the IN TCON or PIE registers. Th e exit sequenc e
is initiated when the corresponding interrupt flag bit is
set. On all exits from Low-Power mode by interrupt,
code execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
Note: If application code is timing sensitive, it
should wait for the OSTS bit to become set
before continuing. Use the interval during
the low-power exit sequence (before
OSTS is set) to perform timing insensitive
“housekeeping” tasks.
© 2006 Microchip Technology Inc. DS39605D-page 29
PIC18F1220/1320
TABLE 3-3: ACTIVITY AND EXIT DELAY ON WAKE FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock in Power
Managed Mode Primary System
Clock
Power
Managed
Mode Exit
Delay
Clock Ready
Status Bit
(OSCCON)
Activity during Wake-up from
Power Managed Mode
Exit by Interrupt Exit by Reset
Primary System
Clock
(PRI_IDLE mode)
LP, XT, HS
5-10 μs(5) OSTS CPU and peripherals
clocked by primary
clock and executing
instructions.
Not cl ocked or
Two-Speed Start-up
(if enabled)(3).
HSPLL
EC, RC, INTRC(1)
INTOSC(2) IOFS
T1OSC or
INTRC(1)
LP, XT, HS OST OSTS CPU and peripherals
clocked by selected
power m an age d mo de
clock and executing
instructions until
primary clock source
becomes ready.
HSPLL OST + 2 ms
EC, RC, INTRC(1) 5-10 μs(5)
INTOSC(2) 1ms
(4) IOFS
INTOSC(2)
LP, XT, HS OST OSTS
HSPLL OST + 2 ms
EC, RC, INTRC(1) 5-10 μs(5)
INTOSC(2) None IOFS
Sleep mode
LP, XT, HS OST OSTS Not clocked or
Two-S pee d Start-up (if
enabled) unti l prim ary
clock source becomes
ready(3).
HSPLL OST + 2 ms
EC, RC, INTRC(1) 5-10 μs(5)
INTOSC(2) 1ms
(4) IOFS
Note 1: In this instance, refers specifically to the INTRC clock source.
2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3: Two-Speed Start-up is covered in greater detail in Section 19 .3 “Two-Speed Start-up”.
4: Execution continues during the INTOSC stabilization period.
5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other
required delays (see Section 3.3 “Idle Modes”).
PIC18F1220/1320
DS39605D-page 30 © 2006 Microchip Technology Inc.
3.5. 2 EXIT BY RESET
Normally, the device is held in Reset by the Oscillator
St art-up Timer (O ST) until th e primary clo ck (defined in
Configuration Register 1H) becomes ready. At that
time, the OSTS bit is set and the device begins
executing code.
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 19.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 19.4 “Fail-Safe Clock
Monitor”) are enabled in Configuration Register 1H,
the device may begin execution as soon as the Reset
source has cleared. Execution is clocked by the
INTOSC multiplexer driven by the internal oscillator
block. Since the OSCCON register is cleared following
all Resets, the INTRC clock source is selected. A
higher speed clock may be selected by modifying the
IRCF bits in the OSCCON register. Execution is
clocked by the internal oscillator block until either the
primary clock becomes ready, or a power managed
mode is entered before the primary clock becomes
ready; the primary clock is then shut down.
3.5.3 EXIT BY WDT TIME-OUT
A WDT time -out will caus e diffe rent action s, dependin g
on which power managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in a wake from the
power managed mode (see Sections 3.2 through 3.4).
If the device is executing code (all Run modes), the
time-out will result in a WDT Reset (see Section 19.2
“Watchdog Timer (WDT)”).
The WDT timer and postscaler are cleared by
executing a SLEEP or CLRWDT instru ction, the loss of a
currently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is the
system clock source.
3.5.4 EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power managed modes do not
invoke the OST at all. These are:
PRI_IDLE mode, where the primary clock source
is not stopped; or
the primary clock source is not any of LP, XT, HS
or HSPLL modes.
In these cases, the primary clock source either does
not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes).
However, a fixed delay (appro xi ma tel y 10 μs) f ollowing
the wak e event is required when leaving Sleep an d Idle
modes. This delay is required for the CPU to prepare
for execution. Instruction execution resumes on the first
clock cycle following this delay.
3.6 INTOSC Frequency Drift
The factory calibrates the internal oscillator block
output (INT OSC) for 8 MHz (see Tabl e 22-6). However ,
this frequency may drift as VDD or temperature
changes, which can affect the controller operation in a
variety of ways.
It is possible to adjust the INTOSC frequency by
modifying the value in the OSCTUNE register
(Register 2-1). This has the side effect that the INTRC
clock source frequency is also affected. However, the
features that use the INTRC source often do not require
an exact frequency . These features include the Fail-Safe
Clock Monitor, the Watchdog Timer and the RC_RUN/
RC_IDLE modes when the INTRC clock source is
selected.
Being able to adjust the INTOSC requires knowing
when an adjustment is required, in which direction it
should be made and in some cases, how large a
change is needed. Three examples follow but other
techniques may be used.
© 2006 Microchip Technology Inc. DS39605D-page 31
PIC18F1220/1320
3.6.1 EXAMPLE – EUSART
An adjustment may be indicated when the EUSART
begins to generate framing errors, or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the system clock frequency is too high –
try decrem enting the valu e in the OSCTUNE reg ister to
reduce the system clock frequency. Errors in data may
suggest that the system clock speed is too low –
increm ent OSCTUNE.
3.6.2 EXAMPLE – TIMERS
This technique compares system clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Tim er1 oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is greater than expected, then the internal oscillator
block is running too fast – decrement OSCTUNE.
3.6.3 EXAMPLE – CCP IN CAPTURE
MODE
A CCP module can use free running Timer1 (or
Timer 3), cl oc ke d by th e int ernal oscilla tor bl ock and an
external event with a known period (i.e., AC power
frequenc y). The ti me of the first ev ent is c aptured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the firs t eve nt is su btra cte d fro m the tim e of th e
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast – decrement OSCTUNE. If the measured time
is much less than the calculated time, the internal
oscillator block is running too slow – increment
OSCTUNE.
PIC18F1220/1320
DS39605D-page 32 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS39605D-page 33
PIC18F1220/1320
4.0 RESET
The PIC18F1220/1320 devices differentiate between
various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during Sleep
d) Watchdog Ti mer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Inst ruction
g) Stack Full Reset
h) Stack Underflow Reset
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state”, depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register
(Register 4-1), RI, TO, PD, POR and BOR, are set or
cleared differently in different Reset situations, as
indicated in Table 4-2. These bits are used in software
to determ in e t he nature of the Reset. See Table 4-3 for
a full description of the Reset states of all registers.
A simplif ied block diagra m of the On-Chip Rese t Circu it
is sh own i n Figure 4-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
The MC LR pin is not driven low by any internal Resets,
inc luding the WDT.
The MCLR input provided by the MCLR pin can be
disabled with the MCLRE bit in Configuration
Regi ster 3H (CONFIG3H< 7>).
FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External Reset
MCLR
VDD
OSC1
WDT
Time-out
VDD Rise
Detect
OST/PWRT
INTRC
(1)
POR Pulse
OST
10-bit Ripple Counter
PWRT
Chip_Reset
11-bit Ripple Counter
Enable OST(2)
Enable PWRT
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 4-1 for time-out situations.
Brown-out
Reset BOR
RESET
Instruction
Stack
Pointer Stack Full/Underflow Reset
Sleep
( )_IDLE
1024 Cycles
65.5 ms
32 μs
MCLRE
PIC18F1220/1320
DS39605D-page 34 © 2006 Microchip Technology Inc.
4.1 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR
circuitry, just tie the MCLR pin through a resistor (1k to
10 kΩ) to VDD. This will eliminate external RC compo-
nents usually needed to create a Power-on Reset
delay. A minimum rise rate for VDD is specified
(param eter D004) . For a slow rise t ime, see Figure 4-2.
When the device start s normal operation (i.e ., ex its the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
FIGURE 4-2: EXTERN AL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
4.2 Power-up Timer (PWRT)
The Power-up T imer (PWRT) of the PIC18F1220/1320 is
an 11-bit counter, which uses the INTRC source as the
clock input. This yields a count of 2048 x 32 μs=65.6ms.
While the PWRT is counting, the device is held in Reset.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC
parameter 33 for details.
The PWRT is enabled by clearing configuration bit,
PWRTEN.
4.3 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from most low-power modes.
4.4 PLL Lock Time -out
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A portion of the
Power-up Timer is used to provi de a fix ed time-ou t that
is suf ficie nt for t he PLL to l ock to the main oscillator f re-
quency. This PLL lock time-out (TPLL) is typically 2 ms
and follows the Oscillator Start-up Time-out.
4.5 Brown-out Reset (BOR)
A configuration bit, BOR, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If VDD falls below VBOR (parameter D005) for
greate r than TBOR (p arameter 35) , the brown-o ut situa-
tion will reset the chip. A Reset may not occur if VDD
falls below VBOR for less than TBOR. The chip will
remain in Brown-out Reset until VDD rises above VBOR.
If the Powe r-up T imer is enabled, i t will be invo ked after
VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay, TPWRT
(parameter 33). If VDD drops below VBOR while the
Power-up Timer is running, the chip will go back into a
Brown-ou t Reset and the Power-up T imer will be initia l-
ized. Once VDD rises abov e VBOR, the Power-up T imer
will execute the additional time delay. Enabling BOR
Reset does not automatically enable the PWRT.
4.6 Time-out Sequence
On power-up, the time-out sequence is as follows:
First, afte r t he POR pul se has cle are d, PWRT time-o ut
is inv oked (if e nabled). Th en, the OS T is activa ted. The
tot al time-o ut wi ll var y base d on o scill ator co nfi guratio n
and the st atus of the PWRT. For exam pl e, in R C mod e
with the PWR T disabled , there wi ll be no time-out at all.
Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and
Figure 4-7 depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long e nough, all ti me-outs wi ll exp ire. Brin g-
ing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
Table 4-2 s hows the Re set condi tions for so me Specia l
Function Registers, while Table 4-3 shows the Reset
conditions for all the registers.
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in t he event
of MCLR/VPP pin breakdown due t o Electro-
static Discharge (ESD) or Electrical
Overstress (EOS).
C
R1
R
D
VDD
MCLR
PIC18FXXXX
VDD
© 2006 Microchip Technology Inc. DS39605D-page 35
PIC18F1220/1320
TABLE 4-1: TIME-OUT IN VARIOUS SITUATIONS
REGISTER 4-1: RCON REGISTER BITS AND POSITIONS
TABLE 4-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Oscillator
Configuration
Power-up(2) and Brown-out Exit from
Low-Power Mode
PWRTEN = 0PWRTEN = 1
HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 10 24 TOSC + 2 ms(2) 1024 TOSC + 2 ms (2)
HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
EC, ECIO 66 ms(1) 5-10 μs(3) 5-10 μs(3)
RC, RCIO 66 ms(1) 5-10 μs(3) 5-10 μs(3)
INTIO1, INTIO2 66 ms(1) 5-10 μs(3) 5-10 μs(3)
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time requi red for the 4x PLL to lock.
3: The program memory bias start-up time is always invoked on POR, wake-up from Sleep, or on any exit
from power managed mode that disables the CPU and instruction execution.
R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
IPEN —RITO PD POR BOR
bit 7 bit 0
Note: Refer to Section 5.14 “RCON Re gister” for bit definit io ns.
Condition Program
Counter RCON
Register RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 0--1 1100 1 1 1 0 0 0 0
RESET Inst ruction 0000h 0--0 uuuu 0 u u u u u u
Brown-out 0000h 0--1 11u- 1 1 1 u 0 u u
MCLR during Power Managed
Run modes 0000h 0--u 1uuu u 1 u u u u u
MCLR during Power Managed
Idle modes and Sleep 0000h 0--u 10uu u 1 0 u u u u
WDT Time-out during Full
Power or Power Managed Run 0000h 0--u 0uuu u 0 u u u u u
MCLR during Full Power
Execution 0000h 0--u uuuu u u u u u
uu
Stack Full Reset (STVR = 1)1u
Stack Underflow Reset
(STVR = 1)u1
Stack Underflow Error (not an
actual Reset, STVR = 0)0000h u--u uuuu u u u u u u 1
WDT Time-out during Power
Managed Idle or Sleep PC + 2 u--u 00uu u 0 0 u u u u
Interrupt Exit from Power
Managed modes PC + 2 u--u u0uu u u 0 u u u u
Legend: u = unchanged, x = unknown, = unimplemented bit, read as ‘0
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
inter rupt ve cto r (0x00 000 8h or 0x00 001 8h ).
PIC18F1220/1320
DS39605D-page 36 © 2006 Microchip Technology Inc.
TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable
Devices Power-on Rese t,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU 1220 1320 ---0 0000 ---0 0000 ---0 uuuu(3)
TOSH 1220 1320 0000 0000 0000 0000 uuuu uuuu(3)
TOSL 1220 1320 0000 0000 0000 0000 uuuu uuuu(3)
STKPTR 1220 1320 00-0 0000 00-0 0000 uu-u uuuu(3)
PCLATU 1220 1320 ---0 0000 ---0 0000 ---u uuuu
PCLATH 1220 1320 0000 0000 0000 0000 uuuu uuuu
PCL 1220 1320 0000 0000 0000 0000 PC + 2(2)
TBLPTRU 1220 1320 --00 0000 --00 0000 --uu uuuu
TBLPTRH 1220 1320 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 1220 1320 0000 0000 0000 0000 uuuu uuuu
TABLAT 1220 1320 0000 0000 0000 0000 uuuu uuuu
PRODH 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 1220 1320 0000 000x 0000 000u uuuu uuuu(1)
INTCON2 1220 1320 1111 -1-1 1111 -1-1 uuuu -u-u(1)
INTCON3 1220 1320 11-0 0-00 11-0 0-00 uu-u u-uu(1)
INDF0 1220 1320 N/A N/A N/A
POSTINC0 1220 1320 N/A N/A N/A
POSTDEC0 1220 1320 N/A N/A N/A
PREINC0 1220 1320 N/A N/A N/A
PLUSW0 1220 1320 N/A N/A N/A
FSR0H 1220 1320 ---- 0000 ---- 0000 ---- uuuu
FSR0L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 1220 1320 N/A N/A N/A
POSTINC1 1220 1320 N/A N/A N/A
POSTDEC1 1220 1320 N/A N/A N/A
PREINC1 1220 1320 N/A N/A N/A
PLUSW1 1220 1320 N/A N/A N/A
FSR1H 1220 1320 ---- 0000 ---- 0000 ---- uuuu
FSR1L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cell s ind ic ate co nditions do not apply for the desig nat ed dev ic e.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the w ake -up is due to a n in terru pt a nd the G IEL or G IEH b it i s set, the TO SU, TOSH and TOSL ar e
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 5 of PORTA is enabled if MCLR is disabled.
© 2006 Microchip Technology Inc. DS39605D-page 37
PIC18F1220/1320
BSR 1220 1320 ---- 0000 ---- 0000 ---- uuuu
INDF2 1220 1320 N/A N/A N/A
POSTINC2 1220 1320 N/A N/A N/A
POSTDEC2 1220 1320 N/A N/A N/A
PREINC2 1220 1320 N/A N/A N/A
PLUSW2 1220 1320 N/A N/A N/A
FSR2H 1220 1320 ---- 0000 ---- 0000 ---- uuuu
FSR2L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 1220 1320 ---x xxxx ---u uuuu ---u uuuu
TMR0H 1220 1320 0000 0000 0000 0000 uuuu uuuu
TMR0L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 1220 1320 1111 1111 1111 1111 uuuu uuuu
OSCCON 1220 1320 0000 q000 0000 q000 uuuu qquu
LVDCON 1220 1320 --00 0101 --00 0101 --uu uuuu
WDTCON 1220 1320 ---- ---0 ---- ---0 ---- ---u
RCON(4) 1220 1320 0--1 11q0 0--q qquu u--u qquu
TMR1H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 1220 1320 0000 0000 u0uu uuuu uuuu uuuu
TMR2 1220 1320 0000 0000 0000 0000 uuuu uuuu
PR2 1220 1320 1111 1111 1111 1111 1111 1111
T2CON 1220 1320 -000 0000 -000 0000 -uuu uuuu
ADRESH 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 1220 1320 00-0 0000 00-0 0000 uu-u uuuu
ADCON1 1220 1320 -000 0000 -000 0000 -uuu uuuu
ADCON2 1220 1320 0-00 0000 0-00 0000 u-uu uuuu
CCPR1H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 1220 1320 0000 0000 0000 0000 uuuu uuuu
PWM1CON 1220 1320 0000 0000 0000 0000 uuuu uuuu
ECCPAS 1220 1320 0000 0000 0000 0000 uuuu uuuu
TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable
Devices Power-on Rese t,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cell s ind ic ate co nditions do not apply for the desig nat ed dev ic e.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the w ake -up is due to a n in terru pt a nd the G IEL or G IEH b it i s set, the TO SU, TOSH and TOSL ar e
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 5 of PORTA is enabled if MCLR is disabled.
PIC18F1220/1320
DS39605D-page 38 © 2006 Microchip Technology Inc.
TMR3H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 1220 1320 0-00 0000 u-uu uuuu u-uu uuuu
SPBRGH 1220 1320 0000 0000 0000 0000 uuuu uuuu
SPBRG 1220 1320 0000 0000 0000 0000 uuuu uuuu
RCREG 1220 1320 0000 0000 0000 0000 uuuu uuuu
TXREG 1220 1320 0000 0000 0000 0000 uuuu uuuu
TXSTA 1220 1320 0000 0010 0000 0010 uuuu uuuu
RCSTA 1220 1320 0000 000x 0000 000x uuuu uuuu
BAUDCTL 1220 1320 -1-1 0-00 -1-1 0-00 -u-u u-uu
EEADR 1220 1320 0000 0000 0000 0000 uuuu uuuu
EEDATA 1220 1320 0000 0000 0000 0000 uuuu uuuu
EECON2 1220 1320 0000 0000 0000 0000 0000 0000
EECON1 1220 1320 xx-0 x000 uu-0 u000 uu-0 u000
IPR2 1220 1320 1--1 -11- 1--1 -11- u--u -uu-
PIR2 1220 1320 0--0 -00- 0--0 -00- u--u -uu-(1)
PIE2 1220 1320 0--0 -00- 0--0 -00- u--u -uu-
IPR1 1220 1320 -111 -111 -111 -111 -uuu -uuu
PIR1 1220 1320 -000 -000 -000 -000 -uuu -uuu(1)
PIE1 1220 1320 -000 -000 -000 -000 -uuu -uuu
OSCTUNE 1220 1320 --00 0000 --00 0000 --uu uuuu
TRISB 1220 1320 1111 1111 1111 1111 uuuu uuuu
TRISA(5) 1220 1320 11-1 1111(5) 11-1 1111(5) uu-u uuuu(5)
LATB 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
LATA(5) 1220 1320 xx-x xxxx(5) uu-u uuuu(5) uu-u uuuu(5)
PORTB 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA(5,6) 1220 1320 xx0x 0000(5,6) uu0u 0000(5,6) uuuu uuuu(5,6)
TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable
Devices Power-on Rese t,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cell s ind ic ate co nditions do not apply for the desig nat ed dev ic e.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the w ake -up is due to a n in terru pt a nd the G IEL or G IEH b it i s set, the TO SU, TOSH and TOSL ar e
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 5 of PORTA is enabled if MCLR is disabled.
© 2006 Microchip Technology Inc. DS39605D-page 39
PIC18F1220/1320
FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTER N AL PO R
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
PIC18F1220/1320
DS39605D-page 40 © 2006 Microchip Technology Inc.
FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL R ESET
0V 1V 5V
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note: TOST = 1024 clock cycles.
TPLL 2 ms max. First three stages of the PWRT timer.
© 2006 Microchip Technology Inc. DS39605D-page 41
PIC18F1220/1320
5.0 MEMORY ORGANIZATION
There are three memory types in Enhanced MCU
devices. Th ese memory types are:
Program Memory
Data RAM
Data EEPROM
Data and program memory use separate busses,
which allows for concur rent access of thes e types.
Addition al detai led informat ion for Flas h program mem-
ory and data EEPROM is provided in Section 6.0
“Flash Program Memory” and Section 7.0 “Data
EEPROM Memory”, respec tiv el y.
FIGURE 5-1: PROGRAM MEMORY MAP
AND STACK FOR
PIC18F1220
5.1 Program Memory Organization
A 21-b it progr am count er is capab le of ad dressin g the
2-Mb yte prog ram m emo ry space. Ac ces s ing a l ocation
between the physically implemented memory and the
2-Mbyte address will cause a read of all ‘0’s (a NOP
instruction).
The PIC18F1220 has 4 Kbytes of Flash memory and
can store up to 2,048 single-word instructions.
The PIC18F1320 has 8 Kbytes of Flash memory and
can store up to 4,096 single-word instructions.
The Rese t vector addres s is at 0000h and the interru pt
vector addresses are at 0008h and 0018h.
The program memory maps for the PIC18F1220 and
PIC18F1320 devices are shown in Figure 5-1 and
Figure 5-2, respectively.
FIGURE 5-2: PROGRAM MEMORY MAP
AND STACK FOR
PIC18F1320
PC<20:0>
Stack Level 1
Stack Level 31
Reset Vector
Low Priority Interrupt Vector
CALL,RCALL,RETURN
RETFIE,RETLW
21
0000h
0018h
On-Chip
Program Memory
High Priority Interrupt Vector 0008h
User Memo ry Spa ce
1FFFFFh
1000h
0FFFh
Read ‘0
200000h
PC<20:0>
Stack Level 1
Stack Level 31
Reset Vector
Low Priority Interrupt Vector
CALL,RCALL,RETURN
RETFIE,RETLW
21
0000h
0018h
2000h
1FFFh
On-Chip
Program Mem ory
High Priority Interrupt Vector 0008h
User Memo ry Space
Read ‘0
1FFFFFh
200000h
PIC18F1220/1320
DS39605D-page 42 © 2006 Microchip Technology Inc.
5.2 Return Address Stack
The return address s t ac k al low s any comb in atio n of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALL or RCALL instruction is executed, or an interrupt
is Acknowledged. The PC value is pulled off the stack
on a RETURN, RETLW or a RETFIE instruction. PCLA TU
and PCLATH are not affected by any of the RETURN or
CALL instructi ons .
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the Stack Pointer initialized to
00000B after all Resets. There is no RAM associated
with Stack Pointer, 00000B. This i s o nly a R e se t valu e.
During a CALL type instruction, causing a push onto the
stack, the Stack Pointer is first incremented and the
RAM location pointed to by the Stack Pointer
(STKPTR) registe r is written with the contents of the PC
(already pointing to th e instructio n following the CALL).
During a RETURN type instruction, causing a pop from
the stack, the contents of the RAM location pointed to
by the STKPTR are transferred to the PC and then the
Stack Pointer is decremented.
The stack space is not part of either program or data
space. The Stack Pointer is readable and writable and
the address on the top of the stack is readable and
writable through the top-of-stack Special File
Registers. Data can also be pushed to or popped from
the stack using the top-of-stack SFRs. Status bits
indicate if the stack is full, has overflowed or
underflowed.
5.2.1 TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL, hold the
contents of the stack location pointed to by the
STKPTR register (Figure 5-3). This allows users to
implement a software st a ck if ne ces s ary. After a CALL,
RCALL or interrupt, the software can read the pushed
value by reading the TOSU, TOSH and TOSL registers.
These v alues can b e placed on a u ser define d software
stack. At return time, the software can replace the
TOSU, TOSH and TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
5.2.2 RETURN STACK POINTER
(STKPTR)
The STKP TR reg ister (Re giste r 5-1) co nta ins the st ack
pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. At Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System for return stack maintenance.
After t he PC is pus hed on to the st ack 31 times (wi thout
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVR (Stack Overflow
Reset Enabl e) configura tion bit. (Re fer to Section 19.1
“Configuration Bits for a description of the device
configuration bits.) If STVR is set (default), the 31st
push wil l push the ( PC + 2) value o nto the st ack, set th e
STKFUL bit and reset the device. The STKFUL bit will
remain set and the Stack Pointer will be set to zero.
If STVR is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload th e stack, the ne xt pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or a POR occurs.
FIGURE 5-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Note: Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
00011
001A34h
11111
11110
11101
00010
00001
00000
00010
Return Address Stack
Top-of-Stack 000D58h
TOSLTOSHTOSU 34h1Ah00h STKPTR<4:0>
© 2006 Microchip Technology Inc. DS39605D-page 43
PIC18F1220/1320
REGISTER 5-1: STKPTR REGISTER
5.2.3 PUSH AND POP INSTRUCTIONS
Since the Top- of-Stack (T OS ) is rea dab le a nd w ritable,
the abili ty to push v alues onto the stac k and pull values
off t he st ack, wit hout distu rbing norm al program ex ecu-
tion, is a d esirable optio n. To push th e current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the Stack Pointer and load the cur-
rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place data or a return address
on the stack.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP inst ruction. T he POP instru c-
tion discards the current TOS by decrementing the
Stack Pointer. The previous value pushed onto the
stack then becomes the TOS value.
5.2.4 ST ACK FULL/UNDERFLOW RESETS
These Resets are enabled by programming the STVR
bit in Configuration Register 4L. When the STVR bit is
cleared , a ful l or u nderflow co ndi tio n will set the app ro-
priate STKFUL or STKUNF bit, but not cause a device
Reset. When the STVR bit is set, a full or underflow
condition will set the appropriate STKFUL or STKUNF
bit and then cause a device Reset. The STKFUL or
STKUNF bits are cleared by the user software or a
Power-on Reset.
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL STKUNF SP4 SP3 SP2 SP1 SP0
bit 7 bit 0
bit 7(1) STKFUL: Stack Full Flag bit
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6(1) STKUNF: Stack Underflow Flag bit
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5 Unimplemented: Read as 0
bit 4-0 SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bi t 6 are cleared by user software or by a POR.
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 44 © 2006 Microchip Technology Inc.
5.3 Fast Register St ack
A “fast return” option is available for interrupts. A fast
register stack is provided for the Status, WREG and
BSR regist ers and is only one in depth. The sta ck is not
readable or writable and is loaded with the current
value o f the correspo nding registe r when the pro cessor
vectors for an interrupt. The values in the registers are
then loaded back into the working registers, if the
RETFIE, FAST instruction is used to return from the
interrupt.
All interrupt sources will push values into the stack
registers. If both low and high priority interrupts are
enabled, the stack registers cannot be used reliably to
return from lo w priority interrupt s. If a high pri ority inter-
rupt occurs while servicing a low priority interrupt, the
stac k reg is ter v al ues s tor ed by the l ow p r iori ty in terru pt
will be overwritten. Users must save the key registers
in software during a low priority interrupt.
If interrupt pri ority is not used, all interrupts may use the
fast register stack for returns from interrupt.
If no interrupts are used, the fast register stack can be
used to rest ore the S tatus, WREG and BSR register s at
the end of a subroutine call. To use the fast register
stack for a subroutine call, a CALL LABEL, FAST
instruction must be executed to save the Status,
WREG and BSR registers to the fast register stack. A
RETURN, FAST instruction is then ex ec uted to restore
these registers from the fast register stack.
Example 5-1 shows a source code example that uses
the fast register stack during a subroutine call and
return.
EXAMPLE 5-1: FAST REGISTER STACK
CODE EXAMPLE
5.4 PCL, PCLATH and PCLATU
The Program Counter (PC) spec ifies the addres s of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte, known as the PCL register, is both
readable and writable. The high byte, or PCH register,
cont ains th e PC<15 :8> bit s and is not direc tly read able
or writable. Updates to the PCH register may be per-
formed th rough the PCLATH regis ter . The upper by te is
called PCU. This register contains the PC<20:16> bits
and is not directly readable or writable. Updates to the
PCU register may be performed through the PCLATU
register.
The contents of PCLATH and PCLATU will be
transferred to the program counter by any operation
that writes PCL. Similarly, the upper two bytes of the
program counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 5.8.1
“Compu ted GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of PCL is fixed to a value of ‘0’.
The PC increments by 2 to address sequential
instruc t ion s in the prog ram memo ry.
The CALL, RCALL, GOTO and program branch instruc-
tions write to the program counter directly. For these
instruc tion s, the content s of PC LATH an d PCLATU are
not transferred to the program counter.
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
RETURN, FAST ;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
© 2006 Microchip Technology Inc. DS39605D-page 45
PIC18F1220/1320
5.5 Clocking Scheme/Instruction
Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the
Program Counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 5-4.
5.6 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q 4). The instructio n fe tch and ex ecu te a r e
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then tw o cycles are req uired to com plete the ins truction
(Example 5-2).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the ex ecution cycle , the fetched instruction i s latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q 3 and Q4 c ycles. Data mem ory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-4: CLOCK/INSTRUCTION CYCLE
EXAMPLE 5-2: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC Mode)
PC PC + 2 PC + 4
Fetch INST (PC)
Execute IN ST (P C – 2)
Fetch IN ST (PC + 2)
Execute IN ST (PC)
Fetch INST (PC + 4)
Execute IN ST (PC + 2)
Internal
Phase
Clock
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
PIC18F1220/1320
DS39605D-page 46 © 2006 Microchip Technology Inc.
5.7 Instructi ons in Program Memory
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). Figure 5-5 shows an
exampl e of how instruc tion word s are stored i n the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ‘0’ (see Section 5.4 “PCL,
PCLATH and PCLATU”).
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruc-
tion. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to
PC<20:1 >, which accesses the des ired byte address i n
program memory. Instruction #2 in Figure 5-5 shows
how the instruction ‘GOTO 000006h’ is enc ode d in th e
program memory. Program branch instructions, which
encode a relative address offset, operate in the same
manner. The of fs et v alu e s tore d in a br an ch ins truc tio n
represents the number of single-word instructions that
the PC wi ll be off set by. Section 20.0 “I nstruction Set
Summary” provides further details of the instruction
set.
FIGURE 5-5: INS TRUCTIONS IN PROGRAM MEMORY
5.7.1 TW O-WORD INSTRUCTIONS
PIC18F1220/1320 devices have four two-word
instructions: MOVFF, CALL, GOTO a nd LFSR. The second
word of thes e instructions has the 4 MSBs set to ‘1’s and
is decoded as a NOP instruction. The lower 12 bit s of the
second word contain data to be used by the instruction.
If the first word of the instruction is executed, the data in
the second word is accessed. If the second word of the
instruction is exe cuted by it sel f (first word was skipped),
it will execute as a NOP. This action is necessary when
the two-word instruction is preceded by a conditional
instruction that results in a skip operation. A program
example that demonstrates this concept is shown in
Example 5-3. Refer to Section 20.0 “Instruction Set
Summary” for further details of the instruction set.
EXAMPLE 5-3: TWO-WORD INSTRUCTIONS
Word Address
LSB = 1LSB = 0
Program Memory
Byte Locations 000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 000006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code
© 2006 Microchip Technology Inc. DS39605D-page 47
PIC18F1220/1320
5.8 Look-up Tables
Look-up tables are implemented two ways:
Computed GOTO
Table Reads
5.8.1 COMPUTED GOTO
A comput ed GOTO is a ccom pli shed by addi ng a n offset
to the program counter (see Example 5-4).
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
execut ing a c al l to tha t table. Th e fi rst instructi on of th e
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions, that returns the value 0xnn to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSB = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 5-4: COMPUTED GOTO USING
AN OFFSET VALUE
5.8.2 TABLE READS/TABLE WRITES
A better method of storing data in program memory
allow s two bytes of dat a to be stored in each instruc tion
location.
Look-up table data may be stored two bytes per pro-
gram word by using table reads and writes. The Table
Pointer (TBLPTR) register specifies the byte address
and the Table Latch (TABLAT) register contains the
data that is read from or written to program memory.
Data is transferred to/from program memory, one byte
at a time.
The table read/table write operation is discussed
further in Section 6.1 “Table Reads and Table
Writes”.
5.9 Data Memory Organization
The data memory is im ple me nte d as static RAM . Eac h
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 5-6
shows the data memory organization for the
PIC18F1220/1320 devices.
The data memory map is divided into as many as
16 banks that contain 256 bytes eac h. The lowe r 4 bits
of the Bank Select Register (BSR<3:0>) select which
bank w ill be acce ssed. The upper 4 bit s for the BSR are
not implemented.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and periph eral function s, while GPRs ar e used for dat a
storage and scratch pad operations in the user’s appli-
cation. The SFRs start at the last location of Bank 15
(FFFh) and extend towa rds F80h. Any remaining sp ace
beyond the SFRs in the Bank may be implemented as
GPRs. GPRs start at the first location of Bank 0 and
grow up w ards . An y re ad of a n un im ple me nte d l ocation
will read as ‘0’s.
The entire data memory may be accessed directly or
indirec tly. Dir ect add ress in g m ay re qui re th e us e of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and a corresponding Indi-
rect File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the Data Memory map without banking. See
Section 5.12 “Indirect Addressing, INDF and FSR
Registers” for indirect addressing details.
The instruction set and architecture allow operations
across all banks . This may be acc omplished by indirec t
address ing or by the us e of th e MOVFF instruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is imp lemented. A segm ent of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 5.10
“Access Bank” provides a detailed description of the
Access RAM.
5.9.1 GENERAL PURPOSE
REGISTER FILE
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
Data RAM is available for use as GPR registers by all
instructions. The second half of Bank 15 (F80h to
FFFh) contains SFRs. All other banks of data memory
contain GPRs, starting with Bank 0.
MOVFW OFFSET
CALL TABLE
ORG 0xnn00
TABLE ADDWF PCL
RETLW 0xnn
RETLW 0xnn
RETLW 0xnn
.
.
.
PIC18F1220/1320
DS39605D-page 48 © 2006 Microchip Technology Inc.
FIGURE 5-6: DATA MEMORY MAP FOR PIC18F1220/1320 DEVICES
Bank 0
Bank 14
Bank 15
Data Me mo r y Map
BSR<3:0>
= 0000
= 1111
080h
07Fh
F80h
FFFh
00h
7Fh
80h
FFh
Access Bank
When a = 0,
The BSR is ignored and the
Access Bank is used.
The first 128 bytes are
General Purpose RAM
(from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
The B SR spe ci fie s th e Ba nk
used by the inst ruct ion.
F7Fh
F00h
EFFh
0FFh
000h
Access RAM
FFh
00h
FFh
00h
GPR
SFR
Unused
Access RAM High
Access RAM Low
Bank 1
to Unused
Read ‘00h’
= 1110
= 0001 (SFRs)
© 2006 Microchip Technology Inc. DS39605D-page 49
PIC18F1220/1320
5.9.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 5-1 and Table 5-2.
The SFRs can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are descri bed i n t his s ection, while those rel ate d
to the operation of the peripheral features are
describ ed in the se cti on of that peri pheral feature.
The SFRs are typically distributed among the peripherals
whose functions they control.
The unused SFR locations will be unimplemented and
read as ‘0’s.
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F1220/1320 DEVICES
Address Name Address Name Address Name Address Name
FFFh TOSU FDFh INDF2(2) FBFh CCPR1H F9Fh IPR1
FFEh TOSH FDEh POSTINC2(2) FBEh CCPR1L F9Eh PIR1
FFDh TOSL FDDh POSTDEC2(2) FBDh CCP1CON F9Dh PIE1
FFCh STKPTR FDCh PREINC2(2) FBCh F9Ch
FFBh PCLATU FDBh PLUSW2(2) FBBh F9Bh OSCTUNE
FFAh PCLATH FDAh FSR2H FBAh F9Ah
FF9h PCL FD9h FSR2L FB9h F99h
FF8h TBLPTRU FD8h STATUS FB8h F98h
FF7h TBLPTRH FD7h TMR0H FB7h PWM1CON F97h
FF6h TBLPTRL FD6h TMR0L FB6h ECCPAS F96h
FF5h TABLAT FD5h T0CON FB5h F95h
FF4h PRODH FD4h FB4h F94h
FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB
FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA
FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h
FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h
FEFh INDF0(2) FCFh TMR1H FAFh SPBRG F8Fh
FEEh POSTINC0(2) FCEh TMR1L FAEh RCREG F8Eh
FEDh POSTDEC0(2) FCDh T1CON FADh TXREG F8Dh
FECh PREINC0(2) FCCh TMR2 FACh TXSTA F8Ch
FEBh PLUSW0(2) FCBh PR2 FABh RCSTA F8Bh
FEAh FSR0H FCAh T2CON FAAh BAUDCTL F8Ah LATB
FE9h FSR0L FC9h FA9h EEADR F89h LATA
FE8h WREG FC8h FA8h EEDATA F88h
FE7h INDF1(2) FC7h FA7h EECON2 F87h
FE6h POSTINC1(2) FC6h FA6h EECON1 F86h
FE5h POSTDEC1(2) FC5h FA5h F85h
FE4h PREINC1(2) FC4h ADRESH FA4h F84h
FE3h PLUSW1(2) FC3h ADRESL FA3h F83h
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB
FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA
Note 1: Unimplement ed registers are read as 0’.
2: This is not a physical register.
PIC18F1220/1320
DS39605D-page 50 © 2006 Microchip Technology Inc.
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F1220/1320)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Details on
page:
TOSU Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 36, 42
TO SH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 36, 42
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 36, 42
STKPTR STKFUL STKUNF Return S tack Pointer 00-0 0000 36, 43
PCLATU —bit 21
(3) Holding Register for PC<20:16> ---0 0000 36, 44
PCLATH Holding Regi st er for PC<15: 8> 0000 0000 36, 44
PCL PC Low Byte (PC<7:0>) 0000 0000 36, 44
TBLPTRU bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 36, 60
TBLPTRH Program Memory Table P ointe r High Byte (TBLPTR<15:8>) 0000 0000 36, 60
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 36, 60
TABLAT Program Memory Table Latch 0000 0000 36, 60
PRODH Product Register High Byte xxxx xxxx 36, 71
PRODL Product Register Low Byte xxxx xxxx 36, 71
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 36, 75
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 36, 76
INTCON3 INT2IP INT1IP —INT2IEINT1IE INT2IF INT1IF 11-0 0-00 36, 77
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 36, 53
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 36, 53
POSTDEC0 Uses contents of FSR0 to address data memory– value of FSR0 post-decremented (not a physical register) N/A 36, 53
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 36, 53
PLUSW0 Uses contents of FS R0 to address data memor y – value of FSR0 offset by W (not a physical register) N/A 36, 53
FSR0H Indirect Data Memory Address Pointer 0 High ---- 0000 36, 53
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 36, 53
WREG Worki ng Regi s ter xxxx xxxx 36
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 36, 53
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 36, 53
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 36, 53
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 36, 53
PLUSW1 Uses contents of FS R1 to address data memor y – value of FSR1 offset by W (not a physical register) N/A 36, 53
FSR1H Indirect Data Memory Address Pointer 1 High ---- 0000 36, 53
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 36, 53
BSR Bank Select Register ---- 0000 37, 52
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 37, 53
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 37, 53
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 37, 53
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 37, 53
PLUSW2 Uses contents of FS R2 to address data memor y – value of FSR2 offset by W (not a physical register) N/A 37, 53
FSR2H Indirect Data Memory Address Pointer 2 High ---- 0000 37, 53
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 37, 53
STATUS —NOVZDCC---x xxxx 37, 55
TMR0H Timer0 Register High Byte 0000 0000 37, 101
TMR0L Timer0 Register Low Byte xxxx xxxx 37, 101
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 37, 99
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 q000 37, 17
LVDCON IVRST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 37, 167
WDTCON —SWDTEN--- ---0 37, 180
RCON IPEN —RITO PD POR BOR 0--1 11q0 35, 56, 84
Legend: x = unknow n , u = unchanged, – = unimpl emented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read ‘0
in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RA5 reads ‘0’. This bit is read-only.
© 2006 Microchip Technology Inc. DS39605D-page 51
PIC18F1220/1320
TMR1H Timer1 Register High Byte xxxx xxxx 37, 108
TMR1L Timer1 Register Low Byte xxxx xxxx 37, 108
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 37, 103
TMR2 Timer2 Register 0000 0000 37, 109
PR2 Timer2 Period Register 1111 1111 37, 109
T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 37, 109
ADRESH A/D Result Register High Byte xxxx xxxx 37, 164
ADRESL A/D Result Register Low Byte xxxx xxxx 37, 164
ADCON0 VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 37, 155
ADCON1 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 37, 156
ADCON2 ADFM ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 37, 157
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 37. 116
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 37, 116
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 37, 115
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 37, 126
ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 37, 127
TMR3H Timer3 Register High Byte xxxx xxxx 38, 113
TMR3L Timer3 Register Low Byte xxxx xxxx 38, 113
T3CON RD16 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 38, 111
SPBRGH EUSART Baud Rate Generator High Byte 0000 0000 38
SPBRG EUSART Baud Rate Generator Low Byte 0000 0000 38, 135
RCREG EUSART Receive Register 0000 0000 38, 143,
142
TXREG EUSART Transmit Register 0000 0000 38, 140,
142
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 38, 132
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 38, 133
BAUDCTL RCIDL —SCKPBRG16 WUE ABDEN -1-1 0-00 38
EEADR EEPROM Address Register 0000 0000 38, 67
EEDATA EEPROM Data Register 0000 0000 38, 70
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 38, 58, 67
EECON1 EEPGD CFGS FREE WRERR WREN WR RD xx-0 x000 38, 59, 68
IPR2 OSCFIP —EEIP LVDIP TMR3IP 1--1 -11- 38, 83
PIR2 OSCFIF EEIF —LVDIFTMR3IF0--0 -00- 38, 79
PIE2 OSCFIE —EEIE LVDIE TMR3IE 0--0 -00- 38, 81
IPR1 ADIP RCIP TXIP CCP1IP TMR2IP TMR1IP -111 -111 38, 82
PIR1 ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF -000 -000 38, 78
PIE1 ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE -000 -000 38, 80
OSCTUNE TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 38, 15
TRISB Data Direction Control Register for PORTB 1111 1111 38, 98
TRISA TRISA7(2) TRISA6(1) Data Direc tion C on trol R egist er for PORTA 11-1 1111 38, 89
LATB Read/Write PORTB Data Latch xxxx xxxx 38, 98
LATA LATA<7>(2) LATA<6>(1) Read/Write PORTA Data Latch xx-x xxxx 38, 89
PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 38, 98
PORTA RA7(2) RA6(1) RA5(4) Read PORTA pins, Write PORTA Data Latch xx0x 0000 38, 89
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F1220/1320) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Details on
page:
Legend: x = unknow n , u = unchanged, – = unimpl emented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read ‘0
in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RA5 reads ‘0’. This bit is read-only.
PIC18F1220/1320
DS39605D-page 52 © 2006 Microchip Technology Inc.
5.10 Access Bank
The Access Bank is an architectural enhancement
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
This data memory region can be used for:
Intermediate computational values
Local variables of subroutines
Faster context saving/switching of variables
Comm on va riab les
Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the last 128 bytes in
Bank 15 (SFRs) and the first 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 5-6
indicates the Access RAM areas.
A bit in the instruc tio n w ord sp ec ifie s if the opera tion is
to occur i n the bank sp ec ifi ed by the BSR regis ter o r in
the Access Bank. This bit is denoted as the ‘a’ bit (for
access bit).
When forced in the Access Bank (a = 0), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function Registers, so these registers can
be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
5.11 Bank Select Register (BSR)
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
parti tion ed into as ma ny as sixtee n ban ks. When using
direct addressing, the BSR should be configured for the
desired bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ‘0’s and
writes will have no effect (see Figure 5-7).
A MOVLB instruction has been provided in the instruction
set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all 0’s and all writes are ignored. The
S tatus register bit s will be set/cleared as appro priate for
the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A MOVFF ins truct ion ig nores the BS R, sin ce th e 12- bit
addresses are embedded into the instruction word.
Section 5.12 “Indirect Addressing, INDF and FSR
Registers” provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
FIGURE 5-7: DIRECT ADDRESSING
Note 1: For register file map detail, see Table 5-1.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers
of the Access Bank.
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data
Memory(1)
Direct Addres sing
Bank Select(2) Location Select(3)
BSR<3:0> 7 0
From Opcode(3)
00h 01h 0Eh 0Fh
Bank 0 Bank 1 Bank 14 Bank 15
1FFh
100h
0FFh
000h
EFFh
E00h
FFFh
F00h
BSR<7:4>
0000
© 2006 Microchip Technology Inc. DS39605D-page 53
PIC18F1220/1320
5.12 Indirect Addressing, INDF and
FSR Registers
Indir ect addressing is a mod e of addressing dat a mem-
ory, where the data memory address in the instruction
is not fi xe d. An FSR reg is ter i s u se d as a poi nter to the
data memory locat ion that is to be read or written. Since
this poi nter i s in RAM, the con ten t s c an be mo difi ed by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 5-8
shows how the fetched instruction is modified prior to
being executed.
Indirect addressing is possible by using one of the
INDF registers. Any instruction, using the INDF regis-
ter, actually acce sses the reg ister poin ted to by the Fil e
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = 0), will read 00h. Writing to the INDF
register indirectly, results in a no operation (NOP). The
FSR regi ster cont ains a 12 -bit add ress, which is shown
in Figure 5-9.
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addr essing.
Exampl e 5-5 shows a s imple use o f indirect add ressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 5-5: HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bit wide. To store the 12 bits of
addressing information, tw o 8-bit registers are required:
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the ad dress of the data. If an i nstruct ion w rite s a
value t o IN DF0, the val ue w ill be wr itt en to t he address
pointed to by FSR0H:FSR0L. A read f rom INDF 1 reads
the data from the address pointed to by
FSR1H:FSR1L. INDFn can be used in code anywhere
an operand can be used.
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all ‘0s are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivale nt to a NOP instruction and the
Status bits are not affected.
5.12.1 INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register ass ociated with
it, plus four additional register addresses. Performing an
operation using one of these five registers determines
how the FSR will be modified during indirect addressing.
When data access is performed using one of the five
INDFn locations, the address selected will configure
the FSRn register to:
Do nothing to FSRn after an indirect access (no
change) – INDFn
Auto-decr ement FSRn after an indirect access
(post-decrement) – POSTDECn
Auto-increment FSRn after an indirect access
(post-increment) – POSTINCn
Auto- inc rement FS Rn befo re an indirect access
(pre-increment) – PREINCn
Use the value in the WREG register as an offset
to FSRn . Do not modif y the value of the WREG or
the FSRn register after an indirect access (no
change) – PLUSWn
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
Status register. For example, if the indirect address
causes the FSR to equal ‘0’, the Z bit will not be set.
Auto-incrementing or auto-decrementing an FSR affects
all 12 bits. That is, when FSRnL overflows from an
increment, FSRnH will be incremented automatically.
Adding these features allows the FSRn to be used as a
stac k pointer, in addition to it s uses for tab le operation s
in d ata me mory.
Each FSR has an address associated with it that
performs an indexed indirect access. When a data
access to this INDFn location (PLUSWn) occurs, the
FSRn is configured to add the signed value in the
WREG register and the value in FSR to form the
address before an indirect access. The FSR value is
not cha nge d. The WR EG offset ran ge is -128 to +1 27 .
If an FSR regist er conta ins a value that poin ts to one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(Status bits are not affected).
If an indirect addressing write is performed when the tar-
get address is an FSRnH or FSRnL register, the data is
writte n to the F SR regist er , but no pre- or p ost-inc rement/
decrement is performed.
LFSR FSR0,0x100 ;
NEXT CLRF POSTINC0 ; Clear INDF
; register then
; inc pointer
BTFSS FSR0H, 1 ; All done with
; Bank1?
GOTO NEXT ; NO, clear next
CONTINUE ; YES, continue
PIC18F1220/1320
DS39605D-page 54 © 2006 Microchip Technology Inc.
FIGURE 5-8: INDIRECT ADDRESSING OPERATION
FIGURE 5-9: INDIRECT ADDRESSING
Opcode Address
File Address = Access of an Indirect Addressing Register
FSR
Instruction
Executed
Instruction
Fetched
RAM
Opcode File
12
12
12
BSR<3:0>
8
4
0h
FFFh
Note 1: For register file map detail, see Table 5-1.
Data
Memory(1)
Indirect Addressing
FSRnH:FSRnL
30
0FFFh
0000h
Location Select
11 0
07
© 2006 Microchip Technology Inc. DS39605D-page 55
PIC18F1220/1320
5.13 Status Register
The S tatus register , shown in Register 5-2, contains the
arithmetic status of the ALU. As with any other SFR, it
can be the operand for any inst ruc tio n.
If the Status register is the destina tion for an instruction
that af fect s the Z, DC, C, OV or N bit s, the result s of the
instruction are not written; instead, the status is
updated accord ing to t he inst ruct ion pe rformed. The re-
fore, the res ul t of an ins tru cti on w i th the Status regis ter
as its destinatio n may be dif ferent than intended . As an
example, CLRF STATUS will set the Z bit and leave the
remaining Status bits unchanged (‘000u u1uu’).
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the Status reg-
ister, because thes e instruction s do not a ffect the Z, C ,
DC, OV or N bits in the Status register.
For other i ns truc tio ns that do not a ffect Status bi t s , se e
the instruction set summaries in Table 20-1.
REGISTER 5-2: STATUS REGISTER
Note: The C and DC bits operate as the borrow
and digit borrow bits, respectively, in
subtraction.
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
—NOVZDCC
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0
bit 4 N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1 = Result was neg ative
0 = Result was positive
bit 3 OV: Ov erf low bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude, which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (i n this ari thmetic operation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digi t carry/bor row bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the
2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit
is loaded with either the bit 4 or bit 3 of the source register.
bit 0 C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the
2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit
is loaded with either the high or low-order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 56 © 2006 Microchip Technology Inc.
5.14 RCON Register
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device Reset. These flags include the TO, PD, POR,
BOR and RI bi ts. Thi s register is re adable an d writ able.
REGISTER 5-3: RCON REGISTER
Note 1: If the BOR configu ration bit is set (Bro wn-
out Reset enabled), the BOR bit is ‘1’ on
a Power-on Reset. After a Brown-out
Reset has occurred, the BOR bit will be
cleared and must be set by firmware to
indicate the occurrence of the next
Brown-out Reset.
2: It is re commended that the POR bit be set
after a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detect ed.
R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN —RITO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset
(must be set in software after a Brown-out Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT instructi on
0 = Cleared by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Br own-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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6.0 FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks o f 8 bytes at a ti me . Pro gram m em ory is er ase d
in bloc ks of 64 by tes at a time. A “Bu lk Erase” oper ation
may not be issued from user code.
While writing or erasing program memory, instruction
fetches cease until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value wri tten to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
6.1 Table Reads and Table Writes
In order to read and write program memory, there are
two o per atio ns that al low the proc ess or t o mov e byt es
between the program memory space and the data
RAM:
Table Read (TBLRD)
Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program
memory and place it into TABLAT in the data RAM
space. Figure 6-1 shows the operation of a table read
with program memo ry and data RAM.
Table write operations store data from TABLAT in the
data memory space into holding registers in program
memory. The procedure to write the contents of the
holding registers into program memory is detailed in
Section 6.5 “Writing to Flash Program Memory”.
Figure 6-2 shows the operation of a table write with
program memory and data RAM.
Table operations work with byte entities. A table block
cont aining dat a, rather than program instruct ions, is not
required to be word aligned. Therefore, a table block
can st art and en d at any by te address. If a tab le write is
being used to write executable code into program
memory, program instructions will need to be word
aligned (TBLPTRL<0> = 0).
The EEPROM on-chip timer controls the write and
erase times. The write and erase voltages are gener-
ated by an on-chip charge pump rated to operate over
the voltage range of the device for byte or word
operations.
FIGURE 6-1: TABLE READ OPERATION
Table Pointer(1) Table Latch (8-bit)
Program Mem ory
TBLPTRH TBLPTRL TABLAT
TBLPTRU
Instruction: TBLRD*
Note 1: Table Pointer points to a byte in program memory.
Program Me mory
(TBLPTR)
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FIGURE 6-2: TABLE WRITE OPERATION
6.2 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
6.2.1 EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit , EEPGD, dete rmine s if the a cc ess wil l be to
program or data EEPROM memory. When clear,
operations will access the data EEPROM memory.
When set, program memory is accessed.
Control bit, CFGS, determines if the access will be to
the confi guratio n regis ters, or to p rogram mem ory/da ta
EEPROM memory. When set, subsequent operations
access configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
The FREE bit controls program memory erase opera-
tions. When the FREE bit is set, the erase operation is
initiated on the next WR command. When FREE is
clear, only writes are enabled.
The WREN bit enables and disables erase and write
operations. When set, erase and write operations are
allowed. When clear, erase and write operations are
disabl ed – the WR bit cannot be set w hile the W REN bit
is cle ar . Thi s proces s help s to pre vent accid ental writes
to memory du e to errant (unexp ected) code execution.
Firmware should keep the WREN bit clear at all times,
except when starting erase or write operations. Once
firmware has set the WR bit, the WREN bit may be
cleared. Clearing the WREN bit will not affect the
operation in progress.
The WRERR bit is set when a write operation is
interrupte d by a Reset. In these situati ons, the user ca n
check the WRERR bit and rewrite the location . It will b e
necessary to reload the data and address registers
(EEDAT A and EEAD R) as these registers have cleare d
as a result of the Reset.
Control bits, RD and WR, start read and erase/write
operatio ns, respectiv ely . Thes e bits are se t by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructio ns. See Se ction 6.3 “Reading the
Flash Program Memory” regarding table reads.
Table Pointer(1) Table Latch (8-bit)
TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
TBLPTRU
Instruction: TBLWT*
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by
TBLPTRL<2:0>. The process for physically writing data to the program mem o ry array is discuss ed
in Section 6.5 “Writing to Flash Program Memory”.
Holding Registers
Program Mem ory
Note: Interru pt flag bi t, EEIF in t he PIR2 regi ster,
is set when the write is complete. It must
be cleared in sof tw are.
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REGISTER 6-1: EECON1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS FREE WRERR WREN WR RD
bit 7 bit 0
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access pro gram Fl ash memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EE or Configuration Select bit
1 = Access configuration registers
0 = Access program Flash or data EEPROM memory
bit 5 Unimplemented: Read as0
bit 4 FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation – TBLPTR<5:0> are ignored)
0 = Perform write onl y
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation was prematurely terminated (any Reset during self-timed programming)
0 = The write operation completed normally
Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
bit 2 WREN: Write Enable bit
1 = Allows eras e or write cycles
0 = Inhibits erase or write cycles
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operatio n is self- timed and the bit is cleared by hard ware once wri te is comple te. The
WR bit can only be set (not cleared) in software.)
0 = Write cycle completed
bit 0 RD: Read Control bit
1 = Initiates a memory read
(Read t akes one cycle. R D is cleared in ha rdware. The RD bit can only be set (not cleare d)
in software. RD bit cannot be set when EEPGD = 1.)
0 = Read completed
Legend:
R = Readable bit S = Settable only U = Unimplemented bit, read as ‘0’
W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
x = Bit is unknown
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6.2.2 TABLAT – TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR spa ce. The table latch is use d to hold 8-bit
data during data transfers between program memory
and data RAM.
6.2.3 TBLPTR – TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. Setting the 22nd bit allows
access to the device ID, the user ID and the
configuration bits.
The Table Pointer (TBLPTR) register is used by the
TBLRD and TBLWT instructi ons . T hes e i ns truc t io ns ca n
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 6-1. Th ese operations on th e TBLPTR onl y affect
the low-orde r 21 bi ts.
6.2.4 TABLE POINTER BOUNDARIES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the Table
Pointer determine which byte is read from program or
configuration memory into TABLAT.
When a TBLWT is executed, the three LSbs of the Table
Pointer (TBLPTR<2:0>) determine which of the eight
program memory holding registers is written to. When
the timed write to program memory (long write) begins,
the 19 MSbs of the Table Pointer (TBLPTR<21:3>) will
determine which program memory block of 8 bytes is
written to (TBLPTR<2:0> are ignored). For more detail,
see Section 6.5 “Writing to Flash Program Memory”.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer (TBLP TR<21 :6>) point to
the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION
Example Operation on Table Pointer
TBLRD*
TBLWT* TBLPTR is not modif ied
TBLRD*+
TBLWT*+ TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*- TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+* TBLP TR is incr em en ted before the read /write
21 16 15 87 0
ERASE – TBLPTR<21:6>
LONG WRITE – TBLPTR<21:3>
READ or WRITE – TBLPTR<21:0 >
TBLPTRL
TBLPTRH
TBLPTRU
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6.3 Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and place it into data RAM. Table
reads fro m program memory are pe rformed one byte at
a time.
TBLPTR points to a byte address in program space.
Executing a TBLRD instruction places the byte pointed
to into TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The interna l program memory is typically org anized by
words. The Least Significan t bit of th e address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY
EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD
Odd (High) Byte
Program Memory
Even (Low) Byte
TABLAT
TBLPTR
Instruction Register
(IR) Read Register
LSB = 1
TBLPTR
LSB = 0
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_WORD
TBLRD*+ ; read into TABLAT and increment TBLPTR
MOVFW TABLAT ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment TBLPTR
MOVFW TABLAT ; get data
MOVWF WORD_ODD
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6.4 Erasing Flash Program Memory
The minimum erase block size is 32 words or 64 bytes
under firmware control. Only through the use of an
external programmer, or through ICSP control, can
larger blo cks of program m emory be bulk eras ed. Word
erase in Flash memory is not supported.
When initiating an erase sequence from the micro-
controll er itsel f, a block of 64 by tes of program me mory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
The EECON1 regis te r com ma nds the era se operation.
The EEPGD bit must be set to point to the Flash
program memory. The CFGS bit must be clear to
access program Flash and data EEPROM memory.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. The
WR bit is set as part of the required instruction
sequence (as shown in Example 6-2) and starts the
actual erase operation. It is not necessary to load the
TABLAT register with any data as it is ignored.
For protection, the write initiate sequence using
EECON2 must be used.
A long w rite i s nec essary for erasing th e inte rnal Fl ash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
program ming timer.
6.4.1 FLASH PROGRAM MEMORY
ERAS E S EQ UE N CE
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer with address of row being
erased.
2. Set the EECON1 register for the erase operation:
set EEPGD bit to point to program memory;
clear the CFGS bit to access program
memory;
set WREN bit to enable writes;
set FREE bit to enable the erase.
3. Disable int errup ts.
4. Write 55h to EECON2.
5. Write AAh to EECON2.
6. Set the WR bit. This will begin the row erase
cycle.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
8. Execute a NOP.
9. Re-enable interrupts.
EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_ROW
BSF EECON1, EEPGD ; point to FLASH program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
MOVWF EECON2 ; write 55H
Required MOVLW AAh
Sequence MOVWF EECON2 ; write AAH
BSF EECON1, WR ; start erase (CPU stall)
NOP
BSF INTCON, GIE ; re-enable interrupts
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6.5 Writing to Flash Program Memory
The programming block size is 4 words or 8 bytes.
Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 8 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction must be executed 8 times for
each programming operation. All of the table write
operations will essentiall y be short wri tes, because only
the hold ing re gisters are w ritte n. At the end of upda ting
8 registers , the EECON1 register must be w ritten to, to
start the programming operation with a long write.
The long write is necessary for programming the
internal Flash. Ins tructio n execu tion is halted whil e in a
long write cycle. The long write will be terminated by
the internal programming timer.
FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY
6.5.1 FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1. Read 64 bytes into R AM.
2. Update data values in RAM as necessary.
3. Load Table Pointer with address being erased.
4. Do the row erase procedure (see Section 6.4.1
“Flash Program Memory Erase Sequence”).
5. Load Table Pointer with address of first byte
being written.
6. Write the first 8 bytes into the holding registers
with auto-increment.
7. Set the EECON 1 register for the wri te operation:
set EEPGD bit to point to program memory;
clear the CFGS bit to access program
memory;
set WREN bit to enable byte writes.
8. Disable int errup ts.
9. Write 55h to EECON2.
10. Write AAh to EECON2.
11. Set the WR bit. This will begin the w rite cy cl e.
12. The CPU wil l st all for d uration o f the write (about
2 ms using internal timer).
13. Execute a NOP.
14. Re-enable interrupts.
15. Repeat steps 6-14 seven times to write
64 bytes.
16. Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
Holding Register
TABLAT
Holding Register
TBLPTR = xxxxx7
Holding Register
TBLPTR = xxxxx1
Holding Register
TBLPTR = xxxxx0
88 8 8
Write Register
TBLPTR = xxxxx2
Program Memory
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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW D'64 ; number of bytes in erase block
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW ; 6 LSB = 0
MOVWF TBLPTRL
READ_BLOCK
TBLRD*+ ; read into TABLAT, and inc
MOVF TABLAT, W ; get data
MOVWF POSTINC0 ; store data and increment FSR0
DECFSZ COUNTER ; done?
GOTO READ_BLOCK ; repeat
MODIFY_WORD
MOVLW DATA_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW DATA_ADDR_LOW
MOVWF FSR0L
MOVLW NEW_DATA_LOW ; update buffer word and increment FSR0
MOVWF POSTINC0
MOVLW NEW_DATA_HIGH ; update buffer word
MOVWF INDF0
ERASE_BLOCK
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW ; 6 LSB = 0
MOVWF TBLPTRL
BCF EECON1, CFGS ; point to PROG/EEPROM memory
BSF EECON1, EEPGD ; point to FLASH program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h ; Required sequence
MOVWF EECON2 ; write 55H
MOVLW AAh
MOVWF EECON2 ; write AAH
BSF EECON1, WR ; start erase (CPU stall)
NOP
BSF INTCON, GIE ; re-enable interrupts
WRITE_BUFFER_BACK
MOVLW 8 ; number of write buffer groups of 8 bytes
MOVWF COUNTER_HI
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
PROGRAM_LOOP
MOVLW 8 ; number of bytes in holding register
MOVWF COUNTER
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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
6.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
6.5.3 UNEXPECTED TERMINATION OF
WRITE OPERATION
If a wri te is term in ate d by an unpl an ned ev en t, s uc h a s
loss of power or an unexpected Reset, the memory
locatio n jus t progra mmed shou ld be verifi ed and repr o-
grammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset, or a
WDT T im e-out Reset during norm al operation. In these
situati ons, users c an check the WRERR bit and rewri te
the location.
6.6 Flash Program Operation Duri ng
Code Protection
See Section 19.0 “Special Features of the CPU” for
details on code protection of Flash program memory.
TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
WRITE_WORD_TO_HREGS
MOVF POSTINC0, W ; get low byte of buffer data and increment FSR0
MOVWF TABLAT ; present data to table latch
TBLWT+* ; short write
; to internal TBLWT holding register, increment
TBLPTR
DECFSZ COUNTER ; loop until buffers are full
GOTO WRITE_WORD_TO_HREGS
PROGRAM_MEMORY
BCF INTCON, GIE ; disable interrupts
MOVLW 55h ; required sequence
MOVWF EECON2 ; write 55H
MOVLW AAh
MOVWF EECON2 ; write AAH
BSF EECON1, WR ; start program (CPU stall)
NOP
BSF INTCON, GIE ; re-enable interrupts
DECFSZ COUNTER_HI ; loop until done
GOTO PROGRAM_LOOP
BCF EECON1, WREN ; disable write to memory
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
TBLPTRU bit 21 Program Memory Table Pointer Upper Byte (TBLP TR<20 :16>) --00 0000 --00 0000
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000
TBLPTRL Program Mem ory Table Pointer High Byte (TBLPTR<7:0>) 0000 0000 0000 0000
TABLAT Program Memory Table Latch 0000 0000 0000 0000
INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
EECON2 EEPROM Control Register 2 (not a physical register) ——
EECON1 EEPGD CFGS FREE WRERR WREN WR RD xx-0 x000 uu-0 u000
IPR2 OSCFIP —EEIP LVDIP TMR3IP 1--1 -11- 1--1 -11-
PIR2 OSCFIF —EEIF LVDIF TMR3IF 0--0 -00- 0--0 -00-
PIE2 OSCFIE —EEIE LVDIE TMR3IE 0--0 -00- 0--0 -00-
Legend: x = unknown, u = unchanged, – = unimplemented, read as0’.
Shaded cells are not used during Flash/EEPROM access.
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NOTES:
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7.0 DATA EEPROM MEMORY
The data EEPROM is readable and writable during
normal operation over the entire VDD ra nge. The d ata
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).
There are four SFRs used to read and write the
program and data EEPROM memory. These registers
are:
EECON1
EECON2
EEDATA
EEADR
The EEPROM dat a memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 256 bytes of data EEPROM with
an address range from 00h to FFh.
The EEPROM data memory is rated for high erase/
write cycle endurance. A byte write automatically
erases the location and writes the new data (erase-
befor e-write). The wr ite time is control led by an on- chip
timer. The write time will vary with voltage and
temperature, as well as from chip to chip. Please
refer to parameter D122 (Table 22-1 in Section 22.0
“Electri cal Characteristics”) for exact limits.
7.1 EEADR
The address register can address 256 bytes of data
EEPROM.
7.2 EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit , EEPGD, dete rmine s if the a cc ess wil l be to
program or data EEPROM memory. When clear,
operations will access the data EEPROM memory.
When set, program memory is accessed.
Control bit, CFGS, determines if the access will be to
the configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
The WREN bit enables and disables erase and write
operations. When set, erase and write operations are
allowed. When clear, erase and write operations are
disabl ed – the WR bit cannot be set w hile the W REN bit
is clear. This mechanism helps to prevent accidental
writes to memory due to errant (unexpected) code
execution.
Firmware should keep the WREN bit clear at all times,
except when starting erase or write operations. Once
firmware has set the WR bit, the WREN bit may be
cleared. Clearing the WREN bit will not affect the
operation in progress.
The WRERR bit is set when a write operation is
interrupte d by a Reset. In these situati ons, the user ca n
check the WRERR bit and rewrite the location. It is
necessary to reload the data and address registers
(EEDATA and EEADR), as these registers have
cleared as a result of the Reset.
Control bits, RD and WR, start read and erase/write
operat ions, respec tively . These bi ts are set by fi rmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “Table Read s
and Table Writes” regarding table reads.
Note: Interru pt flag bi t, EEIF in t he PIR2 regi ster,
is set when write is complete. It must be
cleared in software.
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REGISTER 7-1: EECON1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS FREE WRERR WREN WR RD
bit 7 bit 0
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access pro gram Fl ash memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access configuration or calibration registers
0 = Access program Flash or data EEPROM memory
bit 5 Unimplemented: Read as0
bit 4 FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write onl y
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation was prematurely terminated
(MCLR or WDT Reset during self-timed erase or program operation)
0 = The write operation completed normally
Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
bit 2 WREN: Erase/Write Enable bit
1 = Allows erase/write cycles
0 = Inhibits erase/write cycles
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle, or a program memory erase cycle, or w rite cycle.
(The operatio n is self-tim ed and the bit is cleared by hard ware once wri te is complete. The
WR bit can only be set (not cleared) in software.)
0 = Write cycle is completed
bit 0 RD: Read Control bit
1 = Initiates a memory read
(Read t akes one cycle. RD is cleared in hardw are. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0 = Read completed
Legend:
R = Readable bit S = Settable only U = Unimplemented bit, read as ‘0’
W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc. DS39605D-page 69
PIC18F1220/1320
7.3 Reading the Data EEPROM
Memory
To read a data memory location, the user must write th e
address to the EEADR register, clear the EEPGD
control bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available for the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value u ntil another re ad operation, or until it is w ritten to
by the user (during a write operation).
7.4 Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data
written to the EEDATA register. The sequence in
Example 7-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
follow ed (write 55h to E ECON2, write AAh to EECON2,
then set WR bit) for each byte. It is strongly recom-
mended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. The WREN bit must be set on a previous instruc-
tion. Both WR a nd WREN c an not be se t with th e s am e
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt
or poll this bit. EEIF must be cleared by software.
7.5 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.6 Protection Against Spurious Wri te
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
The writ e in iti ate sequence an d the WR EN bi t tog eth er
help prevent an accidental write during brown-out,
power glitch or software malfunction.
EXAMPLE 7-1: DATA E EPROM READ
EXAMPLE 7-2: DATA E EPROM WRITE
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to read
BCF EECON1, EEPGD ; Point to DATA memory
BSF EECON1, RD ; EEPROM Read
MOVF EEDATA, W ; W = EEDATA
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDATA ; Data Memory Value to write
BCF EECON1, EEPGD ; Point to DATA memory
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1, WR ; Set WR bit to begin write
BSF INTCON, GIE ; Enable Interrupts
SLEEP ; Wait for interrupt to signal write complete
BCF EECON1, WREN ; Disable writes
PIC18F1220/1320
DS39605D-page 70 © 2006 Microchip Technology Inc.
7.7 Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
configuration words. External read and write
operations are disabled if either of these mechanisms
are enabled.
The mic rocontroll er its elf can bo th read and write to the
internal data EEPROM, regardless of the state of the
code-protect configuration bit. Refer to Section 19.0
“Special Features of the CPU” for additional
information.
7.8 Using the Data EEPROM
The data EEPROM is a high endurance, byte address-
able array that has been optimized for the storage of fre-
quently changing information (e.g., program variables or
other data that are updated often). Frequently changing
values will typically be updated more often than specifi-
cation D124. If this is not the c ase, an array refresh must
be performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program m emory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE
TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Note: If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124.
CLRF EEADR ; Start at address 0
BCF EECON1, CFGS ; Set for memory
BCF EECON1, EEPGD ; Set for Data EEPROM
BCF INTCON, GIE ; Disable interrupts
BSF EECON1, WREN ; Enable writes
Loop ; Loop to refresh array
BSF EECON1, RD ; Read current address
MOVLW 55h ;
MOVWF EECON2 ; Write 55h
MOVLW AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1, WR ; Set WR bit to begin write
BTFSC EECON1, WR ; Wait for write to complete
BRA $-2
INCFSZ EEADR, F ; Increment address
BRA Loop ; Not zero, do it again
BCF EECON1, WREN ; Disable writes
BSF INTCON, GIE ; Enable interrupts
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Valu e on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
EEADR EEPROM Addres s Registe r 0000 0000 0000 0000
EEDATA EEPROM Data Register 0000 0000 0000 0000
EECON2 EEPROM Control Register 2 (not a physical register)
EECON1 EEPGD CFGS FREE WRERR WREN WR RD xx-0 x000 uu-0 u000
IPR2 OSCFIP —EEIPLVDIP TMR3IP 1--1 -11- 1--1 -11-
PIR2 OSCFIF —EEIFLVDIF TMR3IF 0--0 -00- 0--0 -00-
PIE2 OSCFIE —EEIELVDIE TMR3IE 0--0 -00- 0--0 -00-
Legend: x = unknown, u = unchanged, – = unimplemented, read as0’. Shaded cells are not used during Flash/EEPROM access.
© 2006 Microchip Technology Inc. DS39605D-page 71
PIC18F1220/1320
8.0 8 x 8 HARD WARE MULTIPLIER
8.1 Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F1220/1320 devices. By making the multiply
a har dware operat ion, i t compl etes i n a sing le in struc-
tion cycle. This is an unsigned multiply that gives a
16-bit result. The result is stored into the 16-bit product
register pa ir (PRODH :PRODL). The m ultip lier does not
affect any flags in the Status register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following adv antages:
Higher computational throughput
Reduc es code siz e requ irem en t s for multip ly
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
Enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
TABLE 8-1: PERFORMANCE COMPARISON
8.2 Operation
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one arg um ent of the mul tipl y is al ready loade d i n
the WREG register.
Exampl e 8-2 shows the sequence t o do an 8 x 8 signed
multi ply. To acco unt fo r t he sign bits o f the a rgu men ts,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
Routine Multiply Method Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned Without hardware multiply 13 69 6.9 μs 27.6 μs69 μs
Hardware multiply 1 1 100 ns 400 ns 1 μs
8 x 8 signed Without hard ware multiply 33 91 9.1 μs 36.4 μs91 μs
Hardware multiply 6 6 600 ns 2.4 μs6 μs
16 x 16 unsigned Without hardware multiply 21 242 24.2 μs 96.8 μs 242 μs
Hardware multiply 28 2 8 2.8 μs11.2 μs28 μs
16 x 16 signed Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs
Hardware multiply 35 40 4 μs16 μs40 μs
MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG2
PIC18F1220/1320
DS39605D-page 72 © 2006 Microchip Technology Inc.
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 8-1 shows the algorithm
that is us ed. The 32-b it result is st ored in four re gisters,
RES3:RES0.
EQUATION 8-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8- 3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ment s, each argum ent p ai rs’ M ost S ignifi cant bit (M Sb)
is tested and the appropriate subtractions are done.
EQUATION 8-2: 16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8-4: 16 x 16 SIGNED
MU LTIPLY ROUTINE
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3,F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
RES3:RES0
= ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
SUBWF RES2 ;
MOVF ARG1H, W ;
SUBWFB RES3
;
SIGN_ARG1
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
BRA CONT_CODE ; no, done
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3
;
CONT_CODE
:
RES3:RES0
= ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L) +
(-1 ARG2H<7> ARG1H:ARG1L 216) +
(-1 ARG1H<7> ARG2H:ARG2L 216)
© 2006 Microchip Technology Inc. DS39605D-page 73
PIC18F1220/1320
9.0 INTERRUPTS
The PIC18F1220/1320 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high priority
level or a low priority level. The high priority interrupt
vector is at 000008h and the low priority interrupt vector
is at 000018h. High priority interrupt events will
interrupt any low priority interrupts that may be in
progress.
There are ten registers which are used to control
interrupt operation. These registers are:
RCON
•INTCON
INTCON2
INTCON3
PIR1, PIR2
PIE1, PIE2
IPR1, IPR2
It is recommended that the Microchip header files
suppli ed with MP LAB® IDE be used fo r the symb olic bit
names in these registers. This allows the assembler/
compil er to automa tical ly ta ke care of the pla ceme nt of
these bits within the specified register.
In general, each interrupt source has three bits to
control its operation. The functions of these bits are:
Flag bit to indicate that an interrupt event
occurred
Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
Priority bit to select high priority or low priority
(INT0 has no priority bit and is al ways high priorit y)
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globall y. Setting the GIEH bit (INTCO N<7>) enable s all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
inter rupts that have the pr iority bit cleared ( low prio rity).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 000008h or 000018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
PIC18F1220/1320
DS39605D-page 74 © 2006 Microchip Technology Inc.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PICmicro mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit,
which enables/dis ables all pe ripheral interru pt sources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interru pt priority
levels are used, this wi ll be either the GIEH or G IEL bit.
High priority interrupt sources can interrupt a low
priority interrupt. Low priority interrupts are not
process ed while high priority int errupt s are in progr ess.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bit s must be cleared in software be fore re-enab ling
interrupts to avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or
GIEL, if priority levels are used), which re-enables
interrupts.
For external interrupt events, such as the INT pins or
the POR TB input chang e interrupt, the i nterrupt latenc y
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
FIGURE 9-1: INTE RRUPT LOGIC
Note: Do not use the MOVFF instruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
TMR0IE
GIEH/GIE
GIEL/PEIE
Wake-up if in Low-Po wer Mode
Interrupt to CPU
Vector to Location
0008h
INT2IF
INT2IE
INT2IP
INT1IF
INT1IE
INT1IP
TMR0IF
TMR0IE
TMR0IP
INT0IF
INT0IE
RBIF
RBIE
RBIP
IPEN
TMR0IF
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
GIEL\PEIE
Interrupt to CPU
Vector to Location
IPEN
IPEN
0018h
INT0IF
INT0IE
INT0IF
INT0IE
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
ADIF
ADIE
ADIP
High Priority Interrupt Generation
Low Priority Interrupt Generation
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
GIE\GIEH
© 2006 Microchip Technology Inc. DS39605D-page 75
PIC18F1220/1320
9.1 INTCON Registers
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 9-1: INTCON REGISTER
Note: Interru pt flag bit s ar e set when an inter rupt
conditi on occurs , regardless of the sta te of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
bit 7 bit 0
bit 7 GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high priority interrupts
0 = Disables all interrupts
bit 6 PEIE/GIEL: Periphera l Interr upt Enab le bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all pe ripheral interrupts
When IPEN = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change inte rrup t
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 re gister has overflowe d (must be cleare d in software)
0 = TMR0 re gister did no t overfl ow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note: A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 76 © 2006 Microchip Technology Inc.
REGISTER 9-2: INTCON2 REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5 INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4 INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3 Unimplemented: Read as ‘0
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 Unimplemented: Read as ‘0
bit 0 RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bit s are s et whe n an i nterr upt c ond iti on oc c urs , rega rdle ss of the st a te
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows for software polling.
© 2006 Microchip Technology Inc. DS39605D-page 77
PIC18F1220/1320
REGISTER 9-3: INTCON3 REGISTER
R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
INT2IP INT1IP —INT2IEINT1IE INT2IF INT1IF
bit 7 bit 0
bit 7 INT2IP: INT2 External Interrupt Priority bit
1 = High p riority
0 = Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 = High p riority
0 = Low priority
bit 5 Unimplemented: Read as ‘0
bit 4 INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3 INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2 Unimplemented: Read as ‘0
bit 1 INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0 INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bit s are s et whe n an in terrupt conditi on oc curs , rega rdle ss of the st a te
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows for software polling.
PIC18F1220/1320
DS39605D-page 78 © 2006 Microchip Technology Inc.
9.2 PIR Registers
The PIR regi sters c onta in the ind ividual fl ag bit s for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2).
REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
Note 1: Interrupt flag bit s are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
2: User software should ensure the appropri-
ate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
U-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0
ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUSART receive buffer is empty
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The EUSART transmit buffer is full
bit 3 Unimplemented: Read as ‘0
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurre d (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode .
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (m ust be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc. DS39605D-page 79
PIC18F1220/1320
REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 U-0
OSCFIF EEIF LVDIF TMR3IF
bit 7 bit 0
bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit
1 = System oscill ator faile d, clock input has change d to INT OSC (mu st be clea red in softwa re)
0 = System clock operating
bit 6-5 Unimplemented: Read as0
bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1 = The write operation is complete (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3 Unimplemented: Read as ‘0
bit 2 LVDIF: Low-Volt a ge D etec t Inter rupt Flag bit
1 = A low-voltage condition occurred (must be cleared in software)
0 = The device voltage is above the Low-Voltage Detect trip point
bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 0 Unimplemented: Read as ‘0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 80 © 2006 Microchip Technology Inc.
9.3 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Enable registers (PIE1, PIE2). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 9-6: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 Unimplemented: Read as0
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5 RCIE: EUSART Receiv e Interru pt Enab le bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 Unimplemented: Read as0
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc. DS39605D-page 81
PIC18F1220/1320
REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 U-0
OSCFIE EEIE LVDIE TMR3IE
bit 7 bit 0
bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 6-5 Unimplemented: Re ad as ‘0
bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 3 Unimplemented: Read as0
bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 0 Unimplemented: Read as0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 82 © 2006 Microchip Technology Inc.
9.4 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Priority registers (IPR1, IPR2). Using the
priority bits requires that the Interrupt Priority Enable
(IPEN) bit be set.
REGISTER 9-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
U-0 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1
ADIP RCIP TXIP CCP1IP TMR2IP TMR1IP
bit 7 bit 0
bit 7 Unimplemented: Read as0
bit 6 ADIP: A/D Converter Interrupt Priority bit
1 =High priority
0 = Low priority
bit 5 RCIP: EUSART Receive Interrupt Priority bit
1 =High priority
0 = Low priority
bit 4 TXIP: EUSART Transmit Interrupt Priority bit
1 =High priority
0 = Low priority
bit 3 Unimplemented: Read as0
bit 2 CCP1IP: CCP1 Interrupt Priority bit
1 =High priority
0 = Low priority
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 =High priority
0 = Low priority
bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit
1 =High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc. DS39605D-page 83
PIC18F1220/1320
REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 U-0
OSCFIP EEIP LVDIP TMR3IP
bit 7 bit 0
bit 7 OSCFIP: Oscilla tor Fail Interrupt Priority bit
1 =High priority
0 = Low priority
bit 6-5 Unimplemented: Re ad as ‘0
bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1 =High priority
0 = Low priority
bit 3 Unimplemented: Read as0
bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit
1 =High priority
0 = Low priority
bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit
1 =High priority
0 = Low priority
bit 0 Unimplemented: Read as0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 84 © 2006 Microchip Technology Inc.
9.5 RCON Register
The RCO N register con tains bits used to determine th e
cause of the last Reset or wake-up from a low-power
mode. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 9-10: RCON REGISTER
R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN —RITO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0
bit 4 RI: RESET Instruction Flag bit
For details of bit operation, see Register 5-3.
bit 3 TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 5-3.
bit 2 PD: Power-down Detection Flag bit
For details of bit operation, see Register 5-3.
bit 1 POR: Power-on Reset Status bit
For details of bit operation, see Register 5-3.
bit 0 BOR: Brown-out Reset Status bit
For details of bit operation, see Register 5-3.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc. DS39605D-page 85
PIC18F1220/1320
9.6 INTn Pin Interrupts
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge-triggered: either rising if the
corresp onding INTEDGx b it is set in the INTCON2 re g-
ister, or fall in g i f t he INTEDGx bi t i s cl ear. When a v ali d
edge appears on the RBx/INTx pin, the corresponding
flag bit, INTxF, is set. This interrupt can be disabled by
clearing the corresponding enable bit, INTxE. Flag bit,
INTxF, must be cleared in software in the Interrupt
Service Routine before re-enabling the interrupt. All
external interrupts (INT0, INT1 and INT2) can wake-up
the p roces sor fr om low -pow er mode s if b it INT xE was
set prior to going into low-power modes. If the Global
Interrupt Enable bit, GIE, is set, the processor will
branch to the interrupt vector following wake-up.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits, INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
9.7 TMR0 Interrupt
In 8-bit mode (which is the default), an overflow
(FFh 00h) in the TMR0 register will set flag bit,
TMR0IF. In 16-bit m ode, an overf low (FFFFh 0000h)
in the TMR0H:TMR0L registers will set flag bit,
TMR0IF. The interrupt can be enabled/disabled by
setting/clearing enable bit, TMR0IE (INTCON<5>).
Interrupt priority for Timer0 is determined by the value
contained in the interrupt priority bit, TMR0IP
(INTCON2<2>). See Section 11.0 “Timer0 Module”
for further details on the Timer0 module.
9.8 PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
9.9 Context Saving During Interrupt s
During interrupts, the return PC address i s saved on the
stack. Additional ly , the WREG, S tatus and BSR registers
are saved on the fast return stack. If a fast return from
interrupt is not used (see Section 5.3 “Fast Register
Stack”), the user may need to save the WREG, Status
and BSR registers on entry to the Interrupt Service
Routine. Depending on the user’s application, other
registers may also need to be saved. Example 9-1
saves and restores the WREG, Status and BSR
registers during an Interrupt Service Routine.
EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP ; W_TEMP is in virtual bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR ; Restore BSR
MOVF W_TEMP, W ; Restore WREG
MOVFF STATUS_TEMP, STATUS ; Restore STATUS
PIC18F1220/1320
DS39605D-page 86 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS39605D-page 87
PIC18F1220/1320
10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a perip heral is ena bled, that pi n may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
TRIS register (data direction register)
POR T register (rea ds the lev els on the pin s of the
device)
LAT register (output latch)
The Data Latch (LATA) register is useful for read-
modify-write operations on the value that the I/O pins
are driving.
A simplified model of a generic I/O port without the
interf aces to o ther peripheral s i s sho w n in Fi gure 10-1.
FIGURE 10-1: GENERIC I/O PORT
OPERATION
10.1 PORTA, TRISA and LATA
Registers
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) wi ll
make the correspon ding POR TA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T 0CKI pin.
The sixth pin of PORTA (MCLR/VPP/RA5) is an input
only pin. Its operation is controlled by the MCLRE
configuration bit in Configuration Register 3H
(CONFIG3H<7>). When selected as a port pin
(MCLRE = 0), it functions as a digital input on ly pin; as
such, i t does not have TRIS or LAT bits a ssociated w ith
its operation. Otherwise, it functions as the device’s
Master Clear input. In either configuration, RA5 also
functions as the programming voltage input during
programming.
Pins RA6 and RA7 are multi plexe d with the ma in osci l-
lator pins; they are enabled as oscillator or I/O pins by
the selection of the main oscillator in Configuration
Register 1H (see Section 19.1 “Configuration Bits”
for d etail s). W hen they are not us ed as por t pi ns, R A6
and RA7 and their associated TRIS and LAT bits are
read as ‘0’.
The other PORTA pins are multiplexed with analog
input s, th e analo g V REF+ and V REF- input s and the L VD
input. The op eration of pin s RA3:RA0 as A/D con verter
inputs is selected by clearing/setting the control bits in
the ADCON1 register (A/D Control Register 1).
The RA4/T0CKI pin is a Schmitt Trigger input and an
open-drain output. All other PORTA pins have TTL
input levels and full CMOS output drivers.
The TRISA register controls the direction of the RA
pins, ev en w he n th ey a re being used as ana log inputs .
The user mu st ensure the bit s in the TRISA registe r are
maintained set when using them as analog inputs.
EXAMPLE 10-1: INITIALIZING PORTA
Data
Bus
WR LAT
WR TRIS
RD Port
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O pin(1)
QD
CK
QD
CK
EN
QD
EN
RD LAT
or Port
Note 1: I/O pins have diode protection to VDD and VSS.
Note: On a Power-on Reset, RA5 is enabled as a
digital input only if Master Clear functionality
is disabled.
Note: On a Power-on Reset, RA3:RA0 are
configured as analog inputs and read as
0’. RA 4 is always a digital pin .
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
CLRF LATA ; Alternate method
; to clear output
; data latches
MOVLW 0x7F ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 0xD0 ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as outputs
; RA<7:4> as inputs
PIC18F1220/1320
DS39605D-page 88 © 2006 Microchip Technology Inc.
FIGURE 10-2: BLOCK DIAGRAM OF
RA3:RA0 PINS
FIGURE 10-3: BLOCK DIAGRAM OF
OSC2/CLKO/RA6 PIN
FIGURE 10-4: BLOCK DIAGRAM OF
RA4/T0CKI PIN
FIGURE 10-5: BLOCK DIAGRAM OF
OSC1/CLKI/RA7 PIN
Data
Bus
QD
EN
P
N
WR LATA
WR TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
Analog
Input
Mode
To A/D Converter and LVD Modules
RD LATA
or
PORTA
QD
Q
CK
QD
Q
CK
Schmitt
Trigger
Input
Buffer
Data
Bus
Q
D
Q
CK
QD
EN
P
N
WR LAT A
WR
Data Latch
TRIS Latch
RD
RD PORTA
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
or
PORTA
RD LAT A
RA6 Enable
ECIO or
Enable
RCIO
TRISA
Q
D
Q
CK
TRISA
Schmitt
Trigger
Input
Buffer
Data
Bus
WR TRISA
RD PORTA
Data Latch
TRIS Latch
Schmitt
Trigger
Input
Buffer
N
VSS
I/O pin(1)
TMR0 Clock Input
QD
Q
CK
QD
Q
CK
EN
QD
EN
RD LATA
WR LATA
or
PORTA
Note 1: I/O pins have protection diodes to VDD and VSS.
RD TRISA
Data
Bus
Q
D
Q
CK
QD
EN
P
N
WR LATA
WR
Data Latch
TRIS Latch
RD
RD PORTA
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
or
PORTA
RD LATA
Enable
RA7
TRISA
Q
D
Q
CK
TRISA
RA7 Enab le To Oscillator
Schmitt
Trigger
Input
Buffer
© 2006 Microchip Technology Inc. DS39605D-page 89
PIC18F1220/1320
FIGURE 10-6: MCLR/VPP/RA5 PIN BLOCK DIAGRAM
TABLE 10-1: PORTA FUNCTIONS
TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
MCLR/VPP/RA5
Data Bus
RD PORTA
RD LATA
Schmitt
Trigger
MCLRE
RD TRISA
QD
EN
Latch
Filter Low-Level
MCLR Detect
High-Voltage Detect
Internal M C LR
HV
Name Bit# Buffer Function
RA0/AN0 bi t 0 ST Input/output port pin or analog input.
RA1/AN1/LVDIN bit 1 ST Input/output port pin, analog input or Low-Voltage Detect input.
RA2/AN2/VREF- bit 2 ST Input/output port pin, analog input or VREF-.
RA3/AN3/VREF+ bit 3 ST Input/output port pin, analog input or VREF+.
RA4/T0CKI bit 4 ST Input/output port pin or external clock input for Timer0.
Output is open-drain type.
MCLR/VPP/RA5 bit 5 ST Master Clear inp ut or p r ogra mmin g vo lt a ge input (if MCLR is e nabled); input
only port pin or programming voltage input (if MCLR is disabled).
OSC2/CLKO/RA6 bit 6 ST OSC2, clock output or I/O pin.
OSC1/CLKI/RA7 bit 7 ST OSC1, clock input or I/O pin.
Legend: TTL = TTL input, ST = Schmitt T rig ge r input
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
PORTA RA7(1) RA6(1) RA5(2) RA4 RA3 RA2 RA1 RA0 xx0x 0000 uu0u 0000
LATA LATA7(1) LATA6(1) LATA Data Output Register xx-x xxxx uu-u uuuu
TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register 11-1 1111 11-1 1111
ADCON1 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 -000 0000
Legend: x = unknown, u = unchanged, – = unimplemented locations read as0’. Shad ed cell s are not u sed by P OR TA.
Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as0’.
2: RA5 is an input only if MCLR is disabled.
PIC18F1220/1320
DS39605D-page 90 © 2006 Microchip Technology Inc.
10.2 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make th e corresp onding POR TB pi n an out put (i.e .,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 10-2: INITIALIZI NG PORTB
Pins RB0-RB2 are multiplexed with INT0-INT2; pins
RB0, RB1 and RB4 are multiplexed with A/D inputs;
pins RB1 and RB4 are multiplexed with EUSART; and
pins RB2, RB3, RB6 and RB7 are multiplexed with
ECCP.
Each of th e POR TB pins has a we ak inte rnal pul l-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB7:RB4) have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
b) Clear flag bit, RBIF.
A mismatc h condit ion wil l contin ue to set flag bit , RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 10-7: BLOCK DIAGRAM OF
RB0/AN4/INT0 PIN
Note: On a Power-on Reset, RB4:RB0 are
configu red as analog inp uts by defau lt and
read as ‘0’; RB7:RB5 are configured as
digital inputs.
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
CLRF LATB ; Alternate method
; to clear output
; data latches
MOVLW 0x70 ; Set RB0, RB1, RB4 as
MOVWF ADCON1 ; digital I/O pins
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Data Latch
RBPU(2) P
VDD
Data Bus
WR LATB
WR TRISB
RD TRISB
RD PORTB
Weak
Pull-up
INTx
I/O
pin(1)
Schmitt Trigger
Buffer
TRIS Latch
RD LATB
or PORTB
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2<7>).
To A/D Converter
Analog Input Mode
TTL
Input
Buffer
QD
CK
QD
CK
EN
QD
EN
© 2006 Microchip Technology Inc. DS39605D-page 91
PIC18F1220/1320
FIGURE 10-8: BLOCK DIAGRAM OF RB1/AN5/TX/CK/INT1 PIN
Data Latch
RBPU(2) P
VDD
QD
CK
QD
CK
QD
EN
Data Bus
WR LATB
WR TRISB
RD TRISB
RD PORTB
Weak
Pull-up
RD PORTB
RB1 pin(1)
TRIS Latch
RD LATB
or
PORTB
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
To A/D Converter
INT1/CK Input
Analog Input
Mode
1
0
TX/CK Data
EUSART Enable
Schmitt
Trigger
Input
Buffer
TX/CK TRIS
Analog Input Mode
TTL
Input
Buffer
PIC18F1220/1320
DS39605D-page 92 © 2006 Microchip Technology Inc.
FIGURE 10-9: BLOCK DIAGRAM OF RB2/P1B/INT2 PIN
Data Latch
RBPU(2) P
VDD
QD
CK
QD
CK
QD
EN
Data Bus
WR LATB or
WR TRISB
RD TRISB
RD PORTB
Weak
Pull-up
RD PORTB
RB2 pin (1)
TTL
Input
Buffer
TRIS Latch
RD LATB
PORTB
P1B Data
1
0
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
P1B Enable
INT2 Input Schmitt
Trigger
P1B/D Tri-State
Auto-Shutdown
© 2006 Microchip Technology Inc. DS39605D-page 93
PIC18F1220/1320
FIGURE 10-10: BLOCK DIAGRAM OF RB3/CCP1/P1A PIN
Data Bus
WR LATB or
WR TRISB
Data Latch
TRIS Latch
RD TRISB
QD
Q
CK
QD
EN
ECCP1/P1A Data Out 1
0
QD
Q
CK
P
N
VDD
VSS
RD PORTB
ECCP1 Inpu t
RB3 pin
PORTB
RD LATB
Schmitt
Trigger
VDD
Weak
Pull-up
P
RBPU(2)
TTL Inp ut
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
3: ECCP1 pin output enable active for any PWM mode and Compare mode, where CCP1M<3:0> = 1000 or 1001.
4: ECCP1 pin input enable active for Capture mode only.
ECCP1(3) pin Output Enable
P1A/C Tri-State Auto-Shutdown
ECCP1(4) pin Input Enable
PIC18F1220/1320
DS39605D-page 94 © 2006 Microchip Technology Inc.
FIGURE 10-11: BLOCK DIAGRAM OF RB4/AN6/RX/DT/KBI0 PIN
Data Bus
WR LATB or
WR TRISB
Data Latch
TRIS Latch
RD TRISB
QD
Q
CK
QD
EN
DT Data
1
0
QD
Q
CK
RD PORTB
RB4 pin
PORTB
RD LATB
RBPU(2)
PWeak
Pull-up
Q1
From other QD
EN
Set RBIF
RB7:RB4 pins RD PORTB
Q3
To A/D Converter
EUSART Enabled
TTL
Input
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
DT TRIS
Analog Input Mode
RX/DT Input
Analog Input
Mode
Schmitt
Trigger
VDD
© 2006 Microchip Technology Inc. DS39605D-page 95
PIC18F1220/1320
FIGURE 10-12: BLOCK DIAGRAM OF RB5/PGM/KBI1 PIN
Data Latch
From other
RBPU(2) P
VDD
I/O pin (1)
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR LATB
WR TRISB
Set RBIF
TRIS Latch
RD TRISB
RD PORTB
RB7:RB5 and
Weak
Pull-up
RD PORTB
Latch
TTL
Input
Buffer ST
Buffer
RB7:RB5 in Serial Programming Mode
Q3
Q1
RD LATB
or PORTB
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the ap propriate TRIS bit(s) and clear the RBPU bit
(INTCON2<7>).
RB4 pins
PIC18F1220/1320
DS39605D-page 96 © 2006 Microchip Technology Inc.
FIGURE 10-13: BLOCK DIAGRAM OF RB6/PGC/T1OSO/T13CKI/P1C/KBI2 PIN
Data Bus
WR LATB or
WR TRISB
Data Latch
TRIS Latch
RD TRISB
QD
Q
CK
QD
EN
P1C Data
1
0
QD
Q
CK
RD PORTB
RB6 p i n
PORTB
RD LATB
Schmitt
Trigger
RBPU(2) PWeak
Pull-up
Q1
From other QD
EN
Set RBIF
RB7:RB4 pi ns RD PORTB
Q3
PGC
From RB7 pin
Timer1
Oscillator
T1OSCEN
T13CKI
Note 1: I/O pins have diode protec tion to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
TTL
Buffer
ECCP1 P1C/D Enable
P1B/D Tri-State Auto-Shutdown
VDD
© 2006 Microchip Technology Inc. DS39605D-page 97
PIC18F1220/1320
FIGURE 10-14: BLOCK DIAGRAM OF RB7/PGD/T1OSI/P1D/KBI3 PIN
Data Bus
WR LATB or
WR TRISB
Data Latch
TRIS Latch
RD TRISB
QD
Q
CK
QD
EN
P1D Data
1
0
QD
Q
CK
RD PORTB
RB7 pin
PORTB
RD LATB
Schmitt
Trigger
To RB6 pin
RBPU(2) PWeak
Pull-up
Q1
From other QD
EN
Set RBIF
RB7:RB4 pins RD PORTB
Q3
PGD
ECCP1 P1C/D Enable
TTL
Input
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
P1B/D Tri-State Auto-Shutdown
T1OSCEN
VDD
PIC18F1220/1320
DS39605D-page 98 © 2006 Microchip Technology Inc.
TABLE 10-3: PORTB FUNCTIONS
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit# Buffer Function
RB0/AN4/INT0 b it 0 TTL(1)/ST(2) Input/output port pin, analog input or external interrupt
input 0.
RB1/AN5/TX/CK/INT1 bit 1 TTL(1)/ST(2) Input/output port pin, analog input, Enhanced USART
Asynchronous Transmit, Addressable USART
Synchronou s Clock or external interru pt input 1.
RB2/P1B/INT2 bit 2 TTL(1)/ST(2) Input/output port pin or exter nal interru pt input 2.
Internal software programmable weak pull-up.
RB3/CCP1/P1A bit 3 TTL(1)/ST(3) Input/out put port pin or Capture1 input/Compare1 output/
PWM output. Internal software programmable weak pull-up.
RB4/AN6/RX/DT/KBI0 bit 4 TTL(1)/ST(4) Input/output port pin (with interrupt-on-change), analog input,
Enhanced USART Asynchronous Receive or Addressable
USART Synchronous Data.
RB5/PGM/KBI1 bit 5 TTL(1)/ST(5) Input/output port pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Low-Voltage ICSP enable pin.
RB6/PGC/T1OSO/T13CKI/
P1C/KBI2 bit 6 TTL(1)/ST(5,6) Input/output port pin (with interrupt-on-change), Timer1/
Timer3 clock input or Timer1oscillator output.
Internal software programmable weak pull-up.
Serial program mi ng cl ock .
RB7/PGD/T1OSI/P1D/KBI3 bit 7 TTL(1)/ST(5) Input/output port pin (with interrupt-on-change) or Timer1
oscilla tor input. In ternal sof tware prog rammable w eak pull- up.
Serial program mi ng data.
Legend: TTL = TTL input, ST = Schmitt T rig ge r input
Note 1: This buffer is a TTL input when configured as a port input pin.
2: This buffer is a Schmitt Trigger input when configured as the external interrupt.
3: This buffer is a Schmitt Trigger input when configured as the CCP1 input.
4: This buffer is a Schmitt Trigger input when used as EUSART receive input.
5: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
6: This buffer is a TTL input when used as the T13CKI input.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxq qqqq uuuu uuuu
LATB LATB Data Output Register xxxx xxxx uuuu uuuu
TRISB PORTB Data Direction Register 1111 1111 1111 1111
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 TMR0IP —RBIP1111 -1-1 1111 -1-1
INTCON3 INT2IP INT1IP INT2IE INT1IE INT2IF INT1IF 11-0 0-00 11-0 0-00
ADCON1 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 -000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition. Shaded cells are not used by PORTB.
© 2006 Microchip Technology Inc. DS39605D-page 99
PIC18F1220/1320
11.0 TIMER0 MODULE
The Timer0 module has the following features:
Software selectable as an 8-bit or 16-bit timer/
counter
Readable and writable
Dedicated 8-bit software programmable prescaler
Clock source selectable to be external or internal
Interrupt-on-overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
Edge select for external clock
Figure 11-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
The T0CON register (Register 11-1) is a readable and
writ able registe r th at co ntro ls al l the aspec t s o f Ti mer 0,
including the prescale selection.
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0
bit 7 TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer 0
0 = Stops Timer0
bit 6 T08BIT: Timer0 8-bit/16-bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5 T0CS: Timer0 Clock Sour ce Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 Prescale value
110 = 1:128 Prescale value
101 = 1:64 Prescale value
100 = 1:32 Prescale value
011 = 1:16 Prescale value
010 = 1:8 Prescale value
001 = 1:4 Prescale value
000 = 1:2 Prescale value
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 100 © 2006 Microchip Technology Inc.
FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
RA4/T0CKI
T0SE
0
1
1
0
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks TMR0
(2 TCY Delay)
Data Bus
8
PSA
T0PS2, T0PS1, T0PS0 Set Interr upt
Flag bit TMR0IF
on Overflow
3
pin
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
T0SE
0
1
1
0
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks TMR0L
(2 TCY Delay)
Data Bus<7:0>
8
PSA
T0PS2, T0PS1, T0PS0
Set Interr upt
Flag bit TMR0IF
on Overflow
3
TMR0
TMR0H
High Byte
88
8
Read TMR0L
Write TMR0L
RA4/T0CKI
pin
© 2006 Microchip Technology Inc. DS39605D-page 101
PIC18F1220/1320
11.1 Timer0 O p e r at io n
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruc tion cy cle (with out pr escal er). If the TMR0 regis-
ter is w ritten , the i ncrem ent is inhi bited f or the follow ing
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment either on every
rising or fal ling edge of pi n RA4/T0CKI . The increme nt-
ing edge is determined by the Timer0 Source Edge
Select bit (T0SE). Clearing the T0SE bit selects the
rising edge.
When an external cl ock input i s used for T ime r0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the int ernal
phase clock (TOSC). Also, th ere is a delay in the actual
incrementing of Timer0 after synchronization.
11.2 Prescaler
An 8-bi t counter i s availabl e as a presc aler for the T imer0
modul e. Th e pre sc a le r i s no t re ad able or w ri t able.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing b it PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, x, ..., etc.) will clear the prescaler
count.
11.2.1 SWITCHI NG PRESC ALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program executi on).
11.3 Timer0 Int e rr u p t
The TMR0 interrupt is generated when the TMR0 reg-
ister overfl ows from FFh to 00h in 8-bit mod e, or FFFFh
to 0000h i n 16-bit mode. This overflow sets the TMR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IF bit must be cleared in soft-
ware by the Timer0 module Interrupt Service Routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from Low-Power Sleep
mode, sin ce the tim er require s clock cy cles ev en whe n
T0CS is set.
11.4 16-Bit Mode Timer Reads
and Writes
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of T imer0 (refer to Figure 1 1-2). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16 bits of Timer0, without
having to verify that the read of the high and low byte
were valid due to a rollover between successive reads
of the high and low byte.
A write to the high byte of Timer0 must also take place
through th e TMR0H Buf fer reg ister. T ime r0 high byte i s
updated with the contents of TMR0H when a write
occurs to TMR0L. Th is allows all 1 6 bits of T imer0 to be
updated at onc e.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Note: Writing to TMR0 when the prescaler is
assign ed to Timer0 will clear th e pr escal er
count, but will not change the prescaler
assignment.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all othe r
Resets
TMR0L Timer0 Module Low Byte Register xxxx xxxx uuuu uuuu
TMR0H Timer0 Module High Byte Register 0000 0000 0000 0000
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111
TRISA RA7(1) RA6(1) PORTA Data Direction Register 11-1 1111 11-1 1111
Legend: x = unknown, u = unchanged, – = unimplemented locations read as 0. Shaded cells are not used by Timer0.
Note 1: RA6 and RA7 are enabled as I/O pins, depending on the oscillator mode selected in Configuration Word 1H.
PIC18F1220/1320
DS39605D-page 102 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS39605D-page 103
PIC18F1220/1320
12.0 TIMER1 MODULE
The Timer1 module timer/counter has the following
features:
16-bit timer/counter
(two 8-bit registers: TMR1H and TMR1L)
Readable and writable (both registers)
Internal or external clock select
Interrupt-on-overflow from FFFFh to 0000h
Reset from CCP module special event trigger
Status of system clock operation
Figure 12-1 is a simplified block diagram of the Timer1
module.
Register 12-1 details the Timer1 Control register. This
register controls the operating mode of the Timer1
module and contains the Timer1 Oscillator Enable bit
(T1OSCEN). Timer1 can be enabled or disabled by
setting or clearing control bit, TMR1ON (T1CON<0>).
The T imer1 oscillator can be used as a secondary clock
source in power managed modes. When the T1RUN bit
is set, the Timer1 oscillator is providing the system
clock . If the Fail-Safe Cloc k Monitor is en abled and the
T i mer1 os cilla tor fails whil e provi ding th e syst em clo ck,
polling the T1RUN bit will indicate whether the clock is
being provided by the Timer1 oscillator or another
source.
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications, with only a minimal
addition of external components and code overhead.
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7 RD16: 16 -bit Read /Write Mode Enab le bit
1 = Enables register read/write of TImer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 6 T1RUN: Timer1 System Clock Status bit
1 = System clock is derived from Timer1 oscillator
0 = System c lock is derived from another so urce
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: T im er1 Os ci lla tor Enab le bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB6/PGC /T1OSO/T13CKI/P1C/KBI2 (on the rising ed ge)
0 = Internal clock (Fosc/ 4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 104 © 2006 Microchip Technology Inc.
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
•As a timer
As a synchronous counter
As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer 1 increm ents on
every rising edge of the external clock input, or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB 7/PGD/T1OSI/P1D/KBI3 a nd RB6/T1O SO/
T13CKI/P1C/KBI2 pins become inputs. That is, the
TRISB7:TRISB6 values are ignored and the pins read
as ‘0’.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
FIGURE 12-1: TIMER1 BLOCK DIAGRAM
FIGURE 12-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
TMR1H TMR1L
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0 Peripheral Clocks
FOSC/4
Internal
Clock
TMR1ON
On/Off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
TMR1IF
Overflow TMR1 CLR
CCP Special Event Trigger
T1OSCEN
Enable
Oscillator(1)
T1OSC
Interrupt
Flag bit
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates
power drain.
T1OSI
T13CKI/T1OSO
Timer 1 TMR1L
T1OSC T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Peripheral Clocks
T1OSCEN
Enable
Oscillator(1)
TMR1IF
Overflow
Interrupt
FOSC/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
T13CKI/T1OSO
T1OSI
TMR1
Flag bit
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
High Byte
Data Bus<7:0>
8
TMR1H 8
8
8
Read TMR1L
Write TMR1L
CLR
CCP Special Event Trigger
© 2006 Microchip Technology Inc. DS39605D-page 105
PIC18F1220/1320
12.2 Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit, T1OSCEN (T1CON<3>). The oscil-
lator is a low-powe r os ci ll ator rated for 32 kHz cry stals.
It will c ontinue to run durin g all power manage d modes.
The circuit for a typical LP oscillator is shown in
Figure 12-3. Table 12-1 shows the capacitor selection
for the Timer1 oscillator.
The user m us t pro vi de a sof tware time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 12-3: EXTERNAL
COMPONENTS FOR THE
TI MER1 LP OSCILLATOR
T ABLE 12-1: CAPACITOR SELECTION FOR
THE TIMER OSCILLATOR
Note: The Timer1 oscillator shares the T1OSI
and T1OSO pins with the PGD and PGC
pins used for programming and
debugging.
When using the Timer1 oscillator, In-Circuit
Serial Programming (ICSP) may not
function correctly (high voltage or low
voltage), or the In-Circuit Debugger (ICD)
may not communicate with the controller.
As a result of using either ICSP or ICD, the
Timer1 cryst al m ay be dam aged.
If ICSP or ICD operatio ns are requi red, the
crystal should be disconnected from the
circuit (disconne ct either lead ), or insta lled
after programming. The oscillator loading
capacitors may remain in-circuit during
ICSP or ICD operation.
Osc Type Freq C1 C2
LP 32 kHz 22 pF(1) 22 pF(1)
Note 1: Microchip suggests this value as a starting
point in validating the oscillator circuit.
Oscillat or operation should then be tested
to ensure expected performance under
all expected conditions (VDD and
temperature).
2: Higher capacit ance inc reases the st abilit y
of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design guidance
only.
Note: See the Notes with Table 12-1 for additional
information about capacitor selection.
C1
C2
XTAL
PIC18FXXXX
PGD/T1OSI
PGC/T1OSO
32.768 kHz
22 pF
22 pF
PGD
PGC
PIC18F1220/1320
DS39605D-page 106 © 2006 Microchip Technology Inc.
12.3 Timer1 Oscillator Layout
Considerations
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a hig h-s pee d cir cui t m us t b e loc ate d near the oscilla-
tor (such as the CCP1 pin in output compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single sided PCB, or in addition to a ground plane.
FIGURE 12-4: OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
12.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled/disabled by
setting/clearing Timer1 Interrupt Enable bit, TMR1IE
(PIE1<0>).
12.5 Resetting Ti me r1 Using a CCP
Trigger Output
If the CCP module is configured in Compare mode
to generate a “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1 an d start an A/D conversion , if the A/D mod-
ule is enabled (see Section 15.4.4 “Special Event
Trigger” for more infor mation).
T imer 1 must be c onfigured fo r either T ime r or Synch ro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of o peration, the CCPR1H:CCPR1L regis-
ter pair effectively becomes the period register for
Timer1.
12.6 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON< 7>) is s et, the a ddress for TM R1H is mappe d
to a buffer regis ter f or th e hig h byte of Timer 1. A r ead
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, is
valid, due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through th e TMR1H Buf fer reg ister. T ime r1 high byte i s
updated with the contents of TMR1H when a write
occurs to TMR 1L . Thi s a ll ows a us er to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared o n writes to TMR 1L.
RA1
RA4
RB0
MCLR
VSS
RA2
RA3
Note: Not drawn to scale.
RA3
RB2
OSC1
RB5
OSC2
VDD
RB7
RB6
C2
X1
C3
C4
X2
C5
C1
Note: The special event triggers from the CCP1
module will not set interrupt flag bit,
TMR1IF (PIR1<0>).
© 2006 Microchip Technology Inc. DS39605D-page 107
PIC18F1220/1320
12.7 Using Timer1 as a
Real-Time Clock
Adding an extern al LP os cilla tor to Tim er1 (such a s the
one described in Section 12.2 “Timer1 Oscillator”,
above), g ives user s the optio n to include R TC f unction-
ality to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
dev ice and bat tery backup.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Serv ice R ou tin e. I nc rem enti ng the TM R1 re g-
ister p air to overf low, triggers the i nterrupt and ca lls th e
routine, w hich increme nts the seco nds co unter by on e;
additional counters for minutes and hours are
incremented as the previous counter overflow.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it; the simplest method is to set the MSb of TMR1H
with a BSF instruction. Note that the TMR1L register is
never preloaded or altered; doing so may introduce
cumulative error over many cycles.
For this m ethod to be a ccurate, T i mer1 must o perate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW 0x80 ; Preload TMR1 register pair
MOVWF TMR1H ; for 1 second overflow
CLRF TMR1L
MOVLW b’00001111’ ; Configure for external clock,
MOVWF T1OSC ; Asynchronous operation, external oscillator
CLRF secs ; Initialize timekeeping registers
CLRF mins ;
MOVLW .12
MOVWF hours
BSF PIE1, TMR1IE ; Enable Timer1 interrupt
RETURN
RTCisr
BSF TMR1H, 7 ; Preload for 1 sec overflow
BCF PIR1, TMR1IF ; Clear interrupt flag
INCF secs, F ; Increment seconds
MOVLW .59 ; 60 seconds elapsed?
CPFSGT secs
RETURN ; No, done
CLRF secs ; Clear seconds
INCF mins, F ; Increment minutes
MOVLW .59 ; 60 minutes elapsed?
CPFSGT mins
RETURN ; No, done
CLRF mins ; clear minutes
INCF hours, F ; Increment hours
MOVLW .23 ; 24 hours elapsed?
CPFSGT hours
RETURN ; No, done
MOVLW .01 ; Reset hours to 1
MOVWF hours
RETURN ; Done
PIC18F1220/1320
DS39605D-page 108 © 2006 Microchip Technology Inc.
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Na m e Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
PIE1 ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
IPR1 ADIP RCIP TXIP CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu
Legend: x = unknown, u = unchanged, – = unimplemented, read as0’. Shaded cells are not used by the Timer1 module.
© 2006 Microchip Technology Inc. DS39605D-page 109
PIC18F1220/1320
13.0 TIMER2 MODULE
The Timer2 module timer has the following features:
8-bit timer (TMR2 register)
8-bit period register (PR2)
Readable and writable (both registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Interrupt on TMR2 match with PR2
Timer2 has a control register shown in Register 13-1.
TMR2 can be shut off by cleari ng control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
Figure 13-1 is a simplified block diagram of the Timer2
module. Register 13-1 shows the Timer2 Control
register. The prescaler and postscaler selection of
Timer2 are controlled by this register.
13.1 Timer2 Operation
Timer2 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable and is cleared on any device
Reset. The i npu t clo ck (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits,
T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-
put of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit, TMR2IF (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
A write to the TMR2 register
A write to the T2CON register
Any device Reset (Power-on Reset, MCLR Rese t,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0
bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscal e
0001 = 1:2 Postscal e
1111 = 1:16 Postscale
bit 2 TMR2ON: Ti mer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 110 © 2006 Microchip Technology Inc.
13.2 Timer2 Interrupt
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
13.3 Output of TMR2
The output of TMR2 (before the post scaler) is fed to the
Synchron ous Serial Port mod ule, which opti onally use s
it to generate the shift clock.
FIGURE 13-1: TIMER2 BLOCK DIAGRAM
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Comparator
TMR2 Sets Flag
TMR2
Output(1)
Reset
Postscaler
Prescaler
PR2
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
TOUTPS3:TOUTPS0
T2CKPS1:T2CKPS0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
PIE1 ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
IPR1 ADIP RCIP TXIP CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
TMR2 Timer2 Module Register 0000 0000 0000 0000
T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, – = unimplemented, read as0’. Shaded cells are not used by the Timer2 module.
© 2006 Microchip Technology Inc. DS39605D-page 111
PIC18F1220/1320
14.0 TIMER3 MODULE
The Timer3 module timer/counter has the following
features:
16-bit timer/counter
(two 8-bit registers; TMR3H and TMR3L)
Readable and writable (both registers)
Internal or external clock select
Interrupt-on-overflow from FFFFh to 0000h
Reset from CCP module trigger
Figure 14-1 is a simplified block diagram of the Timer3
module.
Register 14-1 shows the Timer3 Control register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
Register 12-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 Oscillator
Enable bit (T1OSCEN), which can be a clock sour ce for
Timer3.
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 7 bit 0
bit 7 RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
bit 6 Unimplemented: Read as ‘0
bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T3CCP1: Timer3 and Timer1 to CCP1 Enable bits
1 = Timer3 is the clock source for compare/capture CCP module
0 = Timer1 is the clock source for compare/capture CCP module
bit 2 T3SYNC: Timer3 External Clock Input Synchronizat ion C ontr ol bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1 TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T13CKI
(on the rising edge after the first falling edge)
0 = Internal clock (FOSC/4)
bit 0 TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 112 © 2006 Microchip Technology Inc.
14.1 Timer3 Operation
Timer3 can operate in one of these modes:
•As a timer
As a synchronous counter
As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer 3 increm ents on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/PGC/
T1OSO/T13CKI/P1C/KBI2 pins become inputs. That
is, the TRISB7:TRISB6 value is ignored and the pins
are read as ‘0’.
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
FIGURE 14-1: TIMER3 BLOCK DIAGRAM
FIGURE 14-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
TMR3H TMR3L
T1OSC
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
Peripheral Clocks
T1OSCEN
Enable
Oscillator(1)
TMR3IF
Overflow
Interrupt
FOSC/4
Internal
Clock
TMR3ON
On/Off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
T1OSO/
T1OSI
Flag bit
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T13CKI
CLR
CCP Special Event Tr igger
T3CCPx
Timer3
TMR3L
T1OSC T3SYNC
TMR3CS
T3CKPS1:T3CKPS0 Peripheral
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
TMR3ON
On/Off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
T1OSO/
T1OSI
TMR3
T13CKI
CLR
CCP Special Event Trigger
T3CCPx
To T imer1 Clock Input
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. Th is eliminates power drain.
High Byte
Data Bus<7:0>
8
TMR3H 8
8
8
Read TMR3L
Write TMR3L
Set TMR3IF Flag bit
on Overflow
Clocks
© 2006 Microchip Technology Inc. DS39605D-page 113
PIC18F1220/1320
14.2 Timer1 Oscillator
The Timer1 oscill ator may be us ed as the clo ck so urc e
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSC EN (T 1CON<3>) bit. The oscil lator i s a low-
power oscillator rated for 32 kHz crystals. See
Section 12.2 “Timer1 Oscillator” for further details.
14.3 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled/disabled by
setting/clearing TMR3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
14.4 Resetting Ti mer3 Us ing a CCP
Trigger Output
If the CCP module is configured in Compare mode
to generate a “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Ti m e r3 . S e e Section 15.4.4 “Special Event Trigger”
for more information.
T imer 3 must be co nfigured fo r either T i mer or Synch ro-
nized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this Reset operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from CCP1 , the write will t ake precedence. In this mode
of operation, the CCPR1H:CCPR1L register pair
effectively becomes the period register for Timer3.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Note: The special event triggers from the CCP
module will not set interrupt flag bit,
TMR3IF (PIR1<0>).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR2 OSCFIF EEIF LVDIF TMR3IF 0--0 -00- 0--0 -00-
PIE2 OSCFIE EEIE LVDIE TMR3IE 0--0 -00- 0--0 -00-
IPR2 OSCFIP EEIP LVDIP TMR3IP 1--1 -11- 1--1 -11-
TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu
T3CON RD16 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 u-uu uuuu
Legend: x = unknown, u = unchanged, – = unimplemented, read as0’. Shaded cells are not used by the Timer3 module.
PIC18F1220/1320
DS39605D-page 114 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS39605D-page 115
PIC18F1220/1320
15.0 ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
The Enhanced CCP module is implemented as a
standard CCP module with Enhanced PWM
capabilities. These capabilities allow for 2 or 4 output
channels, user-selectable polarity, dead-band control
and autom atic shut down an d restart an d are discus sed
in detail in Section 15.5 “Enhanced PWM Mode”.
The control register for CCP1 is shown in Register 15-1.
In addition to the expanded functions of the CCP1CON
register, the ECCP module has two additional
registers associated with Enhanced PWM operation
and auto-shutdown features:
•PWM1CON
ECCPAS
REGISTER 15-1: CCP1CON REGISTER FOR ENHANCED CCP OPERATION
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
bit 7-6 P1M1:P1M0: PWM Output Configuration bits
If CCP1M<3:2 > = 00, 01, 10:
xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins
If CCP1M<3:2 > = 11:
00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins
01 = Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as
port pins
11 = Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive
bit 5-4 DC1B1:DC1B0: PWM Duty Cycle Least Sign ifi ca nt bit s
Capture mode:
Unused.
Compare mode:
Unused.
PWM mo de:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0 CCP1M3:CCP1M0: ECCP1 Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Unused (reserved)
0010 = Compare mode, toggle output on match (ECCP1IF bit is set)
0011 = Unused (reserved)
0100 = Capture mode, ever y fal lin g edge
0101 = Capture mode, ever y rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, ever y 16t h risin g edge
1000 = Compare mode, set output on match (ECCP1IF bit is set)
1001 = Compare mode, clear output on match (ECCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (ECCP1IF bit is set,
ECCP1 pin returns to port pin operation)
1011 = Compare mode, trigger special event (ECCP1IF bit is set; ECCP resets TMR1 or
TMR3 and starts an A/D conversion if the A/D module is enabled)
1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 116 © 2006 Microchip Technology Inc.
15.1 ECCP Outputs
The Enhanced CCP module may have up to four
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTB. The pin
assignments are summarized in Table 15-1.
To configure I/O pins as PWM o utputs, the prop er PWM
mode must be selected by setting the P1Mn and
CCP1Mn bits (CCP1CON<7:6> and <3:0>,
resp ecti vely) . The a ppro pria te TRI SB dir ecti on bits for
the port pins must also be set as outputs.
TABLE 15-1: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES
15.2 CCP Module
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
TABLE 15-2: CCP MODE – TIMER
RESOURCE
15.3 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the 16-bit
value of the TMR1 or TMR3 registers when an event
occurs on pin RB3/CCP1/P1A. An event is defined as
one of the following:
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
The event is selected by co ntrol bits, CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit, CCP1IF (PIR1<2>), is set; it must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by th e new captured valu e.
15.3.1 CCP PIN CONFIGURATION
In Capture mode, the RB3/CCP1/P1A pin should be
configu red as an input by setting the TRISB<3> bit.
15.3.2 TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture featu re
(either Timer1 and/or T imer3 ) mus t be runn ing i n Timer
mode or Synchronized Counter mode. In Asynchro-
nous Counter mode, the capture operation may not
work. The timer to be used with the CCP module is
selected in the T3CON register.
15.3.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit,
CCP1IE (PIE1<2>), clear while changing capture
modes to avoid false interrupts and should clear the
flag bit, CCP1IF, following any such change in
operating mode.
ECCP Mode CCP1CON
Configuration RB3 RB2 RB6 RB7
Compatible CCP 00xx 11xx CCP1 RB2/INT2 RB6/PGC/T1OSO/T13CKI/KBI2 RB7/PGD/T1OSI/KBI3
Dual PWM 10xx 11xx P1A P1B RB6/PGC/T1OSO/T13CKI/KBI2 RB7/PGD/T1OSI/KBI3
Quad PWM x1xx 11xx P1A P1B P1C P1D
Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.
Note 1: TRIS register values must be configured appropriately.
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
Note: If the RB3/CCP1/P1A is configured as an
output, a write to the port can cause a
capture condition.
© 2006 Microchip Technology Inc. DS39605D-page 117
PIC18F1220/1320
15.3.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cl eare d; therefore, the first c ap ture m ay be fro m
a non-zero prescaler. Example 15-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 15-1: CHANGIN G BETWEEN
CAPTURE PRESCALERS
FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
15.4 Compare Mode
In C ompare mo de, t he 16- bit CC PR1 re gist er va lue is
constantly compared against either the TMR1 register
pair value, or the TMR3 register pair value. When a
match occurs, the RB3/CCP1/P1A pin:
Is driv en high
•Is driven low
Toggles output (high-to-low or low-to-high)
Remains unchanged (interrupt only)
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0. At the same time, interrupt
flag bit, CCP1IF, is set.
15.4.1 CCP PIN CONFIGURATION
The user mus t c onfigure the R B3/ CCP1 /P1A p in as an
output by clearing the TRISB<3> bit.
15.4.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.4.3 SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the RB3/
CCP1/P1A pin is not affected. CCP1IF is set and an
interrupt is genera ted (if enab led).
15.4.4 SPECIAL EVENT TRIGGER
In this mod e, an internal hardw are trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 re giste r pai r. T his allo ws t he CC PR 1 re gis ter to
ef fectively b e a 16-bit progra mmable pe riod registe r for
Timer1.
The special event trigger also sets the GO/DONE bit
(ADCON0<1>). This starts a conversion of the
currently selected A/D channel if the A/D is on.
CLRF CCP1CON ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF CCP1CON ; Load CCP1CON with
; this value
CCPR1H CCPR1L
TMR1H TMR1L
Set Flag bit CCP1IF TMR3
Enable
Q’s CCP1CON<3:0>
CCP1 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
TMR3H TMR3L
TMR1
Enable
T3CCP1
T3CCP1
Note: Clearing the CCP1CON register will force
the RB3/CCP1/P1A compare output latch
to the default low level. This is not the
PORTB I/O data latch.
PIC18F1220/1320
DS39605D-page 118 © 2006 Microchip Technology Inc.
FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Event Trigger
Set Flag bit CCP1IF
Match
RB3/CCP1/P1A pin
TRISB<3> CCP1CON<3:0>
Mode Select
Output Enable
Special Event Trig ger will:
Reset Timer1 or Timer3, but does not set Timer1 or Timer3 interrupt flag bit
and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion.
TMR3H TMR3L
T3CCP1 1
0
Name Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
PIE1 ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
IPR1 ADIP RCIP TXIP CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
TRISB PORTB Data Direction Register 1111 1111 1111 1111
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
T3CON RD16 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 u-uu uuuu
ADCON0 VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 00-0 0000
Legend: x = unknown, u = unchanged, – = unimplemented, read as0’. Shaded cells are not used by Capture and Timer1.
© 2006 Microchip Technology Inc. DS39605D-page 119
PIC18F1220/1320
15.5 Enhanced PWM Mode
The Enhanced PWM Mode provides additional PWM
output options for a broader range of control applica-
tions. Th e module i s an upwardl y compat ible vers ion of
the st andard CCP m odule and o ffers up to four output s,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active -low). The module’ s outpu t mode an d polarit y are
configured by setting the P1M1:P1M0 and
CCP1M3CCP1M0 bits of the CCP1CON register
(CCP1CON<7:6> and CCP1CON<3:0>, respectively).
Figure 15-3 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary w hen Ti mer2 resets) in order to prevent
glitches on any of the outputs. The exception is the PWM
Delay register , ECCP1DEL, which is loaded at either the
duty cycle boundary or the boundary period (whichever
comes first). Because of the buf fering, the m odule w ait s
until the assigned timer resets instead of starting imme-
diately. This means that Enhanced PWM waveforms do
not exactly match the standard PWM waveforms, but
are instead of fse t by one full ins truction cy cle (4 TOSC).
As before, the user must manually configure the
appropriate TRIS bits for output.
15.5.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
equation:
EQUATION 15-1: PWM PERIOD
PWM frequency is defined as 1/[PWM period]. When
TMR2 is e qual to PR 2, the fol lowing three event s occur
on the next increment cycle:
TMR2 is cl eare d
The CCP 1 pin i s set (if PWM duty cycl e = 0%, the
CCP1 pin will not be set)
The PWM duty cy c le is copied from CCPR 1 L into
CCPR1H
15.5.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10- b i t re so l uti on is av ai l ab le. T he CC PR 1 L c ontai ns
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the equation:
EQUATION 15-2: PWM DUTY CYCLE
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not copied into
CCPR1H un til a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read- only regi ster.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation. When the CCPR1H and 2-bit latch match
TMR2, concatenated with an internal 2-bit Q clock or
two bits of the TMR2 prescaler, the CCP1 pin is
cleared. The maximum PWM resolution (bits) for a
given PWM frequency is given by the equation:
EQUATION 15-3: PWM RESOLUTION
15.5.3 PWM OUTPUT CONFIGURATIONS
The P1M1:P1M0 bits in the CCP1CON register allow
one of four configurations:
Single Output
Half-Bridge Output
Full-Brid ge Output, For ward mode
Full-Bridge Output, Reverse mode
The Single Output mode is the Standard PWM mode
discussed in Section 15.5 “Enhanced PWM Mode”.
The Half-Bridge and Full-Bridge Output modes are
covered in detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 15-4.
TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
Note: The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
pos ts caler c ould be us ed to have a servo
update rate at a different frequency than
the PWM output.
PWM Period = [(PR2) + 1] • 4 • TOSC
(TMR2 Prescale Value)
Note: If the PWM d uty c ycle v alu e i s lon ger tha n
the PWM period, the CCP1 pin will not be
cleared.
PWM Duty Cycle = (CCP R1L:CCP1CON<5: 4>)
TOSC • (TMR2 Prescale Value)
( )
PWM Resolution (max) =
FOSC
FPWM
log
log(2) bits
PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16) 1641111
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolut ion (bits) 10 10 10 8 7 6.58
PIC18F1220/1320
DS39605D-page 120 © 2006 Microchip Technology Inc.
FIGURE 15-3: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
FIGURE 15-4: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty Cycle Registers CCP1CON<5:4>
Clear Timer,
set CCP1 pin and
latch D.C.
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the
10-bit time base.
TRISB<3>
RB3/CCP1/P1A
TRISB<2>
RB2/P1B/INT2
TRISB<6>
RB6/PGC/T1OSO/T13CKI/
TRISB<7>
RB7/PGD/T1OSI/P1D/KBI3
Output
Controller
P1M1<1:0> 2CCP1M<3:0>
4
CCP1DEL
CCP1/P1A
P1B
P1C
P1D
P1C/KBI2
0
Period
00
10
01
11
SIGNAL PR2+1
CCP1CON<7:6>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Acti ve
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Ac tive
P1D Inactive
Duty
Cycle
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
© 2006 Microchip Technology Inc. DS39605D-page 121
PIC18F1220/1320
FIGURE 15-5: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0
Period
00
10
01
11
SIGNAL PR2+1
CCP1CON<7:6>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Ac ti ve
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Duty
Cycle
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
Relationships:
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Duty Cyc le = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Pre scale Value)
Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 15.5.6 “Programmable Dead-Band
Delay).
PIC18F1220/1320
DS39605D-page 122 © 2006 Microchip Technology Inc.
15.5.4 HALF-BRIDGE MODE
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output
signal is output on the RB3/CCP1/P1A pin, while the
complementary PWM output signal is output on the
RB2/P1B/INT2 pin (Figure 15-6). This mode can be
used for half-bridge applications, as shown in
Figure 15-7, or for full-bridge applications, where four
power switches are being modulated with two PWM
signals.
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits,
PDC6:PDC0 (PWM1CON<6:0>), sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. See
Section 15.5.6 “Programmable Dead-Band Delay”
for more details of the dead -ba nd delay op erations.
The TRISB<3> and TRISB<2> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 15-6: HALF-BRIDGE PWM
OUTPUT (ACTIVE-HIGH)
FIGURE 15-7: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
Period
Duty Cycle
td
td
(1)
P1A
P1B
td = Dead-Band Delay
Period
(1) (1)
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
PIC18F1220/1320
P1A
P1B
FET
Driver
FET
Driver
Load
+
V
-
+
V
-
FET
Driver
FET
Driver
V+
V-
Load
FET
Driver
FET
Driver
PIC18F1220/1320
P1A
P1B
St andard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
© 2006 Microchip Technology Inc. DS39605D-page 123
PIC18F1220/1320
15.5.5 FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as
outputs; however , only two outputs are active at a time.
In the Forward mode, pin RB3/CCP1/P1A is continu-
ously active and pin RB7/PGD/T1OSI/P1D/KBI3 is
modulated. In the Reverse mode, pin RB6/PGC/
T1OSO/T13CKI/P1C/KBI2 is continuously active and
pin RB2/P1B/INT2 is modulated. These are illustrated
in Figure 15-8.
The TRISB<3:2> and TRISB<7:6> bits must be cleare d
to make the P1A, P1B, P1C and P1D pins output.
FIGURE 15-8: FULL-BRIDGE PWM OUTPUT (ACTIVE-HIGH)
Period
Duty Cycle
P1A
P1B
P1C
P1D
Forwar d Mo de
(1)
Period
Duty Cycle
P1A
P1C
P1D
P1B
Reverse Mode
(1)
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
PIC18F1220/1320
DS39605D-page 124 © 2006 Microchip Technology Inc.
FIGURE 15-9: EXAMPL E OF FULL-BRIDGE APPLICATION
15.5.5.1 Directi on Chang e in Full- Bridge M ode
In the Full-Bridge Output mode, the P1M1 bit in the
CCP1CON register allows the user to control the
Forward/Reverse direction. When the application
firmware changes this direction control bit, the module
will assume the new direction on the next PWM cycle.
Just before the end of the current PWM period, the
modulated outputs (P1B and P1D) are placed in their
inactiv e state, whil e the unmodula ted outputs (P1A and
P1C) are switched to drive in the opposite direction.
This occurs in a time interval of (4 TOSC * (Timer2
Prescale Value) before the next PWM period begins.
The Timer2 prescaler will be either 1,4 or 16, depend-
ing on the value of the T2CKPS bit (T2CON<1:0>).
During the interval from the switch of the unmodulated
outputs to the beginning of the next period, the
modulated outputs (P1B and P1D) remain inactive.
This relationship is shown in Figure 15-10.
Note that in the Full-Bridge Output mode, the ECCP
module does not provide any dead-band delay. In
general, since only one output is modulated at all times,
dead-band delay is not required. However, there is a
situation where a dead-band delay might be required.
This situation occurs when both of the following
conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The tu rn-off ti me of the po wer swi tch, incl uding
the power device and driver circuit, is greater
than the turn-on tim e.
Figure 15-1 1 shows an example where the PWM direc-
tion changes from forward to reverse, at a near 100%
duty cy cle. At time t1, the output P1A a nd P1D becom e
inactive, while output P1C becomes active. In this
exampl e, since the turn-off time of the power devi ces is
longer than the turn-on time, a shoot-through current
may flow through power devices QC and QD (see
Figure 15-9) for the duration of ‘t’. The same phenom-
enon will occur to power devices QA and QB for PWM
direction change from reverse to forward.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must b e met:
1. Reduce PWM for a PWM period before
changing directions.
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
PIC18F1220/1320
P1A
P1C
FET
Driver
FET
Driver
V+
V-
Load
FET
Driver
FET
Driver
P1B
P1D
QA
QB QD
QC
© 2006 Microchip Technology Inc. DS39605D-page 125
PIC18F1220/1320
FIGURE 15-10: PWM DIRECTION CHANGE (ACTIVE-HIGH)
FIGURE 15-11: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE (ACTIVE-HIGH)
DC
PWM Period(1)
SIGNAL
Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C toggle one Ti mer2 count before the end of the current PWM cycle.
The modulated P1B and P1D signals are inactive at this time.
PWM Period
One Time r2 Count(2)
P1A
P1B
P1C
P1D
DC
Forward Period Reverse Period
P1A
tON
tOFF
t = tOFF – tON
P1B
P1C
P1D
External Switch D
Potential
Shoot-Through
Current
Note 1: tON is the turn-on delay of power switch QC and its driver.
2: tOFF is the turn-off delay of power switch QD and its driver.
External Switch C
t1
DC
DC
PIC18F1220/1320
DS39605D-page 126 © 2006 Microchip Technology Inc.
15.5.6 PROGRAMMABLE DEAD-BAND
DELAY
In half-b ridge applications where all power switches are
modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switc he s a re sw it ched at the same time (one turne d o n
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interv al, a very hig h current (sho ot-
through current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentia lly des tructiv e shoot -through current from flow-
ing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
In the Half-Bridge Output mode, a digitally programmable
dead-band delay is available to avoid shoot-through
curre nt fro m destro ying t he bri dge po wer swit ches. The
delay oc curs at the sign al tra nsitio n from the non-acti ve
state to the active state. See Figure 15-6 for an illustra-
tion. The lower seven bits of the PWM1CON register
(Register 15-2) sets the delay period in terms of
microcontroller instruction cycles (TCY or 4 TOSC).
15.5.7 ENHANCED PWM
AUTO-SHUTDOWN
When the ECCP is programmed for any of the
Enhanced PWM modes, the active output pins may be
configured for auto-shutdown. Auto-shutdown immedi-
ately places the Enhanced PWM output pins into a
defined shutdown state when a shutdown event
occurs.
A shutdown event can be caused by the INT0, INT1 or
INT2 pi ns (or an y c ombin ation of these thre e s ourc es ).
The auto-shutdown feature can be disabled by not
selecting any auto-shutdown sources. The auto-
shutdown sources to be used are selected using the
ECCPAS2:ECCPAS0 bits (bits <6:4> of the ECCPAS
register).
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states, spec-
ified by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0
bits (ECCPAS<3:0>). Each pin pair (P1A/P1C and
P1B/P1D) may be set to drive high, drive low or be tri-
stated (not driving). The ECCPASE bit (ECCPAS<7>)
is also set to hold the Enhanced PWM outputs in their
shutdown states.
The ECCPASE bit is s et by hardware when a shutdow n
event o cc urs. If automati c re starts are no t e nab led , th e
ECCPASE bit is c leared by f irmware when t he caus e of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM o utputs remain in their shutdown state for that
entire PW M peri od. Wh en the ECCPASE bi t is cle ared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
REGISTER 15-2: PWM1CON: PWM CONFIGURATION REGISTER
Note: Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
bit 7 bit 0
bit 7 PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event
goes away; the PWM restarts automatically
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
bit 6-0 PDC<6:0>: PWM Delay Count bits
Number of FOSC/4 (4 * TOSC) cycles b etween the sch edu led tim e w he n a PW M s ig nal should
transition active and the actual time it transitions active.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc. DS39605D-page 127
PIC18F1220/1320
REGISTER 15-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM/AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0
bit 7 bit 0
bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit
0 = ECCP outputs are operating
1 = A shutdown event has occurred; ECCP outputs are in shutdown state
bit 6 ECCPAS2: ECCP Auto-Shutdown bit 2
0 = INT0 pin has no eff e ct
1 = INT0 pin low causes shutdown
bit 5 ECCPAS1: ECCP Auto-Shutdown bit 1
0 = INT2 pin has no eff e ct
1 = INT2 pin low causes shutdown
bit 4 ECCPAS0: ECCP Auto-Shutdown bit 0
0 = INT1 pin has no eff e ct
1 = INT1 pin low causes shutdown
bit 3-2 PSSACn: Pins A and C Shutdown State Control bits
00 = Drive Pins A and C to ‘0
01 = Drive Pins A and C to ‘1
1x = Pins A and C tri-state
bit 1-0 PSSBDn: Pins B and D Shutdown State Control bits
00 = Drive Pins B and D to ‘0
01 = Drive Pins B and D to ‘1
1x = Pins B and D tri-state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 128 © 2006 Microchip Technology Inc.
15.5.7.1 Auto-Shutdown and
Automatic Restart
The auto-shutdown feature can be configured to allow
automatic restarts of the module, following a shutdown
event. This is enabled by setting the PRSEN bit of the
PWM1CON register (PWM1CON<7>).
In Shut down mode with PRSEN = 1 (Figure 15-12), the
ECCPASE bit will remain set for as long as the cause
of the shutdown continues. When the shutdown
condition clears, the ECCPASE bit is automatically
cleared. If PRSEN = 0 (Figure 15-13), once a shutdown
conditi on occurs , the ECCPASE bit will rem ain set unti l
it is cleared by firmware. Once ECCPASE is cleared,
the Enhanc ed PWM will res ume at the be ginning of th e
next PWM period.
Independent of the PRSEN bit setting, the ECCPASE
bit cannot be cleared as long as the cause of the
shutdown persists.
The Auto-Shu tdown mode can be forced by writing a ‘1
to the ECCPASE bit.
15.5.8 START-UP CONSIDERATIONS
When the EC CP module is use d in the PWM mode, th e
applic ation hardware m ust use the p roper external pull-
up and/or pull-down resistors on the PWM output pins.
When the microcontroller is released from Reset, all of
the I/O pins are in the high-impedance state. The
external circuit s must keep the power switch de vices in
the off state, until the microcontroller drives the I/O pins
with the proper signal levels, or activates the PWM
output(s).
The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow
the user to choose whether the PW M output signals are
active-high or active-low for each pair of PWM output
pins (P1A/P1C and P1B/P1D). The PWM output
polarities must be selected before the PWM pins are
configu red as output s. Changin g the p olarity conf igura-
tion while the PWM pins are configured as outputs is
not recom mended, sinc e it may result i n damage to th e
application circuits.
The P1A, P1B, P1C and P1D outpu t latches m ay not be
in the proper sta tes when the PWM module is initial ized.
Enabling the PWM pins for output at the same time as
the ECCP module may cause damage to the applic ation
circuit. The ECCP module must be enabled in the proper
output mode and complete a full PWM cycle, before con-
figuring the PWM pins as outputs. The completion of a
full PWM cycle is indicated by the TMR2IF bit being set
as the second PWM period begins .
FIGURE 15-12: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)
FIGURE 15-13: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)
Note: Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
Shutdown
PWM
ECCPASE bit
Activity
Event
PWM Period PWM Period PWM Per iod
Duty Cycle
Dead Time
Duty Cycle Duty Cycle
Dead Time
Dead Time
Shutdown
PWM
ECCPASE b i t
Activity
Event
PWM Period PWM Period PWM Period
ECCPASE
Cleared by Firmware
Duty Cycle
Dead Time
Duty Cycle Duty Cycle
Dead TimeDead Time
© 2006 Microchip Technology Inc. DS39605D-page 129
PIC18F1220/1320
15.5.9 SETUP FOR PWM OPERA TIO N
The following steps should be taken when configuring
the ECCP1 module for PWM operation:
1. Configure the PWM pins P1A and P1B (and
P1C and P1D, if used) as inputs by setting the
corresponding TRISB bits.
2. Set the PWM period by loading the PR2 register .
3. Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
Select one of the available output
configurations and direction with the
P1M1:P1M0 bits.
Select the polarities of the PWM output
signals with the CCP1M3:CCP1M0 bits.
4. Set the PWM du ty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
5. For Half-Bridge Output mode, set the dead-
band delay by loading PWM1CON<6:0> with
the appropriate value.
6. If auto-shutdown operation is required, load the
ECCPAS register:
Select the auto-shutdown sources using the
ECCPAS<2:0> bits.
Select the shutdown states of the PWM
output pins using PSSAC1:PSSAC0 and
PSSBD1:PSSBD0 bits.
Set the ECCPASE bit (ECCPAS<7>).
7. If auto-restart operation is required, set the
PRSEN bit (PWM1CON<7>).
8. Configure and start TMR2:
Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit (PIR1<1>).
Set the TMR2 prescale value by loading the
T2CKPS bits (T2CON<1:0>).
Enable Timer2 by setting the TMR2ON bit
(T2CON<2>).
9. Enable PWM outputs after a new PWM cycle
has started:
W a it until TMR 2 overflo ws (TMR 2IF bit is se t).
Enable the CCP1/P1A, P1B, P1C and/or P1D
pin outputs by clearing the respective TRISB
bits.
Clear the ECCPASE bit (ECCPAS<7>).
15.5.10 OPE RATION IN LOW-POW ER
MODES
In the Low-Power Sleep mode, all clock sources are
disabl ed. Timer2 will not inc r em en t a nd the s t ate of the
module will not change. If the ECCP pin is driving a
value, it will continue to drive that value. When the
device wake s up, i t will conti nue from this s tat e. If Two-
Speed Start-ups are enabled, the initial start-up
frequency may not be stable if the INTOSC is being
used.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change.
In all other low-power modes, the selected low-power
mode clock will clock Timer2. Other low-power mode
clocks will most likely be different than the primary
clock frequency.
15.5.10.1 Operation with Fail-Safe
Clock Monitor
If the Fail-Safe Clock Monitor is enabled
(CONFIG1H<6> is programmed), a clock failure will
force the device into the Low-Power RC_RUN mode
and the OSCFIF bit (PIR2<7>) will be set. The ECCP
will then be clocked from the INTRC clock source,
which may have a different clock frequency than the
primary clock. By loading the IRCF2:IRCF0 bits on
Resets, the user can enable the INTOSC at a high
clock speed in the event of a clock failure.
See the previous section for additional details.
15.5.11 EFFECTS OF A RESET
Both power-on and subsequent Resets will force all
ports to input mode and the CCP registers to their
Reset states.
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
PIC18F1220/1320
DS39605D-page 130 © 2006 Microchip Technology Inc.
TABLE 15-5: REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
RCON IPEN RI TO PD POR BOR 0--1 11qq 0--q qquu
PIR1 ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
PIE1 ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
IPR1 ADIP RCIP TXIP CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
TMR2 Timer2 Module Register 0000 0000 0000 0000
PR2 Timer2 Module Period Register 1111 1111 1111 1111
T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
TRISB PORTB Data Direc tion Register 1111 1111 1111 1111
CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu
CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 uuuu uuuu
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 qq00 0000 qq00
Legend: x = unknown, u = unchanged, – = unimplemented, read as0’.
Shaded cells are not used by the ECCP module in Enhanced PWM mode.
© 2006 Microchip Technology Inc. DS39605D-page 131
PIC18F1220/1320
16.0 ENHANCED ADDRESSABLE
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Addressable Universal Synchronous
Asynchronous Receiver Transmitter (EUSART) mod-
ule can be configured as a full-duplex asynchronous
system that can communicate with peripheral devices,
such as CRT terminals an d personal com pu ters . It ca n
also be configured as a half-duplex synchronous
system that can communicate with peripheral devices,
such as A/D or D/A integrated circuits, serial
EEPROMs, etc.
The Enhanced Addressable USART module
implements additional features, including automatic
baud rat e detecti on and c alibratio n, automa tic wake-u p
on Sync Break reception and 12-bit Break character
transmit. These features make it ideally suited for use
in Local Interconnect Network (LIN) bus systems.
The EUSART can be configured in the following
modes:
Asynchronous (full duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break charac ter tran sm is si on
Synchronous – Master (half duplex) with
selectable clock polarity
Synchron ous – Sl ave (half duplex) w ith sele ctable
clock polarity
The RB1/AN5/TX/CK/INT1 and RB4/AN6/RX/DT/KBI0
pins must be configured as follows for use with the
Universal Synchronous Asynchronous Receiver
Transmitter:
SPEN (RCSTA<7>) bit must be set ( = 1),
PCFG6:PCFG5 (ADCON1<5:6>) must be set ( = 1),
TRISB<4> bit must be set ( = 1) and
TRISB<1> bit must be set ( = 1).
The operation of the Enhanced USART module is
controlled through three registers:
Transmit Status and Control (TXSTA)
Receive Status and Control (RCSTA)
Baud Rate Control (BAUDCTL)
These are detailed in on the following pages in
Register 16-1, Register 16-2 and Register 16-3,
respectively.
16.1 Asynchronous Operation in Power
Managed Modes
The EUSART may operate in Asynchronous mode
while the peripheral clocks are being provided by the
internal oscillator block. This makes it possible to
remove the crystal or resonator that is commonly
connected as the primary clock on the OSC1 and
OSC2 pins.
The factory calibrates the internal oscillator block out-
put (INTOSC) for 8 MHz (see Table 22-6). However,
this frequency may drift as VDD or temperature
changes and this directly affects the asynchronous
baud rate. Two methods may be used to adjust the
baud rate clock, but both require a reference clock
source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output back to 8 MHz.
Adjustin g the value i n the OSCTUNE reg ister allows f or
fine res olution changes to the system clock source (see
Section 3.6 “INTOSC Frequency Drift” for more
information).
The other method adjusts the value in the Baud Rate
Generator (BRG). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
Note: The EUSART control will automatically
reconfigure the pin from input to output as
needed.
PIC18F1220/1320
DS39605D-page 132 © 2006 Microchip Technology Inc.
REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in Sync mode.
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode .
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR Idle
0 =TSR busy
bit 0 TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc. DS39605D-page 133
PIC18F1220/1320
REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode Slave:
Don’t care.
bit 4 CREN: Continuo us Receiv e Enab le bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)
0 = Disables con t in uou s r ece iv e
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, generates RCIF interrupt and loads RCREG when RX9D is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care.
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG regi ster and receiving next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 134 © 2006 Microchip Technology Inc.
REGISTER 16-3: BAUDCTL: BAUD RATE CONTROL REGISTER
U-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
RCIDL SCKP BRG16 WUE ABDEN
bit 7 bit 0
bit 7 Unimplemented: Re ad as ‘0
bit 6 RCIDL: Receive Operation Idle Status bit
1 = Receiver is Idle
0 = Receiver is busy
bit 5 Unimplemented: Re ad as ‘0
bit 4 SCKP: Synchronous Cl ock Polarity Select bi t
Asynchronous mode:
Unused in this mode.
Synchronous mode:
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level
bit 3 BRG16: 16-bit Baud Rate Register Enable bit
1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG
0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored
bit 2 Unimplemented: Re ad as ‘0
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit
cleared in hardware on following rising edge
0 = RX pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate meas ure me nt on the next ch ara cte r – require s rec ept ion of a Sync by te
(55h); cleared in hardware upon completion
0 = Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc. DS39605D-page 135
PIC18F1220/1320
16.2 EUSART Baud Rate Generator
(BRG)
The BRG is a dedicated 8-bit or 16-bit generator, that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCTL<3>)
selects 16-bit mode.
The SPBRGH:SPBRG regi ste r p air co ntro ls the perio d
of a free running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 also control the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 16-1 shows the formula for computation of the
baud rate for different EUSART modes which only
apply in Master mode (internally generated clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH:SPBRG registers can be
calculated u sing the f ormulas in Table 16-1. From this,
the erro r in baud rate can be determine d. An example
calculation is shown in Example 16-1. Typical baud
rates and error values for the various asynchronous
modes are shown in Table 16-2. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG to reduce the baud rate error, or
achiev e a slow bau d rate for a fast osc illato r frequ ency.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
16.2.1 POWER MANAGED MODE
OPERATION
The sys tem cl ock is used to generate the des ired bau d
rate; however, when a power managed mode is
entered, the clock source may be operating at a differ-
ent frequency than in PRI_RUN mode. In Sleep mode,
no clocks are present and in PRI_IDLE mode, the
primary clock sourc e cont inues to pr ovide clocks to the
Baud Rate Generator; however, in other power
managed modes, the clock frequency will probably
change. This may require the value in SPBRG to be
adjusted.
If the s ys tem c lo ck is changed duri ng an active r ece iv e
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit
and make sure that the rece iv e o peration is Idl e b efo re
changing the system clock.
16.2.2 SAMPLING
The data on the RB4/AN6/RX/DT/KBI0 pin is sampled
three time s by a maj ority de tect cir cuit to de termine if a
high or a low level is present at the RX pin.
TABLE 16-1: BAUD RATE FORMULAS
EXAMPLE 16-1: CALCULATING BAUD RATE ERROR
Configuration Bits BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
000 8-bit/Asynchronous FOSC/[64 (n + 1)]
001 8-bit/Asynchronous FOSC/[16 (n + 1)]
010 16-bit/Asynchronous
011 16-bit/Asynchronous FOSC/[4 (n + 1)]10x 8-bit/Synchronous
11x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair
For a device with FOSC of 16 MHz, desired bau d rat e of 9600, Asyn chronous mo de , 8-b it BRG :
Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1))
Solving for SPBRGH:SPBRG:
X = ((FOSC/De s ired B aud Ra te)/64 ) – 1
= ((16 000000/96 00)/64) – 1
= [25.042] = 25
Ca l culated Baud Rate= 16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)/ D esi re d Ba ud Ra te
= (961 5 – 9600)/960 0 = 0. 16%
PIC18F1220/1320
DS39605D-page 136 © 2006 Microchip Technology Inc.
TABLE 16-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Value on all
other Resets
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 -010 0000 -010
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
BAUDCTL RCIDL SCKP BRG16 WUE ABDEN -1-1 0-00 -1-1 0-00
SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000
SPBRG Baud Rate Generator Register Low Byte 0000 0000 0000 0000
Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3———————————
1.2 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103
2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51
9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12
19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7
57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2
115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51
1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12
2.4 2.404 0.16 25 2403 -0.16 12
9.6 8.929 -6.99 6
19.2 20.833 8.51 2
57.6 62.500 8.51 0
115.2 62.500 -45.75 0
© 2006 Microchip Technology Inc. DS39605D-page 137
PIC18F1220/1320
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
2.4 2.441 1.73 255 2403 -0.16 207
9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 300 -0.16 207
1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51
2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25
9.6 9.615 0.16 25 9615 -0.16 12
19.2 19.231 0.16 12
57.6 62.500 8.51 3
115.2 125.000 8.51 1
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665
1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415
2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207
9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207
1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51
2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25
9.6 9.615 0.16 25 9615 -0.16 12
19.2 19.231 0.16 12
57.6 62.500 8.51 3
115.2 125.000 8.51 1
TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
PIC18F1220/1320
DS39605D-page 138 © 2006 Microchip Technology Inc.
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665
1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665
2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832
9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207
19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103
57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34
115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832
1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207
2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103
9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25
19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12
57.6 58.824 2.12 16 55555 3.55 8
115.2 111.111 -3.55 8
TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
© 2006 Microchip Technology Inc. DS39605D-page 139
PIC18F1220/1320
16.2.3 AUTO-BAUD RATE DETECT
The Enhan ced USART module s up ports the autom ati c
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 16-1) begins whenever a S tart bit is received and
the ABDEN bit is set. The calculation is s elf-averaging .
In the Auto-Bau d Rate Detect (ABD) mode, the clock to
the BRG i s reversed. Rather than the BRG c locking the
incomi ng RX signal, the RX signal is tim ing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a coun ter to time the bit p eriod of the inco ming serial
byte stream.
Once th e ABDEN bit is set, th e st ate machine w ill c lear
the BRG an d look for a St art b it. The Au to-Baud Detect
must receive a byte with the value 55h (ASCII “U”,
which is also the LIN bus Sync character), in order to
calculate the proper bit rate. The measurement is t aken
over both a low and a high bit time in order to minim ize
any effects caused by asymmetry of the incoming sig-
nal. After a Start bit, the SPBRG begins counting up
using the preselected clock source on the first rising
edge of RX. After eight bits on the RX pin, or the fifth
rising edge, an accumulated value totalling the proper
BRG period is left in the SPBRGH:SPBRG registers.
Once the 5th edge is seen (should correspond to the
Stop bit), the ABDEN bit is automatically cleared.
While calibrating the baud rate period, the BRG
registers are clocked at 1/8th the preconfigured clock
rate. Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, bo th the SPBRG and SPBRGH will b e use d a s
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes, by checking for 00h in
the SPBRGH register. Refer to Table 16-4 for counter
clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. RCREG content should be discarded.
16.2.4 RECEIVING A SYNC (AUTO-BAUD
RATE DETECT)
To receive a Sync (Auto-Baud Rate Detect):
1. Configure the EUSART for asynchronous receive.
TXEN should remain clear. SPBRGH:SPBRG
may be left as is. Th e cont rolle r sh ould opera te i n
either PRI_ RUN o r PRI _IDLE.
2. Enable RXIF interrupts. Set RCIE, PEIE, GIE.
3. Enable Auto-Baud Rate Detect. Set ABDEN.
4. When the next RCIF interrupt occurs, the
received baud rate has been measured. Read
RCREG to clear RCIF and discard. Check
SPBRGH:SPBRG for a valid value. The
EUSART is ready for normal communications.
Return from the interrupt. Allow the primary
clock to run (PRI_RUN or PRI_IDLE).
5. Process subsequent RCIF interrupts normally
as in asynchronous reception. Remain in
PRI_RUN or PRI_IDLE until communications
are complete.
TABLE 16-4: BRG COUNTER CLOCK
RATES
Note 1: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system
timing and communication baud rates
must be taken into consideration when
using the Auto-Baud Rate Detection
feature.
BRG16 BRGH BRG Counter Clock
00 FOSC/512
01 FOSC/128
10 FOSC/128
11 FOSC/32
Note: During the ABD seq uence, SPBRG and
SPBRGH are both used as a 16-bit counter,
independent of BRG16 setting.
PIC18F1220/1320
DS39605D-page 140 © 2006 Microchip Technology Inc.
FIGURE 16-1: AUTOMATIC BAUD RATE CALCULATION
16.3 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA<4>). In this mode, the
EUSART uses st andard Non-Return-to-Zero (NRZ) for-
mat (o n e Start bi t , ei gh t or n ine da ta b i ts an d on e Stop
bit). The mos t common dat a format is 8 bit s. An on-chip
dedicated 8-bit/16-bit Baud Rate Generator can be
used to d erive st andard ba ud rate frequ encies fro m the
oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate, depending on the BRGH
and BRG16 bit s (TXSTA<2> and BAUDCTL<3>). Parity
is not supported by the hardware, but can be
implemented in softw are and stored as the 9 th data bit.
Asynchronous mode is available in all low-power
modes; it is available in Sleep mode only when auto-
wake-up o n Sync Break is en abled. Wh en in PRI_ IDLE
mode, no changes to the Baud Rate Generator values
are required; however, other low-power mode clocks
may operate at another frequency than the primary
clock . Therefore, the Baud Ra te Generator va lues may
need to be adjusted.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
Baud Rate Ge nerator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
Auto-Wake-up on Sync Break Character
12-bit Break Character Transmit
Auto-Baud Rate Detec tio n
16.3.1 EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 16-2. The heart of the transmitter is the T ransmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from t he TXREG register (if availabl e).
Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG register is
empty and flag bit, TXIF (PIR1<4>), is set. This interrupt
can be enabled/disabled by setting/clearing enable bit,
TXIE (PIE1<4>). Flag bit, TXIF, will be se t, regardless of
the state of enable bit, TXIE, and cannot be cleared in
software. Flag bit, TXIF, is not cleared immediately upon
loading the Transmit Buffer register, TXREG. TXIF
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following a
load of TXREG will return inva lid result s .
While flag bit, TXIF, indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. Status bit, TRMT, is a read-
only bit, which is set when the TSR register is empty.
No interrupt logic is tied to this bit, so the user has to
poll this bit in order to determine if the TSR register is
empty.
BRG Value
RX pin
ABDEN bit
RCIF bit
Bit 0 Bit 1
(Interrupt)
Read
RCREG
BRG Clock
Start
Auto-Cleared
Set by User
XXXXh 0000h
Edge #1 Bit 2 Bit 3
Edge #2 Bit 4 Bit 5
Edge #3 Bit 6 Bit 7
Edge #4 Edge #5
001Ch
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
SPBRG XXXXh 1Ch
SPBRGH XXXXh 00h
Stop Bit
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit, TXIF, is set when enable bit,
TXEN, is set.
© 2006 Microchip Technology Inc. DS39605D-page 141
PIC18F1220/1320
To set up an Asynchronous Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
If using i nterrupt s, e nsure th at the GIE and PEIE bit s in
the INTCON register (INTCON<7:6>) are set.
FIGURE 16-2: EUSART TRANSMIT BLOCK DIAGRAM
FIGURE 16-3: ASYNCHRONOUS TRANSMISSION
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator TX9D
MSb LSb
Data Bus
TXREG Register
TSR Register
(8) 0
TX9
TRMT SPEN
RB1/AN5/TX/CK/INT1 pin
Pin Buffer
and Cont rol
8
• •
SPBRGH
BRG16
Word 1
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG Word 1
BRG Output
(Shift Clock)
RB1/AN5/TX/
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Tran s mit Sh ift
Reg. Empty Flag)
1 TCY
CK/INT1 (pin) Stop bit
PIC18F1220/1320
DS39605D-page 142 © 2006 Microchip Technology Inc.
FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
TABLE 16-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Tra nsmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
RB1/AN5/TX/
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Stop bit Start bit
Transmit Shift Reg.
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
CK/INT1 (pin) Start bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all othe r
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
PIE1 ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
IPR1 ADIP RCIP TXIP CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
TXREG EUSART Transmit Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
BAUDCTL RCIDL SCKP BRG16 WUE ABDEN -1-1 0-00 -1-1 0-00
SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000
SPBRG Baud Rate Generator Register Low Byte 0000 0000 0000 0000
Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchron ous transmiss ion.
© 2006 Microchip Technology Inc. DS39605D-page 143
PIC18F1220/1320
16.3.2 EUSART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 16-5.
The data is received on the RB4/AN6/RX/DT/KBI0 pin
and drives the data recovery block. The data recovery
block is actually a high-speed shifter, operating at x16
times the baud rate, whereas the main receive serial
shifter operates at the bit rate or at FOSC. This mode
would typically be used in RS-232 systems.
To set up an A synchrono us Re ception:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit, RCIF, will be set when reception is
complete and an interrupt will be generated if
enable bit R CI E was set.
7. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during r eception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit C RE N.
10. If using int errupt s, ensu re that t he GIE a nd PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
16.3.3 SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asy nch ron ous seri al port by clearin g
the SYNC bit and setting the SPEN bit.
3. If in terrupts a re requ ired, se t the RCE N bit and
select the desired priori ty level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
7. The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if app lic able).
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
FIGURE 16-5: EUSART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
Baud Rate Generato r
RB4/AN6/RX/DT/KBI0
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE Data Bus
8
÷ 64
÷ 16
or Stop Start
(8) 7 1 0
RX9
• • •
SPBRGSPBRGH
BRG16
or
÷ 4
PIC18F1220/1320
DS39605D-page 144 © 2006 Microchip Technology Inc.
To set up an Asynchronous Transmission:
1. Initialize th e SPBRG re gis te r for the ap prop ria te
baud rate. If a high-speed baud rate is desired,
set bit BRGH (see Section 16.2 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
If using i nterrupt s, e nsure th at the GIE and PEIE bit s in
the INTCON register (INTCON<7:6>) are set.
FIGURE 16-6: ASYNCHRONOUS RECEPTION
TABLE 16-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
bit bit 7/8
bit 1bit 0 bit 7/8 bit 0Stop
bit
Start
bit Start
bit
bit 7/8 Stop
bit
RX (pin)
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after
the third word, causing the OERR (overrun) bit to be set.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
PIE1 ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
IPR1 ADIP RCIP TXIP CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
RCREG EUSART Receive Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
BAUDCTL RCIDL SCKP BRG16 WUE ABDEN -1-1 0-00 -1-1 0-00
SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000
SPBRG Baud Rate Generator Register Low Byte 0000 0000 0000 0000
Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
© 2006 Microchip Technology Inc. DS39605D-page 145
PIC18F1220/1320
16.3.4 A UTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. Th e auto-wak e-up feature al lows the cont roller
to wake-up due to activity on the RX/DT line while the
EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCTL<1 >). Onc e s et, the typ ical rec eiv e
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, mon itoring for a wake-up event
independent of the CPU mode. A wake-up event con-
sist s of a hig h-to-low t ransition on the RX/ DT line. (This
coinc ides wi th the star t of a Syn c Break or a Wake -up
Signal character for the LIN protocol.)
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 16-7) and asynchronously if the device is in
Sleep mode (Figure 16-8). The interrupt condition is
cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low- to-high
transition is observed on the RX line, following the wake-
up event. At this point, the EUSART module is in Idle
mode and returns to normal operation. This signals to
the user that the Sync Break event is over.
16.3.4.1 Special Considerations Using
Auto-Wake-up
Since auto-wake-up functions by sensing rising edge
transitions on RX/DT, information with any state changes
before the Stop bit may signal a false end-of-character
and cause data or framing errors. To work properly,
therefore, the initial character in the transmission must
be all ‘0’s. This can be 00h (8 bytes) for standard RS-232
devices, or 000h (12 bit s) for LIN bus.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., LP, XT or HS/PLL mode). The
Sync Break (or Wake-up Signal) character must be of
sufficient length and be followed by a sufficient period,
to allow enough time for the selected oscillator to start
and provide proper initialization of the EUSART.
16.3.4.2 Special Considerations Using
the WUE Bit
The timing of WUE and RCIF events may cause some
confusion when it comes to determining the validity of
receive d data. As noted , setting the WUE bit pl aces the
EUSART in an Idle mode. The wake-up event causes
a receiv e interrupt by setting th e RCIF bit. The WU E bit
is cleared after this when a rising edge is seen on RX/
DT. The interrupt condition is then cleared by reading
the RCREG register . Ordinarily, the dat a in RCREG will
be dummy data and should be discarded.
The fact that the WUE bit has been cleared (or is still
set) and the RCIF flag is set should not be used as an
indicator of the integrity of the data in RCREG. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assu re th at n o act ual data is los t, che ck th e RCI DL
bit to ve rify th at a receive ope rati on is not in proces s. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
FIGURE 16-7: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
FIGURE 16-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE b i t
RX/DT Line
RCIF Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
Bit Set by User Clear ed by hard w ar e
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit
RX/DT Line
RCIF Cleared due to User Read of RCREG
Note 1: If the wake-up event requires a long oscillator warm-up time, the WUE bit may be cleared while the primary clock is still starting.
2: The EUSART remains in Idle while the WUE bit is set.
Sleep En ds
Enters Sleep
Bit Set by User Cleared by hardware
Note 1
PIC18F1220/1320
DS39605D-page 146 © 2006 Microchip Technology Inc.
16.3.5 BREAK CHARACTER SEQUENCE
The Enhanced USART module has the capability of
sending the special Break character sequences that
are required by the LIN bus standard. The Break char-
acter trans mit co nsist s of a Start bit, fol lowed by twelve
0’ bits and a Stop bit. The Frame Break character is
sent whene ve r the SEN DB an d TXEN bi t s (TXSTA<3>
and TXSTA<5>) are set while the Transmit Shift
register is loaded w ith data. Note th at th e v alu e o f da ta
written to TXREG will be ignored and all ‘0’s will be
transmitted.
The SENDB bit i s automaticall y reset by ha rdware after
the correspon din g Stop bit is s ent. This al lo w s the us er
to preloa d the trans mit FIFO with the n ext transm it byte
following the Break character (typically, the Sync
character in the LIN specification).
Note that the data value written to the TXREG for the
Break ch aracter is ignored. Th e write si mply se rves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 16-9 for the timing of the Break
character sequence.
16.3.5.1 Transmitting A Break Signal
The Enhanced USART module has the capability of
sendin g the Break si gnal that is required by th e LIN bus
standard. The Break signal consists of a Start bit,
followed by twelve0’ bits and a S top bit. The Break sig-
nal is sent whenever the SENDB (TXSTA<3>) and
TXEN (TXSTA<5>) bits are set and TXREG is loaded
with data. The data written to TXREG will be ignored
and all0’s will be transmitted.
SENDB is autom atical ly clea red by hardw are whe n the
Break signal has been sent. This allows the user to
preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal
transmission.
To send a Break Signal:
1. Configure the EUSART for asynchronous trans-
missions (steps 1-5). Initialize the SPBRG register
for the appropriate baud rate. If a high-speed baud
rate is desired, set bit BRGH (see Section 16.2
“EUSAR T Bau d Rate Gene rator ( BRG)” ).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. Set the SENDB bit.
7. Load a byte into TXREG. This triggers sending a
Break signal. The Break signal is complete
when TRMT is set. SEN DB will also be cleared.
See Figure 16-9 for the timing of the Break signal
sequence.
16.3.6 RECEIVIN G A BREAK CHARACTER
The Enhanced USART module can receive a Break
character in two ways.
The first method forces configuration of the baud rate
at a freq uency of 9/ 13 the typi cal spee d. This allow s for
the Stop bit transition to be at the correct sampling
location (12 bits for Break versus Start bit and 8 data
bits for typic al dat a ) .
The second method uses the auto-wake-up feature
describ ed in Section 16.3.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitio ns on RX/DT,
cause an RCIF interru pt and receiv e the n ext da ta byte
followed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. Fo r both methods, th e user can set the ABD bit
before placing the EUSART in its Sleep mode.
16.3.6.1 Transmitting a Break Sync
The following sequence will send a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This s equence is ty pical of a LIN bus master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to set up the
Break character.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transm it FIFO buf fe r.
5. After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode. When the
TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
© 2006 Microchip Technology Inc. DS39605D-page 147
PIC18F1220/1320
16.3.6.2 Receiving a Break Sync
To receive a Break Sync:
1. Configure the EUSART for asynchronous
transmit and receive. TXEN should remain
clear. SPBRGH:SPBRG may be left as is.
2. Enable auto-wake-up. Set WUE.
3. Enable RXIF interrupts. Set RCIE, PEIE, GIE.
4. The controller may be placed in any power
managed mode.
5. An RCIF will be generated at the beginning of
the Break s ignal. Whe n the interrupt i s received,
read RCREG to clear RCIF and discard. Allow
the controller to return to PRI_RUN mode.
6. Wai t for the RX line to go high at the end of the
Break sig nal. Wait for any of the foll owin g: WUE
to clear automatically (poll), RB4/RX to go high
(poll) or for RBIF to be set (poll or interrupt). If
RBIF is used, chec k to be sure that RB4/RX is
high before continuing.
7. Enable Auto-Baud Rate Detect. Set ABDEN.
8. Return from the interrupt. Allow the primary
clock to start and stabilize (PRI_RUN or
PRI_IDLE).
9. When the next RCIF interrupt occurs, the
received baud rate has been measured. Read
RCREG to clear RCIF and discard. Check
SPBRGH:SPBRG for a valid value. The
EUSART is ready for normal communications.
Return from the interrupt. Allow the primary
clock to run (PRI_RUN or PRI_IDLE).
10. Process subsequent RCIF interrupts normally
as in asynchronous reception. TXEN should
now be set if transmissions are needed. TXIF
and TXIE may be set if transmit interrupts are
desired. Remain in PRI_RUN or PRI_IDLE until
commu nication s are comp lete. C lear TXEN and
return to step 2.
FIGURE 16-9: SEND BREAK CHARACTER SEQUENCE
Write to TXREG
BRG Output
(Shift Clock)
Start Bit Bit 0 Bit 1 Bit 11 Stop Bit
Break
TXIF bit
TX (pin)
TRMT bit
SENDB
Dummy Write
PIC18F1220/1320
DS39605D-page 148 © 2006 Microchip Technology Inc.
16.4 EUSART Synchronous Master
Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTA<4>). In addition, enable bit, SPEN
(RCSTA<7>), i s se t i n o rder to configure the R B1/ AN 5/
TX/CK/INT1 and RB4/AN6/RX/DT/KBI0 I/O pins to CK
(clock) and DT (data) lines, respectively.
The Master mode indicates that the processor trans-
mits the master clock on the CK line. Clock polarity is
selected with the SCKP bit (BAUDCTL<5>); setting
SCKP sets the Idle state on CK as high, while clearing
the bit se ts t he Idle st ate as low. This opt ion is prov ided
to support Microwire devices with this module.
16.4.1 EUSART SYNCHRONOUS MASTER
TRANSMISSION
The EUSART transmitter block diagram is shown in
Figure 16-2. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available).
Once the TXR EG register tr ansfers the dat a to the TSR
register (occurs in one TCYCLE), the TXREG is empty
and interrupt bit, TXIF (PIR1<4>), is set. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TXIE (PIE1<4>). Flag bit, TXIF, will be set, regardless
of the state of enable bit, TXIE and cannot be cleared
in software. It will reset only when new data is loaded
into the TXREG regis ter.
While flag bit, TXIF, indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. TRMT is a read-only bit,
which is set when the TSR is em pty. No interrupt logic is
tied to this bit, so the user has to poll this bit in order to
determine if the TSR register is empty. The TSR is not
mapped in data memory , so it is not available to the user .
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. S tart transmission by loading da ta to the TXREG
register.
8. If using interrup ts, ensu re that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 16-10: SYNCHRONOUS TRANSMISSION
bit 0 bit 1 bit 7
Word 1
Q1Q2 Q3Q4 Q1 Q2Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3 Q4 Q1 Q2Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 2 bit 0 bit 1 bit 7
RB4/AN6/RX/
RB1/AN5/TX/
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
TXEN b it 1 1
Word 2
TRMT bit
Write Word 1 Write Word 2
Note: Sync Master mode, SPB RG = 0, continuous transmission of two 8-bit words.
DT/KBI0 pin
CK/INT1 pin
RB1/AN5/TX/
CK/INT1 pin
(SCKP = 0)
(SCKP = 1)
© 2006 Microchip Technology Inc. DS39605D-page 149
PIC18F1220/1320
FIGURE 16-11: SYNCHRONOUS TRANSM ISSION (THROUGH TXEN)
TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
RB4/AN6/RX/DT /KBI 0 pin
RB1/AN5/TX/CK/ INT1 pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
PIE1 ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
IPR1 ADIP RCIP TXIP CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
TXREG EUSART Transmit Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
BAUDCTL RCIDL SCKP BRG16 WUE ABDEN -1-1 0-00 -1-1 0-00
SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000
SPBRG B aud Rate Generator Register Low Byte 0000 0000 0000 0000
Legend: x = unknown, – = unimplemented, read as 0’. Shaded cells are not used for synchronous master transmission.
PIC18F1220/1320
DS39605D-page 150 © 2006 Microchip Technology Inc.
16.4.2 EUSART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RB4/AN6/RX/DT/KBI0 pin on the falling edge of the
clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CRE N tak es prece den ce .
To set up a Synchronous Master Reception:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit, RCIF, will be set when reception
is complete and an interrupt will be generated if
the enable bit, RCIE, was set.
8. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrup ts, ensure tha t the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 16-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
CREN bit
RB4/AN6/RX/
RB1/AN5/TX/
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1Q2 Q3 Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4 Q1 Q2 Q3 Q4
0
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
0
Q1 Q2 Q3 Q4
Note: Timing diagram demonstrates Sync Mas ter mode with bit SREN = 1 and bit BRGH = 0.
RB1/AN5/TX/
CK/INT1 pin
CK/INT1 pin
DT/KBI0 pin
(SCKP = 0)
(SCKP = 1)
© 2006 Microchip Technology Inc. DS39605D-page 151
PIC18F1220/1320
TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
PIE1 ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
IPR1 ADIP RCIP TXIP CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
RCREG EUSART Recei ve Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
BAUDCTL RCIDL SCKP BRG16 WUE ABDEN -1-1 0-00 -1-1 0-00
SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000
SPBRG Baud Rate Generator Register Low Byte 0000 0000 0000 0000
Legend: x = unknown, – = unimplemented, read as 0’. Shaded cells are not used for synchronous master reception.
PIC18F1220/1320
DS39605D-page 152 © 2006 Microchip Technology Inc.
16.5 EUSART Synchronous
Slave Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the RB1/AN5/TX/CK/INT1 pin
(instead of being supplied internally in Master mode).
This allows the device to transfer or receive data while
in any low-power mode.
16.5.1 EUSART SYNCHRONOUS
SLAVE TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG
register.
c) Flag bit, TXIF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit, TXIF, will now be
set.
e) If enable bit, TXIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled , the p rog ram wil l bran ch to the in terrupt
vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. S tart transmission by loading da ta to the TXREG
register.
8. If using interrup ts, ensu re that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Valu e on
all othe r
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
PIE1 ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
IPR1 ADIP RCIP TXIP CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
TXREG EUSART Transmit Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
BAUDCTL RCIDL SCKP BRG16 WUE ABDEN -1-1 0-00 -1-1 0-00
SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000
SPBRG B aud Rate Generator Register Low Byte 0000 0000 0000 0000
Legend: x = unknown, – = unimplemented, read as ‘0. Shaded cells are not used for synchronous slave transmission.
© 2006 Microchip Technology Inc. DS39605D-page 153
PIC18F1220/1320
16.5.2 EUSART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR registe r will transfer the data to the
RCREG register; if the RCIE enable bit i s set, t he inter-
rupt generated will wake the chip from low-power
mode. If the global interrupt is enabled, the pro gram will
branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit, RCIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCIE, was set.
6. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrup ts, ensu re that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on
POR, BOR
Value on
all othe r
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
PIE1 ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
IPR1 ADIP RCIP TXIP CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
RCREG EUSART Receive Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
BAUDCTL RCIDL —SCKPBRG16WUE ABDEN -1-1 0-00 -1-1 0-00
SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000
SPBRG Baud Rate Generator Register Low Byte 0000 0000 0000 0000
Legend: x = unknown,= unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
PIC18F1220/1320
DS39605D-page 154 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS39605D-page 155
PIC18F1220/1320
17.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) converter module has
seven inputs for the PIC18F1220/1320 devices. This
module allows conversion of an analog input signal to
a corresponding 10-bit digital number.
A new feature for the A/D converter is the addition of
programmable acquisition time. This feature allows the
user to select a new channel for conversion and to set
the GO/DONE b it immedia tely. When th e GO/DONE bit
is set, the selected channel is sampled for the pro-
grammed acquisition time before a conversion is actu-
ally started. This removes the firmware overhead that
may have been required to allow for an acquisition
(sampl ing) period (see Register 17-3 and Section 17.3
“Selecting and Configuring Automatic Acquisition
Time).
The module has five registers:
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
A/D Control Register 2 (ADCON2)
The ADCON0 register, shown in Register 17-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 17-2, configures
the functions of the port pins. The ADCON2 register,
shown in Register 17-3, configures the A/D clock
source, p rogrammed acquisi tion time and justification.
REGISTER 17-1: ADCON0: A/D CONTROL REGISTER 0
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
bit 7-6 VCFG<1:0>: Voltage Reference Configuration bits
bit 5 Unimplemented: Read as ‘0
bit 4-2 CHS2:CHS0: Analog Channel Select bits
000 = Channel 0 (AN0)
001 = Channel 1 (AN1)
010 = Channel 2 (AN2)
011 = Channel 3 (AN3)
100 = Channel 4 (AN4)
101 = Channel 5 (AN5)
110 = Channel 6 (AN6)
111 = Unimplemented(1)
bit 1 GO/DONE: A/D Conve rsion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0 ADON: A/D On bit
1 = A/D converter module is enabled
0 = A/D converter module is disabled
Note 1: Performing a conversion on unimplemented channels returns full-scale results.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
A/D V REF+A/D VREF-
00 AVDD AVSS
01 External VREF+AVSS
10 AVDD External VREF-
11 External VREF+ External VREF-
PIC18F1220/1320
DS39605D-page 156 © 2006 Microchip Technology Inc.
REGISTER 17-2: ADCON1: A/D CONTROL REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0
bit 6 PCFG6: A/D Port Configuration bit – AN6
1 = Pin configured as a digital port
0 = Pin configured as an analog channel – digital input disabled and reads ‘0
bit 5 PCFG5: A/D Port Configuration bit – AN5
1 = Pin configured as a digital port
0 = Pin configured as an analog channel – digital input disabled and reads ‘0
bit 4 PCFG4: A/D Port Configuration bit – AN4
1 = Pin configured as a digital port
0 = Pin configured as an analog channel – digital input disabled and reads ‘0
bit 3 PCFG3: A/D Port Configuration bit – AN3
1 = Pin configured as a digital port
0 = Pin configured as an analog channel – digital input disabled and reads ‘0
bit 2 PCFG2: A/D Port Configuration bit – AN2
1 = Pin configured as a digital port
0 = Pin configured as an analog channel – digital input disabled and reads ‘0
bit 1 PCFG1: A/D Port Configuration bit – AN1
1 = Pin configured as a digital port
0 = Pin configured as an analog channel – digital input disabled and reads ‘0
bit 0 PCFG0: A/D Port Configuration bit – AN0
1 = Pin configured as a digital port
0 = Pin configured as an analog channel – digital input disabled and reads ‘0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc. DS39605D-page 157
PIC18F1220/1320
REGISTER 17-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6 Unimplemented: Re ad as ‘0
bit 5-3 ACQT2:ACQT0: A/D Acquis iti on Time Selec t bits
000 = 0 TAD(1)
001 = 2 TAD
010 = 4 TAD
011 = 6 TAD
100 = 8 TAD
101 = 12 TAD
110 = 16 TAD
111 = 20 TAD
bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock derived from A/D RC oscillator)(1)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC (clock derived from A/D RC oscillator)(1)
Note: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is
added bef ore the A/D c lock st arts. This allows the SLEEP inst ruction to be executed
before starting a conversion.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 158 © 2006 Microchip Technology Inc.
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS), or the voltage level on the
RA3/AN3/VREF+ and RA2/AN2/VREF- pins.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, th e A/D conv ersion clock must b e derive d
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input, or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH/ADRESL
registers, the GO/DONE bit (ADCON0 register) is
cleared and A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is s hown in Figure 17-1.
FIGURE 17-1: A/D BLOCK DIAGRAM
(Input Voltage)
VAIN
VREFH
Reference
Voltage
AVDD
VCFG1:VCFG0
CHS2:CHS0
AN6(1)
AN5
AN4
AN3/VREF+
AN2/VREF-
AN1
AN0
111
110
101
100
011
010
001
000
10-bit
Converter
VREFL
AVSS
A/D
Note 1: I/O pins have diode protection to VDD and VSS.
0x
1x
x1
x0
AVDD
© 2006 Microchip Technology Inc. DS39605D-page 159
PIC18F1220/1320
The value in the ADRESH/ADRESL registers is not
modified for a Power-on Reset. The ADRESH/ADRESL
registers will contain unknown data after a Power-on
Reset.
After the A/D module has been configured as desired,
the sele cted channe l m ust be acquire d b efor e the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 17.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur bet ween setting th e GO/DONE bit an d the actual
start of the conversion.
To do an A/D Conversion:
1. Configure the A/D module:
Config ure an alog pins, volt age refere nce a nd
digital I/O (ADCON1)
Select A/D input channel (ADCON0)
Select A/D acquisition time (ADCON2)
Select A/D conversion clock (AD CON2)
Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
Clear ADIF bit
Set ADIE bit
Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
Set GO/DONE bit (ADCON0 register)
5. Wait for A/D conversion to complete, by either:
Polling for the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
7. For the next conversion, go to step 1 or step 2,
as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
FIGURE 17-2: ANALOG INPUT MODEL
VAIN CPIN
Rs ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V ILEAKAGE
RIC 1k
Sampling
Switch
SS RSS
CHOLD = 120 pF
VSS
6V
Sampling Switch
5V
4V
3V
2V
567891011
(kΩ)
VDD
± 500 nA
Legend: CPIN = input capacitance
VT= threshold voltage
ILEAKAGE = leakage current at the pin due to
various junctions
RIC = interconnect resistance
SS = sampling switch
CHOLD = sample/hold capacitance (from DAC)
RSS = sam pling sw itch resistan ce
PIC18F1220/1320
DS39605D-page 160 © 2006 Microchip Technology Inc.
17.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 17-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance va ries ov er the dev ice vol tag e
(VDD). The sour ce impedanc e af fects th e offse t voltag e
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
To calculate the minimum acquisition time,
Equation 17-1 may be used. This equation assumes
that 1/2 LSb erro r is used (1024 step s for the A/D). The
1/2 LSb e rror is th e ma ximu m erro r a llowed fo r t he A/D
to meet its specified resolution.
Example 17-1 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
CHOLD = 120 pF
Rs = 2.5 kΩ
Conversion Error 1/2 LSb
VDD =5V RSS = 7 kΩ
Temperature = 50°C (system max.)
VHOLD = 0V @ time = 0
17.2 A/D VREF+ and VREF- References
If external voltage references are used instead of the
internal AVDD and AVSS sources, the source imped-
ance of the VREF+ and VREF- volta ge sour c e s must be
considered. During acquisition, currents supplied by
these sources are insignificant. However, during
conversion, the A/D module sinks and sources current
through the reference sources.
In order to maintain the A/D accuracy, the voltage
reference source impedances should be kept low to
reduce volt ag e cha nges. These volt age chan ges o ccur
as reference currents flow through the reference
source impedance. The maximum recommended
impedance of the VREF+ and VREF- external
reference voltage sources is 250Ω.
EQUATION 17-1: ACQUISITION TIME
EQUATION 17-2: A/D MINIMUM CHARGING TIME
EXAMPLE 17-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
Note: When the conversion is started, the
holding cap ac itor i s di scon nected from the
input pin.
TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=T
AMP + TC + TCOFF
VHOLD = (ΔVREF – (ΔVREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
or
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048)
TACQ =TAMP + TC + TCOFF
TAMP =5 μs
TCOFF = (Temp – 25ºC)(0. 05 μs/ºC)
(50ºC – 25º C)(0.05 μs/ºC)
1.25 μs
Temper at ure coeffici ent is on ly required for tem p e r atures > 25ºC. Below 25 ºC, TCOFF = 0 μs.
TC =-(CHOLD)(RIC + RSS + RS) ln(1/2047) μs
-(120 pF) (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004 883) μs
9.61 μs
TACQ =5 μs + 1.25 μs + 9.61 μs
12.86 μs
© 2006 Microchip Technology Inc. DS39605D-page 161
PIC18F1220/1320
17.3 Selecting and Configuring
Automatic Acquisition Time
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
When the GO/DON E bit is set, sampling is stopped and
a conve rsion begins. Th e user is responsi ble for ens ur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT2:ACQT0
bits (ADCON2<5 :3>) remai n in their Re set state (‘000’)
and is compatible with devices that do not offer
progra mmab le ac qui sition times.
If desired, the ACQT bits can be set to select a
programmable acquisition time for the A/D module.
When the GO/DONE bit is set, the A/D module contin-
ues to sample the input for the selected acquisition
time, th en automatic ally begins a conversio n. Since the
acquis iti on time is pro gram m ed, t here ma y be no need
to wait for an acquisition time between selecting a
channel and setting the GO/DONE bit.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
17.4 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D c on vers ion re qui res 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
•2 T
OSC
•4 TOSC
•8 TOSC
•16 TOSC
•32 TOSC
•64 TOSC
Intern al RC osc il lat or
For correct A/D conversions, the A/D conversion clock
(TAD) must be as sh ort as possible, bu t greater than the
minimum TAD (approximately 2 μs, see parameter 130
for more information).
Table 17-1 shows the resultant TAD t im es der i ve d fr o m
the device operating frequencies and the A/D clock
source selected.
TABLE 17-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD) Maximum Device Frequency
Operation ADCS2:ADCS0 PIC18F1220/1320 Feature2(4)
2 TOSC 000 1.25 MHz 666 kHz
4 TOSC 100 2.50 MHz 1.33 MHz
8 TOSC 001 5.00 MHz 2.66 MHz
16 TOSC 101 10 .0 MHz 5.33 MHz
32 TOSC 010 20.0 MHz 10.65 MHz
64 TOSC 110 40.0 MHz 21.33 MHz
RC(3) x11 1.00 MHz(1) 1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 4 μs.
2: The R C source has a ty pical TAD time of 6 μs.
3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of spec ificati on.
4: Low-power devices only.
PIC18F1220/1320
DS39605D-page 162 © 2006 Microchip Technology Inc.
17.5 Operation in Low-Power Modes
The sele ction of the au tom atic acquis it ion time and th e
A/D conversion clock is determined, in part, by the low-
power mode clock source and frequency while in a
low-power mode.
If the A/D is expected to operate while the device is
in a low-power mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the low-power mode clock that will be
used. After the low-power mode is entered (either of
the Run mo des), an A/D ac quisi tion or con versio n may
be started. Once an acquisition or conversion is
start ed, the device should continue to be clo cked by the
same low-power mode clock source until the conver-
sion has been complete d. If desired , the devi ce may be
placed into the corresponding low-power (ANY)_IDLE
mode during the conversion.
If the low-power mode clock frequency is less than
1 M Hz, the A/D RC clock source should be selected.
Operation in the Low-Power Sleep mode requires the
A/D RC clock to be selected. If bits, ACQT2:ACQT0, are
set t o ‘000’ and a conversion is started, the conversion
will be delayed one instruction cycle to allow execution
of the SLEEP instruction and entry to Low-Power Sleep
mode. The IDLEN and SCS bits in the OSCCON register
must have already been cleared prior to starting the
conversion.
17.6 Configuring Analog Port Pins
The ADCON1, TRISA and TRISB registers all configure
the A/D port pins. The port pins needed as analog in puts
must have their corresponding TRIS bits set (input). If
the TRIS bit is cleared (output), the digital output level
(VOH or V OL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Note 1: When reading the Port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins con-
figured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
© 2006 Microchip Technology Inc. DS39605D-page 163
PIC18F1220/1320
17.7 A/D Conversions
Figure 17-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are cleared. A conversion is started aft er the follow-
ing instruction to allow entry into Low-Power Sleep
mode before the conversion begins.
Figure 17-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are set to ‘010’ and selecting a 4 TAD acquisition
time before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2T
AD wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
FIGURE 17-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 17-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note: The GO/DONE bit should NOT be set in
the sam e inst ructio n that tu rns on the A/D.
TAD1TAD2TAD3 TAD4TAD5 TAD6TAD7TAD8 TAD11
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9TAD10TCY – TAD
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion S tarts
b0
b9 b6 b5 b4 b3 b2 b1
b8 b7
123 4 5 67811
Set GO bit
(Hol ding capacitor is disconnected)
910
Next Q4: ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
Conversion Starts
1234
(Holding capacitor continues
acquiring input)
TACQT Cycles TAD Cycles
Automatic
Acquisition
Time
b0b9 b6 b5 b4 b3 b2 b1
b8 b7
PIC18F1220/1320
DS39605D-page 164 © 2006 Microchip Technology Inc.
17.8 Use of the CCP1 Trigger
An A/D convers ion can be st arted by the “special eve nt
trigger” of the CCP1 module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-
grammed as ‘1011’ and tha t the A/D modu le is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conv ersio n and the Time r1 (or T i mer3) c ounter w ill
be reset to zero. Timer1 (or Timer3) is reset to auto-
matically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input
channel must b e selecte d and the mi nimum ac quisitio n
period is either timed by the user, or an appropriate
TACQ time selected before the “special event trigger”
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (A DON is c leared), the
“special event trigger” will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
TABLE 17-2: SUMMARY OF A/D REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Val ue on
POR, BOR
Value on
all other
Resets
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000
PIR1 —ADIFRCIF TXIF CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
PIE1 —ADIERCIE TXIE CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
IPR1 —ADIPRCIP TXIP CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
PIR2 OSCFIF EEIF LVDIF TMR3IF 0--0 -00- 0--0 -00-
PIE2 OSCFIE EEIE LVDIE TMR3IE 0--0 -00- 0--0 -00-
IPR2 OSCFIP EEIP LVDIP TMR3IP 1--1 -11- 1--1 -11-
ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
ADCON0 VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 00-0 0000
ADCON1 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 -000 0000
ADCON2 ADFM ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 0-00 0000
PORTA RA7(3) RA6(2) RA5(1) RA4 RA3 RA2 RA1 RA0 qq0x 0000 uu0u 0000
TRISA TRISA7(3) TRISA6(2) PORTA Data Direction Register qq-1 1111 11-1 1111
PORTB Read PORTB pins, Write LATB Latch xxxx xxxx uuuu uuuu
TRISB PORTB Data Direction Register 1111 1111 1111 1111
LATB PORTB Output Data Latch xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, q = depends on CONFIG1H<3:0>, – = unimplemented, read as ‘0’.
Shaded cells are not used for A/D conversion.
Note 1: RA5 port bit is available only as an input pin when the MCLRE bit in the configuration register is ‘0’.
2: RA6 and TRISA6 are available only when the primary oscillator mode selection offers RA6 as a port pin; otherwise, RA6
always reads ‘0’, TRISA6 always reads 1’ and writes to both are ignored (see CONFIG1H<3:0>).
3: RA7 and TRISA7 are available only when the internal RC oscillator is configured as the primary oscillator in
CONFIG1H<3:0>; otherwise, RA7 always reads ‘0’, TRISA7 always reads ‘1’ and writes to both are ignored.
© 2006 Microchip Technology Inc. DS39605D-page 165
PIC18F1220/1320
18.0 LOW-VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application soft-
ware can do “housekeeping tasks”, before the device
voltage exits the valid operating range. This can be
done using the Low-Voltage Detect module.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When the v oltage of the device becomes lower th en the
specif ied poin t, an inter rupt flag is set. If the interrupt is
enabled , the program exec ution will bran ch to the inter-
rupt vec tor addre ss and th e softw are c an then respon d
to that interrupt source.
The Low-Voltage Detect circuitry is completely under
software control. This allows the circuitry to be turned
off by the software, which minimizes the current
consum pt ion for the devic e.
Figur e 18-1 sho ws a po ssible a pplication v olt age curve
(typically for batteries). Over time, the device voltage
decreas es. When the device voltage equals volt age V A,
the LVD logic generates an interrupt. This occurs at
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to sh ut down the s ystem. Voltage poi nt VB is the
minimum valid operating voltage specification. This
occur s at time TB. The difference, TB – TA, is the total
time for shutdown.
The block diagram for the LVD module is shown in
Figure 18-2 (following page). A comparator uses an
internally generated reference voltage as the set point.
When the selected tap output of the device voltage
crosses the set point (is lower than), the LVDIF bit is set.
Each node in the resistor divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate
before the LVD module asserts an interrupt. When the
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array is equal to the 1.2V
internal reference voltage generated by the voltage
reference module. The comparator then generates an
interrupt signal setting the LVDIF bit. This voltage is
software programmable to any one of 16 values (see
Figure 18-2). The trip point is selected by
programming the LVDL3:LVDL0 bits (LVDCON<3:0>).
FIGURE 18-1: TYP ICAL LOW-VOLTAGE DETECT APPLICATION
Time
Voltage
VA
VB
TATB
Legend: VA = LVD trip point
VB = Minimum valid device
operating voltage
PIC18F1220/1320
DS39605D-page 166 © 2006 Microchip Technology Inc.
FIGURE 18-2: LOW-VOLT AGE DETECT (LVD) BLOCK DIAGRAM
The LVD module has an additional feature that allows
the user to supply the trip voltage to the module from
an external source. This mode is enabled when bits,
LVDL3:LVDL0, are set to ‘1111’. In this st ate , the com-
parator input is multiplexed from the external input pin,
LVDIN (Figure 18-3). This gives users flexibility,
because it allows them to configure the Low-Voltage
Detect interrupt to occur at any voltage in the valid
operating range.
FIGURE 18-3: LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
LVDIF
VDD
16- to- 1 MUX
LVDEN
LVD Control
Register
Internally Generated
Reference Voltage
LVDIN
1.2V
LVD
EN
LVD Control
16-to-1 MUX
BGAP
BODEN
LVDEN
VxEN
LVDIN
Register
VDD VDD
Externally Generated
Trip Point
© 2006 Microchip Technology Inc. DS39605D-page 167
PIC18F1220/1320
18.1 Control Register
The Low-Voltage Detect Control register controls the
operation of the Low-Voltage Detect circuitry.
REGISTER 18-1: LVDCON REGISTER
U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0
bit 5 IRVST: Intern al Reference Voltage Stable Fl ag bit
1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified
voltage range
0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
bit 4 LVDEN: Low-Voltage Detect Power Enable bit
1 = Enables LVD, powers up LVD circuit
0 = Disables LVD, powers down LVD circuit
bit 3-0 LVDL3:LVDL0: Low-Voltage Detection Limit bits
1111 = External analog input is used (input comes from the LVDIN pin)
1110 = 4.04V-5.15V
1101 = 3.76V-4.79V
1100 = 3.58V-4.56V
1011 = 3.41V-4.34V
1010 = 3.23V-4.11V
1001 = 3.14V-4.00V
1000 = 2.96V-3.77V
0111 = 2.70V-3.43V
0110 = 2.53V-3.21V
0101 = 2.43V-3.10V
0100 = 2.25V-2.86V
0011 = 2.16V-2.75V
0010 = 1.99V-2.53V
0001 = Reserved
0000 = Reserved
Note: LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage
of the device, are not tested.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320
DS39605D-page 168 © 2006 Microchip Technology Inc.
18.2 Operation
Depen ding on the power s our ce for th e devi ce volt ag e,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be
constantly operating. To decrease the current require-
ments, the LVD circuitry only needs to be enabled for
short periods, where the voltage is checked. After
doing the check, the LVD module may be disabled.
Each tim e that the LVD mo dule i s enab led, th e circ uitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
The following steps are needed to set up the LVD
module:
1. Write the value to the LVDL3:LVDL0 bits
(LVDCON register), which selects the desired
LVD trip point.
2. Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
3. Enable the LVD module (set the LVDEN bit in
the LVDCON register).
4. Wait for the LVD module to stabilize (the IRVST
bit to become set).
5. Clear the LVD interrupt flag, which may have
falsely become set, until the LVD module has
stabilized (clear the LVDIF bit).
6. Enable the LVD interru pt (set the LVDIE and th e
GIE bits).
Figure 18-4 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 18-4: LOW-VOLTAGE DETECT WAVEFORMS
VLVD
VDD
LVDIF
VLVD
VDD
Enable LVD
Internally Generated TIVRST
LV DIF may not be set.
Enable LVD
LVDIF
LVDIF cleared in software
LVDIF cleared in software
LV DIF cleared in software,
CASE 1:
CASE 2:
LV DIF remains set since LVD condition still exists
Reference Stable
Internally Generated
Reference Stable TIVRST
© 2006 Microchip Technology Inc. DS39605D-page 169
PIC18F1220/1320
18.2.1 REFERENCE VOLTAGE SET POINT
The internal reference voltage of the LVD module may
be used by other internal circuitry (the programmable
Brown-out Reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires a time to become stable before a low-voltage
condition can be reliably detected. This time is invariant
of system clock speed. This start-up time is specified in
electrical specification parameter 36. The low-voltage
interrupt flag will not be enabled until a stable reference
voltage is reached. Refer to the waveform in Figure 18-4.
18.2.2 CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume st atic cur-
rent. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter D022B.
18.3 Operation During Sleep
When enabled, the LVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the L VDIF bit will be set and the devi ce will wake-
up from Sleep. Device execution will continue from the
interr upt vecto r address if interru pts h ave been globall y
enabled.
18.4 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the LVD module to be turned off.
PIC18F1220/1320
DS39605D-page 170 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS39605D-page 171
PIC18F1220/1320
19.0 SPECIAL FEATURES OF
THE CPU
PIC18F1220/1320 devices include several features
intended to maximize system reliability, minimize cost
through elimination of external components and offer
code protection. These are:
Oscillator Selection
Resets:
- Power-on Reset (P OR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
Interrupts
Watchdog Timer (WDT)
Fail-Safe Clock Monitor
Two-Speed Start-up
Code Protection
ID Locations
In-Circuit Serial Programming
Several oscillator options are available to allow the part
to fit the application. The RC oscillator option saves
system cost, while the LP crystal option saves power.
These are discussed in detail in Section 2.0 “Oscillator
Configurations”.
A complete discussion of device Resets and interrupts
is avail able in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
T imers p rovided for Res ets, PIC18F 1220/1320 de vices
have a Watchdog Timer, which is either permanently
enabled via the configuration bits, or software
controlled (if configured as disabled).
The inclu sio n of an in ternal RC oscill ator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immedi ately on s tart-up, while th e primary clock so urce
completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate configuration register bits.
19.1 Configuration Bits
The configuration bits can be programmed (read as
0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh),
which can only be accessed using table reads and
table writes.
Programming the configuration registers is done in a
manner s imilar to p rogrammin g the Flas h memo ry. The
EECON1 regist er WR bit sta rts a se lf-tim ed w rite to the
configuration register. In normal operation mode, a
TBLWT instruction, with the TBLPTR pointing to the
configu ration regist er , sets up the addre ss and the data
for the configuration register write. Setting the WR bit
start s a long write to the configuration register . The con-
figuratio n regis ters are writt en a by te at a t ime. To write
or erase a configuration cell, a TBLWT instruction can
write a ‘1’ or a ‘0into the cell. For additional details on
Flash programming, refer to Section 6.5 “Writing to
Flash Program Memory”.
TABLE 19-1: CONFIGURATION BITS AND DEVICE IDS
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0 Default/
Unprogrammed
Value
300001h CONFIG1H IESO FSCM FOSC3 FOSC2 FOSC1 FOSC0 11-- 1111
300002h CONFIG2L BORV1 BORV0 BOR PWRTEN ---- 1111
300003h CONFIG2H WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDT ---1 1111
300005h CONFIG3H MCLRE 1--- ----
300006h CONFIG4L DEBUG —LVP—STVR1--- -1-1
300008h CONFIG5L —CP1CP0---- --11
300009h CONFIG5H CPD CPB 11-- ----
30000Ah CONFIG6L WRT1 WRT0 ---- --11
30000Bh CONFIG6H WRTD WRTB WRTC 111- ----
30000Ch CONFIG7L EBTR1 EBTR0 ---- --11
30000Dh CONFIG7H —EBTRB -1-- ----
3FFFFEh DEVID1(1) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(1)
3FFFFFh DEVID2(1) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 0111
Legend: x = unknown, u = unchanged, – = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: See Register 19-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
PIC18F1220/1320
DS39605D-page 172 © 2006 Microchip Technology Inc.
REGISTER 19-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
IESO FSCM FOSC3 FOSC2 FOSC1 FOSC0
bit 7 bit 0
bit 7 IESO: Internal External Switchover bit
1 = Internal External Switchover mode enabled
0 = Internal External Switchover mode disabled
bit 6 FSCM: Fail-Safe Clock Moni tor Enab le bit
1 = Fail- Safe Clock Monitor enabled
0 = Fail-Safe Clock Monitor disabled
bit 5-4 Unimplemented: Read as ‘0
bit 3-0 FOSC<3:0>: Oscillat or Selection bits
11xx = External RC oscillator, CLKO function on RA6
1001 = Internal RC oscillator, CLKO function on RA6 and port function on RA7
1000 = Internal RC oscillator, port function on RA6 and port function on RA7
0111 = External RC oscillator, port function on RA6
0110 = HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
0101 = EC oscillator, port function on RA6
0100 = EC oscillator, CLKO function on RA6
0010 = HS oscillator
0001 = XT oscillator
0000 = LP oscillator
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
© 2006 Microchip Technology Inc. DS39605D-page 173
PIC18F1220/1320
REGISTER 19-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
BORV1 BORV0 BOR PWRTEN
bit 7 bit 0
bit 7-4 Unimplemented: Read as ‘0
bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits
11 = Reserved
10 = VBOR se t to 2.7V
01 = VBOR se t to 4.2V
00 = VBOR se t to 4.5V
bit 1 BOR: Brown-out R eset Enable bit(1)
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
bit 0 PWRTEN: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
Note 1: The Power-up T im er is decoupled from Brown-out Rese t, allowing thes e features to
be independently controlled.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
PIC18F1220/1320
DS39605D-page 174 © 2006 Microchip Technology Inc.
REGISTER 19-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0
bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
bit 0 WDT: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
© 2006 Microchip Technology Inc. DS39605D-page 175
PIC18F1220/1320
REGISTER 19-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
REGISTER 19-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0
MCLRE
bit 7 bit 0
bit 7 MCLRE: MCLR Pin Enable bit
1 =MCLR pin enabled, RA5 input pin disabled
0 = RA5 input pin enabled, MCLR disabled
bit 6-0 Unimplemented: Read as ‘0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
R/P-1 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1
DEBUG —LVP—STVR
bit 7 bit 0
bit 7 DEBUG: Background Debugger Enable bit (see note)
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6-3 Unimplemented: Read as ‘0
bit 2 LVP: Low-Voltage ICSP Enable bit
1 = Low-Voltage ICSP enabled
0 = Low-Voltage ICSP disabled
bit 1 Unimplemented: Read as ‘0
bit 0 STVR: Stack Full /U nd erfl ow Reset Enab le bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
Note: The Timer1 oscillator shares the T1OSI and T1OSO pins with the PGD and PGC
pins used for programming and debugging.
When using the Timer1 oscillator, In-Circuit Serial Programming (ICSP) may not
function correctly (hi gh voltag e or low v oltage), o r the In-Circuit Debugger (ICD) may
not communicate with the controller. As a result of using either ICSP or ICD, the
Timer1 crystal may be damaged.
If ICSP or ICD ope rati ons a r e requ ire d, the c rys tal shou ld be d is con ne cte d f r om th e
circuit (d isco nnect eit her lea d) or in st alled after pr ogra mming. T he oscilla tor loa din g
capacitors may remain in-circuit during ICSP or ICD operation.
PIC18F1220/1320
DS39605D-page 176 © 2006 Microchip Technology Inc.
REGISTER 19-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
REGISTER 19-7: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1
—CP1CP0
bit 7 bit 0
bit 7-2 Unimplemented: Read as0
bit 1 CP1: Code Protection bit (PIC18F1320)
1 = Block 1 (001000-001FFFh) not code-protected
0 = Block 1 (001000-001FFFh) code-protected
bit 0 CP0: Code Protection bit (PIC18F1320)
1 = Block 0 (00200-000FFFh) not code-protected
0 = Block 0 (00200-000FFFh) code-protected
bit 1 CP1: Code Protection bit (PIC18F1220)
1 = Block 1 (000800-000FFFh) not code-protected
0 = Block 1 (000800-000FFFh) code-protected
bit 0 CP0: Code Protection bit (PIC18F1220)
1 = Block 0 (000200-0007FFh) not code-protected
0 = Block 0 (000200-0007FFh) code-protected
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0
-n = Value when device is unprogrammed u = Unchanged from programmed state
R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0
CPD CPB
bit 7 bit 0
bit 7 CPD: Data EEPROM Code Protection bit
1 = Data EEPROM not code-protected
0 = Data EEPROM code-protected
bit 6 CPB: Boot Block Code Protection bit
1 = Boot Block (000000-0001FFh) not code-protected
0 = Boot Block (000000-0001FFh) code-protected
bit 5-0 Unimplemented: Read as ‘0
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
© 2006 Microchip Technology Inc. DS39605D-page 177
PIC18F1220/1320
REGISTER 19-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)
REGISTER 19-9: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)
U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1
WRT1 WRT0
bit 7 bit 0
bit 7-2 Unimplemented: Read as ‘0
bit 1 WRT1: Write Protection bit (PIC18F1320)
1 = Block 1 (001000-001FFFh) not write-protected
0 = Block 1 (001000-001FFFh) write-protected
bit 0 WRT0: Write Protection bit (PIC18F1320)
1 = Block 0 (00200-000FFFh) not write-protected
0 = Block 0 (00200-000FFFh) write-protected
bit 1 WRT1: Write Protection bit (PIC18F1220)
1 = Block 1 (000800-000FFFh) not write-protected
0 = Block 1 (000800-000FFFh) write-protected
bit 0 WRT0: Write Protection bit (PIC18F1220)
1 = Block 0 (000200-0007FFh) not write-protected
0 = Block 0 (000200-0007FFh) write-protected
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
R/P-1 R/P-1 R-1 U-0 U-0 U-0 U-0 U-0
WRTD WRTB WRTC
bit 7 bit 0
bit 7 WRTD: Data EEPROM Write Protection bit
1 = Data EEPROM not write-protected
0 = Data EEPROM write-protected
bit 6 WRTB: Boot Block Write Protection bit
1 = Boot Block (000000-0001FFh) not write-protected
0 = Boot Block (000000-0001FFh) write-protected
bit 5 WRTC: Configuration Register Write Protection bit
1 = Configuration registers (300000-3000FFh) not write-protected
0 = Configuration registers (300000-3000FFh) write-protected
Note: This bit is read-only in normal execution mode; it can be written only in Program mode.
bit 4-0 Unimplemented: Read as ‘0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
PIC18F1220/1320
DS39605D-page 178 © 2006 Microchip Technology Inc.
REGISTER 19-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
REGISTER 19-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1
EBTR1 EBTR0
bit 7 bit 0
bit 7-2 Unimplemented: Read as0
bit 1 EBTR1: Table Read Protection bit (PIC18F1320)
1 = Block 1 (001000-001FFFh) not protected from table reads executed in other blocks
0 = Block 1 (001000-001FFFh) protected from table reads executed in other blocks
bit 0 EBTR0: Table Read Protection bit (PIC18F1320)
1 = Block 0 (00200-000FFFh) not protected from table reads executed in other blocks
0 = Block 0 (00200-000FFFh) protected from table reads executed in other blocks
bit 1 EBTR1: Table Read Protection bit (PIC18F1220)
1 = Block 1 (000800-000FFFh) not protected from table reads executed in other blocks
0 = Block 1 (000800-000FFFh) protected from table reads executed in other blocks
bit 0 EBTR0: Table Read Protection bit (PIC18F1220)
1 = Block 0 (000200-0007FFh) not protected from table reads executed in other blocks
0 = Block 0 (000200-0007FFh) protected from table reads executed in other blocks
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
U-0 R/P-1 U-0 U-0 U-0 U-0 U-0 U-0
EBTRB
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0
bit 6 EBTRB: Boot Bl ock Table Read Protect ion bit
1 = Boot Block (000000-0001FFh) not protected from table reads executed in other blocks
0 = Boot Block (000000-0001FFh) protected from table reads executed in other blocks
bit 5-0 Unimplemented: Read as ‘0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
© 2006 Microchip Technology Inc. DS39605D-page 179
PIC18F1220/1320
REGISTER 19-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F1220/1320 DEVICES
REGISTER 19-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F1220/1320 DEVICES
RRRRRRRR
DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0
bit 7 bit 0
bit 7-5 DEV2:DEV0: Device ID bits
111 = PIC18F1220
110 = PIC18F1320
bit 4-0 REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
Legend:
R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
RRRRRRRR
DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3
bit 7 bit 0
bit 7-0 DEV10:DEV3: Device ID bits
These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the
part number.
0000 0111 = PIC18F1220/1320 devices
Note: These values for DEV10:DEV3 may be shared with other devices. The specific
device is always identified by using the entire DEV10:DEV0 bit sequence.
Legend:
R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
PIC18F1220/1320
DS39605D-page 180 © 2006 Microchip Technology Inc.
19.2 Watchdog Timer (WDT)
For PIC18F1220/1320 devices, the WDT is driven by the
INTRC source. When the WDT is enabled, the clock
source is also enabled. The nominal WDT period is 4 ms
and has the same stability as the INTRC osc illator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscal er . Any output of the WDT postscal er is selected
by a multiplexer, controlled by bits in Configuration
Register 2H. Available periods range from 4 ms to
131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: execute a SLEEP or CLRWDT instruction, the IRCF
bits ( OSCCON<6:4>) are chang ed or a clock failure has
occurred.
Adjustm ents to the internal o scillator c lock pe riod using
the OSCTUNE register also affect the period of the
WDT by the same factor. For example, if the INTRC
period is increased by 3%, then the WDT period is
increased by 3%.
19.2.1 CONTROL REGIST ER
Regi ste r 19-14 sh ows the WDT CON re gi s te r. Th is is a
readable and wri table re gister, which cont ains a control
bit that allows software to override the WDT enable
configuration bit, only if the configuration bit has
disabled the WDT.
FIGURE 19-1: WDT BLOCK DIAGRAM
REGISTER 19-14: WDTCON REGISTER
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: Changing the setting of the IRCF bits
(OSCCON<6:4>) clears the WDT and
postscaler counts.
3: When a CLRWDT instruction is executed
the postscaler count will be cleared.
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
—SWDTEN
bit 7 bit 0
bit 7-1 Unimplemented: Read as ‘0
bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note: This bit has no effec t if the configurat ion bit, WDT EN (CONFIG2H< 0>), is enable d.
Legend:
R = Readable bit W = Writable bit -n = Value at POR
U = Unimplemented bit, read as ‘0’
INTRC Oscillator
WDT
Wake-up
Reset
WDT
WDT C o unter
(31 kHz)
Program ma ble P ostscaler
1:1 to 1:32,768
Enable WDT
WDTPS<3:0>
SWDTEN
WDTEN
CLRWDT
4
from Sleep
Reset
All Device
Sleep
INTRC Control
Resets
÷125
© 2006 Microchip Technology Inc. DS39605D-page 181
PIC18F1220/1320
TABLE 19-2: SUMMARY OF WATCHDOG TIMER REGISTERS
19.3 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator st art-up to code execution
by allowing the microcontroller to use the INTRC oscil -
lator as a clo ck sourc e until the prim ary c loc k so urc e i s
available. It is enabled by setting the IESO bit in
Conf iguration Register 1H (CONFIG1H<7>).
T wo-Speed Start-up is available only if the primary oscil-
lator mode is LP, XT, HS or HSPLL (crystal-based
modes). Oth er sour ces do not r equir e an OST start -up
delay; fo r these, Two-Speed Start-up is disabled.
When ena bled, Resets and wake- ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator block as the clock source, following
the time-out of the Power-up Timer after a Power-on
Reset is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switch es to PRI_RUN mode.
Because the OSCCON register is cleared on Reset
events , the IN T O SC (or pos tscaler) cloc k s ource is not
initially available after a Reset event; the INTRC clock
is used directly at its base frequency. To use a higher
clock speed on wake-up, the INTOSC or postscaler
clock sour ces can be sele cted to provide a higher cloc k
speed by set ti ng bi ts, IFR C2: IFR C0, im medi at ely aft er
Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting
IFRC2:IFRC0 prior to entering Sleep mode.
In all other power managed modes, T wo-Speed S tart-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
19.3.1 SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed Start-
up, the device still obeys the normal command
sequences for entering power managed modes, includ-
ing serial SLEEP instructions (refer to Section 3.1.3
“Multiple Sleep Commands”). In pr actice, this me ans
that user co de can chang e the SCS1:SCS0 bit settings
and iss ue SLEEP commands before the OST times out.
This w ould allo w an a pplic ation to briefly w ake-u p, per-
form routine “housekeeping” tasks and return to Sleep
before the device starts to operate from the primary
oscillator.
User code can a lso c heck if t he primar y clo ck s our ce i s
currently providing th e system cloc king by check ing the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the system clock.
Otherwise, the internal oscillator block is providing the
clock during wake-up from Reset or Sleep mode.
FIGURE 19-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CONFIG2H WDTPS3 WDTPS2 WDTPS2 WDTPS0 WDTEN
RCON IPEN RI TO PD POR BOR
WDTCON —SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
Q1 Q3 Q4
OSC1
Peripheral
Program PC PC + 2
INTOSC
PLL Clock
Q1
PC + 6
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 4
Clock
Counter
Q2 Q2 Q3 Q4
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake from Interrupt Event
TPLL(1)
12345678
Clock Transition
OSTS bit Set
Multiplexer
TOST(1)
PIC18F1220/1320
DS39605D-page 182 © 2006 Microchip Technology Inc.
19.4 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the micro-
controller to continue operation, in the event of an
external oscillator failure, by automatically switching
the system clock to the internal oscillator block. The
FSCM function is enabled by setting the Fail-Safe
Clock Monitor Enable bit, FSCM (CONFIG1H<6>).
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provide
an ins tant ba ckup c lock in the e vent of a cloc k fail ure.
Clock monitoring (shown in Figure 19-3) is accom-
plished by creating a sample clock signal, which is the
INTRC output divided by 64. This allows ample time
between FSCM sample clocks for a peripheral clock
edge to occur. The peripheral system clock and the
sample clock are presented as inputs to the Clock
Monitor latch (CM). The CM is set on the falli ng edge of
the sys tem clock source, but cleare d on the risi ng edge
of the sample clock.
FIGURE 19-3: FSCM BLOCK DIAGRAM
Clock failure is tested for on the falling edge of the sam-
ple clock. If a sample clock falling edge occurs while
CM is still set, a clock failure has been detected
(Figure 19-4). This causes the following:
the FSCM genera tes an oscillator fail int erru pt by
setting bit, OSCFIF (PIR2<7>);
the system clock source is sw itched to t he intern al
oscill ato r blo ck (O SCC ON i s not up dated to show
the current clock source – this is the Fail-Safe
condition); and
•the WDT is reset.
Since the postscaler frequency from the internal oscil-
lator block may not be sufficiently stable, it may be
desirable to select another clock configuration and
enter an alternate power managed mode (see
Section 19.3.1 “Special Considerations for Using
Two-Speed Start-up” and Section 3.1.3 “Multiple
Sleep Commands” for more details). This can be
done to attempt a partial recovery, or execute a
controlled shutdown.
To use a higher clock speed on wake-up, the INTOSC
or postscaler clock sources can be selected to provide
a higher clock speed by setting bits, IFRC2:IFRC0,
immediate ly a fter Res et. Fo r wake-u p s fro m Sle ep, th e
INTOSC or postscaler clock sources can be selected
by setting IFRC2:IFRC0 prior to entering Sleep mode.
Adjustments to the internal oscillator block, using the
OSCTUNE register, also affect the period of the FSCM
by the same factor. This can usually be neglected, as
the cloc k freq uen cy be ing monitored is generally m uc h
higher than the sample clock frequency.
The FS CM will dete ct failure s of the p rimary or sec ond-
ary clock sources only. If the internal oscillator block
fails, no failure would be detected, nor would any actio n
be possible.
19.4.1 FSCM AND THE WATCHDOG T IMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no ef fect on the op eration of the INTRC oscill ator when
the FSCM is enabled.
As already noted, the clock source is switched to the
INTOSC clock when a clock failure is detected.
Depending on the frequency selected by the
IRCF2:IRCF0 bits, this may mean a substantial change
in the speed of code execution. If the WDT is enabled
with a small prescale value, a decrease in clock speed
allows a WDT time-out to occur and a subsequent
device Reset. For this reason, Fail-Safe Clock events
also reset the WDT and postscaler, allowing it to start
timing from when execution speed was changed and
decreasing the likelihood of an erroneous time-out.
Peripheral
INTRC ÷ 64
S
C
Q
(32 μs) 488 Hz
(2.048 ms)
Clock Monitor
Latc h ( C M)
(edge-triggered)
Clock
Failure
Detected
Source
Clock
Q
© 2006 Microchip Technology Inc. DS39605D-page 183
PIC18F1220/1320
19.4.2 EXITING FAIL-SAFE OPERATION
The Fail-Sa fe condition is te rminated by eith er a device
Reset, or by entering a power managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 1H (with any
required start-up delays that are required for the
oscillator mode, such as OST or PLL timer). The
INT OSC multiplex er provides the sy stem clock unt il the
primary clock so urce becom es ready (similar to a Two-
Speed Start-up). The clock system source is then
switched to the primary clock (indicated by the OSTS
bit in the OSCCON register becoming set). The Fail-
Safe Clock Monitor then resumes monitoring the
periphe ral clock.
The primary clock source may never become ready
during st art-up. In thi s case, operatio n is clocked by the
INTOSC multiplexer . The OSCCON register will remain
in its Reset state until a power managed mode is
entered.
Entering a power managed mode by loading the
OSCCON register and executing a SLEEP instruction
will clear the Fail-Safe condition. When the Fail-Safe
condition is cleared, the clock monitor will resume
monitoring the peripheral clock.
19.4.3 FSCM INTERRUPTS IN POWER
MANAGED MODES
As previously mentioned, entering a power managed
mode clears the Fail-Safe condition. By entering a
power managed mode, the clock multiplexer selects
the clock source selected by the OSCCON register.
Fail-Safe monitoring of the power managed clock
source resumes in the power managed mode.
If an oscillator failure occurs during power managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTOSC multiplexer. An automatic transition
back to the failed clock source will not occur.
If the interrupt is disabled, the device will not exit the
power managed mode o n oscillato r failure. Inste ad, the
device will continue to operate as before, but clocked
by the INTOSC m ul tip lex er. While in Id le mode, su bs e-
quent interrupts will cause the CPU to begin executing
instructions while being clocked by the INTOSC multi-
plexer. The de vi ce will not trans itio n t o a diff e rent cl oc k
source until the Fail-Safe condition is cleared.
FIGURE 19-4: FSCM TIMING DIAGRAM
OSCFIF
CM Output
System
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note: The system c lock is normally at a much higher frequency than the sample clock . The relative frequencies in
this example have been chosen for clarity.
(Q)
CM Test CM Test CM Test
PIC18F1220/1320
DS39605D-page 184 © 2006 Microchip Technology Inc.
19.4.4 POR OR WAKE FROM SLEEP
The FS CM is designed to detect osc illator failu re at any
point after the device has exited Power-on Reset
(POR) or Low-Power Sleep mode. When the primary
system clock is EC, RC or INTRC modes, monitoring
can begin immediately following these events.
For oscillator modes involving a crystal or resonator
(HS, HSPLL, LP or XT), the situation is somewhat dif-
ferent. Since the oscillator may require a start-up time
consid erably longer th an the FCSM s ample clock tim e,
a false clock failure may be detected. To prevent this,
the internal oscillator block is automatically configured
as the system clock and functions until the primary
clock is stable (the OST and PLL timers have timed
out). This is identical to Two-Speed Start-up mode.
Once the primary clock is stable, the INTRC returns to
its role as the FSCM source
As not ed in Section 19.3.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alter-
nate power managed mode while waiting for the
primary sy s t em c loc k to become st able. When the new
powere d manag ed mode is selecte d, th e primary cl ock
is disabled.
Note: The sa me logi c tha t prevents false oscill a-
tor failure interrupts on POR or wake from
Sleep will al so prevent t he detectio n of the
oscillator’s failure to start at all following
these events. This can be avoided by
monitoring the OSTS bit and using a
timing routine to determine if the oscillator
is taking too long to start. Even so, no
oscillator failure interrupt will be flagged.
© 2006 Microchip Technology Inc. DS39605D-page 185
PIC18F1220/1320
19.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro devices.
The user p r og ram me mo ry is di vided into three blocks .
One of these is a boot block of 512 bytes. The remain-
der of the memory is divided into two blocks on binary
boundaries.
Each of the three blocks has three protection bits
associated with them. They are:
Code-Protect bit (CPn)
Write-Protect bit (WRTn)
External Block Table Read bit (EBTRn)
Figure 19-5 shows the program memory organization
for 4 and 8-Kbyte de vice s and the specifi c code protec -
tion bit associated with each block. The actual locations
of the bits are summarized in Table 19-3.
FIGURE 19-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F1220/1320
TABLE 19-3: SUMMARY OF CODE PROTECTION REGISTERS
Block Code
Protection
Controlled By:
MEMORY SIZE/DEVICE Block Code
Protection
Controlled By:
Address
Range 4Kbytes
(PIC18F1220) 8Kbytes
(PIC18F1320) Address
Range
CPB, WRTB, EBTRB 000000h
0001FFh Boot Block Boot Block 000000h
0001FFh CPB, WRTB, EBTRB
CP0, WRT0, EBTR0 000200h
0007FFh Bloc k 0 Block 0
000200h
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1 000800h
000FFFh Block 1 000FFFh
(Unimplemented
Memory Space)
001000h
Unimplemented
Read ‘0’s
Block 1
001000h
CP1, WRT1, EBTR1
001FFFh
1FFFFFh
Unimplemented
Read ‘0’s
002000h
1FFFFFh
(Unimplemented
Memory Space)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
300008h CONFIG5L ——————CP1CP0
300009h CONFIG5H CPD CPB ——————
30000Ah CONFIG6L ————— WRT1 WRT0
30000Bh CONFIG6H WRTD WRTB WRTC —————
30000Ch CONFIG7L ————— EBTR1 EBTR0
30000Dh CONFIG7H EBTRB ——————
Legend: Shaded cells are uni mp lem en t ed .
PIC18F1220/1320
DS39605D-page 186 © 2006 Microchip Technology Inc.
19.5.1 PROGRAM MEMORY
CODE PROTECTION
The program memory may be read to, or written from,
any location using the table read and table write
instructions. The device ID may be read with table
reads. The configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTn configuration bit is 0’. The EBTRn
bits control table reads. For a block of user memory
with the EBTRn bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
A table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading0’s. Figures 19-6 through 19-8
ill ustrate table write and table read protect ion.
FIGURE 19-6: TABLE WRITE (WRTn) DISALLOWED: PIC18F1320
Note: Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1 to a bit in the ‘0’ st ate. Code p ro-
tection b its are only set to ‘1’ by a fu ll Chi p
Erase or Block Erase function. The full
Chip Erase and Blo ck Erase func tions can
only be initiated via ICSP or an external
programmer.
000000h
0001FFh
000200h
000FFFh
001000h
001FFFh
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
TBLWT *
TBLPTR = 0002FFh
PC = 0007FEh
TBLWT *
PC = 0017FEh
Register Values Program Memory Configuration Bit Settings
Results: All table writes disabled to Blockn whenever WRTn = 0.
WRT1, EBTR1 = 11
© 2006 Microchip Technology Inc. DS39605D-page 187
PIC18F1220/1320
FIGURE 19-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED: PIC18F1320
FIGURE 19-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED: PIC18F1320
000000h
0001FFh
000200h
000FFFh
001000h
001FFFh
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
WRT1, EBTR1 = 11
TBLPTR = 0002FFh
Register Values Program Memory Configuration Bit Settings
PC = 001FFEh TBLRD *
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
000000h
0001FFh
000200h
000FFFh
001000h
001FFFh
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
WRT1, EBTR1 = 11
TBLRD *
TBLPTR = 0002FFh
PC = 0007FEh
Register Values Program Memory Configuration Bit Settings
Results: Table reads permitte d within Blockn, even when EBTRBn = 0.
TABLAT register returns the value of the data at the location TBLPTR.
PIC18F1220/1320
DS39605D-page 188 © 2006 Microchip Technology Inc.
19.5.2 DATA EEPROM
CODE PROTECTION
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits external writes to data EEPROM. The
CPU can continue to read and write data EEPROM,
regardless of the protection bit settings.
19.5.3 CONFIGURATION REGISTER
PROTECTION
The con figurat ion registers can be write-pro tected. Th e
WRTC bit controls protection of the configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP or
an external programmer.
19.6 ID Locations
Eight memory locations (200000h-200007h) are
designated as ID locations, where the user can store
checksum or other code identification numbers. These
locatio ns are b oth read abl e a nd w ri table durin g no rma l
execution through the TBLRD and TBLWT instructions,
or du r ing p r ogr am / ve rif y. Th e ID lo cat io n s c a n be r e ad
when the de vice is code-protected.
19.7 In-Circuit Serial Programming
PIC18F1220/1320 microcontrollers can be serially
progra mmed w hile in t he en d app licati on c ircuit. This i s
simply done with tw o lines for cl ock and data and thre e
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed (see Table 19-4).
19.8 In-Circuit Debugger
When the DEBUG bit in configuration register,
CONFIG4L, is programmed to a ‘0’, the In-Circuit
Debugg er fun cti on ali ty is ena ble d. Thi s fun cti on allo w s
simple debugging functions when used with MPLAB®
IDE. When the microcontroller has this feature
enabled, some resources are not available for general
use. Table 19-5 shows which resources are required by
the background debugger.
TABLE 19-5: DEBUGGER RESOURCES
To use the In-Circuit Debugger function of the
microcontroller, the design must implement In-Circuit
Serial Programming connections to MCLR/VPP, VDD,
VSS, RB7 and RB6. This will interface to the In-Circuit
Debu gger modu le avail able from Microchip , or one of the
thir d party developm ent tool compa nies (see th e note fol -
lowing Section 19.7 “In-Circuit Serial Programming”
for mo re in formation).
Note: The Timer1 oscillator shares the T1OSI
and T1OSO pins with the PGD and PGC
pins used for programming and
debugging.
When using the Timer1 oscillator, In-Circuit
Serial Programming (ICSP) may not
function correctly (high voltage or low
voltage), or the In-Circuit Debugger (ICD)
may not communicate with the controller.
As a result of using either ICSP or ICD, the
Timer1 cryst al m ay be dam aged.
If ICSP or ICD operatio ns are requi red, the
crystal should be disconnected from the
circuit (disconne ct either lead ), or insta lled
after programming. The oscillator loading
capacitors may remain in-circuit during
ICSP or ICD operation.
TABLE 19-4: ICSP/ICD CONNECTIONS
Signal Pin Notes
PGD RB7/PGD/T1OSI/
P1D/KBI3 Shared with T1OSC – protect
crystal
PGC RB6/PGC/T1OSO/
T13CKI/P1C/KBI2 Shared with T1OSC – protect
crystal
MCLR MCLR/VPP/RA5
VDD VDD
VSS VSS
PGM RB5/PGM/KBI1 O ptional – pull RB5 low is
LV P enabled
I/O pins: RB6, RB7
Stack: 2 levels
Program Memory: 512 bytes
Data Memory: 10 bytes
© 2006 Microchip Technology Inc. DS39605D-page 189
PIC18F1220/1320
19.9 Low-Voltage ICSP Programming
The LVP bit in configuration register, CONFIG4L,
enables Low-Voltage Programming (LVP). When LVP
is enabled, the microcontroller can be programmed
without requiring high voltage being applied to the
MCLR/VPP/RA5 pin, but the RB5/PGM/KBI1 pin is then
dedica ted to controll ing Program mo de entry and is not
available as a general purpose I/O pin.
LVP is enabled in erased de vices.
While programming using LVP, VDD is applied to the
MCLR/VPP/RA5 pin as in normal execution mode. To
enter Programming mode, VDD is applied to the PGM
pin.
If Low-V olt age Programming mode will not be used, the
LVP bit can be cleared and RB5/PGM/KBI1 becomes
availa ble as the digi tal I/ O pin RB5. The LVP bit may be
set or cleared only when using standard high-voltage
programm ing (VIHH applied to the MCL R/VPP/RA5 pin).
Once LVP has been disabled, only the standard high-
voltage programming is available and must be used to
program the device.
Memory that is not code-protected can be erased,
using either a Block Erase, or erased row by row, then
written at any spec ified V DD. If co de -protect ed mem ory
is to be erased, a Block Erase is required. If a Block
Erase is to be performed when using Low-Voltage
Programm ing, the dev ice mu st be suppl ied with V DD of
4.5V to 5.5V.
Note 1: High-voltage programming is always
available, regardless of the state of the
LVP bit or the PGM pin, by applying VIHH
to the MCLR pin.
2: When Low-Voltage Programming is
enabled, the RB5 pin can no longer be
used as a general purpose I/O pin.
3: When LVP is enabled, externally pull the
PGM pin to VSS to allow norm al pr ogr am
execution.
PIC18F1220/1320
DS39605D-page 190 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS39605D-page 191
PIC18F1220/1320
20.0 INSTRUCTION SET SUMMARY
The PIC18 instruction set adds many enhancements to
the previous PICmicro instruction sets, while maintaining
an easy m igration from thes e PICmicro instruc tion set s.
Most instructions are a single program memory word
(16 bits), but there are three instructions that require
two program memory locations.
Each single-word instruction is a 16-bit word divided
into an o pcode, whi ch specifies the instructi on type and
one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
Byte-oriented operations
Bit-oriented operations
Literal operati ons
Control operations
The PIC18 instruction set summary in Table 20-1 lists
byte-oriented, bit-oriented, literal and control
operations. Table 20-1 shows the opcode field
descriptions.
Most byte-oriented in str uct ions have t hree op erands:
1. The file register (specified by ‘f’)
2. The destination of the result
(specified by ‘d’)
3. The access ed memory
(specified by ‘a’)
The file register designator ‘f’ specifies which file
register is to be used by the instruction.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If ‘d’ is zero, the
result is placed in the WREG register. If ‘d’ is one, the
result is placed in the file register specified in the
instruction.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
2. The bit in the file register
(specified by ‘b’)
3. The access ed memory
(specified by ‘a’)
The bit field design ator ‘b’ sele cts the numb er of the bit
affected by the operation, while the file register desig-
nator ‘f’ represents the number of the file in which the
bit is located.
The literal instructions may use some of the following
operands:
A literal value to be loaded into a file register
(specified by ‘k’)
The desired FSR r egister to load the literal value
into (specified by ‘f’)
No operan d requi red
(specified by ‘—’)
The control instruct ions may u se some of t he followin g
operands:
A program memory address (specified by ‘n’)
The mode of the CALL or RETURN instructions
(specified by ‘s’)
The mode of the table read and table write
ins tructions (specif ied by ‘m’)
No operand requir ed
(specified by ‘—’)
All instructions are a single word, except for three
double-word instructions. These three instructions
were made double-word instructions so that all the
required information i s av ail abl e i n t hes e 3 2 b it s . I n th e
second word, the 4 MSbs are ‘1s. If this second word
is executed as an instruction (by itself), it will execute
as a NOP.
All single-word instructions are executed in a single
inst ruction cycle, unl ess a conditi onal test is true, or th e
program counter is changed as a result of the instruc-
tion. In th ese cases, the execution takes two i nstruction
cycle s, with the addit ional instru ction cyc le(s) exec uted
as a NOP.
The doub le-word inst ructions exe cute in two ins truction
cycles.
One in struction cycle consist s of f our oscil lator peri ods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
Two-word branch instructions (if true) would take 3 μs.
Figure 20-1 shows the general formats that the
inst ruc t ion s can have .
All examp le s us e the fo rma t ‘nnhto represent a hexa-
decimal number, where ‘h’ signifies a hexadecimal
digit.
The Instruction Set Summary, shown in Table 20-1,
lists the instructions recognized by the Microchip
Assembler (MPASMTM). Section 20.2 “Instruction
Set” provides a description of each instruction.
20.1 Read-Modify-Write Operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operatio n. The register i s read, the dat a is modifie d and
the result is stored ac cording to ei ther the inst ruction or
the destination designator ‘d’. A read operation is
perfor med on a regi ste r ev en i f the ins truc ti on wr i tes to
that register.
For example, a “BCF PORTB,1” instruction will read
PORTB, clear bit 1 of the data, then write the result
back to PORTB. The read operation would have the
unintended result that any condition that sets the RBIF
flag would be cleared. The R-M-W operation may also
copy the level of an input pin to its corresponding output
latch.
PIC18F1220/1320
DS39605D-page 192 © 2006 Microchip Technology Inc.
TABLE 20-1: OPCODE FIELD DESCRIPTIONS
Field Description
aRAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb Bit address within an 8-bit file register (0 to 7).
BSR Bank Select Register. Used to select the current RAM bank.
dDestination select bit
d = 0: store result in WREG
d = 1: store result in file register f
dest Destination either the WREG register or the specified register file location.
f8-bit register file address (0x00 to 0xFF).
fs 12-bit register file address (0x000 to 0xFFF). This is the source address.
fd 12-bit register file address (0x000 to 0xFFF). This is the destination address.
kLiteral field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label Label name.
mm The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*No change to register (such as TBLPTR with table reads and writes)
*+ Post-Increment register (suc h as TBLPTR with table reads and writes)
*- Post-Decrement register (such as TBLPTR with table reads and writes)
+* Pre-Increment register (such as TBLPTR with table reads and writes)
nThe relative address (2’s complement number) for relative branch instructions, or the direct address for
call/branch and return instructions.
PRODH Product of Multiply High Byte.
PRODL Product of Multiply Low Byte.
sFast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (F ast m ode)
uUnused or unchanged.
WREG Working register (accumulator).
xDon’t care (‘0’ or ‘1’).
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.
TBLPTR 21-bit Table Pointer (points to a program memory location).
TABLAT 8-bit Table Latch.
TOS Top-of-Stack.
PC Program Counter.
PCL Program Counter Low Byte.
PCH Program Counter High Byte.
PCLATH Program Counter High Byte Latch.
PCLATU Program Counter Upper Byte Latch.
GIE Global Interrupt Enable bit.
WDT Watchdog Timer.
TO Time-out bit.
PD Power-down bit.
C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
[ ] Optional.
( ) Contents.
Assigned to.
< > Register bit field.
In the set of.
italics User defined term (font is Courier).
© 2006 Microchip Technology Inc. DS39605D-page 193
PIC18F1220/1320
FIGURE 20-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10 9 8 7 0
d = 0 for result destination to be WREG register
OPCODE d a f (FILE #)
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
Bit-oriented file register operations
15 12 11 9 8 7 0
OPCODE b (BIT #) a f (FILE #)
b = 3-bit position of bit in file register (f)
Literal operations
15 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
Byte to Byte move operations (2-word)
15 12 11 0
OPCODE f (Source FILE #)
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal)
n = 20-bit immediate value
a = 1 for BSR to select bank
f = 8-bit file register address
a = 0 to force Acc ess Bank
a = 1 for BSR to select bank
f = 8-bit file register address
15 12 11 0
1111 n<19:8> (literal)
15 12 11 0
1111 f (Destina tion FILE #)
f = 12-bit file register address
Control operations
Example Instruction
ADDWF MYREG, W, B
MOVFF MYREG1, MYREG2
BSF MYREG, bit, B
MOVLW 0x7F
GOTO Label
15 8 7 0
OPCODE n<7:0> (literal)
15 12 11 0
n<19:8> (literal)
CALL MYFUNC
15 11 10 0
OPCOD E n<10:0> ( li t e r a l )
S = Fast bit
BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
S
PIC18F1220/1320
DS39605D-page 194 © 2006 Microchip Technology Inc.
TABLE 20-1: PIC18FXXXX INSTRUCTION SET
Mnemonic,
Operands Description Cycles 16-Bit Instruction Word Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
SUBWF
SUBWFB
SWAPF
TSTFSZ
XORWF
f, d , a
f, d , a
f, d , a
f, a
f, d , a
f, a
f, a
f, a
f, d , a
f, d , a
f, d , a
f, d , a
f, d , a
f, d , a
f, d , a
f, d , a
fs, fd
f, a
f, a
f, a
f, d , a
f, d , a
f, d , a
f, d , a
f, a
f, d , a
f, d , a
f, d , a
f, d , a
f, a
f, d , a
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move fs (source) to 1st word
fd (destination) 2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
borrow
Subtract WREG from f
Subtract WREG from f with
borrow
Swap nibble s in f
Test f, skip if 0
Exclusive OR WREG with f
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1 (2 or 3)
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
0101
0101
0011
0110
0001
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
11da
10da
10da
011a
10da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
C, DC, Z, OV, N
C, DC, Z, OV, N
None
None
Z, N
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1, 2
1, 2
1, 2
1, 2
4
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b , a
f, b , a
f, b , a
f, b , a
f, d , a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1
1
1 (2 or 3)
1 (2 or 3)
1
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1, 2
1, 2
3, 4
3, 4
1, 2
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the pr escaler will be cleared
if assigned.
3: If Program Coun ter (PC) is mo dified or a c onditional te st is true, th e instructi on requires two cycles. Th e second
cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP,
unless th e firs t word of the instruct ion r etrieve s the inform ation e mbedd ed in these 16 bit s. T his en sures that al l
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
© 2006 Microchip Technology Inc. DS39605D-page 195
PIC18F1220/1320
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
CLRWDT
DAW
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
RETLW
RETURN
SLEEP
n
n
n
n
n
n
n
n
n
n, s
n
n
s
k
s
Branch if Carry
Branch if Negat ive
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unco nd itio nally
Branch if Zero
Call subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
No Operation
No Operation
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
Return with literal in WREG
Return from Subroutine
Go into Standby mode
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
1
1
2
1
1
1
1
2
1
2
2
2
1
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
0000
0000
0000
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
1100
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
kkkk
0001
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
kkkk
001s
0011
None
None
None
None
None
None
None
None
None
None
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
None
None
TO, PD
4
TABLE 20-1: PIC18FXXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands Description Cycles 16-Bit Instruction Word Status
Affected Notes
MSb LSb
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the pr escaler will be cleared
if assigned.
3: If Program Coun ter (PC) is mo dified or a c onditional te st is true, th e instructi on requires two cycles. Th e second
cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP,
unless th e firs t word of the instruct ion r etrieve s the inform ation e mbedd ed in these 16 bit s. T his en sures that al l
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
PIC18F1220/1320
DS39605D-page 196 © 2006 Microchip Technology Inc.
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
f, k
k
k
k
k
k
k
Add literal and WREG
AND literal with WREG
Inclusive OR lite ral with WREG
Move literal (12-bit) 2nd word
to FSRx 1st word
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from litera l
Exclusive OR literal wi th WREG
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
None
None
None
None
C, DC, Z, OV, N
Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD*
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table read
Table r ead with post-increment
Table r ead with post-decrement
Table read with pre- increment
Table write
Table write with post-increment
Table write with post-decrement
Table write with pre-increment
2
2 (5)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
TABLE 20-1: PIC18FXXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands Description Cycles 16-Bit Instruction Word Status
Affected Notes
MSb LSb
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the pr escaler will be cleared
if assigned.
3: If Program Coun ter (PC) is mo dified or a c onditional te st is true, th e instructi on requires two cycles. Th e second
cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP,
unless th e firs t word of the instruct ion r etrieve s the inform ation e mbedd ed in these 16 bit s. T his en sures that al l
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
© 2006 Microchip Technology Inc. DS39605D-page 197
PIC18F1220/1320
20.2 Instruction Set
ADDLW ADD literal to W
Syntax: [ label ] ADDLW k
Operands: 0 k 255
Operation: (W) + k W
Status Affected: N, OV, C, DC, Z
Encoding: 0000 1111 kkkk kkkk
Desc ription: The c ontents of W are added to the
8-bit literal ‘k’ and the result is
placed in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write to W
Example:ADDLW 0x15
Before Instruction
W = 0x10
After Instruction
W = 0x25
ADDWF ADD W to f
Syntax: [ label ] ADDWF f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) + (f) dest
Status Affecte d: N, OV, C, DC, Z
Encoding: 0010 01da ffff ffff
Description: Add W to register ‘f’. If ‘d’ is ‘0’, the
result is store d in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is0’, the Access
Bank will be selected. If ‘a’ is ‘1’,
the BSR is used.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:ADDWF REG, W
Before Instruc tio n
W = 0x17
REG = 0xC2
After Instruction
W=0xD9
REG = 0xC2
PIC18F1220/1320
DS39605D-page 198 © 2006 Microchip Technology Inc.
ADDWFC ADD W and Carry bit to f
Syntax: [ label ] ADDWFC f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) + (f) + (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0010 00da ffff ffff
Description: Add W, the Carry flag and data
memory location ‘f’. If ‘d’ is ‘0’, the
result is placed in W. If ‘d’ is ‘1’, the
result is placed in data memory
location ‘f’. If ‘a’ is ‘0’, the Access
Bank wil l b e s ele cte d. If ‘a’ is ‘1’, the
BSR will not be overridden.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:ADDWFC REG, W
Before Instruction
Carry bit = 1
REG = 0x02
W = 0x4D
After Instruction
Carry bit = 0
REG = 0x02
W = 0x50
ANDLW AND literal with W
Syntax: [ label ] ANDLW k
Operands: 0 k 255
Operation: (W) .AND. k W
St at us Af fe cte d: N, Z
Encoding: 0000 1011 kkkk kkkk
Descr iption: The co ntents of W are AND’ed with
the 8-bit literal ‘k’. The result is
placed in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’ Proces s
Data Write to W
Example:ANDLW 0x5F
Before Instruc tio n
W=0xA3
After Instruction
W = 0x03
© 2006 Microchip Technology Inc. DS39605D-page 199
PIC18F1220/1320
ANDWF AND W with f
Syntax: [ label ] ANDWF f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .AND. (f) dest
Status Affected: N, Z
Encoding: 0001 01da ffff ffff
Desc ription: The co ntents of W are AND’ed with
register ‘f’. If ‘d’ is0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected. If ‘a’ is1’, the BSR will
not be overridden (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:ANDWF REG, W
Before Instruction
W = 0x17
REG = 0xC2
After Instruction
W = 0x02
REG = 0xC2
BC Branch if Carry
Syntax: [ label ] BC n
Operands: -128 n 127
Operation: if Carry bit is ‘1
(PC) + 2 + 2n PC
St at us Af fe cte d: None
Encoding: 1110 0010 nnnn nnnn
Description: If the Carry bit is ‘1’, then the
progr am w ill branc h.
The 2’s complement nu mber ‘2n’ i s
added to the PC. Since the PC will
have incremented to fetch the next
instruc tion, the n ew a ddr ess will be
PC + 2 + 2n. T his instruction is then
a two -cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump :Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BC JUMP
Before Instruc tio n
PC = address (HERE)
After Instruction
If Carry = 1;
PC = address (JUMP)
If Carry = 0;
PC = address (HERE + 2)
PIC18F1220/1320
DS39605D-page 200 © 2006 Microchip Technology Inc.
BCF Bit Clear f
Syntax: [ label ] BCF f,b[,a]
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 0 f<b>
Status Affected: None
Encoding: 1001 bbba ffff ffff
Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’
is ‘0’, the Access Bank will be
selec ted, over riding the BSR value .
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example:BCF FLAG_REG, 7
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
BN Branch if Negative
Syntax: [ label ] BN n
Operands: -128 n 127
Operation: if Negative bit is ‘1
(PC) + 2 + 2n PC
St at us Af fe cte d: None
Encoding: 1110 0110 nnnn nnnn
Description: If the Negative bit is ‘1, then the
progr am w ill branc h.
The 2’s complement nu mber ‘2n’ i s
added to the PC. Since the PC will
have incremented to fetch the next
instruc tion, the n ew a ddr ess will be
PC + 2 + 2n. T his instruct ion is then
a two -cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump :Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BN Jump
Before Instruc tio n
PC = address (HERE)
After Instruction
If Negative = 1;
PC = address (Jump)
If Negative = 0;
PC = address (HERE + 2)
© 2006 Microchip Technology Inc. DS39605D-page 201
PIC18F1220/1320
BNC Branch if Not Carry
Syntax: [ label ] BNC n
Operands: -128 n 127
Operation: if Carry bit is ‘0
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0011 nnnn nnnn
Description: If the Carry bit is ‘0’, then the
program will branch.
The 2’s co mp lem en t nu mb er ‘ 2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n . This instruct ion is then
a two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BNC Jump
Before Instruction
PC = address (HERE)
After Instruction
If Carry = 0;
PC = address (Jump)
If Carry = 1;
PC = address (HERE + 2)
BNN Branch if Not Negative
Syntax: [ label ] BNN n
Operands: -128 n 127
Operation: if Negative bit is ‘0
(PC) + 2 + 2n PC
St at us Af fe cte d: None
Encoding: 1110 0111 nnnn nnnn
Description: If the Negative bit is ‘0, then the
progr am w ill branc h.
The 2’s complement nu mber ‘2n’ i s
added to the PC. Since the PC will
have incremented to fetch the next
instruc tion, the n ew a ddr ess will be
PC + 2 + 2n. T his instruction is then
a two -cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump :Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BNN Jump
Before Instruc tio n
PC = address (HERE)
After Instruction
If Negative = 0;
PC = address (Jump)
If Negative = 1;
PC = address (HERE + 2)
PIC18F1220/1320
DS39605D-page 202 © 2006 Microchip Technology Inc.
BNOV Branch if Not Overflow
Syntax: [ label ] BNOV n
Operands: -128 n 127
Operation: if Overflow bit is ‘0
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0101 nnnn nnnn
Description: If the Overfl ow bit is ‘0’, then the
program will branch.
The 2’s co mp lem en t nu mb er ‘ 2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n . This instruct ion is then
a two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BNOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If Overflow = 0;
PC = address (Jump)
If Overflow = 1;
PC = address (HERE + 2)
BNZ Branch if Not Zero
Syntax: [ label ] BNZ n
Operands: -128 n 127
Operation: if Zero bit is ‘0
(PC) + 2 + 2n PC
St at us Af fe cte d: None
Encoding: 1110 0001 nnnn nnnn
Description: If the Zero bit is ‘0’, then the
progr am w ill branc h.
The 2’s complement nu mber ‘2n’ i s
added to the PC. Since the PC will
have incremented to fetch the next
instruc tion, the n ew a ddr ess will be
PC + 2 + 2n. T his instruct ion is then
a two -cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump :Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BNZ Jump
Before Instruc tio n
PC = address (HERE)
After Instruction
If Zero = 0;
PC = address (Jump)
If Zero = 1;
PC = address (HERE + 2)
© 2006 Microchip Technology Inc. DS39605D-page 203
PIC18F1220/1320
BRA Unconditional Branch
Syntax: [ label ] BRA n
Operands: -1024 n 1023
Operation: (PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 0nnn nnnn nnnn
Description: Add the 2’s complement number
‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
Example:HERE BRA Jump
Before Instruction
PC = address (HERE)
After Instruction
PC = address (Jump)
BSF Bit Set f
Syntax: [ label ] BSF f,b[,a]
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 1 f<b>
St at us Af fe cte d: None
Encoding: 1000 bbba ffff ffff
Descr iption : Bit ‘b’ in re gister ‘f’ is s et. If ‘a’ is ‘0’,
the Access Bank will be selected,
overridi ng the BSR v alu e. If ‘ a’ = 1,
then the bank will be selected as
per the BSR va lue.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example:BSF FLAG_REG, 7
Before Instruc tio n
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
PIC18F1220/1320
DS39605D-page 204 © 2006 Microchip Technology Inc.
BTFSC Bit Test File, Skip if Clear
Syntax: [ label ] BTFSC f,b[,a]
Operands: 0 f 255
0 b 7
a [0,1]
Operation: skip if (f<b>) = 0
Status Affected: None
Encoding: 1011 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next
instruc tio n f etc hed du ring the curren t
instruction execution is discarded
and a NOP is executed instead,
making this a two-cycle instruction. If
‘a’ is 0’, the Access Bank will be
selec ted, overriding the BSR value. If
‘a’ = 1, then the bank will be se lecte d
as per the BSR value (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (TRUE)
If FLAG<1> = 1;
PC = address (FALSE)
BTFSS Bit Test File, Skip if Set
Syntax: [ label ] BTFSS f,b[,a]
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: skip if (f<b>) = 1
St at us Af fe cte d: None
Encoding: 1010 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next
instruc tion fetche d during the cu rrent
instruction execution is discarded
and a NOP is executed instead,
making this a two-cycle instruction. If
‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ = 1, then the ban k will be s elect ed
as pe r the BSR valu e (defaul t).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1
Before Instruc tio n
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (FALSE)
If FLAG<1> = 1;
PC = address (TRUE)
© 2006 Microchip Technology Inc. DS39605D-page 205
PIC18F1220/1320
BTG Bit Toggle f
Syntax: [ label ] BTG f,b[,a]
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: (f<b>) f<b>
Status Affected: None
Encoding: 0111 bbba ffff ffff
Description: Bit ‘b’ in data memory location ‘f’ is
inverte d. If ‘a ’ is ‘0’, th e Ac cess Bank
will be selected, overriding the BSR
value. If ‘ a’ = 1, then the ban k w i ll be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example:BTG PORTB, 4
Before Instruction:
PORTB = 0111 0101 [0x75]
After Instruction:
PORTB = 0110 0101 [0x65]
BOV Branch if Ov erflow
Syntax: [ label ] BOV n
Operands: -128 n 127
Operation: if Overflow bit is ‘1
(PC) + 2 + 2n PC
St at us Af fe cte d: None
Encoding: 1110 0100 nnnn nnnn
Description: If the Overflow bit is1’, then the
progr am w ill branc h.
The 2’s complement nu mber ‘2n’ i s
added to the PC. Since the PC will
have incremented to fetch the next
instruc tion, the n ew a ddr ess will be
PC + 2 + 2n. T his instruction is then
a two -cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump :Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BOV JUMP
Before Instruc tio n
PC = address (HERE)
After Instruction
If Overflow = 1;
PC = address (JUMP)
If Overflow = 0;
PC = address (HERE + 2)
PIC18F1220/1320
DS39605D-page 206 © 2006 Microchip Technology Inc.
BZ Branch if Zero
Syntax: [ label ] BZ n
Operands: -128 n 127
Operation: if Zero bit is ‘1
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0000 nnnn nnnn
Description: If the Zero bit is ‘1’, then the
program will branch.
The 2’s co mp lem en t nu mb er ‘ 2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n . This instruct ion is then
a two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example:HERE BZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If Zero = 1;
PC = address (Jump)
If Zero = 0;
PC = address (HERE + 2)
CALL Subroutine Call
Syntax: [ label ] CALL k [,s]
Operands: 0 k 1048575
s [0,1]
Operati on: (PC) + 4 TOS,
k PC<20:1>,
if s = 1
(W) WS,
(Status) STATUSS,
(BSR) BSRS
St at us Af fe cte d: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>) 1110
1111
110s
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description: Subroutine call of entire 2-Mbyte
memory range. First, return
address (PC + 4) is pushed onto
the return stack. If ‘s’ = 1, the W,
Status and BSR registers are also
pushed into their respective
shadow registers, WS, STATUSS
and BSRS. If ‘s’ = 0, no update
occu rs (default). Then, the 20- bit
value ‘k’ is loaded into PC<20:1>.
CALL is a two-cycle instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’<7:0>, Push PC to
stack Read literal
‘k’<19:8>,
Write to PC
No
operation No
operation No
operation No
operation
Example:HERE CALL THERE, FAST
Before Instruc tio n
PC = address (HERE)
After Instruction
PC = address (THERE)
TOS = address (HERE + 4)
WS = W
BSRS = BSR
STATUSS = Status
© 2006 Microchip Technology Inc. DS39605D-page 207
PIC18F1220/1320
CLRF Clear f
Syntax: [ label ] CLRF f [,a]
Operands: 0 f 255
a [0,1]
Operation: 000h f
1 Z
Status Affected: Z
Encoding: 0110 101a ffff ffff
Description: Clears the contents of the specified
register. If ‘a’ is ‘0’, the Access
Bank w ill be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example:CLRF FLAG_REG
Before Instruction
FLAG_REG = 0x5A
After Instruction
FLAG_REG = 0x00
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 000h WDT,
000h WDT postscal er,
1 TO,
1 PD
St at us Af fe cte d: TO, PD
Encoding: 0000 0000 0000 0100
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits,
TO and PD, are set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation Process
Data No
operation
Example:CLRWDT
Before Instruc tio n
WDT Counter = ?
After Instruction
WDT Counter = 0x00
WDT Postscaler = 0
TO =1
PD =1
PIC18F1220/1320
DS39605D-page 208 © 2006 Microchip Technology Inc.
COMF Complement f
Syntax: [ label ] COMF f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) des t
Status Affected: N, Z
Encoding: 0001 11da ffff ffff
Desc ript ion : The content s of regi ste r ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is store d in W. If ‘d’ is ‘1’, the
result is sto r ed back in register ‘f’
(default). If ‘a’ is0’, the Access
Bank w ill be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:COMF REG, W
Before Instruction
REG = 0x13
After Instruction
REG = 0x13
W=0xEC
CPFSEQ Compare f with W, skip if f = W
Syntax: [ label ] CPFSEQ f [,a]
Operands: 0 f 255
a [0,1]
Operation: (f) – (W),
skip if (f) = (W)
(unsign ed comparis on )
St at us Af fe cte d: None
Encoding: 0110 001a ffff ffff
Description: Compares the contents of data
memory location ‘f ’ to the contents
of W by performing an unsigned
subtraction.
If ‘f’ = W, then the fetched
instruction is discarded and a NOP
is execut ed instead, m aking this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overridi ng the BSR v alu e. If ‘ a’ = 1,
then the bank will be selected as
per the BSR value (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE CPFSEQ REG
NEQUAL :
EQUAL :
Before Instruc tio n
PC Address = HERE
W=?
REG = ?
After Instruction
If REG = W;
PC = Address (EQUAL)
If REG W;
PC = Address (NEQUAL)
© 2006 Microchip Technology Inc. DS39605D-page 209
PIC18F1220/1320
CPFSGT Compare f with W, skip if f > W
Syntax: [ label ] CPFSGT f [,a]
Operands: 0 f 255
a [0,1]
Operation: (f) – (W),
skip if (f) > (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 010a ffff ffff
Description: Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If the conten ts of ‘f’ are greater t han
the contents of WREG, then the
fetched instruct ion is disca rded and
a NOP is exec uted instead, making
this a two-cycle instruction. If ‘a’ is
0’, the Access Bank will be
selec ted, over riding the BSR value .
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if s k ip a nd fo llo w ed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE CPFSGT REG
NGREATER :
GREATER :
Before Instruction
PC = Address (HERE)
W= ?
After Instruction
If REG > W;
PC = Address (GREATER)
If REG W;
PC = Address (NGREATER)
CPFSLT Compare f with W, skip if f < W
Syntax: [ label ] CPFSLT f [,a]
Operands: 0 f 255
a [0,1]
Operation: (f) – (W),
skip if (f) < (W)
(unsign ed comparis on )
St at us Af fe cte d: None
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data
memory location ‘f ’ to the contents
of W by performing an unsigned
subtraction.
If the contents of ‘f’ are less than
the con tents of W , then the fet che d
instruction is discarded and a NOP
is execut ed instead, m aking this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’
is ‘1’, the BSR will not be
overridden (default).
Words: 1
Cycles: 1(2)
Note: 3 cy cl es i f s ki p and fo llowed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE CPFSLT REG
NLESS :
LESS :
Before Instruc tio n
PC = Address (HERE)
W= ?
After Instruction
If REG < W;
PC = Address (LESS)
If REG W;
PC = Address (NLESS)
PIC18F1220/1320
DS39605D-page 210 © 2006 Microchip Technology Inc.
DAW Decimal Adjust W Register
Syntax: [ label ] DAW
Operands: None
Operation: If [W<3:0> > 9] or [DC = 1] then
(W<3:0>) + 6 W<3:0>;
else
(W<3:0>) W<3:0>;
If [W<7:4> > 9] or [C = 1] then
(W<7:4>) + 6 W<7:4>;
else
(W<7:4>) W<7 :4>;
Status Affected: C, DC
Encoding: 0000 0000 0000 0111
Description: DAW adjusts the eight-bit value in
W, resulting from the earlier addi-
tion of two variables (each in
packed BCD format) and produces
a correct packed BCD result. Th e
Carry bit may b e set b y DAW reg ard-
less of its setting prior to the DAW
instruction.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register W Process
Data Write
W
Example 1:DAW
Before Instruction
W=0xA5
C=0
DC = 0
After Instruction
W = 0x05
C=1
DC = 0
Example 2:
Before Instruction
W=0xCE
C=0
DC = 0
After Instruction
W = 0x34
C=1
DC = 0
DECF Decre ment f
Syntax: [ label ] DECF f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest
Status Affected: C, DC, N, OV, Z
Encoding: 0000 01da ffff ffff
Description: Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in W. If ‘d’ is ‘1’,
the resu lt is stor ed bac k in regi ste r
‘f’ (default). If ‘a’ is 0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (defaul t).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:DECF CNT
Before Instruc tio n
CNT = 0x01
Z=0
After Instruction
CNT = 0x00
Z=1
© 2006 Microchip Technology Inc. DS39605D-page 211
PIC18F1220/1320
DECFSZ Decrement f, skip if 0
Syntax: [ label ] DECFSZ f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest,
skip if result = 0
Status Affected: None
Encoding: 0010 11da ffff ffff
Desc ript ion : The content s of regi ste r ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is plac ed in W. If ‘d’ is 1’, the result
is pl aced back in register ‘f
(default).
If the result is ‘0’, the next instruc-
tion, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank w ill be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE DECFSZ CNT
GOTO LOOP
CONTINUE
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT – 1
If CNT = 0;
PC = Address (CONTINUE)
If CNT 0;
PC = Address (HERE + 2)
DCFSNZ Decrement f, skip if not 0
Syntax: [ label ] DCFSNZ f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest,
skip if result 0
St at us Af fe cte d: None
Encoding: 0100 11da ffff ffff
Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is plac ed in W. If ‘d ’ is ‘1’, the result
is pl aced back in register ‘f
(default).
If the result is not ‘0’, the next
instruction, which is already
fetched, is discarded and a NOP is
executed instead, making it a two-
cycl e instruction. If ‘a ’ is ‘0’, the
Access Bank will be selected,
overridi ng the BSR val ue. If ‘a’ = 1,
then the bank will be selected as
per the BSR value (default).
Words: 1
Cycles: 1(2)
Note: 3 cy c les if sk ip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE DCFSNZ TEMP
ZERO :
NZERO :
Before Instruc tio n
TEMP = ?
After Instruction
TEMP = TEMP – 1,
If TEMP = 0;
PC = Address (ZERO)
If TEMP 0;
PC = Address (NZERO)
PIC18F1220/1320
DS39605D-page 212 © 2006 Microchip Technology Inc.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 1048575
Operation: k PC<20:1>
Status Affected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>) 1110
1111
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description: GOTO allows an unconditional
branch anywhere within the entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>.
GOTO is always a two-cycle
instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’<7:0>, No
operation Read literal
‘k’<19:8>,
Write to PC
No
operation No
operation No
operation No
operation
Example:GOTO THERE
After Instruction
PC = Address (THERE)
INCF I ncrem ent f
Syntax: [ label ] INCF f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest
Status Affected: C, DC, N, OV, Z
Encoding: 0010 10da ffff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is plac ed in W. If ‘d ’ is ‘1’, th e result
is pl aced back in register ‘f
(default). If ‘a’ is0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (defaul t).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:INCF CNT
Before Instruc tio n
CNT = 0xFF
Z=0
C=?
DC = ?
After Instruction
CNT = 0x00
Z=1
C=1
DC = 1
© 2006 Microchip Technology Inc. DS39605D-page 213
PIC18F1220/1320
INCFSZ Increment f, skip if 0
Syntax: [ label ] INCFSZ f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if result = 0
Status Affected: None
Encoding: 0011 11da ffff ffff
Desc ript ion : The content s of regi ste r ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is plac ed in W. If ‘d ’ is ‘1’, th e result
is pl aced back in register ‘f
(default).
If the result is ‘0’, the next instruc-
tion, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank w ill be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1(2)
Note: 3 cycl es if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE INCFSZ CNT
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT + 1
If CNT = 0;
PC = Address (ZERO)
If CNT 0;
PC = Address (NZERO)
INFSNZ Increment f, skip if not 0
Syntax: [ label ] INFSNZ f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if result 0
St at us Af fe cte d: None
Encoding: 0100 10da ffff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is plac ed in W. If ‘d ’ is ‘1’, th e result
is pl aced back in register ‘f
(default).
If the result is not ‘0, the next
instruction, which is already
fetched, is discarded and a NOP is
executed instead, making it a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding th e BSR value. If ‘a’ = 1, th en
the b ank wi ll be selec ted as per th e
BSR value (defaul t).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE INFSNZ REG
ZERO
NZERO
Before Instruc tio n
PC = Address (HERE)
After Instruction
REG = REG + 1
If REG 0;
PC = Address (NZERO)
If REG = 0;
PC = Address (ZERO)
PIC18F1220/1320
DS39605D-page 214 © 2006 Microchip Technology Inc.
IORLW Inclusive OR literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. k W
Status Affected: N, Z
Encoding: 0000 1001 kkkk kkkk
Description: The contents of W are OR’ed with
the eight-bit literal ‘k’. The result is
placed in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write to W
Example:IORLW 0x35
Before Instruction
W = 0x9A
After Instruction
W=0xBF
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .OR. (f) dest
St at us Af fe cte d: N, Z
Encoding: 0001 00da ffff ffff
Description: Inclusive OR W with register ‘f’. If
‘d’ is0’, the result is pla ced in W. If
‘d’ is ‘1’, the result is p laced back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding th e BSR value. If ‘a’ = 1, th en
the bank wi ll be selec ted as p er the
BSR value (defaul t).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:IORWF RESULT, W
Before Instruc tio n
RESULT = 0x13
W = 0x91
After Instruction
RESULT = 0x13
W = 0x93
© 2006 Microchip Technology Inc. DS39605D-page 215
PIC18F1220/1320
LFSR Load FSR
Syntax: [ label ] LFSR f,k
Operands: 0 f 2
0 k 4095
Operation: k FSRf
Status Affected: None
Encoding: 1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Desc ription: The 12-bi t literal ‘k’ is loade d into
the file select register pointed to
by ‘f’.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’ MSB Process
Data W r ite literal
‘k’ MSB to
FSRfH
Decode Read literal
‘k’ LSB Process
Data Write literal
‘k’ to FSRfL
Example:LFSR 2, 0x3AB
After Instruction
FSR2H = 0x03
FSR2L = 0xAB
MOVF Move f
Syntax: [ label ] MOVF f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: f dest
St at us Af fe cte d: N, Z
Encoding: 0101 00da ffff ffff
Description: The contents of register ‘f’ are
moved to a destination dependent
upon the sta t us o f ‘ d’. If ‘d’ is ‘f’, the
result is placed in W. If ‘d’ is ‘f’, the
result is placed back in regi ster ‘f
(default). Location ‘f’ can be any-
where in the 25 6-b yte bank . If ‘a ’ is
0’, the Access Bank will be
selec ted, overri ding the BSR value .
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write W
Example:MOVF REG, W
Before Instruc tio n
REG = 0x22
W=0xFF
After Instruction
REG = 0x22
W = 0x22
PIC18F1220/1320
DS39605D-page 216 © 2006 Microchip Technology Inc.
MOVFF Move f to f
Syntax: [ label ] MOVFF fs,fd
Operands: 0 fs 4095
0 fd 4095
Operation: (fs) fd
Status Affected: None
Encoding:
1st word (source)
2nd word (destin.) 1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Description: The contents of source register ‘fs
are moved to destination register
‘fd’. Location of source ‘fs’ can be
anywhere in the 4096-byte data
space (000h to FFFh) and location
of destination ‘fd’ can also be
anywhere from 000h to FFFh.
Either so urc e or de st ination can be
W (a useful special situat ion).
MOVFF is particularly useful for
transferring a data memory location
to a periph eral register (such as the
transmit buffer or an I/O port).
The MOVFF instruction cannot use
the PCL, T OSU, T OSH or TOSL as
the destination register.
The MOVFF instruction should not
be use d to modi fy in terrupt s etting s
while any interrupt is enabled (see
page 74).
Words: 2
Cycles: 2 (3)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
(src)
Process
Data No
operation
Decode No
operation
No dummy
read
No
operation Write
register ‘f’
(dest)
Example:MOVFF REG1, REG2
Before Instruction
REG1 = 0x33
REG2 = 0x11
After Instruction
REG1 = 0x33,
REG2 = 0x33
MOVLB M ove literal to low nibble in BSR
Syntax: [ label ] MOVLB k
Operands: 0 k 255
Operation: k BSR
St at us Af fe cte d: None
Encoding: 0000 0001 kkkk kkkk
Description: The 8-bit literal ‘k’ is loaded into
the Bank Select Register (BSR).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’ Proces s
Data Write
literal ‘k’ to
BSR
Example:MOVLB 5
Before Instruc tio n
BSR register = 0x02
After Instruction
BSR register = 0x05
© 2006 Microchip Technology Inc. DS39605D-page 217
PIC18F1220/1320
MOVLW Move literal to W
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k W
Status Affected: None
Encoding: 0000 1110 kkkk kkkk
Description: The eight-bit literal ‘k’ is loaded
into W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write to W
Example:MOVLW 0x5A
After Instruction
W = 0x5A
MOVWF Move W to f
Syntax: [ label ] MOVWF f [,a]
Operands: 0 f 255
a [0,1]
Operation: (W) f
St at us Af fe cte d: None
Encoding: 0110 111a ffff ffff
Description: Move data from W to register ‘f’.
Location ‘f’ can be anywher e in the
256-byte bank. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding th e BSR value. If ‘a’ = 1, th en
the b ank wi ll be selec ted as per th e
BSR value (defaul t).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example:MOVWF REG
Before Instruc tio n
W = 0x4F
REG = 0xFF
After Instruction
W = 0x4F
REG = 0x4F
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MULLW Multiply Literal with W
Syntax: [ label ] MULLW k
Operands: 0 k 255
Operati on: (W) x k PRODH:PRODL
Status Affected: None
Encoding: 0000 1101 kkkk kkkk
Description: An unsigned multiplication is
carried out be tween the conte nts
of W and the 8-bit literal ‘k’. The
16-bit result is placed in the
PRODH:PRODL register pair.
PRODH contains the high byte.
W is unchanged.
None of t he Status flags are
affected.
Note that neither Overflow nor
Carry is possible in this opera-
tion. A Zero resu lt is possi ble but
not detected.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write
registers
PRODH:
PRODL
Example:MULLW 0xC4
Before Instruction
W=0xE2
PRODH = ?
PRODL = ?
After Instruction
W=0xE2
PRODH = 0xAD
PRODL = 0x08
MULWF Mult iply W with f
Syntax: [ label ] MULWF f [,a]
Operands: 0 f 255
a [0,1]
Operation: (W) x (f) PRODH:PRODL
St at us Af fe cte d: None
Encoding: 0000 001a ffff ffff
Description: An unsigned multiplication is
carried o ut betw een the content s
of W and the reg ister file location
‘f’. The 16-bit result is stored in
the P RODH :PROD L regi ster
pair . PRODH contains the high
byte.
Both W and ‘f’ are unchanged.
None of the Status flags are
affected.
Note that neither Overflow nor
Carry is possible in this opera-
tion. A Zero result is possible,
but not detected. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If
‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
registers
PRODH:
PRODL
Example:MULWF REG
Before Instruc tio n
W=0xC4
REG = 0xB5
PRODH = ?
PRODL = ?
After Instruction
W=0xC4
REG = 0xB5
PRODH = 0x8A
PRODL = 0x94
© 2006 Microchip Technology Inc. DS39605D-page 219
PIC18F1220/1320
NEGF Negate f
Syntax: [ label ] NEGF f [,a]
Operands: 0 f 255
a [0,1]
Operation: (f) + 1 f
Status Affected: N, OV, C, DC, Z
Encoding: 0110 110a ffff ffff
Description: Location ‘f’ is negated using two’s
compl ement. The re sult is pla ced in
the dat a mem ory loca tio n ‘f’. If ‘a ’ is
0’, the Access Bank will be
selec ted, over riding the BSR value .
If ‘a’ = 1, then the bank will be
selected as per the BSR value.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example:NEGF REG, 1
Before Instruction
REG = 0011 1010 [0x3A]
After Instruction
REG = 1100 0110 [0xC6]
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
St at us Af fe cte d: None
Encoding: 0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
Description: No operation.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
Example:
None.
PIC18F1220/1320
DS39605D-page 220 © 2006 Microchip Technology Inc.
POP Pop Top of Return Stack
Syntax: [ label ] POP
Operands: None
Operation: (TOS) bit bucket
Status Affected: None
Encoding: 0000 0000 0000 0110
Description: The TOS value is pulled off the
return stack and is discarded. The
TOS value then becomes the
previous value th at was pushed
onto the return stack.
This instruction is provided to
enable the user to properly manage
the return stack to incorporate a
software stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation Pop TOS
value No
operation
Example:POP
GOTO NEW
Before Instruction
TOS = 0x0031A2
Stack (1 level down) = 0x014332
After Instruction
TOS = 0x014332
PC = NEW
PUSH Push Top of Return Stack
Syntax: [ label ] PUSH
Operands: None
Operati on: (PC + 2) TOS
St at us Af fe cte d: None
Encoding: 0000 0000 0000 0101
Description: The PC + 2 is pushed onto the top
of the return stack. The previous
TOS value is pushed down on the
stack.
This instruction allows implement-
ing a software stack by modifying
TOS and then pushing it onto the
return stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Push
PC + 2 onto
return stack
No
operation No
operation
Example:PUSH
Before Instruc tio n
TOS = 0x00345A
PC = 0x000124
After Instruction
PC = 0x000126
TOS = 0x000126
Stack (1 level down) = 0x00345A
© 2006 Microchip Technology Inc. DS39605D-page 221
PIC18F1220/1320
RCALL Relative Call
Syntax: [ label ] RCALL n
Operands: -1024 n 1023
Operation: (PC) + 2 TOS,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 1nnn nnnn nnnn
Description: Subroutine call with a jump up to 1K
from the current location. First,
return address (PC + 2) is pushed
onto the stack. Then, add the 2’s
compl ement number ‘2n’ to the PC.
Since t he PC will hav e incremented
to fetch the next instruction, the new
address will be PC + 2 + 2n. This
instruction is a two-cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Push PC to
stack
Process
Data Write to PC
No
operation No
operation No
operation No
operation
Example:HERE RCALL Jump
Before Instruction
PC = Address (HERE)
After Instruction
PC = Address (Jump)
TOS = Address (HERE + 2)
RESET Reset
Syntax: [ label ] RESET
Operands: None
Operation: Reset all registers and flags that
are affect ed by a MCLR Reset.
St at us Af fe cte d: All
Encoding: 0000 0000 1111 1111
Description: This instruction provides a way to
execute a MCLR Reset in software.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Start
Reset No
operation No
operation
Example:RESET
After Instruction
Registers = Reset Value
Flags* = Reset Value
PIC18F1220/1320
DS39605D-page 222 © 2006 Microchip Technology Inc.
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE [s]
Operands: s [0,1]
Operation: (TOS) PC,
1 GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) W,
(STATUSS) Status,
(BSRS) BSR,
PCLATU, PCLATH are unchanged.
Status Affected: GIE/GIEH, PEIE/GIEL.
Encoding: 0000 0000 0001 000s
Description: Return from interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers, WS,
STATUSS and BSRS, are loaded
into their corresponding registers,
W, Status and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation Pop PC
from stack
Set GIEH or
GIEL
No
operation No
operation No
operation No
operation
Example:RETFIE 1
After Interrupt
PC = TOS
W=WS
BSR = BSRS
Status = STATUSS
GIE/ GIEH, PEIE/GIEL = 1
RETLW Return Literal to W
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k W,
(TOS) PC,
PCLATU, PCLATH are unchanged
St at us Af fe cte d: None
Encoding: 0000 1100 kkkk kkkk
Descr ipti on : W is loaded w ith the e igh t-bi t lit eral
‘k’. The program counter is loaded
from the top of t he st ack (the retu rn
address) . The high address latch
(PCLATH) remains unchanged.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Pop PC
from stack,
Write to W
No
operation No
operation No
operation No
operation
Example:
CALL TABLE ; W contains table
; offset value
; W now has
; table value
:
TABLE
ADDWF PCL ; W = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:
RETLW kn ; End of table
Before Instruc tio n
W = 0x07
After Instruction
W = value of kn
© 2006 Microchip Technology Inc. DS39605D-page 223
PIC18F1220/1320
RETURN Return from Subroutine
Syntax: [ label ] RETURN [s]
Operands: s [0,1]
Operation: (TOS) PC,
if s = 1
(WS) W,
(STATUSS) Status,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding: 0000 0000 0001 001s
Description: Return from subroutine. The stack
is popped and the top of the stack
is loaded into the program counter.
If ‘s ’= 1, the content s of th e shadow
registers, WS, STATUSS and
BSRS, are loaded into their corre-
sponding registers, W, Status and
BSR. If ‘s’ = 0, no update of these
registers occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation Process
Data Pop PC
from stack
No
operation No
operation No
operation No
operation
Example:RETURN
After Interrupt
PC = TOS
RLCF Rotate Left f through Carry
Syntax: [ label ] RLCF f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n + 1>,
(f<7>) C,
(C) dest<0>
St at us Af fe cte d: C, N, Z
Encoding: 0011 01da ffff ffff
Description: The contents of register ‘f are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the resu lt
is place d in W . If ‘d’ is ‘1’, the result
is stored back in register ‘f
(default). If ‘a’ is 0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:RLCF REG, W
Before Instruc tio n
REG = 1110 0110
C=0
After Instruction
REG = 1110 0110
W=1100 1100
C=1
Cregister f
PIC18F1220/1320
DS39605D-page 224 © 2006 Microchip Technology Inc.
RLNCF Rotate Left f (no carry)
Syntax: [ label ] RLNCF f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n + 1>,
(f<7>) dest<0>
Status Affected: N, Z
Encoding: 0100 01da ffff ffff
Description: The contents of register ‘f’ are
rotate d one bit to th e left. If ‘d’ is ‘0’,
the resul t is plac ed in W. If ‘d ’ is ‘1’,
the result is stored back in register
‘f’ (default). If ‘a’ is 0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is1’, then the
bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:RLNCF REG
Before Instruction
REG = 1010 1011
After Instruction
REG = 0101 0111
register f
RRCF Rot ate Right f through Carry
Syntax: [ label ] RRCF f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n – 1>,
(f<0>) C,
(C) dest<7>
Status Affecte d: C, N, Z
Encoding: 0011 00da ffff ffff
Description: The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘0’, the result
is plac ed in W. If ‘d ’ is ‘1’, th e result
is pl aced back in register ‘f
(default). If ‘a’ is0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (defaul t).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:RRCF REG, W
Before Instruc tio n
REG = 1110 0110
C=0
After Instruction
REG = 1110 0110
W=0111 0011
C=0
Cregister f
© 2006 Microchip Technology Inc. DS39605D-page 225
PIC18F1220/1320
RRNCF Rotate Right f (no carry)
Syntax: [ label ] RRNCF f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n – 1>,
(f<0>) dest<7>
Status Affected: N, Z
Encoding: 0100 00da ffff ffff
Desc ript ion : The content s of regi ste r ‘f’ are
rotated one bit to the right. If ‘d’ is
0’, the res ult is pl aced in W. If ‘d ’ is
1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is
1’, then the bank will be selected
as per the BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example 1:RRNCF REG, 1, 0
Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2:RRNCF REG, W
Before Instruction
W=?
REG = 1101 0111
After Instruction
W=1110 1011
REG = 1101 0111
register f
SETF Set f
Syntax: [ label ] SETF f [,a]
Operands: 0 f 255
a [0,1]
Operation: FFh f
St at us Af fe cte d: None
Encoding: 0110 100a ffff ffff
Description: The contents of the specified
register are set to FFh. If ‘a’ is0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is
1’, then the bank will be selected
as pe r the BSR valu e (defaul t).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example:SETF REG
Before Instruc tio n
REG = 0x5A
After Instruction
REG = 0xFF
PIC18F1220/1320
DS39605D-page 226 © 2006 Microchip Technology Inc.
SLEEP Enter Sleep mode
Syntax: [ label ] SLEEP
Operands: None
Operation: 00h WDT,
0 WDT postscaler,
1 TO,
0 PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0011
Description: The Power-down status bit (PD) is
cleared. The Time-out status bit
(TO) is set. The Watchdog Timer
and its postscaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation Process
Data Go to
Sleep
Example:SLEEP
Before Instruction
TO =?
PD =?
After Instruction
TO =1
PD =0
† If WDT causes wake-up, this bit is cleared.
SUBFWB Subtract f from W with borrow
Syntax: [ label ] SUBFWB f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) – (f) – (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 01da ffff ffff
Description: Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored in register ‘f’ (default). If ‘a’ is
0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example 1:SUBFWB REG
Before Instruc tio n
REG = 0x03
W = 0x02
C = 0x01
After Instruction
REG = 0xFF
W = 0x02
C = 0x00
Z = 0x00
N = 0x01 ; res ult is negative
Example 2:SUBFWB REG, 0, 0
Before Instruc tio n
REG = 2
W=5
C=1
After Instruction
REG = 2
W=3
C=1
Z=0
N = 0 ; result is positive
Example 3:SUBFWB REG, 1, 0
Before Instruc tio n
REG = 1
W=2
C=0
After Instruction
REG = 0
W=2
C=1
Z=1; result is zero
N=0
© 2006 Microchip Technology Inc. DS39605D-page 227
PIC18F1220/1320
SUBLW Subtract W from literal
Syntax: [ label ]SUBLW k
Operands: 0 k 255
Operation: k – (W) W
Status Affected: N, OV, C, DC, Z
Encoding: 0000 1000 kkkk kkkk
Descriptio n: W is subtracted from the ei ght-bit
literal ‘k’. The result is placed
in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write to W
Example 1: SUBLW 0x02
Before Instruction
W=1
C=?
After Instruction
W=1
C = 1 ; result is positive
Z=0
N=0
Example 2:SUBLW 0x02
Before Instruction
W=2
C=?
After Instruction
W=0
C = 1 ; result is zero
Z=1
N=0
Example 3:SUBLW 0x02
Before Instruction
W=3
C=?
After Instruction
W = F F ; (2’s complement)
C = 0 ; result is negative
Z=0
N=1
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operati on: (f) – (W) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 11da ffff ffff
Description: Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is0’,
the result is stored in W. If ‘d’ is
1’, the result is stored back in
register ‘f’ (default ). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is
1’, then the bank will be selected
as per the BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example 1:SUBWF REG
Before Instruc tio n
REG = 3
W=2
C=?
After Instruction
REG = 1
W=2
C = 1 ; result is positive
Z=0
N=0
Example 2:SUBWF REG, W
Before Instruc tio n
REG = 2
W=2
C=?
After Instruction
REG = 2
W=0
C=1; result is zero
Z=1
N=0
Example 3:SUBWF REG
Before Instruc tio n
REG = 0x01
W = 0x02
C=?
After Instruction
REG = 0xFFh ;(2’s complement)
W = 0x02
C = 0x00 ;result is negative
Z = 0x00
N = 0x01
PIC18F1220/1320
DS39605D-page 228 © 2006 Microchip Technology Inc.
SUBWFB Subtract W from f with Borrow
Syntax: [ label ] SUBWFB f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – (W) – (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 10da ffff ffff
Description: Subtract W and the Carry flag
(borrow) from register ‘f’ (2’s comple-
ment method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default). If
‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example 1:SUBWFB REG, 1, 0
Before Instruction
REG = 0x19 (0001 1001)
W= 0x0D (0000 1101)
C = 0x01
After Instruction
REG = 0x0C (0000 1011)
W= 0x0D (0000 1101)
C = 0x01
Z = 0x00
N = 0x00 ; result is positive
Example 2: SUBWFB REG, 0, 0
Before Instruction
REG = 0x1B (0001 1011)
W= 0x1A (0001 1010)
C = 0x00
After Instruction
REG = 0x1B (0001 1011)
W = 0x00
C = 0x01
Z = 0x01 ; result is zero
N = 0x00
Example 3: SUBWFB REG, 1, 0
Before Instruction
REG = 0x03 (0000 0011)
W= 0x0E (0000 1101)
C = 0x01
After Instruction
REG = 0xF5 (1111 0100)
; [2’s co mp]
W= 0x0E (0000 1101)
C = 0x00
Z = 0x00
N = 0x01 ; result is negative
SWAPF Swap f
Syntax: [ label ] SWAPF f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<3:0>) dest<7:4>,
(f<7:4>) dest<3:0>
St at us Af fe cte d: None
Encoding: 0011 10da ffff ffff
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
0’, the res ult is pl aced in W. If ‘d’ is
1’, the resul t is p laced in reg ister ‘f’
(default). If ‘a’ is0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (defaul t).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:SWAPF REG
Before Instruc tio n
REG = 0x53
After Instruction
REG = 0x35
© 2006 Microchip Technology Inc. DS39605D-page 229
PIC18F1220/1320
TBLRD Table Read
Syntax: [ label ] TBLRD ( *; *+; *-; +*)
Operands: None
Operation: if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) + 1 TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) – 1 TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 TBLPTR;
(Prog Mem (TBLPTR)) TABLAT;
Status Affected: None
Encoding: 0000 0000 0000 10nn
nn = 0*
= 1*+
= 2*-
= 3+*
Description: This instruction is us ed to read the
contents of Program Memory (P.M.). To
address the program memory , a pointer
called Table Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2-Mbyte address
range.
TBLPTR [0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR [0] = 1: Most Significant
Byte of Program
Memory Word
The TBLRD instruction can modify the
value of TBLPTR as follows:
no change
post-increment
post-decrement
pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
No
operation No operation
(Read Program
Memory)
No
operation No operati on
(Writ e
TABLAT)
TBLRD Table Rea d (Continued)
Example 1:TBLRD *+ ;
Before Instruc tio n
TABLAT = 0x55
TBLPTR = 0x00A356
MEMORY(0x00A356) = 0x34
After Instruction
TABLAT = 0x34
TBLPTR = 0x00A357
Example 2:TBLRD +* ;
Before Instruc tio n
TABLAT = 0xAA
TBLPTR = 0x01A357
MEMORY(0x01A357) = 0x12
MEMORY(0x01A358) = 0x34
After Instruction
TABLAT = 0x34
TBLPTR = 0x01A358
PIC18F1220/1320
DS39605D-page 230 © 2006 Microchip Technology Inc.
TBLWT Table Write
Syntax: [ label ] TBLWT ( *; *+; *-; +*)
Operands: None
Operation: if TBLWT*,
(TABLAT) Holding Register;
TBLPTR – No Change;
if TBLWT*+,
(TABLAT) Holding Register;
(TBLPTR) + 1 TBLPTR ;
if TBLWT*-,
(TABLAT) Holding Register;
(TBLPTR) – 1 TBLP TR;
if TBLWT+*,
(TBLPTR) + 1 TBLPTR ;
(TABLAT) Holding Register;
Status Affected: None
Encoding: 0000 0000 0000 11nn
nn = 0*
= 1*+
= 2*-
= 3+*
Description: This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABL AT is
written to. The holding registers are
used to program the co nten ts of
Program Memory (P.M.). (Refer
to Section 6.0 “Flash Program
Memory” for additional details on
programming Flash memory.)
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2-Mbyte address
range. The LSb of the TBLPTR
selects which byte of the program
memory location to access.
TBLPTR[0] = 0:Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1:Most Significant
Byte of Program
Memory Word
The TBLWT instruction ca n modify the
value of TBLPTR as follows:
no chang e
post-increment
post-decrement
pre-increment
TBLWT Table Write (Continued)
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
No
operation No
operation
(Read
TABLAT)
No
operation No
operation
(Write to
Holding
Register)
Example 1:TBLWT *+;
Before Instruc tio n
TABLAT = 0x55
TBLPTR = 0x00A356
HOLD ING REGIST ER
(0x00A356) = 0xFF
After Instructions (table write completion)
TABLAT = 0x55
TBLPTR = 0x00A357
HOLD ING REGIST ER
(0x00A356) = 0x55
Example 2:TBLWT +*;
Before Instruc tio n
TABLAT = 0x34
TBLPTR = 0x01389A
HOLD ING REGIST ER
(0x01389A) = 0xFF
HOLD ING REGIST ER
(0x01389B) = 0xFF
After Instruction (table write completion)
TABLAT = 0x34
TBLPTR = 0x01389B
HOLD ING REGIST ER
(0x01389A) = 0xFF
HOLD ING REGIST ER
(0x01389B) = 0x34
© 2006 Microchip Technology Inc. DS39605D-page 231
PIC18F1220/1320
TSTFSZ Test f, skip if 0
Syntax: [ label ] TSTFSZ f [,a]
Operands: 0 f 255
a [0,1]
Operation: skip if f = 0
Status Affected: None
Encoding: 0110 011a ffff ffff
Description: If ‘f’ = 0, the nex t inst ruct io n,
fetched during the current
instruction execution is discarded
and a NOP is exec uted, m aking this
a two-cycle instruction. If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is
1’, then the bank will be selected
as per the BSR value (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE TSTFSZ CNT
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
If CNT = 0x00,
PC = Address (ZERO)
If CNT 0x00,
PC = Address (NZERO)
XORLW Exclusive OR literal with W
Syntax: [ label ] XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W
St at us Af fe cte d: N, Z
Encoding: 0000 1010 kkkk kkkk
Description: The contents of W are XOR’ed
with the 8-bit literal ‘k’. The result
is placed in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write to W
Example:XORLW 0xAF
Before Instruc tio n
W=0xB5
After Instruction
W = 0x1A
PIC18F1220/1320
DS39605D-page 232 © 2006 Microchip Technology Inc.
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .XOR. (f) dest
Status Affected: N, Z
Encoding: 0001 10da ffff ffff
Description: Exclusive OR the contents of W
with register ‘f. If ‘d’ is ‘0’, the result
is stored in W. If ‘d’ is ‘1’, the result
is stored bac k in t he regi ste r ‘f’
(default). If ‘a’ is0’, the Access
Bank w ill be selected, overriding
the BSR value. If ‘a’ is ‘1, then the
bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example:XORWF REG
Before Instruction
REG = 0xAF
W=0xB5
After Instruction
REG = 0x1A
W=0xB5
© 2006 Microchip Technology Inc. DS39605D-page 233
PIC18F1220/1320
21.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full ran ge of hardware a nd softwa re develo pment to ols:
Integrated Development Environment
- MPLAB® IDE Software
Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
Simulators
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
•Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
In-Circuit Debugger
- MPLAB ICD 2
Device Progra mmers
-PRO MATE
® II Universa l D evi ce P rogramm er
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
Low-Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM De monstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
Evaluation Kits
-K
EELOQ® Evaluation and Programming Tools
- P ICDEM MSC
-microID
® Developer Kits
-CAN
- PowerSmart® Developer Kits
-Analog
21.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
based application that contains:
An interface to debugging t ools
- simulator
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
A full-featured editor with color coded context
A multiple project manager
Customizable data windows with direct edit of
contents
High-level source code debugging
Mouse over variable inspection
Exten si ve on-l in e help
The MPLAB IDE allows you to:
Edit your source files (eithe r asse mbly or C)
One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
Debug us ing :
- source files (as sembl y or C)
- mixed assembly and C
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve whe n upgrading to tools with increasin g flexibi lity
and power.
21.2 MPASM Assembler
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard HEX
files, M AP files to detail memory u sage and symbol re f-
erence, a bsolute LST files that cont ain source lines and
generated machine code and COFF files for
debugging.
The MPASM assembler features include:
Integration into MPLAB IDE projects
User de fined m acros to strea mline assemb ly cod e
Condit ion al as sem bl y for multi-purpose sourc e
files
Directives that allow complete control over the
assembly process
PIC18F1220/1320
DS39605D-page 234 © 2006 Microchip Technology Inc.
21.3 MPLAB C17 and MPLAB C18
C Compilers
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
21.4 MPLINK Object Linker/
MPLIB Object Librari an
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB object librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file , only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
Efficient linking of single libraries instead of many
smaller files
Enhanced code maintainability by grouping
related modules together
Flexible creation of libraries with easy module
listing, replacement, de letion and extraction
21.5 MPLAB C30 C Compiler
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command
line options and language extensions to take full
adv antage of the dsPIC 30F dev ice ha rdwar e capab ili-
ties and afford fine control of the compiler code
generator.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been vali-
dated an d c on form to the ANSI C li brary standard. Th e
library includes functions for string manipulation,
dynamic memory allocation, data conversion, time-
keepin g and math func tions (trigonome tric, expone ntial
and hyperbolic). The compiler provides symbolic
information for high-level source debugging with the
MPLAB IDE.
21.6 MPLAB ASM30 Assembler, Linker
and Librarian
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or linke d with other relocatable ob ject files and
arch ives to c rea te an e xecu tabl e fil e. N otabl e fe atu res
of the assembler include:
Support for the entire dsPIC30F instruction set
Support for fixed-point and floating-point data
Command line interface
Rich dire cti ve set
Flexible macro language
MPLAB IDE compatibility
21.7 MPLAB SIM Software Simulator
The MPLAB SIM sof tware simulat or allows code deve l-
opment in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or use r de fined key p ress, to any pin. The exec u-
tion can be performed in Single-Step, Execute Until
Break or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
21.8 MPLAB SIM30 Software Simulator
The MPLAB SIM30 software simulator allows code
develop ment in a PC hosted en vironment by simulating
the dsPIC30F series microcontrollers on an instruct ion
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler . The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high-speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
© 2006 Microchip Technology Inc. DS39605D-page 235
PIC18F1220/1320
21.9 MPLAB ICE 2000
High-Performance Universal
In-Circui t Emu lator
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which all ows ed iting, b uildin g, do wnlo ading and sourc e
debuggi ng from a singl e envi ronm en t.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
featur es. Interchangea ble processo r modules al low the
system to be easi ly reconfi gured for emula tion of d iffer-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
21.10 MPLAB ICE 4000
High-Performance Universal
In-Circui t Emu lator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a co mplete micro controller de sign tool se t for high-
end PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debuggi ng from a singl e envi ronm en t.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanc ed emulator fe atures inc lude complex t riggering
and timing, up to 2 Mb of emulation memory and the
ability to view variables in real-time.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
21.11 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the Flash devices. This feature, along with
Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM)
protocol , offe rs cost ef fective i n-circuit Flash debug ging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-tim e. MPLAB ICD 2 also serves as a de velop ment
programmer for selected PICmicro devices.
21.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maxi mum reli abili ty. It feature s
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
21.13 MPLAB PM3 Device Programmer
The MPLAB PM3 is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maxi mum reli abili ty. It feature s
a large LCD display (128 x 64) for menus and error
messages and a modular detachable socket assembly
to support various package types. The ICSP™ cable
assembly is included as a standard item. In Stand-
Alone mode , the M PLAB PM3 devi ce pr ogra mmer ca n
read, verify and program PICmicro devices without a
PC connection. It can also set code protection in this
mode. M PLAB PM3 con nects t o the host PC via an RS-
232 or USB cable. MPLAB PM3 has high-speed com-
munications and optimized algorithms for quick pro-
gramming of large memory devices and incorporates
an SD/ MMC card fo r file s torage an d secure d ata a ppli-
cations.
PIC18F1220/1320
DS39605D-page 236 © 2006 Microchip Technology Inc.
21.14 PICSTART Plus Development
Programmer
The PICSTART Plus development programmer is an
easy-to-use, low-cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Inte grated Dev elopmen t En vironme nt so ftware makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
21.15 PICDEM 1 PICmicro
Demonstration Board
The PICDEM 1 demo nstrat ion boa rd demo nstrate s the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provi d ed wi t h the P IC DE M 1 de mo ns t rat i on b oar d c an
be pro gramme d with a PRO MATE II de vice pr ogram-
mer or a PICSTART Plus development programmer.
The PICDE M 1 demonstrati on board can be conne cted
to the MPLAB ICE in-circuit emulator for testing. A
proto type area extends the ci rcuitry for a dditio nal appli-
cation components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
21.16 PICDEM.net Internet/E thernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface con-
nector, an Ethernet interface, RS-232 interface and a
16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by Jeremy Bentham
21.17 PICDEM 2 Plus
Demonstration Board
The PICDEM 2 Plus demonstration board supports
many 18, 28 and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the neces-
sary ha rdware and s oftware is included to run the dem-
onstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device program-
mer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB I CD 2 and MPLAB ICE in-circuit emul ators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display , a piezo speaker , an on-board temperature
sensor, four LEDs and sample PIC18F452 and
PIC16F877 Flash microcontrollers.
21.18 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
21.19 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capa-
bilities of the 8, 14 and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320
family of microcontrollers. PICDEM 4 is intended to
showcase the many features of these low pin count
parts, including LIN and Motor Control using ECCP.
Special provisions are made for low-power operation
with the supercapacitor circuit and jumpers allow on-
board hardware to be disabled to eliminate current
draw in this mode. Included on the demo bo ard are pro-
visions for Crystal, RC or Canned Oscillator modes, a
five volt regulator for use with a nine volt wall adapter
or battery, DB-9 RS-232 interface, ICD connector for
programming via ICSP and development with MPLAB
ICD 2, 2 x 16 liqui d crystal dis play, PCB footpri nts for
H-Bridge motor driver, LIN transceiver and EEPROM.
Also in clude d are: head er for expansi on, eig ht L EDs,
four potentiometers, three push buttons and a proto-
typi ng are a. Incl uded wit h the ki t is a P IC16F62 7A and
a PIC18F1320. Tutorial firmware is included along
with th e User’s Guide.
© 2006 Microchip Technology Inc. DS39605D-page 237
PIC18F1220/1320
21.20 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A pro-
gramme d sample i s included. The PR O MA TE I I device
programmer, or the PICSTART Plus development pro-
gramme r , can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board Flash memory. A
generous proto typ e area is av ailab le for user hardw are
expansion.
21.21 PICDEM 18R PIC18C601/801
Demonstration Board
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/Demultiplexed and 16-bit
Memory modes. The board includes 2 Mb external
Flash memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
21.22 PICDEM LIN PIC16C43X
Demonstration Board
The pow erfu l LI N hard w are a nd s of tw are kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
on-board LIN transceivers. A PIC16F874 Flash
microcontroller serves as the master. All three micro-
controllers are programmed with firmware to provide
LIN b us communication.
21.23 PICkitTM 1 Flash Starter Kit
A complete “developmen t system in a box”, the PICkit™
Flash Starter Kit includes a convenient multi-section
board for programming, evaluation and development of
8/14-pin Flash PIC® microc ontrollers. Powered via USB,
the board operates under a simple Windows GUI. The
PICkit 1 Starter Kit includes the User’s Guide (on CD
ROM), PICkit 1 tutorial software and code for various
applications. Also included are MPLAB® IDE (Integrated
Development Environment) software, software and
hardware “Tips 'n Tricks for 8-pin Flash PIC®
Microcontrollers” Handbook and a USB interface cable.
Supports all current 8/14-pin Flash PIC microc ontrollers,
as well as many future planned dev ices .
21.24 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM U SB Demo ns trati on Board sho w s o f f th e
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
21.25 Evaluation and
Programming Tools
In additio n to the PICDEM seri es of circuits, Microchip
has a line of evaluation kits and demonstration software
for the se products.
•K
EELOQ evaluation and prog ram mi ng too ls for
Microchip’s HCS Secure Data Products
CAN developers kit for automotive network
applications
Analog design boards and filter design software
PowerSmart battery charging evaluation/
calibration kits
•IrDA
® development kit
microID development and rfLabTM development
software
SEEVAL® designer k it f or m em ory ev al uation and
endurance calculations
PICDEM MSC demo boards for Switching mode
power supply, high-power IR driver, delta sigma
ADC and flow rate sensor
Check the Microchip web page and the latest Product
Selector Guide for the complete list of demonstration
and evaluation kits.
PIC18F1220/1320
DS39605D-page 238 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS39605D-page 239
PIC18F1220/1320
22.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4)..........................................-0.3V to (VDD + 0.3V)
Vo lt a ge on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V
Vo lt a ge on MCLR with respect to VSS (Note 2)......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V
Total power diss ipation (Note 1) ...............................................................................................................................1.0W
Maximum curr ent o ut of VSS pin ...........................................................................................................................300 mA
Maximum curr ent i nto VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin....................................................................................................25 mA
Maximum curr ent su nk by all ports .......................................................................................................................200mA
Maximum current sourced by all ports..................................................................................................................200 mA
Note 1: Power dissipation is calcu lated as follows:
Pdis = VDD x {IDD IOH} + {(VDDVOH) x IOH} + (VOL x IOL)
2: V o ltage sp ikes below VSS at the MCLR/VPP pin, induc ing c urrent s g reater than 8 0 mA , ma y ca use l atch-u p.
Thus, a se ries resisto r of 50-100Ω should be u sed w he n a ppl yi ng a “low” level to the MC L R/VPP pin, rath er
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC18F1220/1320
DS39605D-page 240 © 2006 Microchip Technology Inc.
FIGURE 22-1: PIC18F1220/1320 VOLTAGE-FREQUE NCY GRAPH (INDUSTRIAL)
FIGURE 22-2: PIC18LF1220/1320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
40 MHz
5.0V
3.5V
3.0V
2.5V
PIC18F1X20
4.2V
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
40 MHz
5.0V
3.5V
3.0V
2.5V
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V ) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PICmicro® de vi ce in the app lic ation.
4 MHz
4.2V
PIC18LF1X20
© 2006 Microchip Technology Inc. DS39605D-page 241
PIC18F1220/1320
FIGURE 22-3: PIC18F1220/1320 VOLTAGE-FREQUENCY GRAPH (EXTENDED)
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
25 MHz
5.0V
3.5V
3.0V
2.5V
PIC18F1X20-E
4.2V
PIC18F1220/1320
DS39605D-page 242 © 2006 Microchip Technology Inc.
22.1 DC Characteristics: Supply Voltage
PIC18F1220/1320 (I ndustrial)
PIC18LF1220/1320 (I ndustrial)
PIC18LF1220/1320
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC18F1220/1320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Typ Max Units Conditions
VDD Supply Vol tage
D001 PIC18LF1220/1320 2.0 5.5 V HS, XT, RC and LP Oscillator mode
PIC18F1220/1320 4.2 5.5 V
D002 VDR RAM Dat a Retention
Voltage(1) 1.5 V
D003 VPOR VDD Start Voltage to ensure
internal Power-on Reset signal 0.7 V See Section 4.1 “Power-on Reset (POR)”
for details.
D004 SVDD VDD Rise Rate to ensure
internal Power-on Reset signal 0.05 V /m s See Section 4.1 “Power-on Reset (POR)”
for details.
VBOR Brown-out Reset Vol tage
D005D PIC18LF1220/1320 Industrial Low Voltage (-10°C to +85°C)
BORV1:BORV0 = 11 N/A N/A N/A V Reserved
BORV1:BORV0 = 10 2.50 2.72 2.94 V
BORV1:BORV0 = 01 3.88 4.22 4.56 V (Note 2)
BORV1:BORV0 = 00 4.18 4.54 4.90 V (Note 2)
D005F PIC18LF1220/1320 Industrial Low Voltage (-40°C to -10°C)
BORV1:BORV0 = 11 N/A N/A N/A V Reserved
BORV1:BORV0 = 10 2.34 2.72 3.10 V
BORV1:BORV0 = 01 3.63 4.22 4.81 V (Note 2)
BORV1:BORV0 = 00 3.90 4.54 5.18 V (Note 2)
D005G PIC18F1220/1320 Industrial (-10°C to +85°C)
BORV1:BORV0 = 1x N/A N/A N/A VReserved
BORV1:BORV0 = 01 3.88 4.22 4.56 V(Note 2)
BORV1:BORV0 = 00 4.18 4.54 4.90 V(Note 2)
D005H PIC18F1220/1320 Industrial (-40°C to -10°C)
BORV1:BORV0 = 1x N/A N/A N/A VReserved
BORV1:BORV0 = 01 N/A N/A N/A VReserved
BORV1:BORV0 = 00 3.90 4.54 5.18 V(Note 2)
D005J PIC18F1220/1320 Extended (-10°C to +85°C)
BORV1:BORV0 = 1x N/A N/A N/A VReserved
BORV1:BORV0 = 01 3.88 4.22 4.56 V(Note 3)
BORV1:BORV0 = 00 4.18 4.54 4.90 V(Note 3)
D005K PIC18F1220/1320 Extended (-40°C to -10°C, +85°C to +125°C)
BORV1:BORV0 = 1x N/A N/A N/A VReserved
BORV1:BORV0 = 01 N/A N/A N/A VReserved
BORV1:BORV0 = 00 3.90 4.54 5.18 V(Note 3)
Legend: Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
2: When BOR is on and BORV<1:0> = 0x, the device will operate correctly at 40 MHz for any VDD at which the BOR allows
execution (low-voltage and industrial devices only).
3: When BOR is on and BORV<1:0> = 0x, the device will operate correctly at 25 MHz for any VDD at which the BOR allows
execution (extended devices only).
© 2006 Microchip Technology Inc. DS39605D-page 243
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (I ndustrial)
PIC18LF1220/1320 (I ndustrial)
PIC18LF1220/1320
(Industrial) Standard Operating Condit ions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC18F1220/1320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Power-Down Current (IPD)(1)
PIC18LF1220/1320 0.1 0.5 μA -40°C VDD = 2.0V,
(Sleep mode)
0.1 0.5 μA +25°C
0.2 1.9 μA +85°C
PIC18LF1220/1320 0.1 0.5 μA -40°C VDD = 3.0V,
(Sleep mode)
0.1 0.5 μA + 25°C
0.3 1.9 μA +85°C
All devices 0.1 2.0 μA -40°C
VDD = 5.0V,
(Sleep mode)
0.1 2.0 μA +25°C
0.4 6.5 μA +85°C
Extended devices 11.2 50 μA +125°C
Supply Current (IDD)(2,3)
PIC18LF1220/1320 8 40 μA -40°C
FOSC = 31 kHz
(RC_RUN mode,
Internal oscillator source)
940μA+25°C V
DD = 2.0V
11 40 μA+85°C
PIC18LF1220/1320 25 68 μA -40°C
25 68 μA+25°C V
DD = 3.0V
20 68 μA+85°C
All devices 55 80 μA -40°C
VDD = 5.0V
55 80 μA+25°C
50 80 μA+85°C
Extended devices 50 80 μA +125°C
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedanc e state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
PIC18F1220/1320
DS39605D-page 244 © 2006 Microchip Technology Inc.
Supply Current (IDD)(2,3)
PIC18LF1220/1320 140 220 μA -40°C
FOSC = 1 MHz
(RC_RUN mode,
Internal oscillator source)
145 220 μA+25°C V
DD = 2.0V
155 220 μA+85°C
PIC18LF1220/1320 215 330 μA -40°C
225 330 μA+25°C V
DD = 3.0V
235 330 μA+85°C
All devices 385 550 μA -40°C
VDD = 5.0V
390 550 μA+25°C
405 550 μA+85°C
Extended devices 410 6 50 μA +125°C
PIC18LF1220/1320 410 600 μA -40°C
FOSC = 4 MHz
(RC_RUN mode,
Internal oscillator source)
425 600 μA+25°C V
DD = 2.0V
435 600 μA+85°C
PIC18LF1220/1320 650 900 μA -40°C
670 900 μA+25°C V
DD = 3.0V
680 900 μA+85°C
All devices 1.2 1.8 mA -40°C
VDD = 5.0V
1.2 1.8 mA +25°C
1.2 1.8 mA +85°C
Extended devices 1.2 1.8 mA +125°C
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (I ndustrial)
PIC18LF1220/1320 (Industrial) (Conti nued)
PIC18LF1220/1320
(Industrial) Standard Operating Condit ions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC18F1220/1320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedanc e state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperat ure
crystals are available at a much higher cost.
© 2006 Microchip Technology Inc. DS39605D-page 245
PIC18F1220/1320
Supply Current (IDD)(2,3)
PIC18LF1220/1320 4.7 8 μA -40°C
FOSC = 31 kHz
(RC_IDLE mode,
Internal oscillator source)
5.0 8 μA+25°C V
DD = 2.0V
5.8 11 μA+85°C
PIC18LF1220/1320 7.0 11 μA -40°C
7.8 11 μA+25°C V
DD = 3.0V
8.7 15 μA+85°C
All devices 12 16 μA -40°C
VDD = 5.0V
14 16 μA+25°C
14 22 μA+85°C
Extended devices 25 75 μA +125°C
PIC18LF1220/1320 75 150 μA -40°C
FOSC = 1 MHz
(RC_IDLE mode,
Internal oscillator source)
85 150 μA+25°C V
DD = 2.0V
95 150 μA+85°C
PIC18LF1220/1320 110 180 μA -40°C
125 180 μA+25°C V
DD = 3.0V
135 180 μA+85°C
All devices 180 380 μA -40°C
VDD = 5.0V
195 380 μA+25°C
200 380 μA+85°C
Extended devices 350 4 35 μA +125°C
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (I ndustrial)
PIC18LF1220/1320 (I ndustrial) (Continued)
PIC18LF1220/1320
(Industrial) Standard Operating Condit ions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC18F1220/1320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedanc e state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
PIC18F1220/1320
DS39605D-page 246 © 2006 Microchip Technology Inc.
Supply Current (IDD)(2,3)
PIC18LF1220/1320 140 275 μA -40°C
FOSC = 4 MHz
(RC_IDLE mode,
Internal oscillator source)
140 275 μA+25°C V
DD = 2.0V
150 275 μA+85°C
PIC18LF1220/1320 220 375 μA -40°C
220 375 μA+25°C V
DD = 3.0V
220 375 μA+85°C
All devices 390 800 μA -40°C
VDD = 5.0V
400 800 μA+25°C
380 800 μA+85°C
Extended devices 410 8 00 μA +125°C
PIC18LF1220/1320 150 250 μA -40°C
FOSC = 1 M HZ
(PRI_RUN mode,
EC oscillator)
150 250 μA+25°C V
DD = 2.0V
160 250 μA+85°C
PIC18LF1220/1320 340 350 μA -40°C
300 350 μA+25°C V
DD = 3.0V
280 350 μA+85°C
All devices 0.72 1.0 mA -40°C
VDD = 5.0V
0.63 1.0 mA +25°C
0.58 1.0 mA +85°C
Extended devices 0.53 1.0 mA +125°C
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (I ndustrial)
PIC18LF1220/1320 (Industrial) (Conti nued)
PIC18LF1220/1320
(Industrial) Standard Operating Condit ions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC18F1220/1320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedanc e state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperat ure
crystals are available at a much higher cost.
© 2006 Microchip Technology Inc. DS39605D-page 247
PIC18F1220/1320
Supply Current (IDD)(2,3)
PIC18LF1220/1320 415 600 μA -40°C
FOSC = 4 MHz
(PRI_RUN mode,
EC oscillator)
425 600 μA+25°C V
DD = 2.0V
435 600 μA+85°C
PIC18LF1220/1320 0.87 1.0 mA -40°C
0.75 1.0 mA +25°C VDD = 3.0V
0.75 1.0 mA +85°C
All devices 1.6 2.0 mA -40°C
VDD = 5.0V
1.6 2.0 mA +25°C
1.5 2.0 mA +85°C
Extended devices 1.5 2.0 mA +125°C
Extended devices 6.3 9.0 mA +125°C VDD = 4.2V FOSC = 25 MHz
(PRI_RUN mode,
EC oscillator)
9.7 10.0 mA +125°C VDD = 5.0V
All devices 9.4 12 mA -40°C
FOSC = 40 MHZ
(PRI_RUN mode,
EC oscillator)
9.5 12 mA +25°C VDD = 4.2V
9.6 12 mA +85°C
All devices 11.9 15 mA -40°C VDD = 5.0V12.1 15 mA +25°C
12.2 15 mA +85°C
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (I ndustrial)
PIC18LF1220/1320 (I ndustrial) (Continued)
PIC18LF1220/1320
(Industrial) Standard Operating Condit ions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC18F1220/1320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedanc e state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
PIC18F1220/1320
DS39605D-page 248 © 2006 Microchip Technology Inc.
Supply Current (IDD)(2,3)
PIC18LF1220/1320 35 50 μA -40°C
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
35 50 μA+25°C V
DD = 2.0V
35 60 μA+85°C
PIC18LF1220/1320 55 80 μA -40°C
50 80 μA+25°C V
DD = 3.0V
60 100 μA+85°C
All devices 105 150 μA -40°C
VDD = 5.0V
110 150 μA+25°C
115 150 μA+85°C
Extended devices 125 3 00 μA +125°C
PIC18LF1220/1320 135 180 μA -40°C
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
140 180 μA+25°C V
DD = 2.0V
140 180 μA+85°C
PIC18LF1220/1320 215 280 μA -40°C
225 280 μA+25°C V
DD = 3.0V
230 280 μA+85°C
All devices 410 525 μA -40°C
VDD = 5.0V
420 525 μA+25°C
430 525 μA+85°C
Extended devices 450 8 00 μA +125°C
Extended devices 2.2 3.0 mA +125°C VDD = 4.2V FOSC = 25 MHz
(PRI_IDLE mode,
EC oscillator)
2.7 3.5 mA +125°C VDD = 5.0V
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (I ndustrial)
PIC18LF1220/1320 (Industrial) (Conti nued)
PIC18LF1220/1320
(Industrial) Standard Operating Condit ions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC18F1220/1320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedanc e state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperat ure
crystals are available at a much higher cost.
© 2006 Microchip Technology Inc. DS39605D-page 249
PIC18F1220/1320
Supply Current (IDD)(2,3)
All devices 3.2 4.1 mA -40°C
FOSC = 40 MHz
(PRI_IDLE mode,
EC oscillator)
3.2 4.1 mA +25°C VDD = 4.2 V
3.3 4.1 mA +85°C
All devices 4.0 5.1 mA -40°C VDD = 5.0V4.1 5.1 mA +25°C
4.1 5.1 mA +85°C
PIC18LF1220/1320 5.1 9 μA -10°C
FOSC = 32 kHz (4)
(SEC_RUN mode,
Timer1 as clock)
5.8 9 μA+25°C V
DD = 2.0V
7.9 11 μA+70°C
PIC18LF1220/1320 7.9 12 μA -10°C
8.9 12 μA+25°C V
DD = 3.0V
10.5 14 μA+70°C
All devices 12.5 20 μA -10°C VDD = 5.0V16.3 20 μA+25°C
18.4 25 μA+70°C
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (I ndustrial)
PIC18LF1220/1320 (I ndustrial) (Continued)
PIC18LF1220/1320
(Industrial) Standard Operating Condit ions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC18F1220/1320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedanc e state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
PIC18F1220/1320
DS39605D-page 250 © 2006 Microchip Technology Inc.
Supply Current (IDD)(2,3)
PIC18LF1220/1320 9.2 15 μA -10°C
FOSC = 32 kHz (4)
(SEC_IDLE mode,
Timer1 as clock)
9.6 15 μA+25°C V
DD = 2.0V
12.7 18 μA+70°C
PIC18LF1220/1320 22 30 μA -10°C
21 30 μA+25°C V
DD = 3.0V
20 35 μA+70°C
All devices 50 80 μA -10°C VDD = 5.0V45 80 μA+25°C
45 80 μA+70°C
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (I ndustrial)
PIC18LF1220/1320 (Industrial) (Conti nued)
PIC18LF1220/1320
(Industrial) Standard Operating Condit ions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC18F1220/1320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedanc e state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperat ure
crystals are available at a much higher cost.
© 2006 Microchip Technology Inc. DS39605D-page 251
PIC18F1220/1320
Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD)
D022
(ΔIWDT)Watchdog Timer 1.5 4.0 μA -40°C
2.2 4.0 μA+25°C V
DD = 2.0V
3.1 5.0 μA+85°C
2.5 6.0 μA -40°C
3.3 6.0 μA+25°C V
DD = 3.0V
4.7 7.0 μA+85°C
3.7 10.0 μA -40°C
4.5 10.0 μA+25°C V
DD = 5.0V
6.1 13.0 μA+85°C
D022A
(ΔIBOR)Brown-out Reset 19 35.0 μA-40°C to +85°CV
DD = 3.0V
24 45.0 μA-40°C to +85°CV
DD = 5.0V
D022B
(ΔILVD)Low-Voltage Detect 8.5 25.0 μA-40°C to +85°CV
DD = 2.0V
16 35.0 μA-40°C to +85°CV
DD = 3.0V
20 45.0 μA-40°C to +85°CV
DD = 5.0V
D025
(ΔIOSCB)Timer1 Oscillator 1.7 3.5 μA-40°C
1.8 3.5 μA+25°CV
DD = 2.0V 32 kHz on Timer1(4)
2.1 4.5 μA+85°C
2.2 4.5 μA-40°C
2.6 4.5 μA+25°CV
DD = 3.0V 32 kHz on Timer1(4)
2.8 5.5 μA+85°C
3.0 6.0 μA-40°C
3.3 6.0 μA+25°CV
DD = 5.0V 32 kHz on Timer1(4)
3.6 7.0 μA+85°C
D026
(ΔIAD)A/D Converter 1.0 3.0 μA-40°C to +85°CV
DD = 2.0V
A/D on, not converting
1.0 4.0 μA-40°C to +85°CV
DD = 3.0V
2.0 10.0 μA-40°C to +85°CV
DD = 5.0V
1.0 8.0 μA-40°C to +125°CV
DD = 5.0V
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (I ndustrial)
PIC18LF1220/1320 (I ndustrial) (Continued)
PIC18LF1220/1320
(Industrial) Standard Operating Condit ions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC18F1220/1320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedanc e state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
PIC18F1220/1320
DS39605D-page 252 © 2006 Microchip Technology Inc.
22.3 DC Characteristics: PIC18F1220/1320 (Industria l)
PIC18LF1220/1320 (I ndustrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for indu strial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Max Units Conditions
VIL Input Low Voltage
I/O ports:
D030 with TTL buffer VSS 0.15 VDD VVDD < 4.5V
D030A 0.8 V 4.5V VDD 5.5V
D031 with Schmitt Trigger buffer VSS 0.2 VDD V
D032 MCLR VSS 0.2 VDD V
D032A OSC1 (in XT , HS and LP modes)
and T1OSI VSS 0.3 VDD V
D033 OSC1 (in RC and EC mode)(1) VSS 0.2 VDD V
VIH Input High Voltage
I/O ports:
D040 with TTL buffer 0.25 VDD + 0.8V VDD VVDD < 4.5V
D040A 2.0 VDD V4.5V VDD 5.5V
D041 with Schmitt Trigger buffer 0.8 VDD VDD V
D042 MCLR, OSC1 (EC mode) 0.8 VDD VDD V
D042A OSC1 (in XT, HS and LP modes)
and T1OSI 1.6 VDD VDD V
D043 OSC1 (RC mode)(1) 0.9 VDD VDD V
IIL Input Leakage Current(2,3)
D060 I/O ports ±1μAVSS VPIN VDD,
Pin at high-impedance
D061 MCLR ±5μAVSS VPIN VDD
D063 OSC1 ±5μAVSS VPIN VDD
IPU Weak Pull- up C urrent
D070 IPURB PORTB weak pull-up current 50 400 μAVDD = 5V, VPIN = VSS
Note 1: In RC oscillator con figuration , the OSC1/CL KI pin is a Schmitt T r igger inpu t. It is not recomm ended that the
PICmicro® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
© 2006 Microchip Technology Inc. DS39605D-page 253
PIC18F1220/1320
VOL Output Low Voltage
D080 I/O ports 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D083 OSC2/CLKO
(RC mode) —0.6VI
OL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
VOH Output High Voltage(3)
D090 I/O ports VDD – 0.7 V IOH = -3.0 mA, VDD = 4.5V ,
-40°C to +85°C
D092 OSC2/CLKO
(RC mode) VDD – 0.7 V IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
D150 VOD Open-Drain High Volt a ge —8.5VRA4 pin
Capacitive Loading Specs
on Output Pins
D100(4) COSC2 OSC2 pin 15 pF In XT, HS and LP modes
when external clock is
used to drive OSC1
D101 CIO All I/O pins and OSC2
(in RC mode) 50 pF To meet the AC timing
specifications
D102 CBSCL, SDA 400 pF In I2C mode
22.3 DC Characteristics: PIC18F1220/1320 (Industria l)
PIC18LF1220/1320 (I ndustrial) (Continued)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Max Units Conditions
Note 1: In RC oscillator con figuration , the OSC1/CL KI pin is a Schmitt Trigger input. It is not recommend ed that the
PICmicro® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
PIC18F1220/1320
DS39605D-page 254 © 2006 Microchip Technology Inc.
TABLE 22-1: MEMORY PROGRAMMING REQUIREMENTS
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Sym Characteristic Min Typ† Max Units Conditions
Internal Program Memory
Programming Specifications(1)
D110 VPP Voltage on MCLR/VPP pin 9.00 13.25 V (Note 2)
D112 IPP Current into MCLR/VPP pin 5 μA
D113 IDDP Supply Current during
Programming ——10mA
Data EEPROM Memory
D120 EDByte Endurance 100K 1M E/W -40°C to +85°C
D121 VDRW VDD for Read/Write VMIN 5.5 V Using EECON to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write Cycle Time 4 ms
D123 TRETD Characteristic Retention 40 Year Provided no other
specifications are violated
D124 TREF Nu mber of Total Eras e/Writ e
Cycles before Re fresh(3) 1M 10M E/W -40°C to +85°C
Program Flash Memory
D130 EPCell Endurance 10K 100K E/W -40°C to +85°C
D131 VPR VDD for Read VMIN —5.5VVMIN = Minimum operating
voltage
D132 VIE VDD for Block Erase 4.5 5.5 V Using ICSP port
D132A VIW VDD for Externally Timed Erase
or Write 4.5 5.5 V Using ICSP port
D132B VPEW VDD for Self-Timed Write VMIN —5.5VVMIN = Minimum operating
voltage
D133 TIE ICSP™ Block Erase Cycle Time 4 ms VDD > 4.5V
D133A TIW ICSP E rase or Write Cycle Time
(externall y tim ed) 1—msVDD > 4.5V
D133A TIW Self-Timed Write Cycle Time 2 ms
D134 TRETD Characteristic Retention 40 Year Provided no other
specifications are violated
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: These specifications are for programming the on-chip program memory through the use of table write
instructions.
2: The pin may be kept in this range at times other than programming, but it is not recommended.
3: Refer to Section 7.8 “Using the Data EEPROM for a more detailed discussion on data EEPROM
endurance.
© 2006 Microchip Technology Inc. DS39605D-page 255
PIC18F1220/1320
FIGURE 22-4: LOW-VOLTAGE DETECT CHARACTERISTICS
VLVD
LVDIF
VDD
(LVDIF set by hardware)
(LVDIF can be
cleared in software)
TABLE 22-2: LOW-VOLTAGE DETECT CHARACTERISTICS
PIC18LF1220/1320
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC18F1220/1320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
D420D LVD Voltage on VDD Transition High-to-Low Industrial Low Voltage (-10°C to +85°C)
PIC18LF1220/1320 LVDL<3:0> = 0000 N/A N/A N/A V Reserved
LVD L<3:0> = 0001 N/A N/A N/A V Reserved
LVD L<3:0> = 0010 2.08 2.26 2.44 V
LVD L<3:0> = 0011 2.26 2.45 2.65 V
LVD L<3:0> = 0100 2.35 2.55 2.76 V
LVD L<3:0> = 0101 2.55 2.77 2.99 V
LVD L<3:0> = 0110 2.64 2.87 3.10 V
LVD L<3:0> = 0111 2.82 3.07 3.31 V
LVD L<3:0> = 1000 3.09 3.36 3.63 V
LVD L<3:0> = 1001 3.29 3.57 3.86 V
LVD L<3:0> = 1010 3.38 3.67 3.96 V
LVD L<3:0> = 1011 3.56 3.87 4.18 V
LVD L<3:0> = 1100 3.75 4.07 4.40 V
LVD L<3:0> = 1101 3.93 4.28 4.62 V
LVD L<3:0> = 1110 4.23 4.60 4.96 V
Legend: Shading of rows is to assist in readability of the table.
Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.
PIC18F1220/1320
DS39605D-page 256 © 2006 Microchip Technology Inc.
D420F LVD Voltage on VDD Transition High-to-Low Industrial Low Voltage (-40°C to -10°C)
PIC18LF1220/1320 LVDL<3:0> = 0000 N/A N/A N/A V Reserved
LVDL<3:0> = 0001 N/A N/A N/A V Reserved
LVDL<3:0> = 0010 1.99 2.26 2.53 V
LVDL<3:0> = 0011 2.16 2.45 2.75 V
LVDL<3:0> = 0100 2.25 2.55 2.86 V
LVDL<3:0> = 0101 2.43 2.77 3.10 V
LVDL<3:0> = 0110 2.53 2.87 3.21 V
LVDL<3:0> = 0111 2.70 3.07 3.43 V
LVDL<3:0> = 1000 2.96 3.36 3.77 V
LVDL<3:0> = 1001 3.14 3.57 4.00 V
LVDL<3:0> = 1010 3.23 3.67 4.11 V
LVDL<3:0> = 1011 3.41 3.87 4.34 V
LVDL<3:0> = 1100 3.58 4.07 4.56 V
LVDL<3:0> = 1101 3.76 4.28 4.79 V
LVDL<3:0> = 1110 4.04 4.60 5.15 V
LVD Voltage on VDD Transition High-to-Low Industrial (-10°C to +85°C)
D420G PIC18F1220/1320 LVDL<3:0> = 1101 3.93 4.28 4.62 V
LVDL<3:0> = 1110 4.23 4.60 4.96 V
LVD Voltage on VDD Transition High-to-Low Industrial (-40°C to -10°C)
D420H PIC18F1220/1320 LVDL<3:0> = 1101 3.76 4.28 4.79 V
LVDL<3:0> = 1110 4.04 4.60 5.15 V
LVD Voltage on VDD Transition High-to-Low Extended (-10°C to +85°C)
D420J PIC18F1220/1320 LVDL<3:0> = 1101 3.94 4.28 4.62 V
LVDL<3:0> = 1110 4.23 4.60 4.96 V
LVD Voltage on VDD Transition High-to-Low Extended (-40°C to -10°C, +85°C to +125°C)
D420K PIC18F1220/1320 LVDL<3:0> = 1101 3.77 4.28 4.79 V
LVDL<3:0> = 1110 4.05 4.60 5.15 V
TABLE 22-2: LOW-VOLTAGE DETECT CHARACTERISTICS (CONTINUED)
PIC18LF1220/1320
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC18F1220/1320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.
© 2006 Microchip Technology Inc. DS39605D-page 257
PIC18F1220/1320
22.4 AC (Timing) Characteristics
22.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp cc CCP1 osc OSC1
ck CLKO rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T13CKI
mc MCLR wr WR
Uppe rcase letters and th eir meanings:
SF Fall P Period
HHigh RRise
I Invalid (High-Impedance) V Valid
L Low Z High-Impedance
I2C only
AA ou tput access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC HD Hold SU Setup
ST DAT DATA input hold STO Stop condition
STA Start condition
PIC18F1220/1320
DS39605D-page 258 © 2006 Microchip Technology Inc.
22.4.2 TIMING CONDITIONS
The temperature and voltages specified in Table 22-3
apply to all timing specifications unless otherwise
noted. Figure 22-5 specifies the load conditions for the
timing specificati o n s.
TABLE 22-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
FIGURE 22-5: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
AC CHARACTERISTICS
S tandard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85° C for industrial
-40°C TA +125°C for extended
Operating voltage VDD range as described in DC spec Section 22.1 and
Section 22.3.
LF parts operate for industrial temperatures only.
VDD/2
CL
RL
pin
Pin
VSS
VSS
CL
RL= 464Ω
CL= 50 pF for all pi ns except OSC2/CLKO
Load Condition 1 Load Condition 2
© 2006 Microchip Technology Inc. DS39605D-page 259
PIC18F1220/1320
22.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 22-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
TABLE 22-4: EXTERNAL CLOCK TIMING REQUIREMENTS
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
Param.
No. Symbol Characteristic Min Max Units Conditions
1A FOSC External CLKI Frequenc y(1) DC 40 MHz EC, ECIO (LF and Industrial)
DC 25 MHz EC, ECIO (Extended)
Oscillator Frequency(1) DC 4 MHz RC oscillator
DC 1 MHz XT oscillator
DC 25 MHz HS oscillator
1 10 MHz HS + PLL oscillator
DC 33 kHz LP Oscillator mode
1T
OSC External CLKI Period (1) 25 ns EC, ECIO (LF and Industrial)
40 ns EC, ECIO (Exte nd ed)
Oscillator Period(1) 250 ns RC oscillator
1000 ns XT oscillator
25
100
1000 ns
ns HS oscillator
HS + PLL oscillator
30 μs LP oscillator
2TCY Instruction Cycle Time(1) 100 ns TCY = 4/FOSC
3 TosL,
TosH External Clock in (OSC1)
High or Low Time 30 ns XT oscillator
2.5 μs LP oscillator
10 ns HS oscillator
4TosR,
TosF External Clock in (OSC1)
Rise or Fall Time — 20 ns XT oscillator
— 50 ns LP oscillator
7.5 ns HS oscillator
Note 1: Instruction cy cle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL . Al l specified va lue s are bas ed on char ac teri zat ion dat a for that particular osci ll ator type under
sta ndard ope rating conditi ons, with the devic e exec uting co de. Exce eding these sp ecifie d limits may res ult
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
PIC18F1220/1320
DS39605D-page 260 © 2006 Microchip Technology Inc.
TABLE 22-5: PLL CLOCK TIMING SPECIFICATIONS, HS/HSPLL MODE (VDD = 4.2V TO 5.5V)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
F10 FOSC Oscilla tor Frequency Range 4 10 MHz HS and HSPLL mod e only
F11 FSYS On-Chip VCO System Frequency 16 40 MHz HSPLL mode only
F12 TPLL PLL Start-up Time (Lock Time) 2 ms HSPLL mode only
F13 ΔCLK CLKO Stability (Jitter) -2 +2 % HSPLL mode only
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
TABLE 22-6: INTERNAL RC ACCURACY: PIC18F1220/1320 (INDUSTRIAL)
PIC18LF1220/1320 (INDUSTRIAL)
PIC18LF1220/1320
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature - 40°C TA +85°C for industrial
PIC18F1220/1320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Min Typ Max Units Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)
PIC18LF1220/1320 -2 +/-1 2 % +25°C VDD = 2.7-3.3V
-5 5 % -10°C to +85°C VDD = 2.7-3.3V
-10 10 % -40°C to +85°C V DD = 2.7-3.3V
PIC18F1220/1320PIC18F
1220/1320 -2 +/-1 2 % +25°C VDD = 4.5-5.5V
-5 5 % -10°C to +85°C VDD = 4.5-5.5V
-10 10 %-40°C to +85°C VDD = 4.5-5.5V
INTRC Accuracy @ Freq = 31 kHz(2)
PIC18LF1220/1320 26.562 35.938 kHz -40°C to +85°C V DD = 2.7-3.3V
PIC18F1220/1320PIC18F
1220/1320 26.562 35.938 kHz -40°C to +85°C VDD = 4.5-5.5V
Legend: Shading of rows is to assist in readability of the table.
Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature and VDD drift.
2: INTRC frequency after calibration.
3: Change of INTRC frequency as VDD changes.
© 2006 Microchip Technology Inc. DS39605D-page 261
PIC18F1220/1320
FIGURE 22-7: CLKO AND I/O TIMING
TABLE 22-7: CLKO AND I/O TI MING REQUIREMENTS
Note: Refer to Figure 22-5 for load conditions.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12
16
Old Value New Value
Param.
No. Symbol Characteristic Min Typ Max Units Conditions
10 TosH2ckL OSC1 to CLKO 75 200 ns (Note 1)
11 TosH2ckH OSC1 to CLKO 75 200 ns (Note 1)
12 TckR CLKO Rise Time 35 100 ns (Note 1)
13 TckF CLKO Fall Time 35 100 ns (Note 1)
14 TckL2ioV CLKO to Port Out Valid 0.5 TCY + 20 ns (Note 1)
15 TioV2ckH Port In Valid before CLKO 0.25 TCY + 25 ns (Note 1)
16 TckH2ioI Port In Hold after CLKO 0—ns(Note 1)
17 TosH2ioV OSC1 (Q1 cycle) to Port Out Valid 50 150 ns
18 TosH2ioI OSC1 (Q2 cycle) to Port
Input Invalid (I/O in hold time) PIC18F1X20 100 ns
18A PIC18LF1X20 200 ns
19 TioV2osH Port Input Valid to OSC1
(I/O in setup time) 0—ns
20 TioR Port Output Rise Time PIC18F1X20 10 25 ns
20A PIC18LF1X20 60 ns
21 TioF Port Outp ut Fa ll Time PIC18F1X20 10 25 ns
21A PIC18LF1X20 60 ns
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
PIC18F1220/1320
DS39605D-page 262 © 2006 Microchip Technology Inc.
FIGURE 22-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 22-9: BROWN-OUT RESET TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pi n s
34
Note: Refer to Figure 22-5 for load conditions.
VDD BVDD
35 VBGAP = 1.2V
VIRVST
Enable Internal
Internal Reference 36
Reference Voltage
Voltage Stable
© 2006 Microchip Technology Inc. DS39605D-page 263
PIC18F1220/1320
TABLE 22-8: RESET, WATCHDOG TIMER, OS CILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
FIGURE 22-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
Param.
No. Symbol Characteristic Min Typ Max Units Conditions
30 TmcL MCLR Pulse Width (low) 2 μs
31 TWDT Watchdog Timer Time-out Period
(No postscaler) 3.48 4.00 4.71 ms
32 TOST Oscillation Start-up Timer Period 1024 TOSC 1024 TOSC —TOSC = OSC1 period
33 TPWRT Power-up Timer Period 65.5 132 ms
34 TIOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset —2μs
35 TBOR Brown-out Reset Pulse Width 200 μsVDD BVDD (see D005)
36 TIVRST Time for Internal Reference
Voltage to become stable —2050 μs
37 TLVD Low-Voltage Detect Pulse Width 200 μsVDD VLVD
Note: Refer to Figure 22-5 for load conditions.
46
47
45
48
41
42
40
T0CKI
T1OSO/T13CKI
TMR0 or
TMR1
PIC18F1220/1320
DS39605D-page 264 © 2006 Microchip Technology Inc.
TABLE 22-9: T IMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
FIGURE 22-11: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)
Param
No. Symbol Characteristic Min Max Units Conditions
40 Tt0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 ns
With presca ler 10 ns
41 Tt0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 ns
With presca ler 10 ns
42 Tt0P T0CKI Period No prescaler TCY + 10 ns
With prescaler Greater of:
20 ns or TCY + 40
N
—nsN = prescale
value
(1, 2, 4,..., 256)
45 Tt1H T1 3CKI H ig h Tim e Synchronou s, no presc ale r 0.5 TCY + 20 ns
Synchronous,
with presca ler PIC18F1X20 10 ns
PIC18LF1X20 25 ns
Asynchronous PIC18F1X20 30 ns
PIC18LF1X20 50 ns
46 Tt1L T13C KI Lo w Time Synchronous, no presc ale r 0.5 TCY + 5 ns
Synchronous,
with presca ler PIC18F1X20 10 ns
PIC18LF1X20 25 ns
Asynchronous PIC18F1X20 30 ns
PIC18LF1X20 50 ns
47 Tt1P T13CKI Input
Period Synchronous Greater of:
20 ns or TCY + 40
N
—nsN = prescale
value
(1, 2, 4, 8)
Asynchronous 60 ns
Ft1 T13CKI Oscillator Input Frequency Range DC 50 kHz
48 Tcke2 t mr I D ela y from Externa l T13CKI Clock Edge to
Timer Increment 2 TOSC 7 TOSC
Note: Refer to Figure 22-5 for load conditions.
CCPx
(Capture Mode)
50 51
52
CCPx
53 54
(Compare or PWM Mode)
© 2006 Microchip Technology Inc. DS39605D-page 265
PIC18F1220/1320
TABLE 22-10: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
FIGURE 22-12: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 22-11: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param.
No. Symbol Characteristic Min Max Units Conditions
50 TccL CCPx In put Low
Time No prescaler 0.5 TCY + 20 ns
With prescaler PIC18F1X20 10 ns
PIC18LF1X20 20 ns
51 TccH CCPx Input High
Time No prescaler 0.5 TCY + 20 ns
With prescaler PIC18F1X20 10 ns
PIC18LF1X20 20 ns
52 TccP CCPx Input Period 3 TCY + 40
N ns N = prescale
value (1, 4 or 16)
53 TccR CCPx Output Fall Time PIC18F1X20 25 ns
PIC18LF1X20 45 ns
54 TccF CCPx Output Fall Time PIC18F1X20 25 ns
PIC18LF1X20 45 ns
121 121
120 122
RB1/AN5/TX/
RB4/AN6/RX/
DT/KBI0 pin
CK/INT1 pin
Note: Refer to Figure 22-5 for load conditions.
Param.
No. Symbol Characteristic Min Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid PIC18F1X20 40 ns
PIC18LF1X20 100 ns
121 Tckrf Clock Out Rise Time and Fall Time
(Master mode) PIC18F1X20 20 ns
PIC18LF1X20 50 ns
122 Tdtrf Data Out Rise Time and Fall Time PIC18F1X20 20 ns
PIC18LF1X20 50 ns
PIC18F1220/1320
DS39605D-page 266 © 2006 Microchip Technology Inc.
FIGURE 22-13: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 22-12: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
TABLE 22-13: A/D CONVERTER CHARACTERISTICS: PIC18F1220/1320 (INDUSTRIAL)
PIC18LF1220/1320 (INDUSTRIAL)
Param.
No. Symbol Characteristic Min Max Units Conditions
125 TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data Hold before CK (DT hold time) 10 ns
126 TckL2dtl Data Hold after CK (DT hold time) 15 ns
Param
No. Symbol Characteristic Min Typ Max Units Conditions
A01 NRResolution 10 bit ΔVREF 3.0V
A03 EIL Integr al Lin ear ity Error 1 LSb ΔVREF 3.0V
A04 EDL Differential Linearity Error 1 LSb ΔVREF 3.0V
A06 EOFF Offset Error 1 LSb ΔVREF 3.0V
A07 EGN Gain Error <±1 LSb ΔVREF 3.0V
A10 Monotonicity guaranteed(2)
A20 ΔVREF Reference Voltage Range
(VREFH – VREFL)3—AV
DD – AVSS V For 10-bit resolution
A21 VREFH Reference Voltage High AVSS + 3.0V AVDD + 0.3V V For 10-bit resolution
A22 VREFL Reference Voltage Lo w AVSS – 0.3V AVDD – 3.0V V For 10-bit r esolution
A25 VAIN Analog Input Voltage VREFL —VREFH V
A28 AVDD Analog Supply Voltage VDD – 0.3 VDD + 0.3 V
A29 AVSS Analog Supply Voltage VSS – 0.3 VSS + 0.3 V
A30 ZAIN Recomm end ed Impedance of
Analog Voltage Source ——2.5kΩ
A40 IAD A/D Convers ion
Current (VDD)PIC18F1X20 180 μA Average current
cons umption when
A/D is on (Note 1)
PIC18LF1X20 90 μA
A50 IREF VREF Input Current (Note 3)
±5
±150 μA
μADuring VAIN acquisition.
During A/D conversion
cycle.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
specification includes any such leakage from the A/D module.
2: The A/D co nve rsion result n ever de creas es wi th an in creas e in the input v olt ag e an d has n o miss ing c odes.
3: VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source.
125
126
Note: Refer to Figure 22-5 for load conditions.
RB1/AN5/TX/
RB4/AN6/RX/
DT/KBI0 pin
CK/INT1 pin
© 2006 Microchip Technology Inc. DS39605D-page 267
PIC18F1220/1320
FIGURE 22-14: A/D CONVERSION TIMING
TABLE 22-14: A/D CONVERSION REQUIREMENTS
131
130
132
BSF ADCON0, GO
Q4
A/D CLK(1)
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
Sampling Stopped
DONE
NEW_DATA
(Note 2)
987 21 0
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . . . . .
TCY
Param
No. Symbol Characteristic Min Max Units Conditions
130 TAD A/D Clock Period PIC18F1X20 1.6 20(5) μsTOSC based, VREF 3.0V
PIC18LF1X20 3.0 20(5) μsTOSC based, VREF full range
PIC18F1X20 2.0 6.0 μs A/D RC mode
PIC18LF1X20 3.0 9.0 μs A/D RC mode
131 TCNV C onversion Time
(not including acquisition time) (Note 1) 11 12 TAD
132 TACQ Acquisition Time (Note 3) 15
10
μs
μs-40°C Temp +125°C
0°C Temp +125°C
135 TSWC Switching Time from Convert Sample (Note 4)
136 TAMP Amplifier Settling Time (Note 2) 1—μs This may be used if the
“new” input voltage has not
changed by more tha n 1 LSb
(i.e., 5 mV @ 5.12 V) from the
last sampled voltage (as
stated on C HOLD).
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 17.0 “10-Bit Ana log-to-Digit al Converter (A/D) M odule” for minim um cond itions when input
voltage has changed more than 1 LSb.
3: The time for the holdi ng capacitor to ac quire the “New” input volt age, when the volt age changes full scale after
the conversion ( AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is 50Ω.
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divide r.
PIC18F1220/1320
DS39605D-page 268 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS39605D-page 269
PIC18F1220/1320
23.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
“T ypical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean 3σ)
respectively, where σ is a standa rd deviation, ov er the whol e temperature range .
FIGURE 23-1: TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C
FIGURE 23-2: MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +85°C
Note: The g r ap hs and t ables prov ide d followin g th is no te a r e a s t ati sti ca l s um ma ry based on a l im ite d n um ber of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
0.0
0.1
0.2
0.3
0.4
0.5
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20
FOSC (MHz)
IDD (mA)
5.0V
5.5V
4.0V
4.5V
3.0V
3.5V
2.0V
2.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20
FOSC (MHz)
IDD (mA)
5.0V
5.5V
4.0V
4.5V
3.0V
3.5V
2.0V
2.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
PIC18F1220/1320
DS39605D-page 270 © 2006 Microchip Technology Inc.
FIGURE 23-3: MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C
FIGURE 23-4: TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20
FOSC (MHz)
IDD (mA)
5.0V
5.5V
4.0V
4.5V
3.0V
3.5V
2.0V
2.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
1.0 1.5 2.0 2.5 3.0 3.5 4.0
FOSC (MHz)
IDD (mA)
5.0V
5.5V
4.0V
4.5V
3.0V
3.5V
2.0V
2.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
© 2006 Microchip Technology Inc. DS39605D-page 271
PIC18F1220/1320
FIGURE 23-5: MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C
FIGURE 23-6: TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C
0.0
0.5
1.0
1.5
2.0
2.5
1.0 1.5 2.0 2.5 3.0 3.5 4.0
FOSC (MHz)
IDD (mA)
5.0V
5.5V
4.0V
4.5V
3.0V
3.5V
2.0V
2.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0
2
4
6
8
10
12
14
16
4 8 12 16 20 24 28 32 36 40
FOSC (MHz)
IDD (mA)
5.0V
5.5V
4.0V
4.5V
3.0V
3.5V
2.0V 2.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
PIC18F1220/1320
DS39605D-page 272 © 2006 Microchip Technology Inc.
FIGURE 23-7: MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C
FIGURE 23-8: TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C
0
2
4
6
8
10
12
14
16
4 8 12 16 20 24 28 32 36 40
FOSC (MHz)
IDD (mA)
5.0V
5.5V
4.0V
4.5V
3.0V
3.5V
2.0V 2.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.000
0.005
0.010
0.015
0.020
0.025
0.030
0.035
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20
FOSC (M Hz)
IDD (mA)
4.0V
4.5V
3.0V
3.5V
2.0V
2.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
© 2006 Microchip Technology Inc. DS39605D-page 273
PIC18F1220/1320
FIGURE 23-9: MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +85°C
FIGURE 23-10 : MAXIMU M IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C
0.000
0.005
0.010
0.015
0.020
0.025
0.030
0.035
0.040
0.045
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20
FOSC (M Hz)
IDD (mA)
4.0V
4.5V
3.0V
3.5V
2.0V
2.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.000
0.010
0.020
0.030
0.040
0.050
0.060
0.070
0.080
0.090
0.100
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20
FOSC (MHz)
IDD (mA)
4.0V
4.5V
3.0V
3.5V
2.0V
2.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
PIC18F1220/1320
DS39605D-page 274 © 2006 Microchip Technology Inc.
FIGURE 23-11: TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C
FIGURE 23-12 : MAXIMU M IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C
Typical I vs F over V PRI_IDLE, EC mode, +25°C
0
100
200
300
400
500
600
1.0 1.5 2.0 2.5 3.0 3.5 4.0
FOSC (MHz)
IDD (μA)
4.0V
4.5V
3.0V
3.5V
2.0V
2.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0
100
200
300
400
500
600
1.0 1.5 2.0 2.5 3.0 3.5 4.0
FOSC (MHz)
IDD (μA)
4.0V
4.5V
3.0V
3.5V
2.0V
2.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
© 2006 Microchip Technology Inc. DS39605D-page 275
PIC18F1220/1320
FIGURE 23-13: TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C
FIGURE 23-14 : MAXIMU M IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
4 8 12 16 20 24 28 32 36 40
FOSC (MHz)
IDD (mA)
4.0V
4.5V
3.0V
3.5V
2.0V
2.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
4 8 12 16 20 24 28 32 36 40
FOSC (MHz)
IDD (mA)
4.0V
4.5V
3.0V
3.5V
2.0V
2.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
PIC18F1220/1320
DS39605D-page 276 © 2006 Microchip Technology Inc.
FIGURE 23-15: TYPICAL IPD vs. VDD (+25°C), 125 kHz TO 8 MHz RC_RUN MODE,
ALL PERIPHERALS DISABLED
FIGURE 23-16 : MAXIMU M IPD vs. VDD (-40°C TO +125°C), 125 kHz TO 8 MHz RC_RUN MODE,
ALL PERIPHERALS DISABLED
0
500
1000
1500
2000
2500
3000
2.02.53.03.54.04.55.05.5
VDD (V)
IPD (μA)
8 MHz
125 kHz
4 MHz
2 MHz
1 MHz
250 kHz and 500 kHz curves are
bounded by 125 k Hz and 1 MHz
curves.
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0
500
1000
1500
2000
2500
3000
3500
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
8 MHz
125 kHz
4 MHz
2 MHz
1 MHz
250 kHz and 500 kHz curves are
bounded by 125 kH z and 1 MHz
curves.
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
© 2006 Microchip Technology Inc. DS39605D-page 277
PIC18F1220/1320
FIGURE 23-17: TYPICAL AND MAXIMUM IPD vs. VDD (-40°C TO +125°C), 31.25 kHz RC_RUN MODE,
ALL PERIPHERALS DISABLED
FIGURE 23-18: TYPICAL IPD vs. VDD (+25°C), 125 kHz TO 8 MHz RC_IDLE MODE,
ALL PERIPHERALS DISABLED
1
10
100
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Typ (+25°C)
Max (+85°C)
Max (+125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
8 MHz
125 kHz
4 MHz
2 MHz
1 MHz
250 kHz and 500 kHz curves are
bounded by 125 k H z and 1 MHz
curves.
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
PIC18F1220/1320
DS39605D-page 278 © 2006 Microchip Technology Inc.
FIGURE 23-19 : MAXIMU M IPD vs. VDD (-40°C TO +125°C), 125 kHz TO 8 MHz RC_IDLE MODE,
ALL PERIPHERALS DISABLED
FIGURE 23-20: TYPICAL AND MAX IMUM I PD vs. VDD (-40°C TO +12 5°C), 31 .2 5 kHz RC_I DLE MODE ,
ALL PERIPHERALS DISABLED
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
8 MHz
125 kHz
4 MHz
2 MHz
1 MHz
250 kHz and 500 kHz curves are
bounded by 125 kHz and 1 MHz
curves.
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
1
10
100
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Typ (+25°C )
Max (+85°C)
Max ( +125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
© 2006 Microchip Technology Inc. DS39605D-page 279
PIC18F1220/1320
FIGURE 23-21 : IPD SEC_RUN MODE, -10°C TO +70°C, 32.768 kHz XTAL , 2 x 22 pF,
ALL PERIPHERALS DISABLED
FIGURE 23-22 : IPD SEC_IDLE MODE, -10°C TO +70°C, 32.768 kHz, 2 x 22 pF,
ALL PERIPHERALS DISABLED
0
10
20
30
40
50
60
70
80
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Typ (+25°C)
Max (+70°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0
2
4
6
8
10
12
14
16
18
20
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Typ (+25°C)
Max (+70°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
PIC18F1220/1320
DS39605D-page 280 © 2006 Microchip Technology Inc.
FIGURE 23-23 : TOTAL IPD, -40°C TO +125°C SLEEP MODE, ALL PERIPHERALS DISABLED
FIGURE 23-24 : VOH vs. IOH OVER TEMPERATURE (-40°C TO +125°C), VDD = 3.0V
0.001
0.01
0.1
1
10
100
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Max (+85°C)
Max (+125°C)
Typ (+25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25
IOH (-mA)
VOH (V)
Max (+125°C)
Min (+125°C)
Typ (+25°C)
© 2006 Microchip Technology Inc. DS39605D-page 281
PIC18F1220/1320
FIGURE 23-25 : VOH vs. IOH OVER TEMPERATURE (-40°C TO +125°C), VDD = 5.0V
FIGURE 23-26 : VOL vs. IOL OVER TEMPERATURE (-40°C TO +125°C), VDD = 3.0V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 5 10 15 20 25
IOH (-mA)
VOH (V)
Max (+125°C)
Min (+125°C)
Typ (+25°C)
V vs I over Temp (-40°C to +125°C) V = 3.0V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25
IOL (-mA)
VOL (V)
Max (+125°C)
Max (+85°C)
Typ (+25°C)
Min (+125°C)
PIC18F1220/1320
DS39605D-page 282 © 2006 Microchip Technology Inc.
FIGURE 23-27 : VOL vs. IOL OVER TEMPERATURE (-40°C TO +125°C), VDD = 5.0V
FIGURE 23-28 : ΔIPD TIMER1 OSCILLATOR, -10°C TO +70°C SLEEP MODE,
TMR1 COUNTER DISABLED
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 5 10 15 20 25
IOL (-mA)
VOL (V)
Max (+125°C)
Max (+85°C)
Typ (+25°C)
Min (+125°C)
IPD Timer1 Oscillator, -10°C to +70°C SLEEP mode, TMR1 counter disabled
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
2.02.53.03.54.04.55.05.5
VDD (V)
IPD (μA)
Typ (+25°C)
Max (- 10°C to +70°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
© 2006 Microchip Technology Inc. DS39605D-page 283
PIC18F1220/1320
FIGURE 23-29 : ΔIPD FSCM vs. VDD OVER TEMPERATURE PR I_ IDLE MODE ,
EC OSCILLATOR AT 32 kHz, -40°C TO +12C
FIGURE 23-30 : ΔIPD WDT, -40°C TO +125°C SLEEP MODE, ALL PERIPHERALS DISABLED
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
ΔIPD (μA)
Typ (+25°C )
Max (-40°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0
2
4
6
8
10
12
14
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
ΔIPD (μA)
Typ (+2 5 °C)
Max (+85°C)
Max (+125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
PIC18F1220/1320
DS39605D-page 284 © 2006 Microchip Technology Inc.
FIGURE 23-31 : ΔIPD LVD vs. VDD SLEEP MODE, LVDL3:LVDL0 = 0001 (2V)
FIGURE 23-32 : ΔIPD BOR vs. VDD, -40°C TO +125°C SLEEP MODE,
BORV1:BORV0 = 11 (2V)
0
5
10
15
20
25
30
35
40
45
50
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Typ (+25 °C)
Max (+85°C)
Max (+125°C)
Low-Voltage Detection Range
Normal Operating Range
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0
5
10
15
20
25
30
35
40
2.02.53.03.54.04.55.05.5
VDD (V)
IPD (μA)
Max (+125°C)
Typ (+25°C)
Device may be in Res et
Device is Operating
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
© 2006 Microchip Technology Inc. DS39605D-page 285
PIC18F1220/1320
FIGURE 23-33 : ΔIPD A/D, -40°C TO +125°C SLEEP MODE, A/D ENABLED (NOT CONVERTING)
FIGURE 23-34: AVERAGE FOSC vs. VDD FOR VARIOUS R’s EXTERNAL RC MODE,
C = 20 pF, TEMPERATURE = +25°C
0.001
0.01
0.1
1
10
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Max (+125°C)
Max (+85°C)
Typ (+25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Freq (MH z)
5.1K
10K
33K
100K
Operation above 4 MHz is not recomended
PIC18F1220/1320
DS39605D-page 286 © 2006 Microchip Technology Inc.
FIGURE 23-35: AVERAGE FOSC vs. VDD FOR VARIOUS R’s EXTERNAL RC MODE,
C = 100 pF, TEMPERATURE = +25°C
FIGURE 23-36: AVERAGE FOSC vs. VDD FOR VARIOUS R’s EXTERNAL RC MODE,
C = 300 pF, TEMPERATURE = +25°C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Freq (MH z)
5.1K
10K
33K
100K
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Freq (MH z)
5.1K
10K
33K
100K
© 2006 Microchip Technology Inc. DS39605D-page 287
PIC18F1220/1320
24.0 PACKAGING INFORMATION
24.1 Package Marking Information
18-Lead PDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC18F1320-I/P
0610017
18-Lead SOIC
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
PIC18F1220-
E/SO0610017
20-Lead SSOP
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Example
PIC18F1220-
E/SS
0610017
28-Lead QFN
XXXXXXXX
XXXXXXXX
YYWWNNN
Example
18F1320
-I/ML
0610017
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanum eri c trac eab il ity code
Pb-free JEDEC designator for Matte Ti n (Sn)
*This packa ge is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the fu ll Mic rochip part nu mber ca nnot be m arked on one line, it w ill
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
3
e
3
e
3
e
PIC18F1220/1320
DS39605D-page 288 © 2006 Microchip Technology Inc.
24.2 Package Details
The following sections give the technical details of the
packages.
18-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 10.929.407.87.430.370.310
eB
Overall Row Spacing §0.560.460.36.022.018.014BLower Lead Width 1.781.461.14.070.058.045
B1
Upper Lead Width 0.380.290.20.015.012.008
c
Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 22.9922.8022.61.905.898.890DOverall Length 6.606.356.10.260.250.240E1Molded Pa ckag e Width 8.267.947.62.325.313.300EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.683.302.92.145.130.115A2Molded Packag e Thickness 4.323.943.56.170.155.140ATop to Seating Plane 2.54.100
p
Pitch 1818
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
1
2
D
n
E1
c
eB
β
E
α
p
A2
L
B1
B
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
§ Significant Characteristic
© 2006 Microchip Technology Inc. DS39605D-page 289
PIC18F1220/1320
18-Lead Plasti c Small Outline (SO) – Wide, 300 mil Body (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Foot A ngle φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.300.270.23.012.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 11.7311.5311.33.462.454.446DOverall Length 7.597.497.39.299.295.291E1Molded Packag e Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff §2.392.312.24.094.091.088A2Molded Pa ckag e Thick ness 2.642.502.36.104.099.093AOverall Height 1.27
.050
p
Pitch 1818
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
L
β
c
φ
h
45°
1
2
D
p
n
B
E1
E
α
A2
A1
A
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
§ Significant Characteristic
PIC18F1220/1320
DS39605D-page 290 © 2006 Microchip Technology Inc.
20-Lead Plasti c Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.38-0.22.015-.009BLead Width
φ
Foot Angle
0.25-0.09.010-.004
c
Lead Thickness
0.950.750.55.037.030.022LFoot Length
7.507.206.90.295.283.272DOverall Length
5.385.255.11.212.207.201E1Molded Package Width
8.207.807.40.323.307.291EOverall Width
--0.05--.002A1Standoff
1.851.751.65.073.069.065A2Molded Package Thickness
2.00--.079--AOverall Height
0.65.026
p
Pitch
2020
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERS*INCHESUnits
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
Notes:
Drawing No. C04-072
*Controlling Parameter
Revised 7-20-06
LA1
A2
A
c
B
p
n
E
E1
D
1
2
φ
© 2006 Microchip Technology Inc. DS39605D-page 291
PIC18F1220/1320
28-Lead Plasti c Quad Flat, No Lead Package (ML) - 6x6 mm Body [QFN]
With 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Number of Pins
Pitch
Overall Height
Standoff
Contact Thickness
Overall Width
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length §
Contact-to-Exposed Pad §
Units
Dimension Limits
N
e
A
A1
A3
E
E2
D
D2
b
L
K
0.80
0.00
3.65
3.65
0.23
0.50
0.20
28
0.65 BSC
0.90
0.02
0.20 REF
6.00 BSC
3.70
6.00 BSC
3.70
0.30
0.55
1.00
0.05
4.20
4.20
0.35
0.70
MIN NOM MAX
MILLIMETERS
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Package is saw singulated
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–105, Sept. 8, 2006
A1
A
A3
TOP VIEW
N
NOTE 1
BOTTOM VIEW
L
K
b
e
D2
2
1
2
1
E
E2
EXPOSED
PAD
N
D
PIC18F1220/1320
DS39605D-page 292 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS39605D-page 293
PIC18F1220/1320
APPENDIX A: REVISION HISTORY
Revision A (August 2002)
Original data sheet for PIC18F1220/1320 devices.
Revision B (November 2002)
This revision includes significant changes to
Section 2.0, Section 3.0 and Section 19.0, as wel l a s
updates to the El ectrical Specificati ons in Section 22.0
and includes minor corrections to the data sheet text.
Revision C (May 2004)
This rev is ion in cl ude s updates to the Elec tric al Spe ci fi-
cations in Section 22.0, the DC and AC Characteristics
Graphs and Tables in Section 23.0 and includes minor
corrections to the data sheet text.
Revision D (October 2006)
This revision includes updates to the packaging
diagrams.
APPENDIX B: DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1.
TABLE B-1: DEVICE DIFFERENCES
Features PIC18F1220 PIC18F1320
Program Memo ry (Bytes ) 4096 8192
Program Memo ry (Instructions) 2048 4096
Interrupt Sources 15 15
I/O Ports Ports A, B Ports A, B
Enhanced Capture/Compare/PWM Modules 1 1
10-bit Analog-to-Digital Module 7 input channels 7 input channels
Packages
18-pin SDIP
18-pin SOIC
20-pin SSOP
28-pin QFN
18-pin SDIP
18-pin SOIC
20-pin S SOP
28-pin QFN
PIC18F1220/1320
DS39605D-page 294 © 2006 Microchip Technology Inc.
APPENDIX C: CONVERSION
CONSIDERATIONS
This appendix discusses the considerations for con-
verting from previous versions of a device to the ones
listed in this data sheet. Typically, these changes are
due to the differences in the process technology used.
An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
Not Applicable
APPENDIX D: MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This section discusses how to migrate from a baseline
device (i.e., PIC16C5X) to an enhanced MCU device
(i.e., PIC18FXXX).
The following are the list of modifications over the
PIC16C5X mic roc on trol ler fam il y:
Not Currently Av ail able
© 2006 Microchip Technology Inc. DS39605D-page 295
PIC18F1220/1320
APPENDIX E: MIGRATION FROM
MID-RANGE TO
ENHANCED DEVICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442”. The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
This Ap plicatio n Note is availab le as L iterature Nu mber
DS00716.
APPENDIX F: MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
A detailed discussion of the migration pathway and
differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration”.
This Ap plication Note is availab le as L iterature Nu mber
DS00726.
PIC18F1220/1320
DS39605D-page 296 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS39605D-page 297
PIC18F1220/1320
INDEX
A
A/D ...................................................................................155
A/D Converter Interrupt, Configuring .......................159
Acquisition Requirements ........................................160
ADCON0 Register ....................................................155
ADCON1 Register ....................................................155
ADCON2 Register ....................................................155
ADRESH Register ....................................................155
ADRESH/ADRESL Registers ..................................158
ADRESL Register ....................................................155
Analog Port Pins, Configuring ..................................162
Associated Registers ...............................................164
Configuring the Module ............................................159
Conversion Clock (Tad) ...........................................161
Conversion Requirements .......................................267
Conversion Status (GO/DONE Bit) ..........................158
Conversions .............................................................163
Converter Characteristics ........................................266
Operation in Low-Power Modes ...............................162
Selecting, Configuring Automatic
Acquisition Time ...............................................161
Special Event Trigger (CCP) ....................................117
Special Event Trigger (CCP1) ..................................164
Use of the CCP1 Trigger ..........................................164
VREF+ and VREF- References ..................................160
Absolute Maximum Ratings .............................................239
AC (Timing) Characteristics .............................................257
Conditions ................................................................258
Load Conditions for Device
Timing Specifications .......................................258
Parameter Symbology .............................................257
Temperature and Voltage Specifications .................258
ADCON0 Register ............................................................155
GO/DONE Bit ...........................................................158
ADCON1 Register ............................................................155
ADCON2 Register ............................................................155
ADDLW ............................................................................197
ADDWF ............................................................................197
ADDWFC .........................................................................198
ADRESH Register ............................................................155
ADRESH/ADRESL Registers ...........................................158
ADRESL Register ............................................................155
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................198
ANDWF ............................................................................199
Assembler
MPASM Ass e mbler ..................................................233
Auto-Wake-up on Sync Break Character .........................145
B
BC ....................................................................................199
BCF ..................................................................................200
Block Diagrams
A/D ...........................................................................158
Analog Input Model ..................................................159
Capture Mode Operation .........................................117
Compare Mode Operation .......................................118
Enhanced PWM .......................................................120
EUSART Receive ....................................................143
EUSART Transmit ...................................................141
Fail-Safe Clock Monitor ............................................182
Generic I/O Port Operation ........................................87
Low-Voltage Detect (LVD) .......................................166
Low-Voltage Detect (LVD) with
External Input .................................................. 166
MCLR/VPP/RA5 Pin ................................................... 89
On-Chip Reset Circuit ................................................ 33
OSC1/CLKI/RA7 Pin .................................................. 88
OSC2/CLKO/RA6 Pin ................................................ 88
PIC18F1220/1320 ....................................................... 7
PLL ............................................................................ 12
RA3:RA0 Pins ............................................................ 88
RA4/T0CKI Pin .......................................................... 88
RB0/AN4/INT0 Pin ..................................................... 90
RB1/AN 5/T X/ C K/ INT1 Pin ......................................... 91
RB2/P1B/INT2 Pi n ..................................................... 92
RB3/CCP1/P1A Pin ................................................... 93
RB4/AN 6/RX/DT/ KBI 0 Pin ......................................... 94
RB5 /PGM/KB I1 Pin .................................................... 95
RB6/PGC/T1O SO/T13CK I/P1C/KBI2 Pin .................. 96
RB7/PGD/T1OSI /P 1D/KB I3 Pi n ................................. 97
Reads from Flash Program Memory .......................... 61
System Clock ............................................................. 16
Table Read Operation ............................................... 57
Table Write Operation ................................................ 58
Table Writes to Flash Program Memory .................... 63
Timer0 in 16-Bit Mode ............................................. 100
Timer0 in 8-Bit Mode ............................................... 100
Timer1 ..................................................................... 104
Timer1 (16-Bit Read/Write Mode) ............................ 104
Timer2 ..................................................................... 110
Timer3 ..................................................................... 112
Timer3 (16-bit Read/Write Mode) ............................ 112
WDT ........................................................................ 180
BN .................................................................................... 200
BNC ................................................................................. 201
BNN ................................................................................. 201
BNOV ............................................................................... 202
BNZ .................................................................................. 202
BOR. See Brown-out Reset.
BOV ................................................................................. 205
BRA ................................................................................. 203
Break Character (12-bit) Transmit and Receive .............. 146
Brown-out Reset (BOR) ..............................................34, 171
BSF .................................................................................. 203
BTFSC ............................................................................. 204
BTFSS ............................................................................. 204
BTG ................................................................................. 205
BZ .................................................................................... 206
C
C Compilers
MPLAB C17 ............................................................. 234
MPLAB C18 ............................................................. 234
MPLAB C30 ............................................................. 234
CALL ................................................................................ 206
Capture (CCP Module) .................................................... 116
CCP Pin Configuration ............................................. 116
CCPR1H:CCPR1L Registers ................................... 116
Softwar e In terrupt .................................................... 116
Timer1/Timer3 Mode Selection ................................ 116
Capture, Compare, Timer1 and Timer3
Associated Registers ............................................... 118
PIC18F1220/1320
DS39605D-page 298 © 2006 Microchip Technology Inc.
Capture/Compare/PWM (CCP)
Capture Mode. See Capture.
CCP1 ........................................................................116
CCPR1H Register ............................................116
CCPR1L Register ............................................116
Compare Mode. See Compare.
Timer Resources ......................................................116
Clock Sources ....................................................................15
Selection Using OSCCON Register ...........................16
Clocking Scheme ...............................................................45
CLRF ................................................................................207
CLRWDT ..........................................................................207
Code Examples
16 x 16 Signed Multiply Routine .................................72
16 x 16 Unsigned Multiply Routine .............................72
8 x 8 Signed Multiply Routine .....................................71
8 x 8 Unsigned Multiply Routine .................................71
Changing Between Capture Prescalers ...................117
Computed GOTO Using an Offset Value ...................47
Data EEPROM Read .................................................69
Data EEPROM Refresh Routine ................................70
Data EEPROM Write ..................................................69
Erasing a Flash Program Memory Row .....................62
Fast Register Stack ....................................................44
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................53
Implementing a Real-Time Clock Using
a Timer1 In terru pt Service ...............................107
Initia lizing PORTA ......................................................87
Initia lizing PORTB ......................................................90
Reading a Flash Program Memory Word ...................61
Saving Status, WREG and
BSR Registers in RAM .......................................85
Writing to Flash Program Memory .......................6465
Code Protection ...............................................................171
COMF ...............................................................................208
Compare (CCP Module) ...................................................117
CCP Pin Configuration .............................................117
CCPR1 Register .......................................................117
Software Interrupt .....................................................117
Special Event Trigger .......................................113, 117
Timer1/Timer3 Mode Selection ................................117
Compare (CCP1 Module)
Special Event Trigger ...............................................164
Computed GOTO ...............................................................47
Configuration Bits .............................................................171
Context Saving During Interrupts .......................................85
Conversion Considerations ..............................................294
CPFSEQ ..........................................................................208
CPFSGT ...........................................................................209
CPFSLT ...........................................................................209
D
Data EEPRO M Memor y .....................................................67
Associated Registers .................................................70
EEADR Register ........................................................67
EECON1 Register ......................................................67
EECON2 Register ......................................................67
Operation During Code-Protect ..................................70
Protection Against Spurious Write .............................69
Reading ......................................................................69
Using ..........................................................................70
Write Verify .................................................................69
Writing ........................................................................69
Data Memory ..................................................................... 47
General Purpose Registers ....................................... 47
Map for PIC18F1220/1320 Devices ........................... 48
Special Function Registers ........................................ 49
DAW ................................................................................ 210
DC and AC Characteristics
Graphs and Tables .................................................. 269
DC Characteristics ........................................................... 252
Power-Down and Supply Current ............................ 243
Supply Voltage ......................................................... 242
DCFSNZ .......................................................................... 211
DECF ............................................................................... 210
DECFSZ .......................................................................... 211
Demonstration Boards
PICDEM 1 ................................................................ 236
PICDEM 17 .............................................................. 237
PICDEM 18R ........................................................... 237
PICDEM 2 Plus ........................................................ 236
PICDEM 3 ................................................................ 236
PICDEM 4 ................................................................ 236
PICDEM LIN ............................................................ 237
PICDEM USB .......................................................... 237
PICDEM.net Internet/Ethernet ................................. 236
Details on Individual Family Members ................................. 6
Development Support ...................................................... 233
Device Differences ........................................................... 293
Direct Addressing ............................................................... 54
E
Effects of Power Managed Modes on
Various Clock Sources .............................................. 18
Electrical Characteristics .................................................. 239
Enhanced Capture/Compare/PWM (ECCP) .................... 115
Outputs .................................................................... 116
PWM Mode. See PWM (ECCP Module).
Enhanced PWM Mode. See PWM (ECCP Module).
Enhanced Universal Synchronous As ynchr onous
Receiver Transmitter (EUSART) ............................. 131
Equations
16 x 16 Signed Multiplication Algorithm ..................... 72
16 x 16 Unsigned Multiplication Algorithm ................. 72
A/D Minimum Charging Time ................................... 160
Acquisition Time ...................................................... 160
Errata ................................................................................... 4
EUSART
Asynchronous Mode ................................................ 140
12-bit Break Transmit and Receive ................. 146
Associated Registers, Receive ........................ 144
Associated Registers, Transmit ....................... 142
Auto-Wake-up on Sync Break ......................... 145
Receiver .......................................................... 143
Setting up 9-bit Mode with
Address Detect ........................................ 143
Transmitter ....................................................... 140
Baud Rate Generator (BRG) ................................... 135
Associated Registers ....................................... 136
Auto-Baud Rate Detect .................................... 139
Baud Rate Error, Calculating ........................... 135
Baud Rates, Asynchronous Modes ................. 136
High Baud Rate Select (BRGH Bit) ................. 135
Power Managed Mode Operation .................... 135
Sampling .......................................................... 135
Serial Port Enable (SPEN Bit) ................................. 131
© 2006 Microchip Technology Inc. DS39605D-page 299
PIC18F1220/1320
Synchronous Master Mode ......................................148
Associated Registers, Reception .....................151
Associated Registers, Transmit .......................149
Reception .........................................................150
Transmission ....................................................148
Synchronous Slave Mode ........................................152
Associated Registers, Receive ........................153
Associated Registers, Transmit .......................152
Reception .........................................................153
Transmission ....................................................152
Evaluation and Programming Tools .................................237
F
Fail-Safe Clock Monitor ....................................................171
Exiting Operation .....................................................183
Interrupts in Power Managed Modes .......................183
POR or Wake from Sleep ........................................184
WDT During Oscillator Failure .................................182
Fail-Safe Clock Monitor (FSCM ) ......................................182
Fast Register Stack ............................................................44
Firmware Instructions .......................................................191
Flash Program Memory ......................................................57
Associated Registers .................................................65
Control Registers .......................................................58
Erase Sequence ........................................................62
Erasing .......................................................................62
Operation During Code-Protect .................................65
Reading ......................................................................61
Table Latch ................................................................60
Table Pointer ..............................................................60
Boundaries Based on Operation ........................60
Table Pointer Boundaries ..........................................60
Table Reads and Table Writes ..................................57
Write Sequence .........................................................63
Writing to ....................................................................63
Unexpected Termination ....................................65
Write Verify ........................................................65
G
GOTO ...............................................................................212
H
Hardware Multiplier ............................................................71
Introduction ................................................................71
Operation ...................................................................71
Performance Comparison ..........................................71
I
I/O Por ts .............................................................................87
ID Locations ............................................................. 171, 188
INCF .................................................................................212
INCFSZ ............................................................................213
In-Circuit Debugger ..........................................................188
In-Circuit Serial Programming (ICSP) ...................... 171, 188
Indirect Addressing ............................................................54
INDF and FSR Registers ...........................................53
Operation ...................................................................53
Indirect Addressing Operation ............................................54
Indirect File Operand ..........................................................47
INFSNZ ............................................................................213
Initialization Conditions for All Registers ...................... 3638
Instruction Cycle .................................................................45
Instruction Flow/Pipelining .................................................45
Instruction Set .................................................................. 191
ADDLW .................................................................... 197
ADDWF .................................................................... 197
ADDWFC ................................................................. 198
ANDLW .................................................................... 198
ANDWF .................................................................... 199
BC ............................................................................ 199
BCF ......................................................................... 200
BN ............................................................................ 200
BNC ......................................................................... 201
BNN ......................................................................... 201
BNOV ...................................................................... 202
BNZ ......................................................................... 202
BOV ......................................................................... 205
BRA ......................................................................... 203
BSF .......................................................................... 203
BTFSC ..................................................................... 204
BTFSS ..................................................................... 204
BTG ......................................................................... 205
BZ ............................................................................ 206
CALL ........................................................................ 206
CLRF ....................................................................... 207
CLRWDT ................................................................. 207
COMF ...................................................................... 208
CPFSEQ .................................................................. 208
CPFSGT .................................................................. 209
CPFSLT ................................................................... 209
DAW ........................................................................ 210
DCFSNZ .................................................................. 211
DECF ....................................................................... 210
DECFSZ .................................................................. 211
General Format ........................................................ 193
GOTO ...................................................................... 212
INCF ........................................................................ 212
INCFSZ .................................................................... 213
INFSNZ .................................................................... 213
IORLW ..................................................................... 214
IORWF ..................................................................... 214
LFSR ....................................................................... 215
MOVF ...................................................................... 215
MOVFF .................................................................... 216
MOVLB .................................................................... 216
MOVLW ................................................................... 217
MOVWF ................................................................... 217
MULLW .................................................................... 218
MULWF .................................................................... 218
NEGF ....................................................................... 219
NOP ......................................................................... 219
POP ......................................................................... 220
PUSH ....................................................................... 220
RCALL ..................................................................... 221
RESET ..................................................................... 221
RETFIE .................................................................... 222
RETLW .................................................................... 222
RETURN .................................................................. 223
RLCF ....................................................................... 223
RLNCF ..................................................................... 224
RRCF ....................................................................... 224
RRNCF .................................................................... 225
SETF ....................................................................... 225
SLEEP ..................................................................... 226
SUBFWB ................................................................. 226
SUBLW .................................................................... 227
PIC18F1220/1320
DS39605D-page 300 © 2006 Microchip Technology Inc.
SUBWF ....................................................................227
SUBWFB ..................................................................228
SWAPF ....................................................................228
TBLRD .....................................................................229
TBLWT .....................................................................230
TSTFSZ ....................................................................231
XORLW ....................................................................231
XORWF ....................................................................232
Summary Table ........................................................194
INTCON Register
RBIF Bit ......................................................................90
INTCON Registers .............................................................75
Internal Oscillator Block .....................................................14
Adjustment .................................................................14
INTIO Modes ..............................................................14
INTRC Output Frequency ..........................................14
OSCTUNE Register ...................................................14
Internal RC Oscillator
Use with WDT ..........................................................180
Interrupt Sources ..............................................................171
A/D Conversion Complete ........................................159
Capture Complete (CCP) .........................................116
Compare Complete (CCP) .......................................117
Interrupt-on-Change (RB7:RB4) ................................90
INTn Pi n .....................................................................85
PORTB, Interrupt-on-Change ....................................85
TMR0 .........................................................................85
TMR0 Overflow ........................................................101
TMR1 Overflow ........................................................103
TMR2 to PR2 Match .................................................110
TMR2 to PR2 Match (PWM) ............................109, 119
TMR3 Overflow ................................................111, 113
Interrupts ............................................................................73
Enable Bits
(CCP1 IE Bit) ....................................................116
Flag Bits
CCP1 Flag (CCP1IF Bit) ..................................116
CCP1IF Flag (CCP1IF Bit) ...............................117
Interrupt-on-Change (RB7:RB4)
Flag (RBIF Bit) ...........................................90
Logic ...........................................................................74
INTOSC Frequency Drift ....................................................30
IORLW .............................................................................214
IORWF .............................................................................214
IPR Registers .....................................................................82
L
LFSR ................................................................................215
Low-Voltage Detect ..........................................................165
Characteristics .........................................................255
Effects of a Reset .....................................................169
Operation .................................................................168
Current Consumption .......................................169
Reference Voltage Set Point ............................169
Operation During Sleep ............................................169
LVD. See Low-Voltage Detect.
M
Memory Organization .........................................................41
Data Memory ..............................................................47
Program Mem ory .......................................................41
Memory Programm ing Requ irements ..............................254
Migration from Baseline to Enhanced Devices ................294
Migration from High-End to Enhanced Devices ...............295
Migration from Mid-Range to
Enhanced Devices ................................................... 295
MOVF .............................................................................. 215
MOVFF ............................................................................ 216
MOVLB ............................................................................ 216
MOVLW ........................................................................... 217
MOVWF ........................................................................... 217
MPLAB ASM30 Assembler, Linker, Librarian .................. 234
MPLAB ICD 2 In-Circuit Debugger .................................. 235
MPLAB ICE 2000 High-Perf orm ance
Universal In-Circuit Emulator ................................... 235
MPLAB ICE 4000 High-Perf orm ance
Universal In-Circuit Emulator ................................... 235
MPLAB Integrated Development
Environment Software ............................................. 233
MPLAB PM3 Device Pr ogramm er ................................... 235
MPLINK Object Linker/MPL IB Object Librarian ............... 234
MULLW ............................................................................ 218
MULWF ............................................................................ 218
N
NEGF ............................................................................... 219
New Core Features
Multiple Oscillator Options and Features ..................... 5
nanoWatt Technology .................................................. 5
NOP ................................................................................. 219
O
Opcode Field Descriptions ............................................... 192
OPTION_REG Register
PSA Bit .................................................................... 101
T0CS Bit .................................................................. 101
T0PS2: T0 PS0 Bits ................................................... 101
T0SE Bit ................................................................... 101
Oscillator Configuration ...................................................... 11
Crystal/Ceramic Resonator ........................................ 11
EC .............................................................................. 11
ECIO .......................................................................... 11
Extern a l C l o ck In put ................................................... 13
HS .............................................................................. 11
HSPLL ..................................................................11, 12
INTIO1 ....................................................................... 11
INTIO2 ....................................................................... 11
LP .............................................................................. 11
RC .........................................................................11, 13
RCIO .......................................................................... 11
XT .............................................................................. 11
Oscillator Selection .......................................................... 171
Oscillator Start-up Timer (OST) ............................18, 34, 171
Oscillator Switching ............................................................ 15
Oscillator Transiti ons ......................................................... 18
Oscillator, Timer1 ......................................................103, 113
Oscillator, Timer3 ............................................................. 111
Other Special Features ........................................................ 5
P
Packaging ........................................................................ 287
Details ...................................................................... 288
Marking Information ................................................. 287
PICkit 1 Flash Starter Kit .................................................. 237
PICSTART Plus Deve lopment Program mer .................... 236
PIE Registers ..................................................................... 80
© 2006 Microchip Technology Inc. DS39605D-page 301
PIC18F1220/1320
Pin Functions
MCLR/VPP/RA5 ............................................................8
OSC1/CLKI/RA7 ..........................................................8
OSC2/CLKO/RA6 ........................................................8
RA0/AN0 ......................................................................8
RA1/AN1/LVDIN ..........................................................8
RA2/AN2/VREF- ............................................................8
RA3/AN3/VREF+ ...........................................................8
RA4/T0CKI ...................................................................8
RB0/AN4/INT0 .............................................................9
RB1/AN5/TX/CK/INT1 ..................................................9
RB2/P1B/INT2 .............................................................9
RB3/CCP1/P1A ............................................................9
RB4/AN6/RX/DT/KBI0 .................................................9
RB5/PGM/KBI1 ............................................................9
RB6/PGC/T1OSO/T13CKI/P1C/KBI2 ..........................9
RB7/PGD/T1OSI/P1D/KBI3 .........................................9
VDD ...............................................................................9
VSS ...............................................................................9
Pinout I/O Descriptions
PIC18F1220/1320 ........................................................8
PIR Registers .....................................................................78
PLL Lock Time-out .............................................................34
Pointer, FSR .......................................................................53
POP ..................................................................................220
POR. See Power-on Reset.
PORTA
Associated Registers .................................................89
Functions ...................................................................89
LATA Register ............................................................87
PORTA Register ........................................................87
TRISA Register ..........................................................87
PORTB
Associated Registers .................................................98
Functions ...................................................................98
LATB Register ............................................................90
PORTB Register ........................................................90
RB7:RB4 Interrupt-on-Change
Flag (RBIF Bit) ...................................................90
TRISB Register ..........................................................90
Postscaler
Timer2 ......................................................................109
WDTAssignment (PSA Bit) ......................................101
Rate Select (T0PS2:T0PS0 Bits) .....................101
Power Managed Modes .....................................................19
Comparison between Run
and Idle Modes ..................................................20
Entering ......................................................................20
Idle Modes .................................................................21
Multiple Sleep Commands .........................................20
Run Modes .................................................................26
Selecting ....................................................................19
Sleep Mode ................................................................21
Summary (table) ........................................................19
Wake from ..................................................................28
Power-on Reset (POR) .............................................. 34, 171
Power-up Delays ................................................................18
Pow e r-up Timer (PWRT) .......................................18, 34, 171
Prescaler
Capture ....................................................................117
Timer0 ......................................................................101
Assignment (PSA Bit) ......................................101
Rate Select (T0PS2:T0PS0 Bits) .....................101
Timer2 ......................................................................119
PRO MATE II Universal Device Programmer .................. 235
Product Identification System .......................................... 307
Program Counter
PCL Register ............................................................. 44
PCLATH Register ...................................................... 44
PCLATU Register ...................................................... 44
Program Mem ory
Instructions in ............................................................ 46
Interrupt Vector .......................................................... 41
Map and Stack for PIC18F1220 ................................ 41
Map and Stack for PIC18F1320 ................................ 41
Reset Vector .............................................................. 41
Program Verificat ion and Code Protection ...................... 185
Associated Registers ............................................... 185
Configuration Register ............................................. 188
Data EEPROM ......................................................... 188
Program Memory ..................................................... 186
Programm ing, Device Ins tr uctions ................................... 191
PUSH ............................................................................... 220
PUSH and POP Instruc t ions .............................................. 43
PWM (CCP Module)
CCPR1H:CCPR1L Registers ................................... 119
Duty Cycle ............................................................... 119
Example Frequencies/Resolution s .......................... 119
Period ...................................................................... 119
TMR2 to PR 2 M atch .........................................109, 119
PWM (ECCP Module) ...................................................... 119
Associated Registers ............................................... 130
Direction Change in Full-Bridge
Output Mode .................................................... 124
Effects o f a Reset .................................................... 129
Enhanced PWM Auto-Shutdown ............................. 126
Full-Bridge Application Example .............................. 124
Full-Bridge PWM Output
(Active-High) Diagram ..................................... 123
Half-Bridge Output
(Active-High) Diagram ..................................... 122
Half-Bridge Output Mode
Applications Example ...................................... 122
Operation in Low-Power Modes .............................. 129
Output Configurations .............................................. 119
Output Relationships (Active-High) .......................... 120
Output Relationships (Active-Low) .......................... 121
Programmable Dead-Band Delay ............................ 126
PWM Direction Change
(Active-High) Diagram ..................................... 125
PWM Direction Change at Near 100%
Duty Cycle (Active-High) Diagram ................... 125
Setup for PWM Operation ........................................ 129
Start-up Considerations ........................................... 128
Q
Q Clock ............................................................................ 119
R
RAM. See Data Me mory.
RCALL ............................................................................. 221
RCIO Oscillator .................................................................. 13
RCON Register
Bit Status During Initializati on .................................... 35
RCSTA Register
SPEN Bit .................................................................. 131
Register File ....................................................................... 47
Register File Summary .................................................5051
PIC18F1220/1320
DS39605D-page 302 © 2006 Microchip Technology Inc.
Registers
ADCON0 (A/D Control 0) .........................................155
ADCON1 (A/D Control 1) .........................................156
ADCON2 (A/D Control 2) .........................................157
BAUDCTL (Baud Rate Control) ...............................134
CCP1CON (Enhanced CCP1 Control) .....................115
CONFIG1H (Configuration 1 High) ..........................172
CONFIG2H (Configuration 2 High) ..........................174
CONFIG2L (Configuration 2 Low) ............................173
CONFIG3H (Configuration 3 High) ..........................175
CONFIG4L (Configuration 4 Low) ............................175
CONFIG5H (Configuration 5 High) ..........................176
CONFIG5L (Configuration 5 Low) ............................176
CONFIG6H (Configuration 6 High) ..........................177
CONFIG6L (Configuration 6 Low) ............................177
CONFIG7H (Configuration 7 High) ..........................178
CONFIG7L (Configuration 7 Low) ............................178
DEVID1 (Device ID 1) ..............................................179
DEVID2 (Device ID 2) ..............................................179
ECCPAS (ECCP Auto-Shutdown Control) ...............127
EECON1 (Data EEPROM Control 1) ...................59, 68
INTCON (Interrupt Control) ........................................75
INTCON2 (Interrupt Control 2) ...................................76
INTCON3 (Interrupt Control 3) ...................................77
IPR1 (Peripheral Interrupt Priority 1) ..........................82
IPR2 (Peripheral Interrupt Priority 2) ..........................83
LVDCON (LVD Control) ...........................................167
OSCCON (Oscillator Control) ....................................17
OSCTUNE (Oscillator Tuning) ...................................15
PIE1 (Peripheral Interrupt Enable 1) ..........................80
PIE2 (Peripheral Interrupt Enable 2) ..........................81
PIR1 (Peripheral Interrupt
Request (Flag) 1) ...............................................78
PIR2 (Peripheral Interrupt
Request (Flag) 2) ...............................................79
PWM1CON (PWM Configuration) ............................126
RCON (Reset Control) .........................................56, 84
RCSTA (Receive Status and Control) ......................133
Status .........................................................................55
STKPTR (Stack Pointer) ............................................43
T0CON (Timer0 Control) ............................................99
T1CON (Timer 1 Control) .........................................103
T2CON (Timer 2 Control) .........................................109
T3CON (Timer3 Control) ..........................................111
TXSTA (Transmit Status and Control) .....................132
WDTCON (Watchdog Tim er Contro l) .......................180
RESET .............................................................................221
Reset ..........................................................................33, 171
RETFIE ............................................................................222
RETLW .............................................................................222
RETURN ..........................................................................223
Return Address Stack ........................................................42
and Associated Registers ..........................................42
Return Stack Pointer (STKPTR) ........................................42
Revision History ...............................................................293
RLCF ................................................................................223
RLNCF .............................................................................224
RRCF ...............................................................................224
RRNCF .............................................................................225
S
SETF ................................................................................225
SLEEP ..............................................................................226
Sleep
OSC1 and OSC2 Pin States ......................................18
Software Simulator (MPLAB SIM) .................................... 234
Software Simulator (MPLAB SIM30) ................................ 234
Special Event Trigger. See Compare.
Special Features of the CPU ........................................... 171
Configuration Registers ....................................172178
Special Function Registers ................................................ 49
Map ............................................................................ 49
Stack Full/Underflow Resets .............................................. 43
SUBFWB ......................................................................... 226
SUBLW ............................................................................ 227
SUBWF ............................................................................ 227
SUBWFB ......................................................................... 228
SWAPF ............................................................................ 228
T
TABLAT Register ............................................................... 60
Table Pointer Operations (table) ........................................ 60
TBLPTR Register ............................................................... 60
TBLRD ............................................................................. 229
TBLWT ............................................................................. 230
Time-out Sequence ........................................................... 34
Timer0 ................................................................................ 99
16-Bit Mode Timer Reads and Writes ...................... 101
Associated Registers ............................................... 101
Clock Source Edge Select (T0SE Bit ) ..................... 101
Clock Source Sel ect (T0CS Bit) ............................... 101
Operation ................................................................. 101
Overflow Interrupt .................................................... 101
Prescaler. See Prescaler, Timer0.
Switching Prescaler Assignment ............................. 101
Timer1 .............................................................................. 103
16-Bit Read/Write Mode .......................................... 106
Associated Registers ............................................... 108
Interrupt ................................................................... 106
Operation ................................................................. 104
Oscillator ...........................................................103, 105
Layout Considerations ..................................... 106
Overflow Interrupt .................................................... 103
Resetting, Using a Special Event
Trigger Output (CCP) ....................................... 106
Special Event Trigger (CCP) ................................... 117
TMR1H Register ...................................................... 103
TMR1L Register ....................................................... 103
Use as a Real-Time Clock ....................................... 107
Timer2 .............................................................................. 109
Associated Registers ............................................... 110
Operation ................................................................. 109
Output ...................................................................... 110
Postscaler. See Postscaler, Timer2.
PR2 Register ....................................................109, 119
Prescaler. See Prescaler, Timer2.
TMR2 Register ......................................................... 109
TMR2 to PR 2 Match Interrupt ...................109, 110, 119
Timer3 .............................................................................. 111
Associated Registers ............................................... 113
Operation ................................................................. 112
Oscillator ...........................................................111, 113
Overflow Interrupt .............................................111, 113
Special Event Trigger (CCP) ................................... 113
TMR3H Register ...................................................... 111
TMR3L Register ....................................................... 111
© 2006 Microchip Technology Inc. DS39605D-page 303
PIC18F1220/1320
Timing Diagrams
A/D Conversion ........................................................267
Asynchronous Reception .........................................144
Asynchronous Transmission ....................................141
Asynchronous Transmission
(Back to Back) ..................................................142
Auto-Wake-up Bit (WUE) During
Normal Operation .............................................145
Auto-Wake-up Bit (WUE) During Sleep ...................145
Brown-out Reset (BOR) ...........................................262
Capture/Compare/PWM (All CCP Modules) ............264
CLKO and I/O ..........................................................261
Clock/Instruction Cycle ..............................................45
EUSART Synchronous Receiv e
(Master/Slave) ..................................................266
EUSART SynchronousT rans miss ion
(Master/Slave) ..................................................265
External Clock (All Modes Except PLL) ...................259
Fail-Safe Clock Monitor ............................................183
Low-Voltage Detect ..................................................168
Low-Voltage Detect Characteristics .........................255
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .....................................128
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) .....................................128
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST) and
Pow e r-up Timer (PWRT) .................................262
Send Break Character Sequenc e ............................147
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................40
Synchronous Reception
(Master Mode, SREN) ......................................150
Synchronous Transmission ......................................148
Synchronous Transmission
(Through TXEN) ...............................................149
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) ...........................................40
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 .......................39
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 .......................39
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise TPWRT) ..............39
Timer0 and Timer1 External Clock ..........................263
Transition for Entry to SEC_IDLE Mode ....................24
Transition for Entry to SEC_RUN Mode ....................26
Transition for Entry to Sleep Mode ............................22
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 181
Transition for Wake from PRI_IDLE Mode ................ 23
Transition for Wake from RC_RUN Mode
(RC_RUN to PRI_RUN) .................................... 25
Transition for Wake from SEC_RUN Mode
(HSPLL) ............................................................. 24
Transition for Wake from Sleep (HSPLL) .................. 22
Transition to PRI_IDLE Mode .................................... 23
Transition to RC_IDLE Mode ..................................... 25
Transition to RC_RUN Mode ..................................... 27
Timing Diagrams and Specifications ............................... 259
Capture/Compare/PWM Requirements
(All CCP Modules) ........................................... 265
CLKO and I/O Requirements ................................... 261
EUSART Synchronous Receive
Requirements .................................................. 266
EUSART Synchronous Transmission
Requirements .................................................. 265
External Clock Requirements .................................. 259
Internal RC Accuracy ............................................... 260
PLL Clock, HS/HSPLL Mode
(VDD = 4.2V to 5.5V) ........................................ 260
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and
Brown-out Reset Requirements ...................... 263
Timer0 and Timer1 External Clock
Requirements .................................................. 264
Top-of-Stack Ac cess .......................................................... 42
TSTFSZ ........................................................................... 231
Two-Speed Start-up ..................................................171, 181
Two-Word Instructions ....................................................... 46
Example Cases .......................................................... 46
TXSTA Register
BRGH Bit ................................................................. 135
W
Watchdog Timer (WDT) ............................................171, 180
Associated Registers ............................................... 181
Control Register ....................................................... 180
During Oscillator Failure .......................................... 182
Programming Considerations .................................. 180
WWW, On-Line Support ...................................................... 4
X
XORLW ............................................................................ 231
XORWF ........................................................................... 232
PIC18F1220/1320
DS39605D-page 304 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. Advance Information DS39605D-page 305
PIC18F1220/1320
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PIC18F1220/1320
DS39605D-page 306 Advance Information © 2006 Microchip Technology Inc.
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DS39605DPIC18F1220/1320
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© 2006 Microchip Technology Inc. DS39605D-page 307
PIC18F1220/1320
PIC18F1220/1320 PR ODUCT IDENTIFICAT ION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device PIC18F1220/1320(1),
PIC18F1220/1320T(2);
VDD range 4.2V to 5.5V
PIC18LF1220/1320(1),
PIC18LF1220/1320T(2);
VDD range 2.5V to 5.5V
Temperature
Range I=-40°C to +85°C(Industrial)
E=-40°C to +125°C (Extended)
Package SO = SOIC SS = SSOP
P=PDIP ML=QFN
Pattern QTP, SQTP, Code or Special Requirements
(blank otherwise)
Examples:
a) PIC18LF1320-I/P 301 = Industrial
temp., PDIP package, Extended
VDD limits, QTP pattern #301.
b) PIC18LF1220-I/SO = Industrial
temp., SOIC package, Extended
VDD limits.
Note 1: F = Standard Voltage range
LF = Wide Voltage Range
2: T = in tape and reel – SOIC
package only
DS39605D-page 308 © 2006 Microchip Technology Inc.
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