TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Very Low Power Consumption
1 mW Typ at VDD = 5 V
D
Capable of Operation in Astable Mode
D
CMOS Output Capable of Swinging Rail
to Rail
D
High Output-Current Capability
Sink 100 mA Typ
Source 10 mA Typ
D
Output Fully Compatible With CMOS, TTL,
and MOS
D
Low Supply Current Reduces Spikes
During Output Transitions
D
Single-Supply Operation From 1 V to 15 V
D
Functionally Interchangeable With the
NE555; Has Same Pinout
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015.2
description
The TLC551 is a monolithic timing circuit
fabricated using the TI LinCMOSprocess. The
timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Compared
to the NE555 timer , this device uses smaller timing capacitors because of its high input impedance. As a result,
more accurate time delays and oscillations are possible. Power consumption is low across the full range of
power supply voltage.
Like the NE555, the TLC551 has a trigger level equal to approximately one-third of the supply voltage and a
threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of
the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is
set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the
threshold level, the flip-flop is reset and the output is low . The reset input (RESET) can override all other inputs
and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low.
Whenever the output is low, a low-impedance path is provided between DISCH and GND. All unused inputs
should be tied to an appropriate logic level to prevent false triggering.
While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC551 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE555.
The TLC551C is characterized for operation from 0°C to 70°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either supply voltage or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies
available from Texas Instruments.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
D, DB, P, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
GND
TRIG
OUT
RESET
VDD
DISCH
THRES
CONT
GND
RESET
CONT
VDD
1
T
HRES
TRIG
R
R
R
DISCH
OUT
S
R
R1
RESET can override TRIG, which can override THRES.
5
6
2
1
7
3
f
unctional block diagram
4
8
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044A – FEBRUAR Y 1984 – REVISED MAY 1997
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
TAVDD
RANGE
SMALL
OUTLINE
(D)
SSOP
(DB) PLASTIC DIP
(P) TSSOP
(PW)
CHIP FORM
(Y)
0°C to 70°C1 V to 16 V TLC551CD TLC551CDBLE TLC551CP TLC551CPWLE TLC551Y
The D package is available taped and reeled. Add the suffix R (e.g., TLC551CDR). The DB and PW packages are only
available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TLC551CDBLE). Chips are
tested at 25°C.
FUNCTION TABLE
RESET
VOLTAGE†TRIGGER
VOLTAGE†THRESHOLD
VOLTAGE†OUTPUT DISCHARGE
SWITCH
<MIN Irrelevant Irrelevant Low On
>MAX <MIN Irrelevant High Off
>MAX >MAX >MAX Low On
>MAX >MAX <MIN As previously established
†For conditions shown as MIN or MAX, use the appropriate value specified under
electrical characteristics.
TLC551Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC551. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
50
64
GND
RESETCONT
VDD
1
THRES
TRIG
R
R
R
DISCH
OUT
S
R
R1
RESET can override TRIG, which can override THRES.
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (1) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
(5)
(6)
(2)
(1)
(7)
(4)
(8)
(3)
TLC551, TLC551Y
LinCMOSTM TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•3
equivalent schematic
THRES
CONT
TRIG RESET
VDD
DISCH
OUT
GND
Transistors
COMPONENT COUNT
Resistors 39
5
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (any input) –0.3 to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sink current, discharge or output 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source current, output, IO 15 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltage values are with respect to network GND.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING
D
DB
P
PW
725 mW
525 mW
1000 mW
525 mW
5.8 mW/°C
4.2 mW/°C
8.0 mW/°C
4.2 mW/°C
464 mW
336 mW
640 mW
336 mW
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD 1 15 V
Operating free-air temperature range, TA0 70 °C
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 1 V
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VIT
Threshold voltage
25°C 0.475 0.67 0.85
V
V
IT
Threshold
v
oltage
Full range 0.45 0.875
V
IIT
Threshold current
25°C 10 p
A
I
IT
Threshold
c
u
rrent
70°C 75
pA
VI(TRIG)
Trigger voltage
25°C 0.15 0.33 0.425
V
V
I(TRIG)
Trigger
v
oltage
Full range 0.1 0.45
V
II(TRIG)
Trigger current
25°C 10 p
A
I
I(TRIG)
Trigger
c
u
rrent
70°C 75
pA
VI(RESET)
Reset voltage
25°C 0.4 0.7 1
V
V
I(RESET)
Reset
v
oltage
Full range 0.3 1
V
II(RESET)
Reset current
25°C 10 p
A
I
I(RESET)
Reset
c
u
rrent
70°C 75
pA
Control voltage (open circuit) as a percentage of
supply voltage 70°C 66.7%
Discharge switch on stage voltage
IOL = 100 µA
25°C 0.02 0.15
V
Discharge
s
w
itch
on
-
stage
v
oltage
I
OL =
100
µ
A
Full range 0.2
V
Discharge switch off stage voltage
25°C 0.1
nA
Discharge
s
w
itch
off
-
stage
v
oltage
70°C 0.5
nA
VOH
High level out
p
ut voltage
IOH =10µA
25°C 0.6 0.98
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
I
OH = –
10
µ
A
Full range 0.6
V
VOL
Low level out
p
ut voltage
IOL = 100 µA
25°C 0.03 0.2
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
I
OL =
100
µ
A
Full range 0.25
V
IDD
Su
pp
ly current
See Note 2
25°C 15 100
µA
I
DD
S
u
ppl
y
c
u
rrent
See
Note
2
Full range 150 µ
A
†Full range is 0°C to 70°C.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 2 V
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VIT
Threshold voltage
25°C 0.95 1.33 1.65
V
IT
Threshold
v
oltage
Full range 0.85 1.75
IIT
Threshold current
25°C 10 p
I
IT
Threshold
c
u
rrent
70°C 75
VI(TRIG)
Trigger voltage
25°C 0.4 0.67 0.95
V
I(TRIG)
Trigger
v
oltage
Full range 0.3 1.05
II(TRIG)
Trigger current
25°C 10 p
I
I(TRIG)
Trigger
c
u
rrent
70°C 75
VI(RESET)
Reset voltage
25°C 0.4 1.1 1.5
V
I(RESET)
Reset
v
oltage
Full range 0.3 1.8
II(RESET)
Reset current
25°C 10 p
I
I(RESET)
Reset
c
u
rrent
70°C 75
Control voltage (open circuit) as a percentage of
supply voltage 70°C 66.7%
Discharge switch on stage voltage
IOL =1mA
25°C 0.03 0.2
Discharge
s
w
itch
on
-
stage
v
oltage
I
OL =
1
mA
Full range 0.25
Discharge switch off stage voltage
25°C 0.1
Discharge
s
w
itch
off
-
stage
v
oltage
70°C 0.5
VOH
High level out
p
ut voltage
IOH = 300 µA
25°C 1.5 1.9
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
I
OH = –
300
µ
A
Full range 1.5
VOL
Low level out
p
ut voltage
IOL =1mA
25°C 0.07 0.3
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
I
OL =
1
mA
Full range 0.35
IDD
Su
pp
ly current
See Note 2
25°C 65 250
I
DD
S
u
ppl
y
c
u
rrent
See
Note
2
Full range 400 µ
†Full range is 0°C to 70°C.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VIT
Threshold voltage
25°C 2.8 3.3 3.8
V
V
IT
Threshold
v
oltage
Full range 2.7 3.9
V
IIT
Threshold current
25°C 10 p
A
I
IT
Threshold
c
u
rrent
70°C 75
pA
VI(TRIG)
Trigger voltage
25°C 1.36 1.66 1.96
V
V
I(TRIG)
Trigger
v
oltage
Full range 1.26 2.06
V
II(TRIG)
Trigger current
25°C 10 p
A
I
I(TRIG)
Trigger
c
u
rrent
70°C 75
pA
VI(RESET)
Reset voltage
25°C 0.4 1.1 1.5
V
V
I(RESET)
Reset
v
oltage
Full range 0.3 1.8
V
II(RESET)
Reset current
25°C 10 p
A
I
I(RESET)
Reset
c
u
rrent
70°C 75
pA
Control voltage (open circuit) as a percentage of
supply voltage 70°C 66.7%
Discharge switch on stage voltage
IOL =10mA
25°C 0.14 0.5
V
Discharge
s
w
itch
on
-
stage
v
oltage
I
OL =
10
mA
Full range 0.6
V
Discharge switch off stage voltage
25°C 0.1
nA
Discharge
s
w
itch
off
-
stage
v
oltage
70°C 0.5
nA
VOH
High level out
p
ut voltage
IOH =1mA
25°C 4.1 4.8
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
I
OH = –
1
mA
Full range 4.1
V
IOL =8mA
25°C 0.21 0.4
I
OL =
8
mA
Full range 0.5
VOL
Low level out
p
ut voltage
IOL =5mA
25°C 0.13 0.3
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
I
OL =
5
mA
Full range 0.4
V
IOL =32mA
25°C 0.08 0.3
I
OL =
3
.
2
mA
Full range 0.35
IDD
Su
pp
ly current
See Note 2
25°C 170 350
µA
I
DD
S
u
ppl
y
c
u
rrent
See
Note
2
Full range 500 µ
A
†Full range is 0°C to 70°C.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 15 V
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VIT
Threshold voltage
25°C 9.45 10.55
V
IT
Threshold
v
oltage
Full range 9.35 10.65
IIT
Threshold current
25°C 10 p
I
IT
Threshold
c
u
rrent
70°C 75
VI(TRIG)
Trigger voltage
25°C 4.65 5 5.35
V
I(TRIG)
Trigger
v
oltage
Full range 4.55 5.45
II(TRIG)
Trigger current
25°C 10 p
I
I(TRIG)
Trigger
c
u
rrent
70°C 75
VI(RESET)
Reset voltage
25°C 0.4 1.1 1.5
V
I(RESET)
Reset
v
oltage
Full range 0.3 1.8
II(RESET)
Reset current
25°C 10 p
I
I(RESET)
Reset
c
u
rrent
70°C 75
Control voltage (open circuit) as a percentage of
supply voltage 70°C 66.7%
Discharge switch on stage voltage
IOL = 100 mA
25°C 0.77 1.7
Discharge
s
w
itch
on
-
stage
v
oltage
I
OL =
100
mA
Full range 1.8
Discharge switch off stage voltage
25°C 0.1
Discharge
s
w
itch
off
-
stage
v
oltage
70°C 0.5
IOH =10mA
25°C 12.5 14.2
I
OH = –
10
mA
Full range 12.5
VOH
High level out
p
ut voltage
IOH =5mA
25°C 13.5 14.6
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
I
OH = –
5
mA
Full range 13.5
IOH =1mA
25°C 14.2 14.9
I
OH = –
1
mA
Full range 14.2
IOL = 100 mA
25°C 1.28 3.2
I
OL =
100
mA
Full range 3.6
VOL
Low level out
p
ut voltage
IOL =50mA
25°C 0.63 1
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
I
OL =
50
mA
Full range 1.3
IOL =10mA
25°C 0.12 0.3
I
OL =
10
mA
Full range 0.4
IDD
Su
pp
ly current
See Note 2
25°C 360 600
I
DD
S
u
ppl
y
c
u
rrent
See
Note
2
Full range 800 µ
†Full range is 0°C to 70°C.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
operating characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Initial error of timing interval‡V
DD
= 5 V to 15 V, R
A
= R
B
= 1 kΩ to 100 kΩ,1% 3%
Supply voltage sensitivity of timing interval
DD ,
CT = 0.1 µF,
AB ,
See Note 3 0.1 0.5 %/V
trRise time, output pulse
RL=10MΩ
CL=10
p
F
20 75
tfFall time, output pulse
R
L =
10
MΩ
,
C
L =
10
pF
15 60
fmax Maximum frequency in astable mode RA = 470 Ω,
CT = 200 pF RB = 200 Ω,
See Note 3 1.2 1.8 MHz
‡Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process
run.
NOTE 3: RA, RB, and CT are as defined in Figure 3.
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at VDD = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT Threshold voltage 2.8 3.3 3.8 V
IIT Threshold current 10 pA
VI(TRIG) T rigger voltage 1.36 1.66 1.96 V
II(TRIG) T rigger current 10 pA
VI(RESET) Reset voltage 0.4 1.1 1.5 V
II(RESET) Reset current 10 pA
Control voltage (open circuit) as a percentage of supply voltage 66.7%
Discharge switch on-state voltage IOL = 10 mA 0.14 0.5 V
Discharge switch off-state current 0.1 nA
VOH High-level output voltage IOH = – 1 mA 4.1 4.8 V
IOL = 8 mA 0.21 0.4
VOL Low-level output voltage IOL = 5 mA 0.13 0.3 V
IOL = 3.2 mA 0.08 0.3
IDD Supply current See Note 2 170 350 µA
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
TYPICAL CHARACTERISTICS
Figure 1
2
1025 75
Discharge Switch On-State Resistance –
DISCHARGE SWITCH ON-STATE RESISTANCE
vs
FREE-AIR TEMPERATURE
50 100
10
4
20
100
40
7
70
Ω
TA – Free-Air Temperature – °C
VDD = 2 V, IO = 1 mA
VDD = 5 V, IO = 10 mA
VDD = 15 V, IO = 100 mA
Figure 2
100
00 2 4 6 8 12 16
PROPAGATION DELAY TIMES (TO DISCHARGE
OUTPUT FROM TRIGGER AND THRESHOLD
SHORTED TOGETHER)
vs
SUPPLY VOLTAGE
10 14
400
200
500
600
300
VDD – Supply Voltage – V 2018
PHL
t,
PLH
t – Propagation Delay Times – ns
tPLH‡
tPHL
IO(on) ≥1 mA
CL ≈0
TA = 25°C
‡The effects of the load resistance on these values must be
taken into account separately.
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
0.1 µF
0.1 µF
CT
CL
RL
Output
RB
RA
GND
TRIG
THRES
RESET
DISCH
CONT VDD
OUT
VDD
2/3 VDD
1/3 VDD
GND
tPHL
tPLH
tc(H) tc(L)
CIRCUIT TRIGGER AND THRESHOLD VOLTAGE WAVEFORM
TLC551
3
85
4
7
6
2
1
VDD
Figure 3. Astable Operation
Connecting TRIG to THRES, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor CT
charges through RA and RB to the threshold voltage level (approximately 0.67 VDD) and then discharges through RB
only to the value of the trigger voltage level (approximately 0.33 VDD). The output is high during the charging cycle
(tc(H)) and low during the discharge cycle (tc(L)). The duty cycle is controlled by the values of RA, and RB, and CT, as
shown in the equations below.
tc(H)
[
CT(RA
)
RB)In2 (In2
+
0.693)
tc(L)
[
CTRBIn 2
Period
+
tc(H)
)
tc(L)
[
CT(RA
)
2RB)In2
Output driver duty cycle
+
tc(L)
tc(H)
)
tc(L)
[
1– RB
RA
)
2RB
Output waveform duty cycle
+
tc(H)
tc(H)
)
tc(L)
[
RB
RA
)
2RB
The 0.1-µF capacitor at CONT in Figure 3 decreases the period by about 10%.
The formulas shown above do not allow for any propagation delay times from TRIG and THRES to DISCH. These
delay times add directly to the period and create differences between calculated and actual values that increase with
frequency. In addition, the internal on-state resistance ron during discharge adds to RB to provide another source of
timing error in the calculation when RB is very low or ron is very high.
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
The equations below provide better agreement with measured values.
tc(H)
+
CT(RA
)
RB)In
ƪ
3–exp
ǒ
–tPLH
CT(RB
)
ron)
Ǔƫ)
tPHL
tc(L)
+
CT(RB
)
ron)In
ƪ
3–exp
ǒ
–tPHL
CT(RA
)
RB)
Ǔƫ)
tPLH
These equations and those given earlier are similar in that a time constant is multiplied by the logarithm of a number
or function. The limit values of the logarithmic terms must be between In 2 at low frequencies and In 3 at extremely
high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic terms can be substituted
with good results. Duty cycles less than 50% tc(H)
tc(H)
)
tc(L) require that tc(H)
tc(L) <1 and possibly RA ≤ ron. These
conditions can be difficult to obtain.
In monostable applications, the trip point of the trigger input can be set by a voltage applied to CONT . An input voltage
between 10% and 80% of the supply voltage from a resistor divider with at least 500-µA bias provides good results.
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040065 /C 10/95
28 PIN SHOWN
Gage Plane
8,20
7,40
0,15 NOM
0,63
1,03
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–8°
0,10
3,30
8
2,70
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE
4040082/B 03/95
0.310 (7,87)
0.290 (7,37)
0.010 (0,25) NOM
0.400 (10,60)
0.355 (9,02)
58
41
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54) 0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040064/E 08/96
14 PIN SHOWN
Seating Plane
0,05 MIN
1,20 MAX
1
A
7
14
0,19
4,50
4,30
8
6,20
6,60
0,30
0,75
0,50
0,25
Gage Plane
0,15 NOM
0,65 M
0,10
0°–8°
0,10
PINS **
A MIN
A MAX
DIM
2,90
3,10
8
4,90
5,10
14
6,60
6,404,90
5,10
16
7,70
20
7,90
24
9,60
9,80
28
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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