Preliminary I] CATALYST SEMICONODUCTEaR CAT28LV64 64K-Bit CMOS E?PROM FEATURES @ 3.0V to 3.6 V Supply m Read Access Times: 250/300/350ns @ Low Power CMOS Dissipation: Active: 8 mA Max. Standby: 100 |1A Max. # Simple Write Operation: On-Chip Address and Data Latches Self-Timed Write Cycle with Auto-Clear @ Fast Write Cycle Time: - 5ms Max. = Commercial and industrial Temperature Ranges m CMOS and TTL Compatible //O @ Automatic Page Write Operation: ~ 1 to 32 Bytes in 5ms Page Load Timer # End of Write Detection: - Toggle Bit - DATA Polling @ Hardware and Software Write Protection 100,000 Program/Erase Cycles @ 100 Year Data Retention DESCRIPTION The CAT28LV64 is a low voltage, low power, CMOS EPROM organized as 8K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and Vcc power up/down write protection eliminate addi- tional timing and protection hardware. DATA Polling and Toggle status bit signal the start and end of the self- timed write cycle. Additionally, the CAT28LV64 features hardware and software write protection. The CAT28LV64 is manufactured using Catalysts ad- vanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP, TSOP and SOIC or 32-pin PLCC and TSOP packages. BLOCK DIAGRAM ADDR. BUFFER ROW 8,192 x8 As-A 2PROM sz DECODER & LATCHES PRON INADVERTENT HIGH VOLTAGE ! Yoo WRITE GENERATOR ISTE. PROTECTION a OE ____ +] CONTROL We ____+| LOGIC ar! VO BUFFERS DATA POLLING | | TIMER AND 1 TOGGLE BIT WOpulO7 107 tomo] coun DECODER 5004 FHO Fo2 1996 by Catalyst Semiconductor, inc. Characteristics subject to change without notice 8-51CAT28LV64 Preliminary PIN CONFIGURATION PIN FUNCTIONS DIP Package (P) soic Package (J, K) Pin Name Function Ne Cet 28 voc NC Cet 28 FI Voc Ao-At2 Address Inputs Aid2 2DWwe Aj2C{2 27 FI] WE A A7 C3 26 [9 NC VOo-V/O7 Data Inputs/Outputs 73 26 FNC _ Ag] 4 25 Ag Agl}4 25 FI Ag CE Chip Enable A515 24 [1 Ag AsC{5 24 Fy Ag = AgC)6 =. a3 Ay AgC46 23 6 An OE Output Enable AgC]7 22 FOE a a PS ne WE Write Enable AoC1s 21M Ain 2 10 Vi . -6 V Suppl Arc 9 20 GE Ai C19 20 [> CE cc 3.0 to 3. pply Ag] 10 19 [voz ion " te J Won Vss Ground VOpC] 11 18 F) VOg 0 PS 6 inne vO, 12 17 19) v5 voy i 120 17 Fi] Ws NG No Connect Woot] 13 16 1 WO, WO2C{ 13 16 = VO4 Vss 4 14 15 F103 Vsg CL 14 15 WO3 TSOP Top View (8mm x 14mm) (T14) PLCC Package (N) TSOP Top View (8mm x 20mm) (T) rn +00 O|S 9 <q22>5/3 2 Ag Gf10 32 HS Ag A, coe 313 Ay 4 3 2 1 323130 Ag 3 30 FP As 297] Ag VOp Hr 4 29 FS Ag 2D A VO, 15 28 PI Az 37 9 Oz H6 273 Aig Py Ay NC 17 26 P= NC 26 (7) NC Vss 18 25 FS NC TOP VIEW 2517 OE NC C19 cc 10 24 P A VO3 = 10 23 NC A10 vO, 11 22 bo WE 237 Ce VOg 4 12 213 NC 12 22 [7 vO7 VOg (2 13 20 A Ag 19 24 ry V6 VO7 Cry 14 19 FO Ag 14 15 16 17 18 19 20 CECH 15 18 FA Any Ato [0116 17 Fr OE - NOOO OT Hw QQvzZge9 5084 FHD Fot TSOP Top View (8mm x 13.4mm) (113) OE Mrf10 28 FO Ajo Aq, Coe 27 CCE Ag C43 26 PO 07 Ag O44 25 FO Og NC C45 24 Fr 1/05 WE 16 23 04 Voc (X47 22 Fr 04 Nc [oe 21 GND Ai2 M19 20 VO2 A7 410 19 Fc3 vo, Ag Co 18 E53 #09 moos eho a cry 1 Ag Cr4t4 15 FT Ag 28LV64 FO 8-52Preliminary CAT28LV64 MODE SELECTION Mode CE WE OE vo Power Read L H L Dout ACTIVE Byte Write (WE Controlled) L VS H Din ACTIVE Byte Write (CE Controlled) VS L H Din ACTIVE Standby, and Write Inhibit H X xX High-Z STANDBY Read and Write Inhibit Xx H H High-Z ACTIVE CAPACITANCE Ta = 25C, f = 1.0 MHz Symbol Test Max. Units Conditions Cryo Input/Output Capacitance pF Vvo = OV Cw) Input Capacitance pF Vin = OV ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ~55C to +125C Stresses above those listed under Absolute Maximum Storage Temperature 0... ee ~65C to +150C Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation Voltage on Any Pin with of the device at these or any other conditions outside of Respect to Ground ........... -2.0V to +Voc + 2.0V those listed in the operational sections of this specifica- Vec with Respect to Ground ............4.. -2.0V to +7.0V tion is not implied. Exposure to any absolute maximum Package Power Dissipation rating for extended periods may affect device perfor- Capability (Ta = 25C) oc. eccceecescceseseceeeee 1.0W mance and reliability. Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current ooo. eee 100 mA RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Test Method Nenp!) Endurance 104 or 105 Cycles/Byte MIL-STD-883, Test Method 1033 Tor") Data Retention 100 Years MiL-STD-883, Test Method 1008 Vzap\) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 IerH4)} | Latch-Up 100 mA JEDEC Standard 17 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum OC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is Vcc +0.5V, which may overshoot to Vcc +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to Voc +1V. 8-53CAT28LV64 Preliminary D.C. OPERATING CHARACTERISTICS Vee = 3.0V to 3.6V, unless otherwise specified. Limits Symbol Parameter Min. | Typ. Max. /|Units Test Conditions lec Vec Current (Operating, TTL) 8 mA CE = OE = Vit, f = 1/trc min, All /Os Open Isact?) Vcc Current (Standby, CMOS) 100 wA | CE=Vinc, All /Os Open fut Input Leakage Current -1 1 HA | Vin =GND to Vcc ILo Output Leakage Current -5 5 pA Vout = GND to Vcc, CE =Vin Vin) High Level Input Voltage 2 Voc +0.3] V ViL Low Level Input Voltage 0.3 0.6 Vv Vou High Level Output Voitage 2 Vv lon = 100nA VoL Low Level Output Voltage 0.3 Vv lo. = 1.0mMA Vwi Write Inhibit Voltage 2 Vv Note: (1) Vide = Voc -0.3V to Voc +0.3V. A.C. CHARACTERISTICS, Read Cycle Voc = 3.0V to 3.6V, unless otherwise specified. 28LV64-25 28LV64-30 28LV64-35 Symbol Parameter Min. Max. | Min. Max. | Min. Max. | Units tre Read Cycle Time 250 300 350 ns tce CE Access Time 250 300 350 ns taa Address Access Time 250 300 350 ns toe OE Access Time 100 150 150 ns tz) CE Low to Active Output ns toz') OE Low to Active Output 0 ns tuz((2)_| CE High to High-Z Output 55 60 60 ns tonz(X2) | OE High to High-Z Output 55 60 60 ns tou!) Output Hold from Address Change 0 0 0 ns Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. {2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. 8-54Preliminary CAT28LV64 Figure 1. A.C. Testing Input/Output Waveform(1) Vee - 0.3V Z0V INPUT PULSE LEVELS xX REFERENCE POINTS 0.0V O6V Note: (1) Input rise and fall times (10% and 90%) < 10 ns. Figure 2. A.C. Testing Load Circuit (example) Device Under OUTPUT Test 1.9K L Cy INCLUDES JIG CAPACITANCE C__ = 100 pF 5096 FHD Fo4 A.C. CHARACTERISTICS, Write Cycle Vec = 3.0V to 3.6V, unless otherwise specified. 28LV64-25 28LV64-30 28LV64-35 Symbol Parameter Min. Max. | Min. Max. | Min. Max. | Units two Write Cycle Time 5 5 5 ms tas Address Setup Time 0 0 0 ns tan Address Hold Time 100 100 100 ns tcs CE Setup Time ) 0 0 ns ton TE Hold Time ) 0 0 ns tow) CE Pulse Time 150 150 150 ns toes OE Setup Time 10 10 10 ns toeH OE Hold Time 10 10 10 ns Swe) WE Pulse Width 150 150 150 ns tos Data Setup Time 100 100 100 ns ton Data Hold Time 0 0 0 ns tint!) Write Inhibit Period After Power-up 5 10 5 10 5 10 ms tarc(M@) Byte Load Cycle Time 0.1 100 0.1 100 | 0.1 100 ps Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Awrite pulse of less than 20ns duration will not initiate a write cycle. (3) A timer of duration taic max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tg.c max. stops the timer. 8-55CAT28LV64 Preliminary DEVICE OPERATION Read Data stored in the CAT28LV64 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architec- ture can be used to eliminate bus contention in asystem environment. Byte Write Awrite cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 5 ms. Figure 3. Read Cycle /+- trac | ADDRESS X x }~<__. to= _| cE ) _ }______ OE } VIH WE +_ Lz tOHZ>| toLz ld toH [- tz DATA OUT HIGH-2 DATA VALID DATA VALID b botan 26LV84 Foe Figure 4. Byte Write Cycle [WE Controlled] a tas >1+-_taH cs ADDRESS XXX XAXAXAXXAAX he tCH 7 4 cal we WA iiiiny toEH HIGH-Z , io + terc _ DATA IN AX DATA VALID XA CX 5006 FHD FO6 8-56Preliminary CAT28LV64 Page Write The page write mode of the CAT28LV64 (essentially an extended BYTE WRITE mode) allows from 1 to 32 bytes of data to be programmed within a single E7PROM write cycle. This effectively reduces the byte-write time by a factor of 32. Following an initial WRITE operation (WE pulsed low, for twp, and then high) the page write mode can begin by issuing sequential WE pulses, which load the address and data bytes into a 32 byte temporary buffer. The page address where data is to be written, specified by bits As to A1z, is latched on the last falling edge of WE. Each byte within the page is defined by address bits Ao to Ag (which can be toaded in any order) during the first and subsequent write cycles. Each successive byte load cycle must begin within tec max of the rising edge of the preceding WE pulse. There is no page write window limitation as long as WE is pulsed low within tatc max. Upon completion of the page write sequence, WE must stay high a minimum of tsic max for the internal auto- matic program cycle to commence. This programming cycle consists of an erase cycle, which erases any data that existed in each addressed ceil, and a write cycle, which writes new data back into the cell. A page write will only write data to the locations that were addressed and will not rewrite the entire page. Figure 5. Byte Write Cycle [CE Controlled] i taH ADDRESS AXA KARR RRKKRX t tBLC+| c.)87F) OS / Wy A * TTT WW nyy os Ht tOES tcH - ; TARNNANAN EN DATA OUT DATA IN DATA VALID a7 AXXXXAMKAK 'DH 5094 FHO FO7 Figure 6. Page Mode Write Cycle OE LLL L/ se \_/ (7 [TJ [Ts [TDs twp tBLC WE |L__ ADDRESS x x x x two , vo LAST BYTE BYTEO BYTE1 BYTE2 BYTEn BYTEn+1 BYTE n+2 5096 FHO F10 8-57CAT28LV64 Preliminary DATA Polling DATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/Oo-I/Og are indeterminate) until the programming cycle is com- plete. Upon completion of the self-timed write cycle, all 1/O's will output true data during a read cycle. Toggle Bit In addition to the DATA Polling feature, the device offers an additional method for determining the completion of a write cycle. While a write cycle is in progress, reading data from the device will result in /Og toggling between one and zero. However, once the write is complete, I/Os stops toggling and valid data can be read from the device. Figure 7. DATA Polling TFN TFN OT T*TN _X - t!OEH le toe na OE | of N\ < two | vO7 DIN =X Dout =X s{ Dour = x) 5094 FHD F11 zi Figure 8. Toggle Bit WE CE \ / {OEH OE Og r Note: (1) Beginning and ending state of i/Og is indeterminate. _ {, 5 , 7 nnn aa $$ two f (i) j \ VS LH >] 28LV64 FI 8-58Preliminary HARDWARE DATA PROTECTION The foltowing is a list of hardware data protection fea- tures that are incorporated into the CAT28LV64. (1) Vcc sense provides for write protection when Vcc falls below 2.0V min. (2) Apower on delay mechanism, tinit (see AC charac- teristics), provides a 5 to 10 ms delay before a write sequence, after Vcc has reached 2.40V min. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high. CAT28LV64 (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. SOFTWARE DATA PROTECTION The CAT28LV64 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write canbe performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28LV64 is in the standard operating mode). Figure 9. Write Sequence for Activating Software Data Protection WRITE DATA: AA ADDRESS: 1555 WRITE DATA: 55 ADDRESS: OAAA WRITE DATA: AO ADDRESS: 1555 SOFTWARE DATA PROTECTION ACTIVATED WRITE DATA: xx TO ANY ADDRESS (1) WRITE LAST BYTE TO LAST ADDRESS 5094 FHD FOB Note: Figure 10. Write Sequence for Deactivating Software Data Protection WRITE DATA: AA ADDRESS: 1555 WRITE DATA: 55 ADDRESS: OAAA WRITE DATA: 80 ADDRESS: 1555 WRITE DATA: AA ADDRESS; 1555 WRITE DATA: 55 ADDRESS: OAAA WRITE DATA: 20 ADDRESS: 1555 5004 FHD Foo (1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within taic Max., after SDP activation.CAT28LV64 , Preliminary To activate the software data protection, the device must To allow the user the ability to program the device with be sent three write commands to specific addresses with an E2PROM programmer (or for testing purposes) there specific data (Figure 9). This sequence of commands is a software command sequence for deactivating the (along with subsequent writes) must adhere to the page data protection. The six step algorithm (Figure 10) will write timing specifications (Figure 11). Once this is done, reset the internal protection circuitry, and the device will all subsequent byte or page writes to the device must be return to standard operating mode (Figure 12 provides preceded by this same set of write commands. The data reset timing). After the sixth byte of this reset sequence protection mechanism is activated until a deactivate has been issued, standard byte or page writing can sequence is issued regardless of power on/off transi- commence. tions. This gives the user added inadvertent write pro- tection on power-up in addition to the hardware protec- tion provided. Figure 11. Software Data Protection Timing DATA AA two >| ADDRESS 1555 CE WRITES ENABLED __ | WE 5094 FHD F139 Figure 12. Resetting Software Data Protection Timing DATA AA 55 80 AA 55 20 + two - sDP ADDRESS 1555 OAAA 1555 1555 OAAA 1555 RESET DEVICE UNPROTECTED 5064 FHO Ft4 ORDERING INFORMATION | Prefix | Device # | Suffix | CAT 28LV64 N -25 TE7 Optional Endurance temperature Range Tape & Reel Company Blank = 10,000 Cycle Blank = Commercial (0C to +70C) TE7: 500/Reel 1D H = 100,000 Cycle | = Industrial (-40C if +85C) TE13: 2000/Reel Product Package Speed Number P: PDI 25: 250ns J: SOIC (JEDEC) 30: 300ns K: SOIC (EtAJ) 35: 350ns N: PLCC T: TSOP (8mmx20mm) T13: TSOP (8mmx13.4mm) 714: TSOP (8mmx14mm) 28LV64 F17 Notes: (1) The device used in the above example is a CAT28LV64HNI-25TE7 (100,000 Cycle Endurance, PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel). 8-60