CY2305C
CY2309C
3.3 V Zero Delay Clock Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-07672 Rev. *K Revised February 3, 2011
Features
■10 MHz to 100–133 MHz operating range
■Zero input and output propagation delay
■Multiple low skew outputs
■One input drives five outputs (CY2305C)
■One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C)
■50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
■Test mode to bypass phase locked loop (PLL) (CY2309C) only,
see Select Input Decoding for CY2309C on page 5
■Available in space saving 16-pin 150 Mil small outline
integrated circuit (SOIC) or 4.4 mm thin shrunk small outline
package (TSSOP) packages (CY2309C), and 8-pin, 150 Mil
SOIC package (CY2305C)
■3.3 V operation
■Commercial, industrial and automotive-A flows available
Functional Description
The CY2305C and CY2309C are die replacement parts for
CY2305 and CY2309.
The CY2309C is a low-cost 3.3 V zero delay buffer designed to
distribute high speed clocks and is available in a 16-pin SOIC or
TSSOP package. The CY2305C is an 8-pin version of the
CY2309C. It accepts one reference input and drives out five low
skew clocks. The -1H versions of each device operate up to
100–133 MHz frequencies and have higher drive than the -1
devices. All parts have on-chip phase locked loops (PLLs) which
lock to an input clock on the REF pin. The PLL feedback is
on-chip and is obtained from the CLKOUT pad.
The CY2309C has two banks of four outputs each that are
controlled by the select inputs as shown in the Select Input
Decoding for CY2309C on page 5. If all output clocks are not
required, Bank B is three-stated. The input clock is directly
applied to the outputs by the select inputs for chip and system
testing purposes.
The CY2305C and CY2309C PLLs enter a power down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off. This
results in less than 12.0 A of current draw for commercial
temperature devices and 25.0 A for industrial and automotive-A
temperature parts. The CY2309C PLL shuts down in one
additional case as shown in the Select Input Decoding for
CY2309C on page 5.
In the special case when S2:S1 is 1:0, the PLL is bypassed and
REF is output from DC to the maximum allowable frequency. The
part behaves as a non-zero delay buffer in this mode and the
outputs are not three-stated.
The CY2305C or CY2309C is available in two or three different
configurations as shown in the Ordering Information on page 11.
The CY2305C-1 or CY2309C-1 is the base part. The CY2305-1H
or CY2309-1H is the high drive version of the -1. Its rise and fall
times are much faster than the -1.
Logic Block Diagram for CY2305C
CLKOUT
REF
CLK4
PLL
CLK1
CLK2
CLK3
[+] Feedback
CY2305C
CY2309C
Document Number: 38-07672 Rev. *K Page 3 of 17
Contents
Pinouts ..............................................................................4
Zero Delay and Skew Control ..........................................5
Absolute Maximum Conditions .......................................6
Operating Conditions for CY2305CSXC-XX and
CY2309CSXC-XX ............................................................... 6
Operating Conditions for CY2305CSXI-XX,
CY2305CSXA-XX and CY2309CSXI-XX ........................... 6
Electrical Characteristics for CY2305CSXC-XX and
CY2309CSXC-XX ............................................................... 6
Switching Characteristics for CY2305CSXC-XX and
CY2309CSXC-XX ............................................................... 7
Switching Characteristics for CY2305CSXI-XX,
CY2305CSXA-XX and CY2309CSXI-XX ........................... 8
Switching characteristics table for CY2305CSXI-1H,
CY2305CSXA-1H and CY2309CSXI-1H ........................... 9
Switching Waveforms ...................................................... 9
Test Circuits .................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definition ........................................... 12
Package Drawing and Dimensions ............................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products ....................................................................17
PSoC Solutions .........................................................17
[+] Feedback
CY2305C
CY2309C
Document Number: 38-07672 Rev. *K Page 4 of 17
Pinouts
CY2305C
CY2309C
Figure 2. Pin Diagram - 16 Pin SOIC/TSSOP (Top View)
Figure 1. Pin Diagram - 8 Pin SOIC (Top View)
Table 1. Pin Description - 8 Pin SOIC
Pin Signal Description
1REF
[1] Input reference frequency
2CLK2
[2] Buffered clock output
3CLK1
[2] Buffered clock output
4 GND Ground
5CLK3
[2] Buffered clock output
6V
DD 3.3 V supply
7CLK4
[2] Buffered clock output
8CLKOUT
[2] Buffered clock output, internal feedback on this pin
CLK2 CY2305C
1
2
3
4
8
7
6
5
CLKOUT
CLK4
VDD
CLK3
REF
CLK1
GND
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
CY2309C
Table 2. Pin Definition - 16 Pin SOIC/TSSOP
Pin Signal Description
1REF
[1] Input reference frequency
2 CLKA1[2] Buffered clock output, Bank A
3 CLKA2[2] Buffered clock output, Bank A
4V
DD 3.3 V supply
5 GND Ground
6 CLKB1[2] Buffered clock output, Bank B
7 CLKB2[2] Buffered clock output, Bank B
8S2
[3] Select input, bit 2
[+] Feedback
CY2305C
CY2309C
Document Number: 38-07672 Rev. *K Page 5 of 17
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input or output delay.
For applications requiring zero input or output delay, all outputs
including CLKOUT are equally loaded. Even if CLKOUT is not
used, it must have a capacitive load equal to that on other
outputs for obtaining zero input or output delay.
For zero output to output skew, all outputs must be loaded
equally.
9S1
[4] Select input, bit 1
10 CLKB3[5] Buffered clock output, Bank B
11 CLKB4[5] Buffered clock output, Bank B
12 GND Ground
13 VDD 3.3 V supply
14 CLKA3[5] Buffered clock output, Bank A
15 CLKA4[5] Buffered clock output, Bank A
16 CLKOUT[5] Buffered output, internal feedback on this pin
Table 2. Pin Definition - 16 Pin SOIC/TSSOP (continued)
Pin Signal Description
Notes
4. Weak pull ups on these inputs.
5. Weak pull down on all outputs.
6. This output is driven and has an internal feedback for the PLL. The load on this output is adjusted to change the skew between the reference and output.
Table 3. Select Input Decoding for CY2309C
S2 S1 CLOCK A1–A4 CLOCK B1–B4 CLKOUT[6] Output Source PLL Shutdown
0 0 Three state Three state Driven PLL N
0 1 Driven Three state Driven PLL N
1 0 Driven Driven Driven Reference Y
1 1 Driven Driven Driven PLL N
[+] Feedback
CY2305C
CY2309C
Document Number: 38-07672 Rev. *K Page 6 of 17
Absolute Maximum Conditions
Supply voltage to ground potential ...............–0.5 V to +4.6 V
DC input voltage (Except REF) ..........–0.5 V to VDD + 0.5 V
DC input voltage REF..........................–0.5 V to VDD + 0.5 V
Storage temperature ................................ –65 °C to +150 °C
Junction temperature................................................. 150 °C
Static discharge voltage
(per MIL-STD-883, Method 3015) ..........................> 2,000 V
Operating Conditions for CY2305CSXC-XX and CY2309CSXC-XX
Operating conditions table for CY2305CSXC-XX and CY2309CSXC-XX commercial temperature devices.
Parameter Description Min Max Unit
VDD Supply voltage 3.0 3.6 V
TAOperating temperature (ambient temperature) 0 70 °C
CLLoad capacitance, below 100 MHz – 30 pF
CLLoad capacitance, from 100 MHz to 133 MHz – 10 pF
CIN Input capacitance – 7 pF
tPU Power-up time for all VDDs to reach minimum specified voltage
(power ramps are monotonic)
0.05 50 ms
Operating Conditions for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX
Operating conditions table for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX industrial/automotive-A
temperature devices.
Parameter Description Min Max Unit
VDD Supply voltage 3.0 3.6 V
TAOperating temperature (ambient temperature) –40 85 °C
CLLoad capacitance, below 100 MHz – 30 pF
CLLoad capacitance, from 100 MHz to 133 MHz – 10 pF
CIN Input capacitance – 7 pF
tPU Power-up time for all VDDs to reach minimum specified voltage
(power ramps are monotonic)
0.05 50 ms
Electrical Characteristics for CY2305CSXC-XX and CY2309CSXC-XX
Electrical characteristics table for CY2305CSXC-XX and CY2309CSXC-XX commercial temperature devices.
Parameter Description Test Conditions Min Max Unit
VIL Input LOW voltage[7] –0.8V
VIH Input HIGH voltage[7] 2.0 – V
IIL Input LOW current VIN = 0 V – 50 A
IIH Input HIGH current VIN = VDD – 100 A
VOL Output LOW voltage[8] IOL = 8 mA (–1)
IOH = 12 mA (–1H)
–0.4V
VOH Output HIGH voltage[8] IOH = –8 mA (–1)
IOL = –12 mA (–1H)
2.4 – V
IDD (PD mode) Power-down supply current REF = 0 MHz – 12 A
IDD Supply current Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
–32mA
Notes
7. REF input has a threshold voltage of VDD/2.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
[+] Feedback
CY2305C
CY2309C
Document Number: 38-07672 Rev. *K Page 7 of 17
Switching Characteristics for CY2305CSXC-XX and CY2309CSXC-XX
Switching characteristics table for CY2305CSXC-1 and CY2309CSXC-1 commercial temperature devices. All parameters are
specified with loaded outputs.
Electrical Characteristics for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX
Electrical characteristics table for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX industrial/automotive-A
temperature devices.
Parameter Description Test Conditions Min Max Unit
VIL Input LOW voltage[9] –0.8V
VIH Input HIGH voltage[9] 2.0 – V
IIL Input LOW current VIN = 0 V – 50 A
IIH Input HIGH current VIN = VDD –100A
VOL Output LOW voltage[10] IOL = 8 mA (–1)
IOH =12 mA (–1H)
–0.4V
VOH Output HIGH voltage[10] IOH = –8 mA (–1)
IOL = –12 mA (–1H)
2.4 – V
IDD (PD mode) Power-down supply current REF = 0 MHz – 25 A
IDD Supply current Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
–35mA
Parameter Name Test Conditions Min Typ Max Unit
t1Output frequency 30 pF load
10 pF load
10
10
–100
133.33
MHz
MHz
tDC Output duty cycle[10] = t2 t1Measured at 1.4 V, Fout > 50 MHz 40 50 60 %
Measured at 1.4 V, Fout 50 MHz 45 50 55 %
t3Rise time[10] Measured between 0.8 V and 2.0 V – – 2.25 ns
t4Fall time[10] Measured between 0.8 V and 2.0 V – – 2.25 ns
t5Output-to-output skew[10] All outputs equally loaded – – 200 ps
t6A Delay, REF rising edge to
CLKOUT rising edge[10] Measured at VDD/2 – 0 ±350 ps
t6B Delay, REF rising edge to
CLKOUT rising edge[10] Measured at VDD/2. Measured in
PLL Bypass mode, CY2309C device
only.
158.7ns
t7Device-to-device skew[10] Measured at VDD/2 on the CLKOUT
pins of devices
–0700ps
tJCycle-to-cycle jitter, peak[10] Measured at 66.67 MHz, loaded
outputs
–50175ps
tLOCK PLL lock time[10] Stable power supply, valid clock
presented on REF pin
––1.0ms
Notes
9. .REF input has a threshold voltage of VDD/2.
10. Parameter is guaranteed by design and characterization. Not 100% tested in production.
[+] Feedback
CY2305C
CY2309C
Document Number: 38-07672 Rev. *K Page 8 of 17
Switching Characteristics for CY2305CSXC-XX and CY2309CSXC-XX
Switching characteristics table for CY2305CSXC-1H and CY2309CSXC-1H commercial temperature devices. All parameters are
specified with loaded outputs.
Parameter Name Description Min Typ Max Unit
t1Output frequency 30-pF load
10-pF load
10
10
–100
133.33
MHz
MHz
tDC Output duty cycle[11] = t2 t1Measured at 1.4 V, Fout > 50 MHz 40 50 60 %
Measured at 1.4 V, Fout 50 MHz 45 50 55 %
t3Rise time[11] Measured between 0.8 V and 2.0 V – – 1.5 ns
t4Fall time[11] Measured between 0.8 V and 2.0 V – – 1.5 ns
t5Output-to-output skew[11] All outputs equally loaded – – 200 ps
t6A Delay, REF rising edge to
CLKOUT rising edge[11]
Measured at VDD/2 – 0 ±350 ps
t6B Delay, REF rising edge to
CLKOUT rising edge[11]
Measured at VDD/2. Measured in PLL
Bypass mode, CY2309C device only.
158.7ns
t7Device-to-device skew[11] Measured at VDD/2 on the CLKOUT pins
of devices
–0700ps
t8Output slew rate[11] Measured between 0.8 V and 2.0 V using
Test circuit #2
1––V/ns
tJCycle-to-cycle jitter, peak[11] Measured at 66.67 MHz, loaded outputs – – 175 ps
tLOCK PLL lock time[11] Stable power supply, valid clock
presented on REF pin
––1.0ms
Note
11. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Switching Characteristics for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX
Switching characteristics table for CY2305CSXI-1, CY2305CSXA-1, and CY2309CSXI-1 industrial temperature devices. All
parameters are specified with loaded outputs.
Parameter Name Test Conditions Min Typ Max Unit
t1Output frequency 30 pF load
10 pF load
10
10
–100
133.33
MHz
MHz
tDC Output duty cycle[11] = t2 t1Measured at 1.4 V, Fout > 50 MHz 40 50 60 %
Measured at 1.4 V, Fout <= 50 MHz 45 50 55 %
t3Rise time[11] Measured between 0.8 V and 2.0 V – – 2.25 ns
t4Fall time[11] Measured between 0.8 V and 2.0 V – – 2.25 ns
t5Output-to-output skew[11] All outputs equally loaded – – 200 ps
t6A Delay, REF rising edge to
CLKOUT rising edge[11]
Measured at VDD/2 – 0 ±350 ps
t6B Delay, REF rising edge to
CLKOUT rising edge[11]
Measured at VDD/2. Measured in PLL
Bypass mode, CY2309C device only.
158.7ns
t7Device-to-device skew[11] Measured at VDD/2 on the CLKOUT pins
of devices
–0700ps
tJCycle-to-cycle jitter, peak[11] Measured at 66.67 MHz, loaded outputs – 50 175 ps
tLOCK PLL lock time[11] Stable power supply, valid clock
presented on REF pin
––1.0ms
[+] Feedback
CY2305C
CY2309C
Document Number: 38-07672 Rev. *K Page 9 of 17
Switching Waveforms
Figure 3. Duty Cycle Timing
Figure 4. All Outputs Rise/Fall Time
Note
12. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Switching characteristics table for CY2305CSXI-1H, CY2305CSXA-1H and CY2309CSXI-1H
Switching characteristics table for CY2305CSXI-1H, CY2305CSXA-1H and CY2309CSXI-1H industrial/automotive-A temperature
device. All parameters are specified with loaded outputs.
Parameter Name Description Min Typ Max Unit
t1Output frequency 30 pF load
10 pF load
10
10
– 100
133.33
MHz
MHz
tDC Output duty cycle[12] = t2 t1Measured at 1.4 V, Fout > 50 MHz 40 50 60 %
Measured at 1.4 V, Fout <= 50 MHz 45 50 55 %
t3Rise time[12] Measured between 0.8 V and 2.0 V – – 1.5 ns
t4Fall time[12] Measured between 0.8 V and 2.0 V – – 1.5 ns
t5Output-to-output skew[12] All outputs equally loaded – – 200 ps
t6A Delay, REF rising edge to
CLKOUT rising edge[12]
Measured at VDD/2 – 0 ±350 ps
t6B Delay, REF rising edge to
CLKOUT rising edge[12]
Measured at VDD/2. Measured in PLL
Bypass mode, CY2309C device only.
158.7ns
t7Device-to-device skew[12] Measured at VDD/2 on the CLKOUT pins
of devices
– 0 700 ps
t8Output slew rate[12] Measured between 0.8 V and 2.0 V using
Test circuit #2
1– –V/ns
tJCycle-to-cycle jitter, peak[12] Measured at 66.67 MHz, loaded outputs – – 175 ps
tLOCK PLL lock time[12] Stable power supply, valid clock
presented on REF pin
––1.0ms
t1
t2
1.4 V 1.4 V 1.4 V
OUTPUT
t3
3.3 V
0 V
0.8 V
2.0 V 2.0 V
0.8 V
t4
[+] Feedback
CY2305C
CY2309C
Document Number: 38-07672 Rev. *K Page 10 of 17
Figure 5. Output-Output Skew
Figure 6. Input-Output Propagation Delay
Figure 7. Device-Device Skew
Test Circuits
1.4 V
1.4 V
t5
OUTPUT
OUTPUT
VDD/2
t6
INPUT
OUTPUT
VDD/2
VDD/2
VDD/2
t7
CLKOUT, Device 1
CLKOUT, Device 2
0.1 F
VDD
0.1 F
VDD
CLK out
CLOAD
OUTPUTS
GND
GND
0.1 F
VDD
0.1 F
VDD
10 pF
OUTPUTS
GND
GND
1 k
1 k
Test Circuit # 1 Test Circuit # 2
For parameter t8 (output slew rate) on -1H devices
[+] Feedback
CY2305C
CY2309C
Document Number: 38-07672 Rev. *K Page 11 of 17
Ordering Information
Ordering Code Package Type Operating Range
Pb-free - CY2305C
CY2305CSXC-1 8-pin 150 Mil SOIC Commercial
CY2305CSXC-1T 8-pin 150 Mil SOIC – Tape and reel Commercial
CY2305CSXC-1H 8-pin 150 Mil SOIC Commercial
CY2305CSXC-1HT 8-pin 150 Mil SOIC – Tape and reel Commercial
CY2305CSXI-1 8-pin 150 Mil SOIC Industrial
CY2305CSXI-1T 8-pin 150 Mil SOIC – Tape and reel Industrial
CY2305CSXI-1H 8-pin 150 Mil SOIC Industrial
CY2305CSXI-1HT 8-pin 150 Mil SOIC – Tape and reel Industrial
CY2305CSXA-1H 8-pin 150 Mil SOIC Automotive-A
CY2305CSXA-1HT 8-pin 150 Mil SOIC – Tape and reel Automotive-A
Pb-free - CY2309C
CY2309CSXC-1 16-pin 150 Mil SOIC Commercial
CY2309CSXC-1T 16-pin 150 Mil SOIC – Tape and reel Commercial
CY2309CSXC-1H 16-pin 150 Mil SOIC Commercial
CY2309CSXC-1HT 16-pin 150 Mil SOIC – Tape and reel Commercial
CY2309CSXI-1 16-pin 150 Mil SOIC Industrial
CY2309CSXI-1T 16-pin 150 Mil SOIC – Tape and reel Industrial
CY2309CSXI-1H 16-pin 150 Mil SOIC Industrial
CY2309CSXI-1HT 16-pin 150 Mil SOIC – Tape and reel Industrial
CY2309CZXC-1 16-pin 4.4 mm TSSOP Commercial
CY2309CZXC-1T 16-pin 4.4 mm TSSOP – Tape and reel Commercial
CY2309CZXC-1H 16-pin 4.4 mm TSSOP Commercial
CY2309CZXC-1HT 16-pin 4.4 mm TSSOP – Tape and reel Commercial
CY2309CZXI-1 16-pin 4.4 mm TSSOP Industrial
CY2309CZXI-1T 16-pin 4.4 mm TSSOP – Tape and reel Industrial
CY2309CZXI-1H 16-pin 4.4 mm TSSOP Industrial
CY2309CZXI-1HT 16-pin 4.4 mm TSSOP – Tape and reel Industrial
[+] Feedback
CY2305C
CY2309C
Document Number: 38-07672 Rev. *K Page 12 of 17
Ordering Code Definition
CY 230XC XX X – 1X (T)
Tape and reel
Output Drive:
1 = standard drive
1H = high drive
Temperature Range:
A = Automotive
C = Commercial
I = Industrial
Package:
SX = SOIC, Pb-free
ZX = TSSOP, Pb-free
Base device part number
2305C = 5-output zero delay buffer, rev C
2309C = 9-output zero delay buffer, rev C
Company ID: CY = Cypress
[+] Feedback
CY2305C
CY2309C
Document Number: 38-07672 Rev. *K Page 15 of 17
Acronyms Document Conventions
Units of Measure
Acronym Description
CMOS Complementary metal oxide semiconductor
PLL phase locked loop
SOIC small outline integrated circuit
TSSOP thin shrunk small outline package
Symbol Unit of Measure
°C degrees Celsius
VVolts
kHz Kilohertz
MHz megahertz
µA microamperes
mA milliamperes
ms milliseconds
ns nanoseconds
pF picofarads
ps picoseconds
[+] Feedback
CY2305C
CY2309C
Document Number: 38-07672 Rev. *K Page 16 of 17
Document History Page
Document Title: CY2305C CY2309C 3.3 V ZERO DELAY CLOCK BUFFER
Document Number: 38-07672
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 224421 See ECN RGL New data sheet
*A 268571 See ECN RGL Added bullet for 5 V tolerant inputs in the features
*B 276453 See ECN RGL Minor Change: Moved one sentence from the features to the Functional
Description
*C 303063 See ECN RGL Updated data sheet as per characterization data
*D 318315 See ECN RGL Data sheet rewrite
*E 344815 See ECN RGL Minor Error: Corrected the header of all the AC/DC tables with the right part
numbers.
*F 127988938 See ECN KVM Changed title from ‚low Cost 3.3 V Zero Delay Buffer to 3.3 V Zero Delay Clock
Buffer
Specified the VIL minimum value to -0.3 V
Specified the VIH maximum value to VDD + 0.3 V
Changed DC Input Voltage (REF) maximum value in Absolute Maximum section
Removed references to 5 V tolerant inputs (pages 1 and 2)
Removed Pentium compatibility reference
Added CY2305C block diagram
Added ‚peak to the jitter specifications
Changed typical jitter from 75 ps to 50 ps for standard drive devices
For standard drive devices, tightened rise/fall times from 2.5 ns to 2.25 ns
Tightened cycle-to-cycle jitter from 200 ps to 175 ps
Tightened output-to-output skew from 250 ps to 200 ps
*G 1561504 See ECN KVM/NSI
/AESA
Added CY2305C Automotive-A grade devices
Extended duty cycle specs to cover entire frequency range
Changed from Preliminary to Final
*H 2558537 08/27/08 KVM/AESA Added CY2305CSXA-1 and CY2305CSXA-1T parts in Ordering Information
table under Pb-free CY2305C
*I 2901743 03/30/2010 VIVG Updated Package Drawing and Dimensions.
Added Ordering Code Definition
Added Sales, Solutions, and Legal Information URLs.
*J 3080990 11/10/2010 BASH Modified pin diagram of Figure 1.
Updated as per new template
Added Acronyms and Units of Measure table
Added TOC
*K 3160535 02/03/2011 BASH Removed min value of VIL and max value of VIH from Electrical Characteristics
Table on page 6 and page 7.
Removed Prune parts CY2305CSXA-1 and CY2305CSXA-1T from the
datasheet.
[+] Feedback
Document Number: 38-07672 Rev. *K Revised February 3, 2011 Page 17 of 17
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY2305C
CY2309C
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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PSoC cypress.com/go/psoc
Touch Sensing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
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