TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 2.95-V to 6-V Input, 3-A Output, 2-MHz, Synchronous Step-Down Switcher With Integrated FETs Check for Samples: TPS54388-Q1 FEATURES DESCRIPTION * * The TPS54388-Q1 device is a full featured 6 V, 3 A, synchronous step down current mode converter with two integrated MOSFETs. 1 2 * * * * * * * * Qualified for Automotive Applications Two 12-m (typical) MOSFETs for High Efficiency at 3-A Loads 200 kHz to 2 MHz Switching Frequency 0.8 V 1% Voltage Reference Over Temperature (-40C to 150C) Synchronizes to External Clock Adjustable Slow Start/Sequencing UV and OV Power Good Output -40C to 150C Operating Junction Temperature Range Thermally Enhanced 3mm x 3mm 16-pin QFN Pin Compatible to TPS54418 APPLICATIONS * * * Low-Voltage, High-Density Power Systems Point of Load Regulation for High Performance DSPs, FPGAs, ASICs and Microprocessors Broadband, Networking and Optical Communications Infrastructure The TPS54388-Q1 enables small designs by integrating the MOSFETs, implementing current mode control to reduce external component count, reducing inductor size by enabling up to 2 MHz switching frequency, and minimizing the IC footprint with a small 3 mm x 3 mm thermally enhanced QFN package. The TPS54388-Q1 provides accurate regulation for a variety of loads with an accurate 1% Voltage Reference (VREF) over temperature. Efficiency is maximized through the integrated 12 m MOSFETs and 515 A typical supply current. Using the enable pin, shutdown supply current is reduced to 5.5 A by entering a shutdown mode. Under voltage lockout is internally set at 2.45 V, but can be increased by programming the threshold with a resistor network on the enable pin. The output voltage startup ramp is controlled by the slow start pin. An open drain power good signal indicates the output is within 93% to 107% of its nominal voltage. Frequency fold back and thermal shutdown protects the device during an over-current condition. SIMPLIFIED SCHEMATIC vertical spacer 100 vertical spacer 3 Vin 95 VIN 85 R4 TPS54388-Q1 EN LO VOUT PH CO R5 R1 PWRGD Efficiency - % BOOT CI 5 Vin 90 CBOOT VIN 80 75 70 65 VSENSE 60 SS/TR RT /CLK COMP GND AGND POWERPAD C ss RT R2 fs = 500kHz 55 50 Vout = 1.8V 0 1 2 3 4 IO - Output Current - A 5 6 R3 C1 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010-2012, Texas Instruments Incorporated TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TJ -40C to 150C PACKAGE QFN - RTE Reel of 2500 ORDERABLE PART NUMBER TPS54388QRTERQ1 TOP-SIDE MARKING 5438Q ABSOLUTE MAXIMUM RATINGS (1) VALUES MIN MAX VIN -0.3 7 EN -0.3 BOOT Input voltage VSENSE -0.3 3 COMP -0.3 3 PWRGD -0.3 7 SS/TR -0.3 3 RT/CLK -0.3 3.3 7 PH PH 10 ns Transient Source current Sink current Temperature (1) 2 3.3 PH + 7 BOOT-PH Output voltage UNIT -0.6 7 -2 10 V V EN 100 A RT/CLK 100 A COMP 100 A PWRGD 10 mA SS/TR 100 A Tj -40 150 C Tstg -65 150 C TA -40 125 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ELECTRICAL SPECIFICATIONS is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 THERMAL INFORMATION TPS54388-Q1 THERMAL METRIC (1) (2) (3) (RTE) UNITS (QFN-16) PINS JA Junction-to-ambient thermal resistance 56.4 (4) JA Junction-to-ambient thermal resistance JT Junction-to-top characterization parameter 0.9 JB Junction-to-board characterization parameter 22.2 JC(top) Junction-to-case(top) thermal resistance 28.7 JC(bottom) Junction-to-case(bottom) thermal resistance 12.5 JB Junction-to-board thermal resistance 22.7 (1) (2) (3) (4) 37 C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Maximum power dissipation may be limited by overcurrent protection Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150C. This is the point where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 150C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more information. Test boards conditions: (a) 2 inches x 2 inches, 4 layers, thickness: 0.062 inch (b) 2 oz. copper traces located on the top of the PCB (c) 2 oz. copper ground planes on the 2 internal layers and bottom layer (d) 4 thermal vias (10mil) located under the device package Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 3 TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com ELECTRICAL CHARACTERISTICS TJ = -40C to 150C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN PIN) Operating input voltage Internal under voltage lockout threshold 6.0 V VIN UVLO START 2.95 2.28 2.5 V VIN UVLO STOP 2.45 2.6 V Shutdown supply current EN = 0 V, 25C, 2.95 V VIN 6 V 5.5 15 A Quiescent Current - Iq VSENSE = 0.9 V, VIN = 5 V, 25C, RT = 400 k 515 750 A Rising 1.25 Falling 1.18 Enable threshold +50 mV -1.6 Enable threshold -50 mV -1.6 ENABLE AND UVLO (EN PIN) Enable threshold Input current V A VOLTAGE REFERENCE (VSENSE PIN) Voltage Reference 2.95 V VIN 6 V, -40C <TJ < 150C 0.79 0.800 0.811 BOOT-PH = 5 V 12 30 BOOT-PH = 2.95 V 16 30 VIN = 5 V 13 30 VIN = 2.95 V 17 30 V MOSFET High-side switch resistance Low-side switch resistance m m ERROR AMPLIFIER Input current 2 nA Error amplifier transconductance (gm) -2 A < I(COMP) < 2 A, V(COMP) = 1 V 245 mhos Error amplifier transconductance (gm) during slow start -2 A < I(COMP) < 2 A, V(COMP) = 1 V, Vsense = 0.4 V 79 mhos Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive 20 A 25 A/V 6.5 A 168 C 20 C COMP to Iswitch gm CURRENT LIMIT Current limit threshold 3.7 THERMAL SHUTDOWN Thermal Shutdown Hysteresis TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) Switching frequency range using RT mode Switching frequency 200 Rt = 400 k 400 Switching frequency range using CLK mode 300 Minimum CLK pulse width RT/CLK voltage 500 2000 kHz 600 kHz 2000 kHz 75 R(RT/CLK) = 400k ns 0.5 RT/CLK high threshold 1.6 RT/CLK low threshold V 0.6 V RT/CLK falling edge to PH rising edge delay Measure at 500 kHz with RT resistor in series 90 ns PLL lock in time Measure at 500 kHz 45 s 4 0.4 V 2.5 Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 ELECTRICAL CHARACTERISTICS (continued) TJ = -40C to 150C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT PH (PH PIN) Minimum On time Minimum Off time Rise Time Fall Time Measured at 50% points on PH, IOUT = 3 A 75 Measured at 50% points on PH, VIN = 6 V, IOUT = 0 A 120 ns 60 ns Prior to skipping off pulses, BOOT-PH = 2.95 V, IOUT = 3 A VIN = 6 V, 6 A 2.25 V/ns 2 BOOT (BOOT PIN) BOOT Charge Resistance VIN = 5 V 16 BOOT-PH UVLO VIN = 2.95 V 2.1 V SLOW START AND TRACKING (SS/TR PIN) Charge Current V(SS/TR) = 0.4 V 2 A SS/TR to VSENSE matching V(SS/TR) = 0.4 V 50 mV SS/TR to reference crossover 98% normal 1.1 V SS/TR discharge voltage (Overload) VSENSE = 0 V 61 mV SS/TR discharge current (Overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 350 A SS discharge current (UVLO, EN, Thermal fault) VIN = 5 V, V(SS) = 0.5 V 1.9 mA VSENSE falling (Fault) 91 % Vref VSENSE rising (Good) 93 % Vref VSENSE rising (Fault) 109 % Vref VSENSE falling (Good) 107 % Vref % Vref POWER GOOD (PWRGD PIN) VSENSE threshold Hysteresis VSENSE falling 2 Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V 7 On resistance 56 Output low I(PWRGD) = 3 mA Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 A nA 100 0.3 0.650 V 1.6 Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 V 5 TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com DEVICE INFORMATION PIN CONFIGURATION VIN 1 VIN 2 VIN EN PWRGD BOOT QFN16 RTE Package (Top View) 16 15 14 13 12 PH 11 PH Exposed Thermal Pad (17) PH GND 4 9 SS/TR 6 7 8 RT/CLK 5 COMP 10 VSENSE 3 AGND GND PIN FUNCTIONS PIN NAME DESCRIPTION NO. AGND 5 Analog Ground should be electrically connected to GND close to the device. BOOT 13 A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed. COMP 7 Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. EN 15 Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Can be used to set the on/off threshold (adjust UVLO) with two additional resistors. 3, 4 Power Ground. This pin should be electrically connected directly to the power pad under the IC. GND PH 10, 11, 12 The source of the internal high side power MOSFET, and drain of the internal low side (synchronous) rectifier MOSFET. PowerPAD TM 17 GND pin should be connected to the exposed power pad for proper operation. This power pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance. PWRGD 14 An open drain output; asserts low if output voltage is low due to thermal shutdown, overcurrent, over/undervoltage or EN shut down. RT/CLK 8 Resistor Timing or External Clock input pin. SS/TR 9 Slow start and tracking. An external capacitor connected to this pin sets the output voltage rise time. This pin can also be used for tracking. VIN 1, 2, 16 VSENSE 6 6 Input supply voltage, 2.95 V to 6 V. Inverting node of the transconductance (gm) error amplifier. Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 FUNCTIONAL BLOCK DIAGRAM EN PWRGD VIN i1 Shutdown 91% ihys Thermal Shutdown Enable Comparator Logic UVLO Shutdown Shutdown Logic 109% Enable Threshold Boot Charge Voltage Reference Boot UVLO Minimum COMP Clamp ERROR AMPLIFIER Current Sense PWM Comparator VSENSE SS/TR BOOT Logic and PWM Latch Shutdown Logic S COMP Slope Compensation PH Frequency Shift Overload Recovery Maximum Clamp Oscillator with PLL GND TPS54388-Q1 Block Diagram AGND POWERPAD RT/CLK Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 7 TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS CURVES FREQUENCY vs TEMPERATURE 525 520 0.023 High Side Rdson Vin = 3.3 V 0.021 Low Side Rdson Vin = 3.3 V 0.019 0.017 0.015 0.013 High Side Rdson Vin = 5 V 0.011 Low Side Rdson Vin = 5 V 0.009 RT = 400 kW, Vin = 5 V 515 fs - Switching Frequency - kHz RDSON - Static Drain-Source On-State Resistance - W HIGH SIDE AND LOW SIDE RDS(ON) vs TEMPERATURE 0.025 510 505 500 495 490 485 480 0.007 0.005 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 475 -50 150 -25 0 25 50 75 100 TJ - Junction Temperature - C Figure 1. 125 150 Figure 2. HIGH SIDE CURRENT LIMIT vs TEMPERATURE VOLTAGE REFERENCE vs TEMPERATURE 8 0.807 Vin = 3.3 V 0.805 7 VI = 3.3 V Vref - Voltage Reference - V High Side Switching Current - A 7.5 6.5 6 5.5 VI = 5 V 5 4.5 0.803 0.801 0.799 0.797 0.795 4 0.793 3.5 3 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 150 0.791 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C Figure 3. 150 Figure 4. SWITCHING FREQUENCY vs RT RESISTANCE LOW FREQUENCY RANGE SWITCHING FREQUENCY vs VSENSE 100 2000 1800 Vsense Falling Nominal Switching Frequency - % fs - Switching Frequency - kHz 125 1600 1400 1200 1000 800 75 Vsense Rising 50 25 400 200 80 180 280 380 480 580 RT - Resistance - kW 680 780 880 980 0 0 0.1 0.3 0.4 0.5 0.6 0.7 0.8 Vsense - V Figure 5. 8 0.2 Figure 6. Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 TYPICAL CHARACTERISTICS CURVES (continued) TRANSCONDUCTANCE (SLOW START) vs JUNCTION TEMPERATURE TRANSCONDUCTANCE vs TEMPERATURE 105 310 Vin = 3.3 V 100 Vin = 3.3 V EA - Transconductance - mA/V EA - Transconductance - mA/V 290 270 250 230 210 95 90 85 80 75 70 65 190 60 170 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 55 -50 150 -25 0 25 50 75 100 TJ - Junction Temperature - C Figure 7. 125 150 Figure 8. EN PIN VOLTAGE vs TEMPERATURE EN PIN CURRENT vs TEMPERATURE 1.3 -3 1.29 -3.1 Vin = 5 V, Ven = Threshold +50 mV 1.28 Vin = 3.3 V, rising 1.27 -3.2 EN - Pin Current - mA EN - Threshold - V 1.26 1.25 1.24 1.23 1.22 1.21 1.2 Vin = 3.3 V, falling 1.19 -3.3 -3.4 -3.5 -3.6 -3.7 1.18 -3.8 1.17 -3.9 1.16 1.15 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 -4 -50 150 -25 0 Figure 9. 125 150 Figure 10. EN PIN CURRENT vs TEMPERATURE CHARGE CURRENT vs TEMPERATURE -1 -1.2 25 50 75 100 TJ - Junction Temperature - C -1.4 Vin = 5 V Vin = 5 V, Ven = Threshold -50 mV -1.6 Iss/tr - Charge Current - mA EN - Pin Current - mA -1.4 -1.6 -1.8 -2 -2.2 -2.4 -1.8 -2 -2.2 -2.4 -2.6 -2.6 -2.8 -2.8 -3 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 150 -3 -50 -30 Figure 11. -10 10 30 50 70 90 TJ - Junction Temperature - C 110 130 150 Figure 12. Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 9 TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) INPUT VOLTAGE vs TEMPERATURE SHUTDOWN SUPPLY CURRENT vs TEMPERATURE 2.8 8 2.7 7 Shutdown Supply Current - mA Vin = 3.3 V VI - Input Voltage - V 2.6 UVLO Stop Switching 2.5 2.4 2.3 UVLO Start Switching 2.2 6 5 4 3 2 1 2.1 2 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 0 -50 150 -25 0 Figure 13. 125 150 Figure 14. SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE VIN SUPPLY CURRENT vs JUNCTION TEMPERATURE 800 8 TJ = 25C Vin = 3.3 V 7 700 6 Ivin - Supply Current - mA Shutdown Supply Current - mA 25 50 75 100 TJ - Junction Temperature - C 5 4 3 2 600 500 400 300 1 0 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 200 -50 6 -25 0 Figure 15. 125 150 Figure 16. VIN SUPPLY CURRENT vs INPUT VOLTAGE PWRGD THRESHOLD vs TEMPERATURE 800 110 TJ = 25C 108 700 106 PWRGD - Threshold - % of Vref Ivin - Supply Current - mA 25 50 75 100 TJ - Junction Temperature - C 600 500 400 300 Vsense Rising, VI = 5V 104 Vsense Falling 102 100 98 96 Vsense Falling 94 Vsense Rising 92 90 200 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 6 88 -50 -25 Figure 17. 10 0 25 50 75 100 TJ - Junction Temperature - C 125 150 Figure 18. Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 TYPICAL CHARACTERISTICS CURVES (continued) SS/TR to VSENSE OFFSET vs TEMPERATURE 100 100 90 90 80 80 70 SSTR - Vsense Offset - mV RDSON - Static Drain-Source On-State Resistance - W PWRGD ON-RESISTANCE vs TEMPERATURE VI = 5 V 60 50 40 30 70 60 50 40 30 20 20 10 10 0 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 150 Vin = 5 V, SS = 0.4 V 0 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C Figure 19. 125 150 Figure 20. OVERVIEW The TPS54388-Q1 is a 6-V, 3-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To improve performance during line and load transients the device implements a constant frequency, peak current mode control which reduces output capacitance and simplifies external frequency compensation design. The wide switching frequency of 200 kHz to 2000 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch turn on to a falling edge of an external system clock. The TPS54388-Q1 has a typical default start up voltage of 2.45 V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition, the pull up current provides a default condition when the EN pin is floating for the device to operate. The total operating current for the TPS54388-Q1 is typically 515 A when not switching and under no load. When the device is disabled, the supply current is less than 5.5 A. The integrated 12 m MOSFETs allow for high efficiency power supply designs with continuous output currents up to 3 amperes. The TPS54388-Q1 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor voltage is monitored by an UVLO circuit and turns off the high side MOSFET when the voltage falls below a preset threshold. This BOOT circuit allows the TPS54388-Q1 to operate approaching 100%. The output voltage can be stepped down to as low as the 0.800 V reference. The TPS54388-Q1 has a power good comparator (PWRGD) with 2% hysteresis. The TPS54388-Q1 minimizes excessive output overvoltage transients by taking advantage of the overvoltage power good comparator. When the regulated output voltage is greater than 109% of the nominal voltage, the overvoltage comparator is activated, and the high side MOSFET is turned off and masked from turning on until the output voltage is lower than 107%. The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor should be coupled to the pin for slow start. The SS/TR pin is discharged before the output power up to ensure a repeatable restart after an overtemperature fault, UVLO fault or disabled condition. The use of a frequency fold-back circuit reduces the switching frequency during startup and over current fault conditions to help limit the inductor current. Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 11 TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com DETAILED DESCRIPTION FIXED FREQUENCY PWM CONTROL The TPS54388-Q1 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current. When the power switch current reaches the COMP voltage level the high side power switch is turned off and the low side power switch is turned on. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level and also implements a minimum clamp for improved transient response performance. SLOPE COMPENSATION AND OUTPUT CURRENT The TPS54388-Q1 adds a compensating ramp to the switch current signal. This slope compensation prevents sub-harmonic oscillations as duty cycle increases. The available peak inductor current remains constant over the full duty cycle range. BOOTSTRAP VOLTAGE (BOOT) AND LOW DROPOUT OPERATION The TPS54388-Q1 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be 0.1 F. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the TPS54388-Q1 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.2 V. The high side MOSFET is turned off using an UVLO circuit, allowing for the low side MOSFET to conduct when the voltage from BOOT to PH drops below 2.2 V. Since the supply current sourced from the BOOT pin is low, the high side MOSFET can remain on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the switching regulator is high. ERROR AMPLIFIER The TPS54388-Q1 has a transconductance amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.800 V voltage reference. The transconductance of the error amplifier is 245A/V during normal operation. When the voltage of VSENSE pin is below 0.800 V and the device is regulating using the SS/TR voltage, the gm is typically greater than 79 A/V, but less than 245 A/V. The frequency compensation components are placed between the COMP pin and ground. VOLTAGE REFERENCE The voltage reference system produces a precise 1% voltage reference over temperature by scaling the output of a temperature-stable bandgap circuit. The bandgap and scaling circuits produce 0.800 V at the non-inverting input of the error amplifier. ADJUSTING THE OUTPUT VOLTAGE The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to use divider resistors with 1% tolerance or better. Start with a 100 k for the R1 resistor and use the Equation 1 to calculate R2. To improve efficiency at light loads consider using larger value resistors. If the values are too high the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable. vertical spacer vertical spacer ae o 0.799 V R2 = R1 c / e VO - 0.799 V o 12 (1) Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 TPS54388-Q1 VO R1 VSENSE R2 0.8 V + Figure 21. Voltage Divider Circuit ENABLE AND ADJUSTING UNDER-VOLTAGE LOCKOUT The TPS54388-Q1 is disabled when the VIN pin voltage falls below 2.6 V. If an application requires a higher under-voltage lockout (UVLO), use the EN pin as shown in Figure 22 to adjust the input voltage UVLO by using two external resistors. It is recommended to use the EN resistors to set the UVLO falling threshold (VSTOP) above 2.6 V. The rising threshold (VSTART) should be set to provide enough hysteresis to allow for any input supply variations. The EN pin has an internal pull-up current source that provides the default condition of the TPS54388Q1 operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 1.6 A of hysteresis is added. When the EN pin is pulled below 1.18 V, the 1.6 A is removed. This additional current facilitates input voltage hysteresis. TPS54388-Q1 I hys VIN 1.6 mA I1 R1 1.6 mA EN R2 + - Figure 22. Adjustable Undervoltage Lock Out aeV o VSTART c ENFALLING / - VSTOP V e ENRISING o R1 = ae VENFALLING o I1 c1 / + Ihys VENRISING o e (2) vertical spacer R2 = R1 VENFALLING VSTOP - VENFALLING + R1(I1 + Ihys ) (3) Where Ihys = 1.6 A, I1 = 1.6 A, VENRISING = 1.25 V, VENFALLING = 1.18 V Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 13 TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com SLOW START/TRACKING PIN The TPS54388-Q1 regulates to the lower of the SS/TR pin and the internal reference voltage. A capacitor on the SS/TR pin to ground implements a slow start time. The TPS54388-Q1 has an internal pull-up current source of 2 A which charges the external slow start capacitor. Equation 4 calculates the required slow start capacitor value where Tss is the desired slow start time in ms, Iss is the internal slow start charging current of 2 A, and Vref is the internal voltage reference of 0.800 V. vertical spacer Tss(mS) Iss(mA) Css(nF) = Vref(V) (4) If during normal operation, the VIN goes below the UVLO, EN pin pulled below 1.2 V, or a thermal shutdown event occurs, the TPS54388-Q1 stops switching. When the VIN goes above UVLO, EN is released or pulled high, or a thermal shutdown is exited, then SS/TR is discharged to below 60 mV before reinitiating a powering up sequence. The VSENSE voltage will follow the SS/TR pin voltage with a 50 mV offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference. SEQUENCING Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open drain or collector output of a power on reset pin of another device. Figure 23 shows the sequential method. The power good is coupled to the EN pin on the TPS54388-Q1 which enables the second power supply once the primary supply reaches regulation. Ratio-metric start up can be accomplished by connecting the SS/TR pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start time the pull up current source must be doubled in Equation 4. The ratio metric method is illustrated in Figure 25. TPS54388-Q1 PWRGD EN EN EN1 SS SS EN2 PWRGD VO1 VO2 Figure 23. Sequential Start-Up Sequence 14 Figure 24. Sequential Startup using EN and PWRGD Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 TPS54388-Q1 EN1 SS/TR1 EN PWRGD1 SS TPS54388-Q1 VO1 EN2 VO2 SS/TR2 PWRGD2 Figure 25. Schematic for Ratiometric Start-Up Sequence Figure 26. Ratio-metric Startup with Vout1 Leading Vout2 Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 27 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 5 and Equation 6, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1. Equation 7 is the voltage difference between Vout1 and Vout2. The V variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and tracking resistors, the Vssoffset and Iss are included as variables in the equations. To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 5 through Equation 7 for V. Equation 7 will result in a positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. Since the SS/TR pin must be pulled below 60mV before starting after an EN, UVLO or thermal shutdown fault, careful selection of the tracking resistors is needed to ensure the device will restart after a fault. Make sure the calculated R1 value from Equation 5 is greater than the value calculated in Equation 8 to ensure the device can recover from a fault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin voltage needs to be greater than 1.1 V for a complete handoff to the internal voltage reference as shown in Figure 26. vertical spacer R1 = Vout2 + D V Vssoffset Vref Iss (5) vertical spacer R2 = Vref R1 Vout2 + DV - Vref (6) vertical spacer DV = Vout1 - Vout2 (7) vertical spacer R1 > 2930 Vout1- 145 DV (8) vertical spacer Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 15 TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com TPS54388-Q1 EN1 VOUT1 EN1 SS/TR1 PWRGD1 SS2 Vout1 TPS54388-Q1 EN2 Vout2 VOUT 2 R1 SS/TR2 R2 PWRGD2 Figure 27. Ratio-metric and Simultaneous Startup Sequence Figure 28. Ratio-metric Start-Up using Coupled SS/TR Pins CONSTANT SWITCHING FREQUENCY and TIMING RESISTOR (RT/CLK Pin) The switching frequency of the TPS54388-Q1 is adjustable over a wide range from 200 kHz to 2000 kHz by placing a maximum of 700 k and minimum of 85 k, respectively, on the RT/CLK pin. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK is typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in Figure 5 or Equation 9. 247530 RT (kW) = Fsw(kHz)1.0533 (9) vertical spacer Fsw(kHz) = 131904 RT(kW)0.9492 (10) To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the efficiency, maximum input voltage and minimum controllable on time should be considered. The minimum controllable on time is typically 60 ns at full current load and 120 ns at no load, and limits the maximum operating input voltage or output voltage. OVERCURRENT PROTECTION The TPS54388-Q1 implements a cycle by cycle current limit. During each switching cycle the high side switch current is compared to the voltage on the COMP pin. When the instantaneous switch current intersects the COMP voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally. This clamp functions as a switch current limit. FREQUENCY SHIFT To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS54388-Q1 implements a frequency shift. If frequency shift was not implemented, during an overcurrent condition the low side MOSFET may not be turned off long enough to reduce the current in the inductor, causing a current runaway. With frequency shift, during an overcurrent condition the switching frequency is reduced from 100%, then 50%, then 25%, as the voltage decreases from 0.800 to 0 volts on VSENSE pin to allow the low side MOSFET to be off long enough to decrease the current in the inductor. During start-up, the switching frequency increases as the voltage on VSENSE increases from 0 to 0.800 volts. See Figure 6 for details. 16 Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 REVERSE OVERCURRENT PROTECTION The TPS54388-Q1 implements low side current protection by detecting the voltage across the low side MOSFET. When the converter sinks current through its low side FET, the control circuit turns off the low side MOSFET if the reverse current is typically more than 4.5 A. By implementing this additional protection scheme, the converter is able to protect itself from excessive current during power cycling and start-up into pre-biased outputs. SYNCHRONIZE USING THE RT/CLK PIN The RT/CLK pin is used to synchronize the converter to an external system clock. See Figure 29. To implement the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on time of at least 75ns. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to the frequency set by the resistor. The square wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of the PH is synchronized to the falling edge of RT/CLK pin. TPS54388-Q1 SYNC Clock = 2 V / div PLL PH = 2 V / div RT/CLK Clock Source RT Time = 500 nsec / div Figure 29. Synchronizing to a System Clock Figure 30. Plot of Synchronizing to System Clock POWER GOOD (PWRGD PIN) The PWRGD pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage enters the fault condition by falling below 91% or rising above 109% of the nominal internal reference voltage. There is a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93% or falls below 107% of the internal voltage reference the PWRGD output MOSFET is turned off. It is recommended to use a pull-up resistor between the values of 1k and 100k to a voltage source that is 6 V or less. The PWRGD is in a valid state once the VIN input voltage is greater than 1.1 V. OVERVOLTAGE TRANSIENT PROTECTION The TPS54388-Q1 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold the high side MOSFET is allowed to turn on the next clock cycle. THERMAL SHUTDOWN The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 168C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 148C, the device reinitiates the power up sequence by discharging the SS pin to below 60 mV. The thermal shutdown hysteresis is 20C. Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 17 TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com SMALL SIGNAL MODEL FOR LOOP RESPONSE Figure 31 shows an equivalent model for the TPS54388-Q1 control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm of 245 A/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor R0 and capacitor Co model the open loop gain and frequency response of the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting a/c shows the small signal response of the frequency compensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing the RL with a current source with the appropriate load step amplitude and step rate in a time domain analysis. PH VO Power Stage 25 A/V a b R1 c R3 C2 RESR RL COMP C1 C0 R0 0.800 V VSENSE gm 245 A/V COUT R2 Figure 31. Small Signal Model for Loop Response SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL Figure 31 is a simple small signal model that can be used to understand how to design the frequency compensation. The TPS54388-Q1 power stage can be approximated to a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 11 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 31) is the power stage transconductance. The gm for the TPS54388-Q1 is 25 A/V. The low frequency gain of the power stage frequency response is the product of the transconductance and the load resistance as shown in Equation 12. As the load current increases and decreases, the low frequency gain decreases and increases, respectively. This variation with load may seem problematic at first glance, but the dominant pole moves with load current [see Equation 13]. The combined effect is highlighted by the dashed line in the right half of Figure 32. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. vertical spacer vertical spacer 18 Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 VO Adc VC RESR fp RL gmps COUT fz Figure 32. Simple Small Signal Model and Frequency Response for Peak Current Mode Control ae c 1+ vo e 2p = Adc vc ae c 1+ e 2p o s / x |z o o s / x |p o (11) Adc = gmps RL |p = C OUT (12) 1 RL 2p (13) 1 RESR 2p (14) vertical spacer |z = COUT SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION The TPS54388-Q1 uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits. The compensation circuits are shown in Figure 33. The Type 2 circuits are most likely implemented in high bandwidth power supply designs using low ESR output capacitors. In Type 2A, one additional high frequency pole is added to attenuate high frequency noise. VO R1 VSENSE COMP gmea R2 Vref RO CO 5pF Type 2A R3 C2 Type 2B R3 C1 C1 Figure 33. Types of Frequency Compensation Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 19 TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com The design guidelines for TPS54388-Q1 loop compensation are as follows: 1. The modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 15 and Equation 16. Derating the output capacitor (COUT) may be needed if the output voltage is a high percentage of the capacitor rating. Use the capacitor manufacturer information to derate the capacitor value. Use Equation 17 and Equation 18 to estimate a starting point for the crossover frequency, fc. Equation 17 is the geometric mean of the modulator pole and the esr zero and Equation 18 is the mean of modulator pole and the switching frequency. Use the lower value of Equation 17 or Equation 18 as the maximum crossover frequency. | p m od = Iout m ax 2 p Vout Cout (15) vertical spacer | z m od = 1 2 p Resr Cout (16) vertical spacer |C = |p mod | z mod (17) vertical spacer |C = |p mod | sw 2 (18) vertical spacer 2. R3 can be determined by 2p x | c Vo COUT R3 = gmea Vref gmps (19) vertical spacer Where is the gmea amplifier gain (245 A/V), gmps is the power stage gain (25 A/V). |p = 3. Place a compensation zero at the dominant pole R COUT C1 = L R3 1 C OUT R L 2 p . C1 can be determined by vertical spacer 4. C2 is optional. It can be used to cancel the zero from Co's ESR. Resr COUT C2 = R3 20 Submit Documentation Feedback (20) (21) Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 APPLICATION INFORMATION DESIGN GUIDE - STEP-BY-STEP DESIGN PROCEDURE This example details the design of a high frequency switching regulator design using ceramic output capacitors. This design is available as the HPA375 evaluation module (EVM). A few parameters must be known in order to start the design process. These parameters are typically determined on the system level. For this example, we start with the following known parameters: Output Voltage 1.8 V Transient Response 1 to 2A load step Vout = 5% Maximum Output Current 3A Input Voltage 5 V nom. 3 V to 5 V Output Voltage Ripple < 30 mV p-p Switching Frequency (Fsw) 1000 kHz SELECTING THE SWITCHING FREQUENCY The first step is to decide on a switching frequency for the regulator. Typically, you want to choose the highest switching frequency possible since this produces the smallest solution size. The high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. However, the highest switching frequency causes extra switching losses, which hurt the converter's performance. The converter is capable of running from 200 kHz to 2 MHz. Unless a small solution size is an ultimate goal, a moderate switching frequency of 1MHz is selected to achieve both a small solution size and a high efficiency operation. Using Equation 9, R5 is calculated to be 180 k. A standard 1% 182 k value was chosen in the design. TPS54388RTE Figure 34. High Frequency, 1.8 V Output Power Supply Design with Adjusted UVLO OUTPUT INDUCTOR SELECTION The inductor selected works for the entire TPS54388-Q1 input voltage range. To calculate the value of the output inductor, use Equation 22. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, KIND is normally from 0.1 to 0.3 for the majority of applications. Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 21 TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com For this design example, use KIND = 0.3 and the inductor value is calculated to be 1.36 H. For this design, a nearest standard value was chosen: 1.5 H. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 24 and Equation 25. For this design, the RMS inductor current is 3.01 A and the peak inductor current is 3.72 A. The chosen inductor is a Coilcraft XLA4020-152ME_. It has a saturation current rating 0f 9.6 A and a RMS current rating of 7.5 A. The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. Vinmax - Vout Vout L1 = Io Kind Vinmax | sw (22) vertical spacer Iripple = Vinmax - Vout Vout L1 Vinmax | sw (23) vertical spacer ILrms = Io 2 + ae Vo (Vinmax - Vo) o 1 c / 12 e Vinmax L1 | sw o 2 (24) vertical spacer ILpeak = Iout + Iripple 2 (25) OUTPUT CAPACITOR There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these three criteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 26 shows the minimum output capacitance necessary to accomplish this. For this example, the transient load response is specified as a 5 % change in Vout for a load step from 0 A (no load) to 1.5 A (50% load). For this example, Iout = 1.5-0 = 1.5 A and Vout= 0.05 x 1.8 = 0.090 V. Using these numbers gives a minimum capacitance of 33 F. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Equation 27 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. Under this requirement, Equation 27 yields 2.3 uF. vertical spacer 2 DIout Co > | sw DVout 22 (26) Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 vertical spacer Co > 1 8 | sw 1 Voripple Iripple Where Iout is the change in output current, Fsw is the regulators switching frequency and Vout is the allowable change in the output voltage. (27) vertical spacer Equation 28 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 28 indicates the ESR should be less than 55 m. In this case, the ESR of the ceramic capacitor is much less than 55 m. Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value. For this example, two 22 F 10 V X5R ceramic capacitors with 3 m of ESR are used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 29 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 29 yields 333 mA. Voripple Resr < Iripple (28) vertical spacer Icorm s = Vout (Vinm ax - Vout) 12 Vinm ax L1 | sw (29) INPUT CAPACITOR The TPS54388-Q1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 F of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54388Q1. The input ripple current can be calculated using Equation 30. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the maximum input voltage. For this example, one 10 F and one 0.1 F 10 V capacitors in parallel have been selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 31. Using the design example values, Ioutmax=3 A, Cin=10 F, Fsw=1 MHz, yields an input voltage ripple of 76 mV and a rms input ripple current of 1.47 A. Icirms = Iout Vout Vinmin (Vinmin - Vout ) Vinmin (30) vertical spacer Ioutmax 0.25 DVin = Cin | sw (31) Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 23 TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com SLOW START CAPACITOR The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54388-Q1 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The slow start capacitor value can be calculated using Equation 32. For the example circuit, the slow start time is not too critical since the output capacitor value is 44 F which does not require much current to charge to 1.8 V. The example circuit has the slow start time set to an arbitrary value of 4ms which requires a 10 nF capacitor. In TPS54388-Q1, Iss is 2.2 A and Vref is 0.800 V. Tss(ms) Iss(mA) Css(nF) = Vref(V) (32) BOOTSTRAP CAPACITOR SELECTION A 0.1 F ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or higher voltage rating. OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION For the example design, 100 k was selected for R6. Using Equation 33, R7 is calculated as 80 k. The nearest standard 1% resistor is 80.5 k. Vref R7 = R6 Vo - Vref (33) Due to the internal design of the TPS54388-Q1, there is a minimum output voltage limit for any given input voltage. The output voltage can never be lower than the internal voltage reference of 0.827 V. Above 0.827 V, the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by Equation 34 Voutmin = Ontimemin Fsmax (Vinmax - Ioutmin 2 RDS ) - Ioutmin (RL + RDS ) Where: Voutmin = minimum achievable output voltage Ontimemin = minimum controllable on-time (65 ns typical. 120 nsec no load) Fsmax = maximum switching frequency including tolerance Vinmax = maximum input voltage Ioutmin = minimum load current RDS = minimum high side MOSFET on resistance (15 - 19 m) RL = series resistance of output inductor (34) There is also a maximum achievable output voltage which is limited by the minimum off time. The maximum output voltage is given by Equation 35 Voutmax = (1 - Offtimemax Fsmax ) (Vinmin - Ioutmax 2 RDS ) - Ioutmax (RL + RDS ) Where: Voutmax = maximum achievable output voltage Offtimeman = maximum off time (60 nsec typical) Fsmax = maximum switching frequency including tolerance Vinmin = minimum input voltage Ioutmax = maximum load current RDS = maximum high side MOSFET on resistance (19 - 30 m) RL = series resistance of output inductor 24 Submit Documentation Feedback (35) Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 COMPENSATION There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54388-Q1. Since the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequency used in the calculations. To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 36 and Equation 37. For Cout, derating the capacitor is not needed as the 1.8 V output is a small percentage of the 10 V capacitor rating. If the output is a high percentage of the capacitor rating, use the capacitor manufacturer information to derate the capacitor value. Use Equation 38 and Equation 39 to estimate a starting point for the crossover frequency, fc. For the example design, fpmod is 6.03 kHz and fzmod is 1210 kHz. Equation 38 is the geometric mean of the modulator pole and the esr zero and Equation 39 is the mean of modulator pole and the switching frequency. Equation 38 yields 85.3 kHz and Equation 39 gives 54.9 kHz. Use the lower value of Equation 38 or Equation 39 as the approximate crossover frequency. For this example, fc is 56 kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole (if needed). | p m od = Iout m ax 2 p Vout Cout (36) 1 2 p Resr Cout (37) vertical spacer | z m od = vertical spacer |C = |p mod | z mod (38) vertical spacer |C = |p mod | sw 2 (39) vertical spacer The compensation design takes the following steps: 1. Set up the anticipated cross-over frequency. Use Equation 40 to calculate the compensation network's resistor value. In this example, the anticipated cross-over frequency (fc) is 56 kHz. The power stage gain (gmps) is 25 A/V and the error amplifier gain (gmea) is 245 A/V. 2p x | c Vo Co R3 = Gm Vref VIgm (40) 2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The compensation network's capacitor can be calculated from Equation 41. Ro Co C3 = R3 (41) 3. An additional pole can be added to attenuate high frequency noise. In this application, it is not necessary to add it. From the procedures above, the compensation network includes a 7.68 k resistor and a 3300 pF capacitor. APPLICATION CURVES Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 25 TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com EFFICIENCY vs LOAD CURRENT 100 EFFICIENCY vs LOAD CURRENT 100 3.3 Vin,1.8 Vout 90 90 80 80 5 Vin, 1.8 Vout 70 Efficiency - % Efficiency - % 70 60 50 40 5 Vin, 1.8 Vout 3.3 Vin,1.8 Vout 60 50 40 30 30 20 20 10 10 0 0 0.5 1 1.5 2 2.5 0 0.001 3 0.01 Output Current - A Figure 35. 0.1 Output Current - A 10 Figure 36. EFFICIENCY vs LOAD CURRENT 1 MHz, 3.3 VIN, TA = 25C EFFICIENCY vs LOAD CURRENT 1 MHz, 5 VIN, TA = 25C 100 100 2.5 V 1.8 V 95 95 90 90 85 85 2.5 V 1.8 V 80 1.05 V 1.2 V Efficience - % 1.5 V Efficience - % 1 1.5 V 75 70 1.2 V 1.05V 3.3 V 80 75 70 65 65 60 60 55 55 50 50 0 0.5 1 1.5 2 IO - Output Current - A 2.5 3 0 Figure 37. 0.5 1 1.5 2 IO - Output Current - A 2.5 3 Figure 38. POWER UP VOUT, VIN POWER DOWN VOUT, VIN VIN = 2 V/div VIN = 2 V/div EN = 1 V/div EN = 1 V/div SS = 1 V/div SS = 1 V/div VOUT = 1 V/div VOUT = 1 V/div Time = 5 ms/div Time = 500 ms/div Figure 39. 26 Figure 40. Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 TRANSIENT RESPONSE, 1.5 A STEP POWER UP VOUT, VIN Vin = 5 V / div Vout = 100 mV / div (ac coupled) Vout = 2 V / div Iout = 1 A / div (0 A to 1.5 A load step) EN = 2 V / div PWRGD = 5 V / div Time = 5 msec / div Time = 200 usec / div Figure 41. Figure 42. POWER UP VOUT, EN OUTPUT RIPPLE, 3 A Vin = 5 V / div Vout = 20 mV / div (ac coupled) Vout = 2 V / div PH = 2 V / div EN = 2 V / div PWRGD = 5 V / div Time = 500 nsec / div Time = 5 msec / div Figure 43. Figure 44. CLOSED LOOP RESPONSE, VIN (5 V), 3 A Gain - dB Vin = 100 mV / div (ac coupled) PH = 2 V / div 60 180 50 150 40 120 30 90 20 60 10 30 0 0 -10 -30 -20 -60 -30 -90 -40 -50 Time = 500 nsec / div -60 10 Figure 45. Phase - Degrees INPUT RIPPLE, 3 A -120 Gain Phase 100 -150 1000 10k Frequency - Hz 100k -180 1M Figure 46. Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 27 TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com LOAD REGULATION vs LOAD CURRENT REGULATION vs INPUT VOLTAGE 0.4 0.4 0.3 Output Voltage Deviation - % Output Voltage Deviation - % 0.3 0.2 Vin = 5 V 0.1 0 Vin = 3.3 V -0.1 -0.2 Iout = 2 A 0.2 0.1 0 -0.1 -0.2 -0.3 -0.3 -0.4 -0.4 0 0.5 1 1.5 2 2.5 3 3 3.5 4 4.5 5 5.5 6 Input Voltage-V Output Current - A Figure 47. Figure 48. POWER DISSIPATION ESTIMATE The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching loss (Psw), gate drive loss (Pgd) and supply current loss (Pq). Pcon = Io2 x RDS(on)_Temp Pd = sw x Io x 0.7 x 60 x 10-9 Psw = 1/2 x Vin x Io x swx 8 x 10-9 Pgd = 2 x Vin x swx 2 x 10-9 Pq = Vin x 515 x 10-6 Where: IO is the output current (A). RDS(on)_Temp is the on-resistance of the high-side MOSFET with given temperature (). Vin is the input voltage (V). sw is the switching frequency (Hz). So Ptot = Pcon + Pd + Psw + Pgd + Pq For given TA, TJ = TA + Rth x Ptot For given TJMAX = 150C TAMAX = TJ MAX - Rth x Ptot Where: Ptot is the total device power dissipation (W). TA is the ambient temperature (C). TJ is the junction temperature (C). Rth is the thermal resistance of the package (C/W). TJMAX is maximum junction temperature (C). TAMAX is maximum ambient temperature (C). 28 Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace resistance that impact the overall efficiency of the regulator. LAYOUT Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. Care should be taken to minimize the loop area formed by the bypass capacitor connections and the VIN pins. See Figure 49 for a PCB layout example. The GND pins and AGND pin should be tied directly to the power pad under the IC. The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC. Additional vias can be used to connect the top side ground area to the internal planes near the input and output capacitors. For operation at full rated load, the top side ground area along with any additional internal ground planes must provide adequate heat dissipating area. Locate the input bypass capacitor as close to the IC as possible. The PH pin should be routed to the output inductor. Since the PH connection is the switching node, the output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The boot capacitor must also be located close to the device. The sensitive analog ground connections for the feedback voltage divider, compensation components, slow start capacitor and frequency set resistor should be connected to a separate analog ground trace as shown. The RT/CLK pin is particularly sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline. Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 29 TPS54388-Q1 SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 www.ti.com VIA to Ground Plane UVLO SET RESISTORS VIN INPUT BYPASS CAPACITOR BOOT PWRGD EN VIN VIN BOOT CAPACITOR VIN OUTPUT INDUCTOR PH VIN PH EXPOSED POWERPAD AREA GND PH PH GND VOUT OUTPUT FILTER CAPACITOR SLOW START CAPACITOR RT/CLK COMP VSENSE AGND SS FEEDBACK RESISTORS ANALOG GROUND TRACE FREQUENCY SET RESISTOR TOPSIDE GROUND AREA COMPENSATION NETWORK VIA to Ground Plane Figure 49. PCB Layout Example 30 Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 TPS54388-Q1 www.ti.com SLVSAF1B - OCTOBER 2010 - REVISED JULY 2012 REVISION HISTORY Changes from Revision A (June, 2011) to Revision B Page * Removed (SWIFTTM) from title. ............................................................................................................................................ 1 * Removed the last two sentences in the description containing SwitcherProTM and SWIFTTM references. .......................... 1 * Removed last sentence of first paragraph, "Use SwitcherPro software for a more accurate design." ............................... 25 Submit Documentation Feedback Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Link(s): TPS54388-Q1 31 PACKAGE OPTION ADDENDUM www.ti.com 12-Jul-2012 PACKAGING INFORMATION Orderable Device TPS54388QRTERQ1 Status (1) ACTIVE Package Type Package Drawing WQFN RTE Pins Package Qty 16 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54388QRTERQ1 Package Package Pins Type Drawing WQFN RTE 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 3.3 B0 (mm) K0 (mm) P1 (mm) 3.3 1.1 8.0 W Pin1 (mm) Quadrant 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54388QRTERQ1 WQFN RTE 16 3000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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