PH
VIN
POWERPAD
BOOT
VSENSE
COMP
TPS54388-Q1
EN
RT /CLK
SS/TR
PWRGD
Css
RTR3
C1
CBOOT
CO
LO
R1
R2
CI
VOUT
VIN
AGND
GND
R4
R5
Efficiency - %
I - Output Current - A
O
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6
3 Vin
5 Vin
f = 500kHz
s
Vout = 1.8V
TPS54388-Q1
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SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
2.95-V to 6-V Input, 3-A Output, 2-MHz, Synchronous Step-Down
Switcher With Integrated FETs
Check for Samples: TPS54388-Q1
1FEATURES DESCRIPTION
The TPS54388-Q1 device is a full featured 6 V, 3 A,
2• Qualified for Automotive Applications synchronous step down current mode converter with
• Two 12-mΩ(typical) MOSFETs for High two integrated MOSFETs.
Efficiency at 3-A Loads The TPS54388-Q1 enables small designs by
• 200 kHz to 2 MHz Switching Frequency integrating the MOSFETs, implementing current
• 0.8 V ± 1% Voltage Reference Over mode control to reduce external component count,
Temperature (–40°C to 150°C) reducing inductor size by enabling up to 2 MHz
switching frequency, and minimizing the IC footprint
• Synchronizes to External Clock with a small 3 mm x 3 mm thermally enhanced QFN
• Adjustable Slow Start/Sequencing package.
• UV and OV Power Good Output The TPS54388-Q1 provides accurate regulation for a
• –40°C to 150°C Operating Junction variety of loads with an accurate ±1% Voltage
Temperature Range Reference (VREF) over temperature.
• Thermally Enhanced 3mm × 3mm 16-pin QFN Efficiency is maximized through the integrated 12 mΩ
• Pin Compatible to TPS54418 MOSFETs and 515 μA typical supply current. Using
the enable pin, shutdown supply current is reduced to
APPLICATIONS 5.5 µA by entering a shutdown mode.
• Low-Voltage, High-Density Power Systems Under voltage lockout is internally set at 2.45 V, but
can be increased by programming the threshold with
• Point of Load Regulation for High Performance a resistor network on the enable pin. The output
DSPs, FPGAs, ASICs and Microprocessors voltage startup ramp is controlled by the slow start
• Broadband, Networking and Optical pin. An open drain power good signal indicates the
Communications Infrastructure output is within 93% to 107% of its nominal voltage.
Frequency fold back and thermal shutdown protects
SIMPLIFIED SCHEMATIC the device during an over-current condition.
vertical spacer
vertical spacer
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TJPACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 150°C QFN – RTE Reel of 2500 TPS54388QRTERQ1 5438Q
ABSOLUTE MAXIMUM RATINGS(1)
VALUES UNIT
MIN MAX
VIN –0.3 7
EN –0.3 3.3
BOOT PH + 7
VSENSE –0.3 3
Input voltage V
COMP –0.3 3
PWRGD –0.3 7
SS/TR –0.3 3
RT/CLK –0.3 3.3
BOOT-PH 7 V
Output voltage PH –0.6 7
PH 10 ns Transient –2 10
EN 100 µA
Source current RT/CLK 100 µA
COMP 100 µA
Sink current PWRGD 10 mA
SS/TR 100 µA
Tj–40 150 °C
Temperature Tstg –65 150 °C
TA–40 125 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under ELECTRICAL
SPECIFICATIONS is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
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SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
THERMAL INFORMATION TPS54388-Q1
THERMAL METRIC(1)(2)(3) (RTE) UNITS
(QFN-16) PINS
θJA Junction-to-ambient thermal resistance 56.4
θJA Junction-to-ambient thermal resistance (4) 37
ψJT Junction-to-top characterization parameter 0.9
ψJB Junction-to-board characterization parameter 22.2 °C/W
θJC(top) Junction-to-case(top) thermal resistance 28.7
θJC(bottom) Junction-to-case(bottom) thermal resistance 12.5
θJB Junction-to-board thermal resistance 22.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Maximum power dissipation may be limited by overcurrent protection
(3) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below
150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more
information.
(4) Test boards conditions:
(a) 2 inches x 2 inches, 4 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer
(d) 4 thermal vias (10mil) located under the device package
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TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
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ELECTRICAL CHARACTERISTICS
TJ= –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 2.95 6.0 V
VIN UVLO START 2.28 2.5 V
Internal under voltage lockout threshold VIN UVLO STOP 2.45 2.6 V
Shutdown supply current EN = 0 V, 25°C, 2.95 V ≤VIN ≤6 V 5.5 15 μA
Quiescent Current - IqVSENSE = 0.9 V, VIN = 5 V, 25°C, RT = 400 kΩ515 750 μA
ENABLE AND UVLO (EN PIN)
Enable threshold Rising 1.25 V
Falling 1.18
Enable threshold +50 mV –1.6
Input current μA
Enable threshold –50 mV –1.6
VOLTAGE REFERENCE (VSENSE PIN)
Voltage Reference 2.95 V ≤VIN ≤6 V, –40°C <TJ< 150°C 0.79 0.800 0.811 V
MOSFET
BOOT-PH = 5 V 12 30
High-side switch resistance mΩ
BOOT-PH = 2.95 V 16 30
VIN = 5 V 13 30
Low-side switch resistance mΩ
VIN = 2.95 V 17 30
ERROR AMPLIFIER
Input current 2 nA
Error amplifier transconductance (gm) –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V 245 μmhos
Error amplifier transconductance (gm) during –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V, 79 μmhos
slow start Vsense = 0.4 V
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±20 μA
COMP to Iswitch gm 25 A/V
CURRENT LIMIT
Current limit threshold 3.7 6.5 A
THERMAL SHUTDOWN
Thermal Shutdown 168 °C
Hysteresis 20 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode 200 2000 kHz
Switching frequency Rt = 400 kΩ400 500 600 kHz
Switching frequency range using CLK mode 300 2000 kHz
Minimum CLK pulse width 75 ns
RT/CLK voltage R(RT/CLK) = 400kΩ0.5 V
RT/CLK high threshold 1.6 2.5 V
RT/CLK low threshold 0.4 0.6 V
RT/CLK falling edge to PH rising edge delay Measure at 500 kHz with RT resistor in series 90 ns
PLL lock in time Measure at 500 kHz 45 μs
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SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
ELECTRICAL CHARACTERISTICS (continued)
TJ= –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION CONDITIONS MIN TYP MAX UNIT
PH (PH PIN)
Minimum On time Measured at 50% points on PH, IOUT = 3 A 75 ns
Measured at 50% points on PH, VIN = 6 V, 120
IOUT = 0 A
Minimum Off time Prior to skipping off pulses, BOOT-PH = 2.95 V, 60 ns
IOUT = 3 A
Rise Time 2.25
VIN = 6 V, 6 A V/ns
Fall Time 2
BOOT (BOOT PIN)
BOOT Charge Resistance VIN = 5 V 16 Ω
BOOT-PH UVLO VIN = 2.95 V 2.1 V
SLOW START AND TRACKING (SS/TR PIN)
Charge Current V(SS/TR) = 0.4 V 2 μA
SS/TR to VSENSE matching V(SS/TR) = 0.4 V 50 mV
SS/TR to reference crossover 98% normal 1.1 V
SS/TR discharge voltage (Overload) VSENSE = 0 V 61 mV
SS/TR discharge current (Overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 350 µA
SS discharge current (UVLO, EN, Thermal VIN = 5 V, V(SS) = 0.5 V 1.9 mA
fault)
POWER GOOD (PWRGD PIN)
VSENSE falling (Fault) 91 % Vref
VSENSE rising (Good) 93 % Vref
VSENSE threshold VSENSE rising (Fault) 109 % Vref
VSENSE falling (Good) 107 % Vref
Hysteresis VSENSE falling 2 % Vref
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V 7 nA
On resistance 56 100 Ω
Output low I(PWRGD) = 3 mA 0.3 V
Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 μA 0.650 1.6 V
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
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PWRGD
BOOT
PH
RT/CLK
EN
AGND
VIN
VSENSE
COMP
15 14 13
GND
12
11
10
9
8
7
6
5
16
GND
VIN
VIN
PH
PH
1
2
3
4 SS/TR
Exposed Thermal Pad
(17)
QFN16
RTE Package
(Top View)
TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
www.ti.com
DEVICE INFORMATION
PIN CONFIGURATION
PIN FUNCTIONS
PIN DESCRIPTION
NAME NO.
AGND 5 Analog Ground should be electrically connected to GND close to the device.
BOOT 13 A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum
required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.
COMP 7 Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
components to this pin.
EN 15 Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Can be used to set the
on/off threshold (adjust UVLO) with two additional resistors.
GND 3, 4 Power Ground. This pin should be electrically connected directly to the power pad under the IC.
PH 10, 11, The source of the internal high side power MOSFET, and drain of the internal low side (synchronous) rectifier
12 MOSFET.
PowerPAD 17 GND pin should be connected to the exposed power pad for proper operation. This power pad should be
™ connected to any internal PCB ground plane using multiple vias for good thermal performance.
PWRGD 14 An open drain output; asserts low if output voltage is low due to thermal shutdown, overcurrent, over/under-
voltage or EN shut down.
RT/CLK 8 Resistor Timing or External Clock input pin.
SS/TR 9 Slow start and tracking. An external capacitor connected to this pin sets the output voltage rise time.
This pin can also be used for tracking.
VIN 1, 2, 16 Input supply voltage, 2.95 V to 6 V.
VSENSE 6 Inverting node of the transconductance (gm) error amplifier.
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ERROR
AMPLIFIER
Boot
Charge
Boot
UVLO
UVLO
Current
Sense
Oscillator
with PLL
Frequency
Shift
Slope
Compensation
PWM
Comparator
Minimum
COMP Clamp
Maximum
Clamp
Voltage
Reference
Overload
Recovery
VSENSE
SS/TR
COMP
RT/CLK
PH
BOOT
VIN
AGND
Thermal
Shutdown
EN
Enable
Comparator
Shutdown
Logic
Shutdown
Enable
Threshold
TPS54388-Q1 Block Diagram
Logic
Shutdown
PWRGD
POWERPAD
GND
Logic
Shutdown
109%
91%
S
Logic and PWM
Latch
i1ihys
TPS54388-Q1
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SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
FUNCTIONAL BLOCK DIAGRAM
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Product Folder Link(s): TPS54388-Q1
0
25
50
75
100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Vsense-V
VsenseFalling
VsenseRising
NominalSwitchingFrequency-%
200
400
800
1000
1200
1400
1600
1800
2000
80 180 280 380 480 580 680 780 880 980
RT - Resistance - kW
f - Switching Frequency - kHz
s
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
-50 -25 0 25 50 75 100 125 150
T -JunctionTemperature-°C
J
V =5V
I
V =3.3V
I
HighSideSwitchingCurrent- A
0.791
0.793
0.795
0.797
0.799
0.801
0.803
0.805
0.807
Vin = 3.3 V
V - Voltage Reference - V
ref
-50 -25 0 25 50 75 100 125 150
T - Junction Temperature - °C
J
475
480
485
490
495
500
505
510
515
520
525
RT = 400 k ,
Vin = 5 V
W
-50 -25 0 25 50 75 100 125 150
T - Junction Temperature - °C
J
f - Switching Frequency - kHz
s
TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
www.ti.com
TYPICAL CHARACTERISTICS CURVES
HIGH SIDE AND LOW SIDE RDS(ON) vs TEMPERATURE FREQUENCY vs TEMPERATURE
Figure 1. Figure 2.
HIGH SIDE CURRENT LIMIT vs TEMPERATURE VOLTAGE REFERENCE vs TEMPERATURE
Figure 3. Figure 4.
SWITCHING FREQUENCY vs
RT RESISTANCE LOW FREQUENCY RANGE SWITCHING FREQUENCY vs VSENSE
Figure 5. Figure 6.
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-3
-2.8
-2.6
-2.4
-2.2
-2
-1.8
-1.6
-1.4
-1.2
-1
Vin = 5 V,
Ven = Threshold -50 mV
-50 -25 0 25 50 75 100 125 150
T - Junction Temperature - °C
J
EN - Pin Current - Am
-50 -30 -10 10 30 50 70 90 110 130 150
T - Junction Temperature - °C
J
Vin = 5 V
-3
-2.8
-2.6
-2.4
-2.2
-2
-1.8
-1.6
-1.4
Iss/tr - Charge Current - Am
1.15
1.16
1.17
1.18
1.19
1.2
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.3
Vin = 3.3 V, rising
Vin = 3.3 V, falling
-50 -25 0 25 50 75 100 125 150
T - Junction Temperature - °C
J
EN - Threshold - V
-4
-3.9
-3.8
-3.7
-3.6
-3.5
-3.4
-3.3
-3.2
-3.1
-3
Vin = 5 V,
Ven = Threshold +50 mV
-50 -25 0 25 50 75 100 125 150
T - Junction Temperature - °C
J
EN - Pin Current - Am
EA - Transconductance - A/Vm
170
190
210
230
250
270
290
310
Vin = 3.3 V
-50 -25 0 25 50 75 100 125 150
T - Junction Temperature - °C
J
55
60
65
70
75
80
85
90
95
100
105
EA - Transconductance - A/Vm
-50 -25 0 25 50 75 100 125 150
T - Junction Temperature - °C
J
Vin = 3.3 V
TPS54388-Q1
www.ti.com
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
TYPICAL CHARACTERISTICS CURVES (continued)
TRANSCONDUCTANCE (SLOW START) vs
TRANSCONDUCTANCE vs TEMPERATURE JUNCTION TEMPERATURE
Figure 7. Figure 8.
EN PIN VOLTAGE vs TEMPERATURE EN PIN CURRENT vs TEMPERATURE
Figure 9. Figure 10.
EN PIN CURRENT vs TEMPERATURE CHARGE CURRENT vs TEMPERATURE
Figure 11. Figure 12.
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Product Folder Link(s): TPS54388-Q1
-50 -25 0 25 50 75 100 125 150
T -JunctionTemperature-°C
J
88
90
92
94
96
98
100
102
104
106
108
110
VsenseFalling
VsenseFalling
VsenseRising,V =5V
I
VsenseRising
PWRGD-Threshold-%ofVref
200
300
400
500
600
700
800
T =25°C
J
3 3.5 4 4.5 5 5.5 6
V -InputVoltage-V
I
Ivin-SupplyCurrent- Am
200
300
400
500
600
700
800
-50 -25 0 25 50 75 100 125 150
T - Junction Temperature - °C
J
Vin = 3.3 V
Ivin - Supply Current - Am
3 3.5 4 4.5 5 5.5 6
V -InputVoltage-V
I
T =25°C
J
0
1
2
3
4
5
6
7
8
ShutdownSupplyCurrent- Am
UVLOStartSwitching
UVLOStopSwitching
-50 -25 0 25 50 75 100 125 150
T -JunctionTemperature-°C
J
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
V -InputVoltage-V
I
-50 -25 0 25 50 75 100 125 150
T - Junction Temperature - °C
J
Vin = 3.3 V
0
1
2
3
4
5
6
7
8
Shutdown Supply Current - Am
TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
www.ti.com
TYPICAL CHARACTERISTICS CURVES (continued)
INPUT VOLTAGE vs TEMPERATURE SHUTDOWN SUPPLY CURRENT vs TEMPERATURE
Figure 13. Figure 14.
SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE VIN SUPPLY CURRENT vs JUNCTION TEMPERATURE
Figure 15. Figure 16.
VIN SUPPLY CURRENT vs INPUT VOLTAGE PWRGD THRESHOLD vs TEMPERATURE
Figure 17. Figure 18.
10 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS54388-Q1
0
10
20
30
40
50
60
70
80
90
100
-50 -25 0 25 50 75 100 125 150
T - Junction Temperature - °C
J
Vin = 5 V,
SS = 0.4 V
SSTR - Vsense Offset - mV
0
10
20
30
40
50
60
70
80
90
100
-50 -25 0 25 50 75 100 125 150
T -JunctionTemperature-°C
J
V =5V
I
RDSON-StaticDrain-SourceOn-StateResistance- W
TPS54388-Q1
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SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
TYPICAL CHARACTERISTICS CURVES (continued)
PWRGD ON-RESISTANCE vs TEMPERATURE SS/TR to VSENSE OFFSET vs TEMPERATURE
Figure 19. Figure 20.
OVERVIEW
The TPS54388-Q1 is a 6-V, 3-A, synchronous step-down (buck) converter with two integrated n-channel
MOSFETs. To improve performance during line and load transients the device implements a constant frequency,
peak current mode control which reduces output capacitance and simplifies external frequency compensation
design. The wide switching frequency of 200 kHz to 2000 kHz allows for efficiency and size optimization when
selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the
RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the
power switch turn on to a falling edge of an external system clock.
The TPS54388-Q1 has a typical default start up voltage of 2.45 V. The EN pin has an internal pull-up current
source that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In
addition, the pull up current provides a default condition when the EN pin is floating for the device to operate.
The total operating current for the TPS54388-Q1 is typically 515 μA when not switching and under no load.
When the device is disabled, the supply current is less than 5.5 μA.
The integrated 12 mΩMOSFETs allow for high efficiency power supply designs with continuous output currents
up to 3 amperes.
The TPS54388-Q1 reduces the external component count by integrating the boot recharge diode. The bias
voltage for the integrated high side MOSFET is supplied by a capacitor between the BOOT and PH pins. The
boot capacitor voltage is monitored by an UVLO circuit and turns off the high side MOSFET when the voltage
falls below a preset threshold. This BOOT circuit allows the TPS54388-Q1 to operate approaching 100%. The
output voltage can be stepped down to as low as the 0.800 V reference.
The TPS54388-Q1 has a power good comparator (PWRGD) with 2% hysteresis.
The TPS54388-Q1 minimizes excessive output overvoltage transients by taking advantage of the overvoltage
power good comparator. When the regulated output voltage is greater than 109% of the nominal voltage, the
overvoltage comparator is activated, and the high side MOSFET is turned off and masked from turning on until
the output voltage is lower than 107%.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin for slow start. The SS/TR pin is
discharged before the output power up to ensure a repeatable restart after an overtemperature fault, UVLO fault
or disabled condition.
The use of a frequency fold-back circuit reduces the switching frequency during startup and over current fault
conditions to help limit the inductor current.
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O
0.799 V
R2 = R1
V 0.799 V
æ ö
´ç ÷
-
è ø
TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
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DETAILED DESCRIPTION
FIXED FREQUENCY PWM CONTROL
The TPS54388-Q1 uses an adjustable fixed frequency, peak current mode control. The output voltage is
compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier
which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error
amplifier output is compared to the high side power switch current. When the power switch current reaches the
COMP voltage level the high side power switch is turned off and the low side power switch is turned on. The
COMP pin voltage increases and decreases as the output current increases and decreases. The device
implements a current limit by clamping the COMP pin voltage to a maximum level and also implements a
minimum clamp for improved transient response performance.
SLOPE COMPENSATION AND OUTPUT CURRENT
The TPS54388-Q1 adds a compensating ramp to the switch current signal. This slope compensation prevents
sub-harmonic oscillations as duty cycle increases. The available peak inductor current remains constant over the
full duty cycle range.
BOOTSTRAP VOLTAGE (BOOT) AND LOW DROPOUT OPERATION
The TPS54388-Q1 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT
and PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor
should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher
is recommended because of the stable characteristics over temperature and voltage.
To improve drop out, the TPS54388-Q1 is designed to operate at 100% duty cycle as long as the BOOT to PH
pin voltage is greater than 2.2 V. The high side MOSFET is turned off using an UVLO circuit, allowing for the low
side MOSFET to conduct when the voltage from BOOT to PH drops below 2.2 V. Since the supply current
sourced from the BOOT pin is low, the high side MOSFET can remain on for more switching cycles than are
required to refresh the capacitor, thus the effective duty cycle of the switching regulator is high.
ERROR AMPLIFIER
The TPS54388-Q1 has a transconductance amplifier. The error amplifier compares the VSENSE voltage to the
lower of the SS/TR pin voltage or the internal 0.800 V voltage reference. The transconductance of the error
amplifier is 245μA/V during normal operation. When the voltage of VSENSE pin is below 0.800 V and the device
is regulating using the SS/TR voltage, the gm is typically greater than 79 μA/V, but less than 245 μA/V. The
frequency compensation components are placed between the COMP pin and ground.
VOLTAGE REFERENCE
The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output
of a temperature-stable bandgap circuit. The bandgap and scaling circuits produce 0.800 V at the non-inverting
input of the error amplifier.
ADJUSTING THE OUTPUT VOLTAGE
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use divider resistors with 1% tolerance or better. Start with a 100 kΩfor the R1 resistor and use the Equation 1
to calculate R2. To improve efficiency at light loads consider using larger value resistors. If the values are too
high the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable.
vertical spacer
vertical spacer
(1)
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Product Folder Link(s): TPS54388-Q1
( )
´
- + +
ENFALLING
STOP ENFALLING 1 hys
R1 V
R2 = V V R1 I I
1
æ ö -
ç ÷
è ø
æ ö
- +
ç ÷
è ø
ENFALLING
START STOP
ENRISING
ENFALLING
1 hys
ENRISING
V
V V
V
R1 = V
I I
V
EN
I1
Ihys
VIN
TPS54388-Q1
+
-
R1
R2
1.6 mA
1.6 mA
VSENSE
VO
+
-
R1
R2 0.8 V
TPS54388-Q1
TPS54388-Q1
www.ti.com
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
Figure 21. Voltage Divider Circuit
ENABLE AND ADJUSTING UNDER-VOLTAGE LOCKOUT
The TPS54388-Q1 is disabled when the VIN pin voltage falls below 2.6 V. If an application requires a higher
under-voltage lockout (UVLO), use the EN pin as shown in Figure 22 to adjust the input voltage UVLO by using
two external resistors. It is recommended to use the EN resistors to set the UVLO falling threshold (VSTOP) above
2.6 V. The rising threshold (VSTART) should be set to provide enough hysteresis to allow for any input supply
variations. The EN pin has an internal pull-up current source that provides the default condition of the TPS54388-
Q1 operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 1.6 μA of hysteresis
is added. When the EN pin is pulled below 1.18 V, the 1.6 μA is removed. This additional current facilitates input
voltage hysteresis.
Figure 22. Adjustable Undervoltage Lock Out
(2)
vertical spacer
(3)
Where Ihys = 1.6 µA, I1= 1.6 µA, VENRISING = 1.25 V, VENFALLING = 1.18 V
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
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EN1
EN2
VO1
VO2
SS
EN
PWRGD
SS
EN
PWRGD
TPS54388-Q1
Tss(mS) Iss( A)
Css(nF) = Vref(V)
´ m
TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
www.ti.com
SLOW START/TRACKING PIN
The TPS54388-Q1 regulates to the lower of the SS/TR pin and the internal reference voltage. A capacitor on the
SS/TR pin to ground implements a slow start time. The TPS54388-Q1 has an internal pull-up current source of 2
μA which charges the external slow start capacitor. Equation 4 calculates the required slow start capacitor value
where Tss is the desired slow start time in ms, Iss is the internal slow start charging current of 2 μA, and Vref is
the internal voltage reference of 0.800 V.
vertical spacer
(4)
If during normal operation, the VIN goes below the UVLO, EN pin pulled below 1.2 V, or a thermal shutdown
event occurs, the TPS54388-Q1 stops switching. When the VIN goes above UVLO, EN is released or pulled
high, or a thermal shutdown is exited, then SS/TR is discharged to below 60 mV before reinitiating a powering up
sequence. The VSENSE voltage will follow the SS/TR pin voltage with a 50 mV offset up to 85% of the internal
voltage reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset
increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference.
SEQUENCING
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins. The sequential method can be implemented using an open drain or collector output of a power on reset pin
of another device. Figure 23 shows the sequential method. The power good is coupled to the EN pin on the
TPS54388-Q1 which enables the second power supply once the primary supply reaches regulation.
Ratio-metric start up can be accomplished by connecting the SS/TR pins together. The regulator outputs ramp
up and reach regulation at the same time. When calculating the slow start time the pull up current source must
be doubled in Equation 4. The ratio metric method is illustrated in Figure 25.
Figure 23. Sequential Start-Up Sequence Figure 24. Sequential Startup using EN and
PWRGD
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R1 2930 Vout1 145 V> ´ - ´ D
V = Vout1 Vout2D -
´
D -
Vref R1
R2 =
Vout2 + V Vref
D´
Vout2 + V Vssoffset
R1 =
Vref Iss
SS/TR1
SS/TR2
TPS54388-Q1
EN1
EN2
PWRGD1
PWRGD2
TPS54388-Q1
EN
SS
VO1
VO2
TPS54388-Q1
www.ti.com
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
Figure 25. Schematic for Ratiometric Start-Up Figure 26. Ratio-metric Startup with Vout1 Leading
Sequence Vout2
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 27 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 5 and Equation 6, the tracking resistors can be calculated to initiate the Vout2
slightly before, after or at the same time as Vout1. Equation 7 is the voltage difference between Vout1 and
Vout2. The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR
to VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and
tracking resistors, the Vssoffset and Iss are included as variables in the equations. To design a ratio-metric start
up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a
negative number in Equation 5 through Equation 7 for ΔV. Equation 7 will result in a positive number for
applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. Since the SS/TR pin
must be pulled below 60mV before starting after an EN, UVLO or thermal shutdown fault, careful selection of the
tracking resistors is needed to ensure the device will restart after a fault. Make sure the calculated R1 value from
Equation 5 is greater than the value calculated in Equation 8 to ensure the device can recover from a fault. As
the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as
the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin
voltage needs to be greater than 1.1 V for a complete handoff to the internal voltage reference as shown in
Figure 26.
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(5)
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(6)
vertical spacer (7)
vertical spacer (8)
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Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS54388-Q1
0.9492
131904
Fsw(kHz) RT(k )
=
W
1.0533
247530
RT (k ) = Fsw(kHz)
W
SS/TR1
TPS54388-Q1
EN1
PWRGD1
SS/TR2
TPS54388-Q1
EN2
PWRGD2
VOUT1
VOUT 2
R1
R2
EN1
Vout2
SS2
Vout1
TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
www.ti.com
Figure 27. Ratio-metric and Simultaneous Startup Figure 28. Ratio-metric Start-Up using Coupled
Sequence SS/TR Pins
CONSTANT SWITCHING FREQUENCY and TIMING RESISTOR (RT/CLK Pin)
The switching frequency of the TPS54388-Q1 is adjustable over a wide range from 200 kHz to 2000 kHz by
placing a maximum of 700 kΩand minimum of 85 kΩ, respectively, on the RT/CLK pin. An internal amplifier
holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The
RT/CLK is typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in
Figure 5 or Equation 9.
(9)
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(10)
To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of
the efficiency, maximum input voltage and minimum controllable on time should be considered.
The minimum controllable on time is typically 60 ns at full current load and 120 ns at no load, and limits the
maximum operating input voltage or output voltage.
OVERCURRENT PROTECTION
The TPS54388-Q1 implements a cycle by cycle current limit. During each switching cycle the high side switch
current is compared to the voltage on the COMP pin. When the instantaneous switch current intersects the
COMP voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low,
the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier
output is clamped internally. This clamp functions as a switch current limit.
FREQUENCY SHIFT
To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS54388-Q1
implements a frequency shift. If frequency shift was not implemented, during an overcurrent condition the low
side MOSFET may not be turned off long enough to reduce the current in the inductor, causing a current
runaway. With frequency shift, during an overcurrent condition the switching frequency is reduced from 100%,
then 50%, then 25%, as the voltage decreases from 0.800 to 0 volts on VSENSE pin to allow the low side
MOSFET to be off long enough to decrease the current in the inductor. During start-up, the switching frequency
increases as the voltage on VSENSE increases from 0 to 0.800 volts. See Figure 6 for details.
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SYNCClock=2V/div
PH=2V/div
Time=500nsec/div
Clock
Source
PLL
RT
RT/CLK
TPS54388-Q1
TPS54388-Q1
www.ti.com
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
REVERSE OVERCURRENT PROTECTION
The TPS54388-Q1 implements low side current protection by detecting the voltage across the low side
MOSFET. When the converter sinks current through its low side FET, the control circuit turns off the low side
MOSFET if the reverse current is typically more than 4.5 A. By implementing this additional protection scheme,
the converter is able to protect itself from excessive current during power cycling and start-up into pre-biased
outputs.
SYNCHRONIZE USING THE RT/CLK PIN
The RT/CLK pin is used to synchronize the converter to an external system clock. See Figure 29. To implement
the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on time of at least
75ns. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a
synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the
internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to the frequency set
by the resistor. The square wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V
typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of the PH is
synchronized to the falling edge of RT/CLK pin.
Figure 29. Synchronizing to a System Clock Figure 30. Plot of Synchronizing to System Clock
POWER GOOD (PWRGD PIN)
The PWRGD pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage enters
the fault condition by falling below 91% or rising above 109% of the nominal internal reference voltage. There is
a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93%
or falls below 107% of the internal voltage reference the PWRGD output MOSFET is turned off. It is
recommended to use a pull-up resistor between the values of 1kΩand 100kΩto a voltage source that is 6 V or
less. The PWRGD is in a valid state once the VIN input voltage is greater than 1.1 V.
OVERVOLTAGE TRANSIENT PROTECTION
The TPS54388-Q1 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output
overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold which is 109%
of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high side
MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the
VSENSE voltage drops lower than the OVTP threshold the high side MOSFET is allowed to turn on the next
clock cycle.
THERMAL SHUTDOWN
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 168°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 148°C, the device reinitiates the power up sequence
by discharging the SS pin to below 60 mV. The thermal shutdown hysteresis is 20°C.
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS54388-Q1
VSENSE
COMP
VO
R1
R3
C1
C2 R2
C0 R0
gm
245 µA/V
0.800 V
Power Stage
25 A/V
PH
RESR
COUT
RL
b
a
c
TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
www.ti.com
SMALL SIGNAL MODEL FOR LOOP RESPONSE
Figure 31 shows an equivalent model for the TPS54388-Q1 control loop which can be modeled in a circuit
simulation program to check frequency response and dynamic load response. The error amplifier is a
transconductance amplifier with a gm of 245 μA/V. The error amplifier can be modeled using an ideal voltage
controlled current source. The resistor R0 and capacitor Co model the open loop gain and frequency response of
the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the
frequency response measurements. Plotting a/c shows the small signal response of the frequency compensation.
Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by
replacing the RLwith a current source with the appropriate load step amplitude and step rate in a time domain
analysis.
Figure 31. Small Signal Model for Loop Response
SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL
Figure 31 is a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54388-Q1 power stage can be approximated to a voltage controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 11 and consists of a dc gain, one dominant pole and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node c in Figure 31) is the power stage
transconductance. The gm for the TPS54388-Q1 is 25 A/V. The low frequency gain of the power stage frequency
response is the product of the transconductance and the load resistance as shown in Equation 12. As the load
current increases and decreases, the low frequency gain decreases and increases, respectively. This variation
with load may seem problematic at first glance, but the dominant pole moves with load current [see Equation 13].
The combined effect is highlighted by the dashed line in the right half of Figure 32. As the load current
decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same
for the varying load conditions which makes it easier to design the frequency compensation.
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vertical spacer
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Vref
VO
R1
R3
C1
C2
R2 CO
5pF
RO
gmea COMP
VSENSE
Type 2A Type 2B
R3
C1
¦´ ´ p
OUT ESR
1
z =
C R 2
¦´ ´ p
OUT L
1
p = C R 2
ps L
Adc = gm R´
s
1+ 2 × z
vo = Adc
vc s
1+ 2 × p
æ ö
ç ÷
p ¦
è ø
´æ ö
ç ÷
p ¦
è ø
VO
RL
VC
fp
fz
Adc
gmps
RESR
COUT
TPS54388-Q1
www.ti.com
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
Figure 32. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
(11)
(12)
(13)
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(14)
SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION
The TPS54388-Q1 uses a transconductance amplifier for the error amplifier and readily supports two of the
commonly used frequency compensation circuits. The compensation circuits are shown in Figure 33. The Type 2
circuits are most likely implemented in high bandwidth power supply designs using low ESR output capacitors. In
Type 2A, one additional high frequency pole is added to attenuate high frequency noise.
Figure 33. Types of Frequency Compensation
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Product Folder Link(s): TPS54388-Q1
´OUT
Resr C
C2 =
R3
´
L OUT
R C
C1 =
R3
¦´ ´ p
OUT L
1
p = C R 2
p ¦ ´ ´
´ ´
OUT
ea ps
2 × c Vo C
R3 = gm Vref gm
¦
¦ ¦ ´
C
sw
= p mod 2
¦ ¦ ´ ¦
C= p mod z mod
¦p ´ ´
1
z m od =
2 Resr Cout
¦p ´ ´
Iout max
p mod = 2 Vout Cout
TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
www.ti.com
The design guidelines for TPS54388-Q1 loop compensation are as follows:
1. The modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 15 and Equation 16.
Derating the output capacitor (COUT) may be needed if the output voltage is a high percentage of the
capacitor rating. Use the capacitor manufacturer information to derate the capacitor value. Use Equation 17
and Equation 18 to estimate a starting point for the crossover frequency, fc. Equation 17 is the geometric
mean of the modulator pole and the esr zero and Equation 18 is the mean of modulator pole and the
switching frequency. Use the lower value of Equation 17 or Equation 18 as the maximum crossover
frequency.
(15)
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(16)
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(17)
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(18)
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2. R3 can be determined by
(19)
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Where is the gmea amplifier gain (245 μA/V), gmps is the power stage gain (25 A/V).
3. Place a compensation zero at the dominant pole . C1 can be determined by
(20)
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4. C2 is optional. It can be used to cancel the zero from Co’s ESR.
(21)
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TPS54388RTE
TPS54388-Q1
www.ti.com
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
APPLICATION INFORMATION
DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE
This example details the design of a high frequency switching regulator design using ceramic output capacitors.
This design is available as the HPA375 evaluation module (EVM). A few parameters must be known in order to
start the design process. These parameters are typically determined on the system level. For this example, we
start with the following known parameters:
Output Voltage 1.8 V
Transient Response 1 to 2A load step ΔVout = 5%
Maximum Output Current 3 A
Input Voltage 5 V nom. 3 V to 5 V
Output Voltage Ripple < 30 mV p-p
Switching Frequency (Fsw) 1000 kHz
SELECTING THE SWITCHING FREQUENCY
The first step is to decide on a switching frequency for the regulator. Typically, you want to choose the highest
switching frequency possible since this produces the smallest solution size. The high switching frequency allows
for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. However, the highest switching frequency causes extra switching losses, which hurt the converter’s
performance. The converter is capable of running from 200 kHz to 2 MHz. Unless a small solution size is an
ultimate goal, a moderate switching frequency of 1MHz is selected to achieve both a small solution size and a
high efficiency operation. Using Equation 9, R5 is calculated to be 180 kΩ. A standard 1% 182 kΩvalue was
chosen in the design.
Figure 34. High Frequency, 1.8 V Output Power Supply Design with Adjusted UVLO
OUTPUT INDUCTOR SELECTION
The inductor selected works for the entire TPS54388-Q1 input voltage range. To calculate the value of the output
inductor, use Equation 22. KIND is a coefficient that represents the amount of inductor ripple current relative to the
maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high
inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a
ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at
the discretion of the designer; however, KIND is normally from 0.1 to 0.3 for the majority of applications.
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 21
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2 Iout
Co >
sw Vout
´ D
¦ ´ D
Iripple
ILpeak = Iout + 2
æ ö
´ -
´ç ÷
´ ´ ¦
è ø
2
21 Vo (Vinmax Vo)
ILrms = Io + 12 Vinmax L1 sw
-´´ ¦
Vinmax Vout Vout
Iripple = L1 Vinmax sw
-´
´ ´ ¦
Vinmax Vout Vout
L1 =
Io Kind Vinmax sw
TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
www.ti.com
For this design example, use KIND = 0.3 and the inductor value is calculated to be 1.36 μH. For this design, a
nearest standard value was chosen: 1.5 μH. For the output filter inductor, it is important that the RMS current
and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from
Equation 24 and Equation 25.
For this design, the RMS inductor current is 3.01 A and the peak inductor current is 3.72 A. The chosen inductor
is a Coilcraft XLA4020-152ME_. It has a saturation current rating 0f 9.6 A and a RMS current rating of 7.5 A.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
(22)
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(23)
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(24)
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(25)
OUTPUT CAPACITOR
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning
from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the
change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor
must be sized to supply the extra current to the load until the control loop responds to the load change. The
output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing
a tolerable amount of droop in the output voltage. Equation 26 shows the minimum output capacitance necessary
to accomplish this.
For this example, the transient load response is specified as a 5 % change in Vout for a load step from 0 A (no
load) to 1.5 A (50% load). For this example, ΔIout = 1.5-0 = 1.5 A and ΔVout= 0.05 × 1.8 = 0.090 V. Using these
numbers gives a minimum capacitance of 33 μF. This value does not take the ESR of the output capacitor into
account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this
calculation.
Equation 27 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. Under this requirement,
Equation 27 yields 2.3 uF.
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(26)
22 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS54388-Q1
Ioutmax 0.25
Vin =
Cin sw
´
D´ ¦
( )
Vinmin Vout
Vout
Icirms = Iout Vinm in Vinmin
-
´ ´
´ -
´ ´ ´ ¦
Vout (Vinmax Vout)
Icorms = 12 Vinmax L1 sw
Voripple
Resr < Iripple
1 1
Co > Voripple
8 sw
Iripple
´
´ ¦
TPS54388-Q1
www.ti.com
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
vertical spacer
Where ΔIout is the change in output current, Fsw is the regulators switching frequency and ΔVout is the
allowable change in the output voltage. (27)
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Equation 28 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 28 indicates the ESR should be less than 55 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 55 mΩ.
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, two 22 μF 10 V X5R ceramic capacitors with 3 mΩof ESR are used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 29 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 29 yields
333 mA.
(28)
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(29)
INPUT CAPACITOR
The TPS54388-Q1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7
μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any
DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54388-
Q1. The input ripple current can be calculated using Equation 30.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the
maximum input voltage. For this example, one 10 μF and one 0.1 μF 10 V capacitors in parallel have been
selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage
ripple can be calculated using Equation 31. Using the design example values, Ioutmax=3 A, Cin=10 μF, Fsw=1
MHz, yields an input voltage ripple of 76 mV and a rms input ripple current of 1.47 A.
(30)
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(31)
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TPS54388-Q1
( ) ( ) ( )
Voutmax 1 Offtimemax Fsmax Vinmin Ioutmax 2 RDS Ioutmax RL RDS= - ´ ´ - ´ ´ - ´ +
( ) ( )
Voutmin Ontimemin Fsmax Vinmax Ioutmin 2 RDS Ioutmin RL RDS= ´ ´ - ´ ´ - ´ +
-
Vref
R7 = R6
Vo Vref
Tss(ms) Iss( A)
Css(nF) = Vref(V)
´ m
TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
www.ti.com
SLOW START CAPACITOR
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is large and would require large amounts of current to quickly charge the
capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54388-Q1 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow start capacitor value can be calculated using Equation 32. For the example circuit, the slow start time is
not too critical since the output capacitor value is 44 μF which does not require much current to charge to 1.8 V.
The example circuit has the slow start time set to an arbitrary value of 4ms which requires a 10 nF capacitor. In
TPS54388-Q1, Iss is 2.2 μA and Vref is 0.800 V.
(32)
BOOTSTRAP CAPACITOR SELECTION
A 0.1 μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or
higher voltage rating.
OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION
For the example design, 100 kΩwas selected for R6. Using Equation 33, R7 is calculated as 80 kΩ. The nearest
standard 1% resistor is 80.5 kΩ.
(33)
Due to the internal design of the TPS54388-Q1, there is a minimum output voltage limit for any given input
voltage. The output voltage can never be lower than the internal voltage reference of 0.827 V. Above 0.827 V,
the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case
is given by Equation 34
Where:
Voutmin = minimum achievable output voltage
Ontimemin = minimum controllable on-time (65 ns typical. 120 nsec no load)
Fsmax = maximum switching frequency including tolerance
Vinmax = maximum input voltage
Ioutmin = minimum load current
RDS = minimum high side MOSFET on resistance (15 - 19 mΩ)
RL = series resistance of output inductor (34)
There is also a maximum achievable output voltage which is limited by the minimum off time. The maximum
output voltage is given by Equation 35
Where:
Voutmax = maximum achievable output voltage
Offtimeman = maximum off time (60 nsec typical)
Fsmax = maximum switching frequency including tolerance
Vinmin = minimum input voltage
Ioutmax = maximum load current
RDS = maximum high side MOSFET on resistance (19 - 30 mΩ)
RL = series resistance of output inductor (35)
24 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS54388-Q1
´Ro Co
C3 =
R3
gm
2 × c Vo Co
R3 = Gm Vref VI
p ¦ ´ ´
´ ´
¦
¦ ¦ ´
C
sw
= p mod 2
¦ ¦ ´ ¦
C= p mod z mod
¦p ´ ´
1
z m od =
2 Resr Cout
¦p ´ ´
Iout max
p mod = 2 Vout Cout
TPS54388-Q1
www.ti.com
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
COMPENSATION
There are several industry techniques used to compensate DC/DC regulators. The method presented here is
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between
60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to
the TPS54388-Q1. Since the slope compensation is ignored, the actual cross over frequency is usually lower
than the cross over frequency used in the calculations.
To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 36 and
Equation 37. For Cout, derating the capacitor is not needed as the 1.8 V output is a small percentage of the 10 V
capacitor rating. If the output is a high percentage of the capacitor rating, use the capacitor manufacturer
information to derate the capacitor value. Use Equation 38 and Equation 39 to estimate a starting point for the
crossover frequency, fc. For the example design, fpmod is 6.03 kHz and fzmod is 1210 kHz. Equation 38 is the
geometric mean of the modulator pole and the esr zero and Equation 39 is the mean of modulator pole and the
switching frequency. Equation 38 yields 85.3 kHz and Equation 39 gives 54.9 kHz. Use the lower value of
Equation 38 or Equation 39 as the approximate crossover frequency. For this example, fc is 56 kHz. Next, the
compensation components are calculated. A resistor in series with a capacitor is used to create a compensating
zero. A capacitor in parallel to these two components forms the compensating pole (if needed).
(36)
vertical spacer
(37)
vertical spacer
(38)
vertical spacer
(39)
vertical spacer
The compensation design takes the following steps:
1. Set up the anticipated cross-over frequency. Use Equation 40 to calculate the compensation network’s
resistor value. In this example, the anticipated cross-over frequency (fc) is 56 kHz. The power stage gain
(gmps) is 25 A/V and the error amplifier gain (gmea) is 245 μA/V.
(40)
2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The compensation
network’s capacitor can be calculated from Equation 41.
(41)
3. An additional pole can be added to attenuate high frequency noise. In this application, it is not necessary to
add it.
From the procedures above, the compensation network includes a 7.68 kΩresistor and a 3300 pF capacitor.
APPLICATION CURVES
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TPS54388-Q1
V =2V/div
IN
EN=1V/div
SS=1V/div
V =1V/div
OUT
Time=500 s/divm
V =2V/div
IN
EN=1V/div
SS=1V/div
V =1V/div
OUT
Time=5ms/div
1.05V 1.2V 1.5V
1.8V 2.5V
50
55
60
65
70
75
80
85
90
95
100
Efficience-%
0 0.5 1 1.5 2 2.5 3
I -OutputCurrent- A
O
50
55
60
65
70
75
80
85
90
95
100
0 0.5 1 1.5 2 2.5 3
I -OutputCurrent- A
O
1.05V
1.2V
1.5V
1.8V
2.5V
3.3V
Efficience-%
40
50
60
70
80
90
0
10
20
30
100
Efficiency - %
0 0.5 2 2.5 3
Output Current - A
1 1.5
5 Vin, 1.8 Vout
3.3 Vin,1.8 Vout
3.3 Vin,1.8 Vout 5 Vin, 1.8 Vout
0.001 0.01 0.1 1 10
Output Current - A
0
10
20
30
40
50
60
70
80
90
100
Efficiency - %
TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
www.ti.com
EFFICIENCY EFFICIENCY
vs vs
LOAD CURRENT LOAD CURRENT
Figure 35. Figure 36.
EFFICIENCY EFFICIENCY
vs vs
LOAD CURRENT LOAD CURRENT
1 MHz, 3.3 VIN, TA= 25°C 1 MHz, 5 VIN, TA= 25°C
Figure 37. Figure 38.
POWER UP VOUT, VIN POWER DOWN VOUT, VIN
Figure 39. Figure 40.
26 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS54388-Q1
10 100 1000 10k 100k 1M
Frequency - Hz
–60
Gain - dB
50
40
30
20
10
0
–10
–20
–30
–40
–50
60
Phase - Degrees
150
120
90
60
30
0
–30
–60
–90
–120
–150
–180
180
Phase
Gain
Vin=100mV/div(accoupled)
PH=2V/div
Time=500nsec/div
Vin=5V/div
Vout=2V/div
EN=2V/div
PWRGD=5V/div
Time=5msec/div
Vout=20mV/div(accoupled)
PH=2V/div
Time=500nsec/div
Vout=100mV/div(accoupled)
Iout=1 A /div(0 A to1.5 A loadstep)
Time=200usec/div
Vin=5V/div
Vout=2V/div
EN=2V/div
PWRGD=5V/div
Time=5msec/div
TPS54388-Q1
www.ti.com
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
TRANSIENT RESPONSE, 1.5 A STEP POWER UP VOUT, VIN
Figure 41. Figure 42.
POWER UP VOUT, EN OUTPUT RIPPLE, 3 A
Figure 43. Figure 44.
INPUT RIPPLE, 3 A CLOSED LOOP RESPONSE, VIN (5 V), 3 A
Figure 45. Figure 46.
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TPS54388-Q1
Vin = 3.3 V
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
Output Voltage Deviation - %
0 0.5 2 2.5 3
Output Current - A
1 1.5
Vin = 5 V
3 3.5 5 6
Input Voltage-V
Iout = 2 A
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
Output Voltage Deviation - %
4 . 5 5.54
TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
www.ti.com
LOAD REGULATION REGULATION
vs vs
LOAD CURRENT INPUT VOLTAGE
Figure 47. Figure 48.
POWER DISSIPATION ESTIMATE
The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM)
operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching
loss (Psw), gate drive loss (Pgd) and supply current loss (Pq).
Pcon = Io2× RDS(on)_Temp
Pd = ƒsw × Io × 0.7 × 60 × 10–9
Psw = 1/2 × Vin × Io × ƒsw× 8 × 10–9
Pgd = 2 × Vin × ƒsw× 2 × 10–9
Pq = Vin × 515 × 10–6
Where:
IOis the output current (A).
RDS(on)_Temp is the on-resistance of the high-side MOSFET with given temperature (Ω).
Vin is the input voltage (V).
ƒsw is the switching frequency (Hz).
So
Ptot = Pcon + Pd + Psw + Pgd + Pq
For given TA,
TJ= TA+ Rth × Ptot
For given TJMAX = 150°C
TAMAX = TJMAX – Rth × Ptot
Where:
Ptot is the total device power dissipation (W).
TAis the ambient temperature (°C).
TJis the junction temperature (°C).
Rth is the thermal resistance of the package (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
28 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS54388-Q1
TPS54388-Q1
www.ti.com
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace
resistance that impact the overall efficiency of the regulator.
LAYOUT
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. Care should be taken to minimize the loop area formed by the
bypass capacitor connections and the VIN pins. See Figure 49 for a PCB layout example. The GND pins and
AGND pin should be tied directly to the power pad under the IC. The power pad should be connected to any
internal PCB ground planes using multiple vias directly under the IC. Additional vias can be used to connect the
top side ground area to the internal planes near the input and output capacitors. For operation at full rated load,
the top side ground area along with any additional internal ground planes must provide adequate heat dissipating
area.
Locate the input bypass capacitor as close to the IC as possible. The PH pin should be routed to the output
inductor. Since the PH connection is the switching node, the output inductor should be located close to the PH
pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The boot capacitor
must also be located close to the device. The sensitive analog ground connections for the feedback voltage
divider, compensation components, slow start capacitor and frequency set resistor should be connected to a
separate analog ground trace as shown. The RT/CLK pin is particularly sensitive to noise so the RT resistor
should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external
components can be placed approximately as shown. It may be possible to obtain acceptable performance with
alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): TPS54388-Q1
VIN
VIN
VIN
GND
EN
GND
VSENSE
SS
PH
PH
PH
PWRGD
BOOT
RT/CLK
COMP
AGND
PH
BOOT
CAPACITOR
VOUT
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
SLOW START
CAPACITOR
COMPENSATION
NETWORK
TOPSIDE
GROUND
AREA
VIA to Ground Plane
FREQUENCY
SET
RESISTOR
ANALOG
GROUND
TRACE
VIN
INPUT
BYPASS
CAPACITOR
VIN
UVLO SET
RESISTORS
FEEDBACK
RESISTORS
VIA to
Ground
Plane
EXPOSED
POWERPAD
AREA
TPS54388-Q1
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
www.ti.com
Figure 49. PCB Layout Example
30 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS54388-Q1
TPS54388-Q1
www.ti.com
SLVSAF1B –OCTOBER 2010–REVISED JULY 2012
REVISION HISTORY
Changes from Revision A (June, 2011) to Revision B Page
• Removed (SWIFT™) from title. ............................................................................................................................................ 1
• Removed the last two sentences in the description containing SwitcherPro™ and SWIFT™ references. .......................... 1
• Removed last sentence of first paragraph, "Use SwitcherPro software for a more accurate design." ............................... 25
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): TPS54388-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 12-Jul-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS54388QRTERQ1 ACTIVE WQFN RTE 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS54388QRTERQ1 WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54388QRTERQ1 WQFN RTE 16 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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