© 2000 Fairchild Semiconductor Corporation DS009595 www.fairchildsemi.com
April 1988
Revised October 2000
74F821 10-Bit D-Type Flip-F lop
74F821
10-Bit D-Type Flip-Flop
General Description
The 74F821 is a 10-bit D-type flip-flop with 3-STATE true
outputs arranged in a broadside pinout.
Features
3-STATE Outputs
Ordering Code:
Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er “X” to the orderin g c ode.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F821SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F821SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F821
Unit Loading/Fan Out
Functional Description
The 74F821 consists of ten D-type edge-triggered flip-
flops. This device has 3-STATE true outputs for bus sys-
tems or ga nized i n a b ro adside pi nn ing. The buff ere d Cl ock
(CP) and buffered Output Enable (OE) are common to all
flip-flops. The flip-flops will store the state of their individual
D inputs that meet the setup and hold times requirements
on the LOW-to- HIGH CP transition. With th e OE LOW the
cont ent of th e flip-fl ops are availab le at the outputs. When
the OE is HIGH, the outputs go to the high impedance
state. Operatio n of the OE input does not affect the state of
the flip-f l ops.
Function Table
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immateri al
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
D0D9Data Inputs 1.0/1.0 20 µA/0.6 mA
OE Output Enable 1.0/1.0 20 µA/0.6 mA
3-STATE Input
CP Clock Input 1.0/1.0 20 µA/0.6 mA
O0O93-STATE Outputs 150/40 (33.3) 3.0 mA/24 mA (20 mA)
Inputs Internal Output Function
OE CP D Q O
H H X NC Z Hold
H L X NC Z Hold
H
L H Z Load
H
H L Z Load
L
L H L Data Available
L
H L H Data Available
L H X NC NC No Change in Data
L L X NC NC No Change in Data
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74F821
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Eith er v oltage lim it or c urrent limit is sufficie nt to protect inputs.
DC Electrical Characteristics
Storage Temperature 65°C to +150°C
Ambient Temper atu re und er Bias 55°C to +125°C
Junction Temperature under Bias 55°C to +150°C
VCC Pin Potential to Ground Pin 0.5V to +7.0V
Input Voltage (Note 2) 0.5V to +7.0V
Input Current (Note 2) 30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standa rd Outp ut 0.5V to VCC
3-STATE Output 0.5V to +5.5V
Current Applied to Output
in LOW State (Ma x) twice the rat ed IOL (mA)
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units VCC Conditions
VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal
VCD Input Clamp Diode Voltage 1.2 V Min IIN = 18 mA
VOH Output HIGH 10% VCC 2.5
VMin
IOH = 1 mA
Voltage 10% VCC 2.4 IOH = 3 mA
5% VCC 2.7 IOH = 1 mA
5% VCC 2.7 IOH = 3 mA
VOL Output LOW Voltage 10% VCC 0.5 V Min IOL = 24 mA
IIH Input HIGH Current 5.0 µAMaxV
IN = 2.7 V
IBVI Input HIGH Current 7.0 µAMaxV
IN = 7.0 V
Breakdown Test
ICEX Output HIGH 50 µAMaxV
OUT = VCC
Leakage Current
VID Input Leakage 4.75 V 0.0 IID = 1.9 µA,
Test All Other Pins Grounded
IOD Output Leakage 3.75 µA0.0
VIOD = 150 mV
Circuit Current All Other Pins Grounded
IIL Input LOW Current 0.6 mA Max VIN = 0.5V
IOZH Output Leakage Current 50 µAMaxV
OUT = 2.7V
IOZL Output Leakage Current 50 µAMaxV
OUT = 0.5V
IOS Output Short-Circuit Current 60 150 mA Max VOUT = 0V
ICCZ Power Supply Current 78 100 mA Max VO = HIGH Z
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74F821
AC Electrical Characteristi cs
AC Operating Requirements
Symbol Parameter
TA = +25°CT
A = 55°C to +125°CT
A = 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF CL = 50 pF
Min Typ Max Min Max Min Max
fMAX Maximum Clock Frequency 100 150 60 70 MHz
tPLH Propagation Delay 2.0 6.4 9.5 2.0 10.5 2.0 10.5 ns
tPHL CP to On2.0 6.2 9.5 2.0 10.5 2.0 10.5
tPZH Output Enable Time 2.0 5.8 10.5 2.0 13.0 2.0 11.5
tPZL OE to On2.0 6.3 10.5 2.0 13.0 2.0 11.5 ns
tPHZ Output Disable Time 1.5 3.4 7.0 1.0 7.5 1.5 7.5
tPLZ OE to On1.53.57.01.07.51.57.5
Symbol Parameter
TA = +25°CT
A = 55°C to +125°CT
A = 0°C to +70°C
UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V
Min Max Min Max Min Max
tS(H) Setup Time, HIGH or LOW 2.5 4.0 3.0
tS(L) Dn to CP 2.5 4.0 3.0 ns
tH(H) Hold Time, HIGH or LOW 2.5 2.5 2.5
tH(L) Dn to CP 2.5 2.5 2.5
tW(H) CP Pulse Width 5.0 6.0 6.0 ns
tW(L) HIGH or LOW 5.0 6.0 6.0
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74F821
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
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74F821 10-Bit D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N24C
Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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to perform when properly used in accordance with
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user.
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