General Description The MAX177 is a complete CMOS sampling 10-bit analog-to-digital converter (ADC) that combines an on-chip track-and-hold and voltage reference along with high conversion speed and low power consump- tion. A conversion time of 8.33s includes settling time for the track-and-hold. An internal buried zener refer- ence provides low drift with low noise. The MAX177 accepts -2.5V to +2.5V inputs. External components are limited to only decoupling capacitors for the power supply and reference voltages. On-chip clock circuitry can either be driven from an external clock source or a crystal. The MAX177 employs a standard microprocessor inter- face. Three-state data outputs can be configured for 8- or 12-bit data buses. Data access and bus release timing specs are compatible with most popular micro- processors without resorting to wait states. __ Applications Digital Signal Processing (DSP) Audio and Telecom Processing High Accuracy Process Control High Speed Data Acquisition Functional Diagram 1k TRAGK-HOLD arn AM MAAIL/VI CMOS 10-Bit A/D Converter with Track-and-Hold Features @ = 12-Bit Resolution and 10-Bit Linearity @ 8.338 Conversion Time @ = Internal Analog Track-Hold = 6MHz Full Power Bandwidth @ = On-Chip +40ppm/* C Voltage Reference @ High Input Resistance (500MM) @ 100ns Data Access Time @ = =180mW (Max) Power Consumption @ 24 Lead Narrow DIP and Wide SO Packages _ _._..__ Ordering Information PART TEMP. RANGE PACKAGE* ERROR MAXI7?7CNG orc te +70C Plastic DIP +1L58 MAX77CWG OPC to +70C Wide SOF 1 LSB MAX177C/D O'Cto 170C Dice* +1LS8 MAXI77ENG = -40C 10 +86Cs~Plastic DIF =1 LSB MAXI77EWG -40C to +85C = Wide SO =) LSB: [MAX177MRG 86C to +125C CERDIP +1LSB * All devices 24 lead packages ** Consult factory for dice specifications. C&P Coorfiguration Top View anc? bel REFEREWCL | 24 Vag Vecr 2] 23] Vss SUCCESSIVE 23 Vse _ AAR APPRORIMATION + [ AGNO DY BUSY MAXIT7 ou i] 6S ow EJ [0] AD ze ; 1 og 09 & eM 41 AL Zed ri | HBEN CONTR | ti Too BO MAX177 m2] CLK OUT 8 a rls. oy (5 P7] CLK IN 4 anal eal [om yo 06 re] 00/8 THREE- ss fe 1 8 oe aur 05 Le] Pe) O19 STATE Ht THREE-3 TATE | cuack . nares quTPUT psciuuaToa LE ik aw 4 Ps] 02/10 DAIVERS a) gay : = pono [e] Pa) 931 fe? je fu 12 [a [is asa Oe DGHD AVIAXL/I _. - Maxim integrated Products 1 AAaxias is a registered trademark of Maxim (ntegrated Products. ZLiXVIMAX177 CMOS 10-Bit A/D Converter with Track-and-Hold ABSOLUTE MAXIMUM RATINGS Von to DGND ....... eee. -O.8V to +7 Operating Temperature Ranges Vss tODGND o.oo. eee eee ee FOLSY to -17V MAXI7T7G oo. eee eee tee 0 to +70C AGND to OGND ...............0..0.-- -0.3V 10 Vpp +0.8V MAXITTE 2.0... eee ee eee -40C to +B5C AINto AGND .. 0... eee eee ee -15V ta +18V MAXMIT7M 2.0. eee eee eee eee -55C to +126C Digital input Voltage te DGND ........ -O.8V to Vop + 0.3V Storage Temperature Range ............ -65G to + 160C (Pins 17, 19-21) Power Dissipation (any Package) even . 1000mw Digital Output Voltage to DGND ........ -0.3V ta Vop +0.3V Derates Above +75C by ..0-... ee eee eee 10mW/? C (Pins 4-11, 13-16, 18, 22) Lead Temperature (Soldering 10 seconds) ........ 1300C Stresses above those listed under Absolute Maximum Rafings may causa permanent damage to the device, These ara stress ratings ently, and funetiona! operation af the device a? these of any other conditions above ihosa indicated in the operational sections of tha specifications is not implied. Exposure to abscluie maximum rating conditions for extended periods may affect device retiability. ELECTRICAL CHARACTERISTICS (Vop = +5V 15%, Vas = -11.4V to -15.75V, Slow Memory Mode, Ta = Twin to Twax, fork = 1.5MHz unless otherwise noted ) PARAMETER | SYMBOL | CONDITIONS | MIN FYP MAX | UNITS ACCURACY Resolution 12 Bits No Missing Code Resolution 10 Bits integral Non-Linearity INL 0.05 %oFSR Offset Error (Note 1) +3 mv Full Seale Error (Note 2) Ta = 25C, Includes Reference Error +0.4 MN Full Scale Tempca (Notes 3, 4) Excludes Internal Reference Drift +5 poms cS Conversion Time tconv Synchronous {13 clock cycies) ae Ss DYNAMIC ACCURACY {Vo0 = 5V, Vss = 15, Sampie Alate = 100kHz} Signat to Noise and SAN+D} | 10kHz Input Signal , Ta = 25C 64 dB Total Harmonic Distortion THD | 10KHz Input Signal, Ta = 25C A |B Staious Noles or 10kHz Input Signal, Ta = 25C -72 | dB Full Power In Sample Mode, 6 MHz Sampling Bandwidth Under-Sampled Waveform ANALOG INPUT Input Voliage Range 25 +295 V Input Leakage Current 45 LA Input Capacitance (Nate 4) 20 pF Track-Hold ; ; bs Acquisition Time REFERENCE Vaer Output Valtage Ta - 25C 4.98 -.00 -.02 Vv Vaer Output Tempco (Note 5} 4145) |ppm/?c Reference Load Sensitivity Tear Loa Change: OtoSmA 0.005 0.02 | %/mA Output Sink Current mA fU AXACMOS 10-Bit A/D Converter with Track-and-Hold ELECTRICAL CHARACTERISTICS (continued) = (Von = +5V 5%, Veg = -11.4V ta -15.75V, Slow Memory Mode, Ts = Twin to Tuax, fork = 1.5MHz unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN] =TYP = MAX | UNITS > LOGIC INPUTS oll, Input Low Voltage ViL CS. RD. HBEN, CLK IN 0.8 Vv J Input High Veitage Vin | GS, RO. HBEN. CLK IN 24 a | Input Capacitance (Note 4) Cin | CS. RD, HBEN, CLK IN ; 10 pF Input Current ling Vin = OV to Von CS, FO CIN, 30 pA LOGIC OUTPUTS D11-D0/8, BUSY, CLK OUT Output Low Voltage You Ian ~ LMA 0.4 v . B11-D0/a, BUSY, CLK OUT Output High Voltage V ' , 4 v ues 4 OF | Nsource = 200HA Three-State _ Leakage Current I | D11-DO/8, Vgyy = OV to Von +10 pA Three-State Output Capacitance (Note 4) Cg 8 pF POWER REQUIREMENTS Postive Supply Voltage Von +5% For Specified Performance 5 Vv Negative Supply Voltage Ves 5% For Specified Performance -12 -15 Vv - adi FS Change, Veg = -15 or -12V Positive Supply Rejection Vis 2 4.75 to 8 25V 7 10.01 Me FS Change, Vp5p = 5V Negative Supply Rejection Veg = -14.24 to -15.75V +0.01 %o Veg = 711.4 te -12 BV Positive Supply Current lop CS - RD - Vpn, AIN = 5V 4 6 mA Negative Supply Current Isc CS=RD= Vpp. AIN = 5V f 10 mA Power Dissipation Vop = +BY, Veg = -12V 104 150 mw Note 1: Note 2: Note 3: Note 4: Typical change over temp is ~imV. Ideal last code transition = FS -1.8mV LSB, agjusted for offset. Full Scale Tempca dF S/dT, where dFS is full scale change from Ta = 25C to Tain Or Twax. Guaranteed by design, not subject to test. Note 5: Veer Teripco = dVper//d7, where dVrer is reference voltage change trom Ta 25C to Tain Tmax. Note 6: All input control signals are specified with t, = t = Sns (10% to 90% of +5V) and timed from a voltage level of +1.6V Note 7: This specification is 100% production tested. Note &: t; and ts are measured with the load circuits of Figure 1 and defined as the time required for an output ta cross 0.8V or 2.4V. Note 8: t; is defined as the time required for the data line to change 0.5V when loaded with the circuits of Figure 2. For additional information on using the MAX177, please refer to MAX163/164/167 data sheet. VIA XALsIMAX177 CMOS 10-Bit A/D Converter with Track-and-Hold TIMING CHARACTERISTICS (Vpp = +5V, Vsg = -12V or -15, Ta = Fin to Trax, Note 6, specifications in bold type are 100% tested, others are quaranteed by design, uniess otherwise noted } Ta = 25C MAXIT7C/E MAX177M PARAMETER SYMBOL CONDITIONS MIN TYP MAX | MIN MAX | MIN MAX| UNITS CS te AD Setup Time t, 0 0 a ns (Note ad Delay tp [CL = 50pF go 170 220 260 | ns Data Access Time - (Notes 7, 8) ty CL = 100pF 50 100 130 150 ns RD Pulse Width 1 100 130 150 ns CS to RD Hold Time ts Q 0 O ns Data Setup Time After t BUSY (Notes 7.8) 6 40 80 105 420) ons Bus Relinquish Time t (Notes 7, 9} ? 30 50 65 75 ns HBEN to RD Setup Time te Q Q fons HBEN te RD Hold Time tg 0 0 ns Delay Between t READ Operations 9 200 200 200 ns Delay Between Conversions tn 1 1 1 Hs Aperture Delay tis Jitter < 509s 25 ns OGD OBN aka T CL a. High-Z to Vou (ta) and Vor to Vou fta) GY aka DBN I CL DGND b. Aigh-Z to Voy ftg) and Vou to Vor (ta) Figure 7. Load Circuits for Access Time OBN 3k : i pF OGNO a Vou to High Z 08H T tOpF ako DGND b. Vaz to High-2 Figure 2. Load Circuits for Bus Relinguish Time Moxim cannot assume responsibility for use of any crciitry offer than circuitry entirely embodied in a Maxim product. No cincuil patent licenses ave wiplipa. Afavirn reserves ite right to change the circuriry and specifications without notice at any time. __ #VLA XL FI