6ES5948-3UA12 - SIEMENS - Datasheet.Directory

Contents

Introduction 1

User Program 2

Program Execution 3

Operating Statuses and Program

Execution Levels 4

Interrupt and Error Diagnostics 5

Integrated Special Functions 6

Extended Data Block DX 0 7

Memory Assignment and Memory

Organization 8

Memory Access Using Absolute

Addresses 9

Multiprocessor Mode and Com-

munication in the S5-155U 10

PG Interfaces and Functions 11

Appendix 12

Indexes:

Abbreviations

Key Words 13

The List of Operations, order no.

6ES5 997-3UA22, is included

with this manual.

10/98

C79000-G8576-C848

Release 04

S5-155U

CPU 948

Programming Guide

This manual has the order number:

6ES5 998–3PR21

SIMATIC S5

!Danger

indicates that death, severe personal injury or substantial property damage will result if proper precautions are not

taken.

!Warning

indicates that death, severe personal injury or substantial property damage can result if proper precautions are not

taken.

!Caution

indicates that minor personal injury or property damage can result if proper precautions are not taken.

Note

draws your attention to particularly important information on the product, handling the product, or to a particular

part of the documentation.

Qualified Personnel

The device/system may only be set up and operated in conjunction with this manual.

Only qualified personnel should be allowed to install and work on this equipment. Qualified persons are defined

as persons who are authorized to commission, to ground, and to tag circuits, equipment, and systems in accor-

dance with established safety practices and standards.

Correct Usage

Note the following:

!Warning

This device and its components may only be used for the applications described in the catalog or the technical

description, and only in connection with devices or components from other manufacturers which have been ap-

proved or recommended by Siemens.

This product can only function correctly and safely if it is transported, stored, set up, and installed correctly , and

operated and maintained as recommended.

Trademarks SIMATICR, SIMA TIC NETR and SIMA TIC HMIR are registered trademarks of SIEMENS AG. Third parties using

for their own purposes any other names in this document which refer to trademarks might infringe upon the rights

of the trademark owners.

We have checked the contents of this manual for agreement with the

hardware and software described. Since deviations cannot be

precluded entirely, we cannot guarantee full agreement. However ,

the data in this manual are reviewed regularly and any necessary

corrections included in subsequent editions. Suggestions for

improvement are welcomed.

E Siemens AG 1998

Subject to change without prior notice.

The reproduction, transmission or use of this document or its

contents is not permitted without express written authority.

Offenders will be liable for damages. All rights, including rights

created by patent grant or registration of a utility model or design, are

reserved.

Siemens AG

Bereich Automatisierungs- und Antriebstechnik

Geschaeftsgebiet Industrie-Automatisierungssysteme

Postfach 4848, D-90327 Nuernberg

Siemens Aktiengesellschaft 6ES5 998-3PR21

Safety Guidelines

This manual contains notices which you should observe to ensure your own personal safety , as well as to protect

the product and connected equipment. These notices are highlighted in the manual by a warning triangle and are

marked as follows according to the level of danger:

1 Introduc tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 3

1.1 Area of Appli c at io n for the S5-155U with the CPU 948 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 4

1.2 Typica l Mode of Opera tion of a CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 5

1.3 The Program s in a CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 7

1.4 Which Operands are availab le to the User Program?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 1 1

1.5 How much Memory is available for the User Progra m? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 14

1.6 How to Ta c kle Progra m ming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 15

1.7 Programming Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 18

1.8 Co nve rting User Programs of the CPU 928B for the CPU 948. . . . . . . . . . . . . . . . . . . . . . . . . 1 - 19

2 User Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3

2.1 STE P 5 Progra mming Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4

2.1. 1 The LAD, CSF, STL Me th ods of Re prese ntation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4

2.1.2 Structu red Programm ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 5

2.1.3 STEP 5 Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 6

2.1.4 Number Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 8

2.1.5 STEP 5 Blocks a nd Storing t hem in Memo ry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 12

2.2 P rogr am , Organiza tion and Se quence Block s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 1 6

2.2.1 Organization Blocks as User Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 18

2.2. 2 Orga ni z atio n Blocks fo r Spe cia l Funct ion s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 22

2.3 F unc tion Bl ocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 23

2.3. 1 St ructu re of Function Bl oc k s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 2 4

2.3.2 Programming Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 26

2.3.3 Calling Function Blocks and Assigning Parameters to them . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 28

2.3.4 Special Function Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 33

2.4 D ata Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 35

2.4.1 Creating Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 37

2.4.2 Opening Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3 8

2.4.3 Sp ec i al Data Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 41

Contents

CPU 948 Progra mming Gu ide

C79000-G8576-C848-04 iii

3 Pro g ram Execu tion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 3

3.1 Princ ip le of Progra m Exec uti on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 4

3.2 P rogr am Organiza t ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 5

3.3 Stori ng Progra m and Data Block s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 10

3.4 Processing the User Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 11

3.4.1 Defi nitio n of Te rm s used in Progra m Exec ut ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 12

3.5 ST E P 5 Operati ons with Examp le s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 15

3.5.1 Bas ic Operati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 19

3.5.2 Programming Examples in the STL, LAD and CSF Methods of Representation. . . . . . . . . . . 3 - 34

3.5.3 Supplementary Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 49

3.5.4 Executive Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 59

3.5. 5 Sem ap hore Ope rati ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 7 5

4 Opera ting Statuse s and Pro gr am Executi on Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 3

4.1 Program Execution Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 4

4.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 9

4.2.1 SOFT ST OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 9

4.2.2 HARD ST O P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 13

4.2.3 OVERALL RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 14

4.3 START-UP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 16

4.3.1 MANUAL and AUTO MATIC COLD RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 17

4.3.2 MANUAL and AUTO MATIC WARM RESTART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 18

4.3. 3 Comp arison bet wee n COLD RESTART and WARM RESTA RT . . . . . . . . . . . . . . . . . . . . . . . 4 - 21

4.3.4 RETENTIVE COLD RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 22

4.3. 5 Comp ar ison of COLD RESTA RT and RET ENT IVE COL D RESTART . . . . . . . . . . . . . . . . . 4 - 23

4.3. 6 Use r Int erfa ce s for Star t-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2 4

4.3.7 Extended AUTOMATIC WARM RESTART with the CPU 948 (HOT RESTART ). . . . . . . . . 4 - 27

4.3. 8 Interru pti ons during START-UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 28

4.4 RUN Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 29

4.4.1 Cyclic Progra m Exec ution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 3 0

4.4. 2 Specif ying T im e and Inte rrupt-Dr ive n Program Execu ti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 32

4.4.3 T im e- Controlled Program Exe c ution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 33

4.4. 4 Inte rrupt-Driv en Pr ogram Executio n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 41

5 Inter rupt and Err or Diagno stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 3

5.1 Fre qu ent Errors in the User Progra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 4

5.2 Erro r Inform atio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 5

5.3 P roc edure for Error Analysi s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 8

5.4 Control Bits and Interrupt Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 9

5.4.1 Control Bit s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 10

5.4.2 ISTACK Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1 4

5.4.3 Ex ample of Err or Diagnosis u sing the ISTACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 19

Contents

CPU 948 Prog ramming Gu id e

iv C79000-G8576-C848-04

5.5 Erro r Handling Using Orga niza tion Block s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 20

5.6 Ca use s o f Er ror and Reac ti ons of th e CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 23

5.6.1 OB 19: Callin g a Logic Block That Is Not Loa de d (KB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 2 4

5.6. 2 OB 19: Call ing a Data Bloc k That Is Not Loade d (KDB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 24

5.6.3 OB 23/24 , OB 28/29:Timeo ut Erro r (QVZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 25

5.6.4 OB 25: Addressing Error (ADF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 26

5.6. 5 OB 26: Cycl e T i me Exce ede d Error (ZYK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 27

5.6.6 OB 27: (Substitution Error SUF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 2 8

5.6. 7 OB 30: Pa rity Error and Time out Err or in the User Memor y (PAR E) . . . . . . . . . . . . . . . . . . . 5 - 28

5.6.8 OB 32: Load and Transfer Error (TRAF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 29

5.6. 9 OB 33: Collision o f Time d Interrupts Error (WEFES/WEFEH ) . . . . . . . . . . . . . . . . . . . . . . . . 5 - 3 0

5.6.10 OB 34: Error with G DB/GX DX (FEDB X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 32

5.6.11 OB 35: Comm uni c at io n Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 32

5.6. 12 OB 36 : Error in Self- te st . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 33

5.7 Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 34

5.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 34

5.7.2 Descriptio n of the Test Functi ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 3 5

5.7.3 Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 3 7

5.7.4 Err or Handl ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 38

6 Integr ated Special Functi on s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 3

6.1 I ntr oductio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 4

6.2 OB 121: Set /Rea d System T i me . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 8

6.3 OB 122: "Disab le Int errupt s" On/Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 12

6.4 OB 124: Dele te STE P 5 Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 14

6.5 OB 125: Generate STEP 5 Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 17

6.6 OB 126: Defi ne , Transfe r Proce s s Image s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 20

6.7 OB 129: Battery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 25

6.8 OB 131: Dele te ACCUs 1, 2, 3 and 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 26

6.9 OB 132/133: Roll- Up ACCU/ Roll- Down ACC U. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 2 7

6.10 OB 141: "Disable Single Cycli c Time d Interru pts" On/Off. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 29

6.1 1 OB 142: "Del ay All Inte rru pts" On/Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 32

6.12 OB 143: "Del ay Singl e Cyc lic Time d Interrup ts" On/O f f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 3 5

6.13 OB 15 0: Set /Rea d System T i me . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 38

6.14 OB 151: Set/ Read Tim e for Clock -Controlled Int er rupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 43

6.15 OB 153: Set/ Re ad T im e for Delayed Inte rrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 50

6.16 OB 180: Va riab le Dat a Bloc k Acce ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 53

6.17 OB 181: Test Data Bloc ks (DB/DX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 57

6.18 OB 182: Copy Data Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 59

6.19 OB 202 to 205: Multi processor Comm unicat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 62

Contents

CPU 948 Progra mming Gu ide

C79000-G8576-C848-04 v

6.20 OB 222: Res tart Cy cl e Monitoring Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 63

6.21 OB 223: Comp are Start-Up Mo des. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 64

6.22 OB 254/2 55: Copy/ Dupl ic ate Da ta Block s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 65

7 Extended Data Block DX 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3

7.1 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4

7.2 S tru cture of DX 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 5

7.2.1 Ex ample of Input in DX 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 7

7.3 Parameters f or DX 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 8

7.4 Ex am p les of Parameter Assign me n t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 12

7.4.1 STEP 5 Programmi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1 2

7.4. 2 Para met e r As signme nt using the PG Sc reen Form. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 14

8 Memor y Assignment and Mem ory Organizatio n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 3

8.1 S tru cture of th e Memory A rea. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 4

8.2 Mem ory Assignm e nt in the CPU 948 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 5

8.2. 1 Memory Assig nmen t fo r the Syste m RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 6

8.2. 2 Mem ory Assignm en t for the Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 8

8.3 User Memor y Organizati on in the CPU 948. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 10

8.3.1 Blo ck Headers in User Mem ory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 12

8.3.2 Blo ck Add r ess Lis t in Data Block DB 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 13

8.3. 3 RI /RJ Ar ea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1 4

8.3.4 RS /RT A rea. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1 5

8.3.5 Bit Assignme nt of the System Dat a Wo rds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 18

8.3.6 Add ressable System Data Are a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 4 2

9 Me mory Acc ess U sing Absolute Addr e sses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 3

9.1 I ntr oductio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 4

9.2 Me mory Acce ss via Addre ss in ACCU 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 8

9.2. 1 LIR/ T IR: Lo ading to or T ra nsfe rr ing from a 16-Bit Mem ory Area Indire c tly . . . . . . . . . . . . . . 9 - 9

9. 2. 2 Example s of Ac c e ss to DW > 255 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 15

9.2.3 LDI/TDI: Loading to or Transferring from a 32-Bit Memory Area Indirectly . . . . . . . . . . . . . 9 - 17

9.3 T r ansferring Memory Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 19

9.4 Ope ra tion s with the Base Address Re gi ster (BR Regi ster) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 22

9.4. 1 Opera tion s fo r T ra nsfe r betwe en Regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 23

9.4. 2 Acc essin g the Local Memor y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 2 4

9.4.3 Accessin g the Globa l Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 25

9.4.4 Accessin g the Dual-Port RAM Mem ory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 29

10 Mult iprocessor M ode and Communi catio n in the S5-155 U . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 - 3

10.1 Multi processor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 - 4

10.1.1 When to use the Multi processor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4

10 .1.2 Wh at Commu nications Mechanisms are Av ai l able?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 - 4

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10 .1.3 Exchang ing Data via IP C Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 5

10.1.4 Exchanging Data via Handling Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 8

10.1. 5 What nee ds to be Progra mme d for the Multiproc e ssor Mode ? . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 9

10.1.6 How to Crea te Data Block DB 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 9

10. 1.7 St ar ti ng up in the Mul tiproc e s sor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 13

10.1.8 Test Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 14

10.2 Mul tiprocessor Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 15

10 .2.1 I ntr odu ction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 15

10.2. 2 How the Tra nsmi tte r and Recei ve r are Identifi e d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 16

10.2.3 Why Data is Buffered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 17

10.2.4 How the B uffer is Proces sed and Manage d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 18

10.2.5 System Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 21

10 .2.6 Cal l ing Co mm un ic a tion OBs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 22

10.2.7 How to Assign Paramet er s to Comm uni cat ion OBs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 23

10.2.8 How to Evalua te the Output Param ete rs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 24

10 .3 R unt ime s of the Communica tion O Bs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 31

10.4 INITI ALI ZE Funct ion (OB 200). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 33

10 .4.1 F unc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 33

10 .4.2 Cal l Parame ters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 35

10.4.3 Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 3 5

10 .4.4 O utput Pa ramet ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 38

10.5 SEND Function (OB 202) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4 0

10 .5.1 F unc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 40

10 .5.2 Cal l Parame ters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 40

10.5.3 Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4 0

10 .5.4 O utput Pa ramet ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 42

10.6 SEND TEST Function (OB 203) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 45

10 .6.1 F unc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 45

10 .6.2 Cal l Parame ters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 45

10.6.3 Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4 5

10 .6.4 O utput Pa ramet ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 45

10.7 RECE IVE Funct ion ( OB 204). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 47

10 .7.1 F unc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 47

10 .7.2 Cal l Parame ters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 47

10.7.3 Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4 7

10 .7.4 O utput Pa ramet ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 48

10.8 RECE IVE TEST Function (OB 205) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 51

10 .8.1 F unc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 51

10 .8.2 Cal l Parame ters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 51

10.8.3 Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 5 1

10 .8.4 O utput Pa ramet ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 51

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10.9 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 53

10.9. 1 Cal li ng the Spec ial Function OB using Function Bloc k s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 53

10 .9.2 Tra nsferr ing Data Bl o ck s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 60

10. 9. 3 E xten ding the IPC Flag Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 66

11 PG Inter fac e s and Functi o ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 3

11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 4

11.2 PG Function s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 5

11. 2. 1 Inf o 11 - 6

11 . 2.2 Install a tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 7

11 . 2.3 Progr am Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 8

1 1 .3 Serial Link PG - PLC via 1st or 2nd Seria l Inte rf ac e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 16

11. 4 P arallel Op eration of Two Serial PG I n t erfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 - 17

11 . 4.1 Install a tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 1 9

11 . 4.2 Operati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 19

11.4.3 Sequence in Certain Operating Situations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 21

11.5 PG Funct ions via the S5 Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 27

11.5.1 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 - 27

11 .5 .2 How the PG Functio ns Work via the S5 Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 29

11 . 5.3 Install a tion and Ge tting Started. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 3 1

11 .5 .4 Co ndition Codes Ind icati ng Proble ms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 35

12 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 3

13 Indexes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 - 3

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Cont ents of Ch apter 1

1.1 Area of Appli c at io n for the S5-155U with the CPU 948 . . . . . . . . . . . . . . . . . . . . . . . . 1 - 4

1.2 Typica l Mode of Opera tion of a CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 5

1.3 The Program s in a CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 7

1.4 Which Operands are availab le to the User Program? . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 11

1.5 How much Memory is available for the User Progra m? . . . . . . . . . . . . . . . . . . . . . . . 1 - 14

1.6 How to Tac kle Progra mmi ng? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 15

1.7 Programming Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 18

1.8 Co nve rting User Programs of the CPU 928B for the CPU 948. . . . . . . . . . . . . . . . . . 1 - 19

Introduction

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Contents

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1 - 2 C79000-G8576-C848-04

1Introduction

Aims of the manual

This manual is intended to provide specialized information about

pr ogra mm ing t he CPU 948 fo r user s who al re ad y have b asi c

kn owle dg e of p rogr amm in g PLCs and wa nt to use the CPU 948 in the

S5- 155U pr ogra m m ab le co ntr oll er. If you do not yet hav e this basic

kn owle dg e, we strong ly advi se yo u re ad the docum e nta t ion

intr oducing th e progra m m ing l angua ge ST EP 5 / 3/ or t ake par t in a

cour se at our tra ining ce nt er. SIEME NS prov ide s co mpre he nsive

tra ining for SIMAT IC S5. For m ore deta iled inf orma tion, contac t your

loc al SIEMENS of fic e.

Contents of Chapter 1

Ch ap ter 1 expl ai ns how to u se the ma nua l and de a ls wit h th e are a s of

appl ic ati on of the S5-15 5U prog ra mma bl e cont rol ler wi th the

CPU 948 and its struc ture.

The chapter explains the typical mode of operation of a CPU and the

struc tur e of the CPU prog ram.

You will also fin d a few suggestions a bout how to ta ck le

pr ogra mm ing an d will lea rn some of the feature s of th e CPU 948

whi ch are imp ort an t for progr amm in g.

If you have alrea dy work ed with the CPU 946/947 and would like to

kn ow the differe nc es betwee n the se m odules and t he CPU 9 48, re fer

to Section 1.8.

Ch apte r 1 also in form s you a bou t diffe re nc e s bet wee n ve rsi ons A0 1

and A02 of the CPU 948 and exp la ins points you shoul d remem ber

when c onv erti ng "928B" pr ogra m s for the CPU 948.

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1.1 Area of Application for the S5-155U with the CPU 948

SIMATIC S5 family

The S5-155U prog ra mm abl e cont rol le r bel ongs to the fami ly of

SIMATIC S5 progr am m a ble c ont rollers. Wi th t he CPU 9 48, it is the

most po wer ful mul tipro ce ssor uni t for proc es s autom atio n (ope n and

clo se d loop c ont rol, signall in g, mon it ori ng, log gin g).

Owi ng to i ts modularity a nd hi gh pe rfo rm an ce, it c an be used for

me diu m to extre m ely lar ge control system s as we ll as for co mple x

aut omation tasks a t the pla nt an d proce s s supervision leve l.

Suitability

The S5-155U wit h the CPU 948 is par ticu larl y suit able for the

foll owin g:

•• Tasks requiring fast bit and word-oriented processing and fast

reaction times, i.e. with extremely fast open and closed loop controls.

Example s of this are fa st proce sses in mechanical engineering

(bottling pla nt, pac king ma chines or s im ilar systems) a nd i n the

automobile industry.

•• Tasks requiring an extremely high storage capacity and fast access

tim es, e .g. in th e autom obi le industry , proc ess an d plant

engineering.

•• Ta sks requ iring fast comm unicat ion with other CPUs installed in

the PLC and ope rati ng in the mult ipr oc essor mode and wit h CP

mod ule s (e.g . when conn ec ted to bus syste m s, host com pu te rs, for

v isua li zat io n, ope ra tion a nd m oni tor ing).

•• Comp le x tasks whic h ca n be h andle d effi c ient ly and clea rl y using

the high level languages C and SCL.

Area of Application for the S5-155U with the CPU 948

CPU 948 Programming Guide

1 - 4 C79000-G8576-C848-04

1.2 Typical Mode of Operation of a CPU

Mode of operation of a CPU

The fol lowi ng mode s of ope ra tion are possib le in a CPU:

Cyclic processing

Thi s is the ma in par t of all ac t iviti e s in the CPU. As the nam e alre a dy

sa ys, t he sam e op er at io ns are re pe a te d in an e ndl e ss cyc le .

Cy cl ic processing can be divided into three ma i n phases, as fol low s:

Phase Sequence

1Al l the input modules assigne d to the

CPU are sca nned by the syste m

pr ogra m and the valu es re a d in are

stored in the process image of the

inputs (PII).

2Th e va lue s co ntaine d in t he PI I ar e

pr ocesse d by the user pro gra m and t he

values to be output are entered in the

pr ocess im age of the outputs (PIQ).

3The values contained in the process

ima ge of the outp uts a re o utp ut by the

syste m program t o the output mo dules

as signed to the CPU.

Cyclic processing

Interrupt-driven processing

Time-controlled processing

1. 2. 3.

Read in process image

of the inputs

Output process image

of the outputs

&=1

I1.5

I1.6

I1.4

I1.3 Q3.1

Evaluate input signals,

set output signals

Input I 1.3

Input I 1.4

Input I 1.5

Output Q 3.1

Output Q 2.0

Output Q 4.7

CPU Process

Typical Mode of Operation of a CPU

CPU 948 Programming Guide

C79000-G8576-C848-04 1 - 5

Time-cont rolled processing

In addition to the cyclic processing, time-controlled proce ssing is

also a va ila ble for proc e sse s req uir ing con trol signal s at con sta nt

inte rv al s, e.g. non-t ime cr itic al m oni tor ing f unc tions pe rfo rm ed eve ry

second.

Interrupt -driven processing

If the rea ction t o a particular process signa l m ust be pa rticularly fast, this

should be ha ndle d with interrupt-driven processing. With, for exa mple,

a system interrupt, triggered via an interrupt generating module, you

can activate a special processing section within your program.

Processin g according to

pri ority

The typ es of proc essin g liste d above are hand le d by the CP U

according to their priority.

Since a fast reaction is required to a time or interrupt event, the CPU

interrupts cyclic processing to handle a time or interrupt event. Cyclic

pr ocessin g there fo re has the lowe st pri ori ty.

Whether or not the time-controlled processing is more important than

the i nt errupt contr oll e d proce s sing de pe nd s, amo ng ot he r things, on

the parti cu lar task. For th is reason , the prio rit y of time an d

inte rr upt -dri ven pro cessing on the CPU 948 ca n be selec ted .

Typical Mode of Operation of a CPU

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1 - 6 C79000-G8576-C848-04

1.3 The Programs in a CPU

The progra m exi stin g on every CPU is divid ed int o the fol lowing :

•• the system program

and

•• the user program.

System program

The system progra m organi zes all the func tions a nd seque nce s of the

CPU whic h do not involve a speci fic cont rol t ask (re fer to F ig. 1-2).

Update process image

of the inputs

Output process image

of the outputs

System

program

Call

user

processing

(inter-

faces)

Execute start-up

Handle errors

Communication with

the PG

Manage memory

Fig. 1-1 Tasks of the system program

The Programs in a CPU

CPU 948 Programming Guide

C79000-G8576-C848-04 1 - 7

Tasks

The tasks i nclu de the followi ng: 1)

•• cold and warm restart,

•• up dati ng th e proc ess im a ge of the input s and ou tpu tt ing the

p roc e ss ima ge of th e outpu ts,

•• ca ll ing the cyclic , time -con trolled a nd int er rupt-driven programs,

•• detection and handling of errors,

•• memory management,

•• communication with the programmer (PG).

User interfaces

As the user, you can influe nce the react ion of the CPU to parti cula r

sit uati ons a nd error s via spe cia l int er face s to the system pro gra m .

Storing the sys tem program

Afte r switchi ng on the powe r supply to t he PLC (POWE R UP) the

system prog ram is rea d from the EPROM t o the in ternal opera ting

system RAM.

System program defaults

The fol lowing cha pter s, e xcep t for Cha pte r 7, descr ibe th e default

system re actio n t o proce ss eve nts or er rors. Depen din g on th e

defa ul ts, the CPU cha nge s to th e stop mode i f an opera ti on code error

occ urs a nd th e erro r orga ni zat io n blo ck is not loa de d.

Modifying the defaults

You can m odi fy the system response by assignin g pa rame ter s for the

da t a bl oc k D X 0.

Chapter 7 describes the system response following modification.

1) When operating with several CPUs (multiprocessing) further tasks are inv olved.

The Programs in a CPU

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1 - 8 C79000-G8576-C848-04

User program

Tasks

The user progr am cont ai ns all the func tions re qui re d for proc e ssing a

specifi c control task. In ge ne ra l te rm s, the se fu nc ti ons can be

as signe d t o the in terfa c e p rovi de d by the system pro gra m for th e

various type s of processing, as follows:

Type of processing Task

Col d and wa rm rest ar t To pr ovi de the co ndi tions unde r whi c h

the other processing functions can start

f rom a defi ne d statu s foll owin g a cold or

wa rm restart of the control syst em (e. g.

assign ing spec if ic value s to signa ls).

Cyc l ic processing C onstant ly rep ea t ed signal pr oc essing

(e.g. logic operations on binary sig nals,

r ea di ng i n and anal yz ing anal og value s,

spe cif ying binary signa l s for out put ,

o utp utt ing anal og va l ues) .

Time-controlled

processing Special, time-dependent processing with

the fol lowing tim e conditions:

- faster than the average cycle,

- at a time interval greater than the

aver age cycle tim e,

- at a specified point in time.

Interrupt-driven processing Special, fast reactions to certain proc ess

signals.

Error reac tion Handling pro blem s with in the norm a l

se que nc e of the pr ogra m .

The Programs in a CPU

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C79000-G8576-C848-04 1 - 9

Structure

Storing the user program

Afte r prog ramm i ng the user pro gra m, you mu st load it in the user

me mo ry of the CPU 948 (dire c tly from the PG) or via a memo ry car d

whose contents are copied to the user memory by an OVERALL

RESET of the CPU.

Interfaces to the

system program

Organization blocks a re ava i labl e as int er face s to the system pro gra m

fo r the specia l type s of p roc essi ng.

User memory

Code blocks

Data blocks

Organization

blocks

PB FB/FX SB

FB 8

SEGMENT 1

NAME :TRANS

0005 :L IB 3

0006 :T FW 200

0007 :C DB 5

0008 :DO FW 200

0009 :L DW 0

000A :T QW 6

000B :BE

1: KH = 0101;

2: KF = +120;

3: KS = xy;

4: KY = 4.5;

5: KG =

6: KM =

1: KH = FFFF;

2: KH = FFFF;

3: KH = FFFF;

4: KH = FFFF;

5: KH = FFFF;

6: KH = FFFF;

STEP 5

operations

static or dynamic data

(bits, bytes, words, double words)

static or dynamic data

(bits, bytes, words, double words)

STEP 5

operations STEP 5

operations

Program

blocks Function

blocks Sequence

blocks

I1.5

I1.6

I1.4

I1.3 Q3.1

F 50.1

F 50.2

F 50.3 Q5.3

F1.7

I2.6 S

I1.3

User program

F ig . 1- 2 St r uct ure of a STE P 5 user pr ogr am

The Programs in a CPU

CPU 948 Programming Guide

1 - 10 C79000-G8576-C848-04

1.4 Which Operands ar e av aila ble to t he User Pro gram?

The CPU 948 pr ovi de s the foll owi ng ope ra nd are a s for pro gra m ming:

•• proc ess im age and I/Os

•• flags (F flags and S flags)

•• timers/counters

•• da t a bl oc k s

Process image of the inputs

and outputs PI I/PIQ

Characteristics Size

The user pr ogra m can ac ce ss the fol lowi ng da t a type s

in the proce ss ima ge e xtremely quic kly:

- sin gle bits,

- bytes,

- words,

- doub le words

12 8 bytes

each for

inputs and

outputs

I/O area (P area)

Characteristics Size

The user pr ogra m can ac cess the I/O m odu les dire c tl y

vi a the S5 bus.

The foll owing data ty pe s are possibl e :

- bytes,

- words.

25 6 bytes

each for

inputs and

outputs

Extended I/O area (O area)

Characteristics Size

The user pr ogra m can ac cess the I/O m odu les dire c tl y

via the S5 bus.

The foll owing data ty pe s are possibl e :

- bytes,

- words.

25 6 bytes

each for

inputs and

outputs

Which Operands are available to the User Program?

CPU 948 Programming Guide

C79000-G8576-C848-04 1 - 11

F flags

Characteristics Size

Th e fla g ar ea is a m em ory a re a whic h th e user

prog ram ca n acc e ss extr em e ly quic kl y with c er tain

operations.

The fla g area should be used idea ll y for wor kin g data

re qui re d often.

The followin g data types can be accessed :

- single bits,

- b ytes,

- wo rds,

- double words.

Single flag bytes ca n be used as interprocessor

comm unic ati on fl ags (IPC fla gs) to exc ha nge data

betwee n the CPUs in the multipro cessor m ode (refe r

to Chapte r 10). IPC fla gs ar e update d by the system

prog ram at the end of the cyc le via a b uffe r in the

coordina to r or CP/IP.

2048 bits

S flags (extended flag area)

Characteristics Size

The CPU 948 also co ntai ns an addi ti onal fla g are a, the

S f lag are a. The use r progra m can also a c cess t his are a

ex tre m e ly q u ickly as with the F fl ags.

S flags cannot howeve r by used as actual operands

wit h funct ion bloc k ca ll s nor as IPC flag s for data

exchange betw een the CPUs. T he bit te st opera t ions of

the CPU 948 ca n also not be used with the S fl ags.

These flags c an o nly be use d with th e PG system

softwa re "S5- DOS" from versio n 3.0 upwa rds or

"S5-DOS/MT " from versio n 1.0 upwards.

3 2 768 bits

Which Operands are available to the User Program?

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1 - 12 C79000-G8576-C848-04

Timers (T )

Characteristics Size

The u s er pr og r am l o ad s time r cell s wi th a time v alue

between 10 ms and 9990 s a nd by means of a start

operation, decreme n ts th e t imer from this value at th e

pres elec ted inte rv als until it r each es the value ze ro.

256 time r

cells

Counters (C)

Characteristics Size

The user pr ogra m loads c ount e r cel ls wit h a start value

(m a x. 9 99) a nd then incre m e nts or de c re m ents them . 256

counters

Data words in the current data

bloc k

Characteristics Size

A data block contains constants and/or variables in the

byte, word or double word format. With STEP 5

operations, you can always access the "current" data

block (refer to Section 2.4.2).

The following data types can be accessed:

- single bits,

- bytes,

- words,

- double words.

256

words

1) In data blocks with a length greater than 256 words, you can only access data

words with the numbers > 25 5 with operations for absolute memory access

(refer to Chapter 9).

Which Operands are available to the User Program?

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C79000-G8576-C848-04 1 - 13

1.5 How much Memory is available for the User Program?

For stori ng logic and da ta bloc ks, t he CPU 948 onl y ha s the user

me mory in the interna l RAM.

The CPU 948 is ava ila ble with two ver sions of t he user m emo ry:

•• Versio n 1: with 640 Kbyt es,

•• Versio n 2: with 1,66 4 Kbytes.

How much Memory is available for the User Program?

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1 - 14 C79000-G8576-C848-04

1.6 How to Tackle Programmi ng

If you a re a n expe ri enc ed user, you hav e probably foun d the most

sui tabl e me tho d for cre a ting program s for yoursel f an d you ca n skip

this sec t ion .

Le ss expe ri en ce d rea de rs wil l find ti ps for de sig nin g, progr am m in g,

test ing an d star ting up yo ur STEP 5 pr ogra m .

Implementation stages

The implementation of the STEP 5 control program can be divided

int o thr ee stag es :

Stage Activity

1 Determining the technological task

2 Desi gni ng th e progra m

3 Cre ati ng, testi ng a nd start ing the progra m

Recursive procedure

In practice, you will recognize that certain steps must be repeated

(r ec ursive procedur e), e. g. when you rea li ze th at more signals are

required to improve the handling of the task.

Stage 1

Deter m inin g t he te c h n o l ogical tas k :

Stage Activity

1 C re at e a general bl oc k diagra m outl ini ng t he control

ta sk s of y our proc ess.

2 C re at e a list of t he input and out put signa l s requ ire d

f or th e task.

3 Imp rove the bloc k di agra m by assign ing the signa ls

and any particular time conditions and/or counter

st at uses to the indiv idual blocks.

How to Tackle Program ming

CPU 948 Programming Guide

C79000-G8576-C848-04 1 - 15

Stage 2

Designing the program

Stage Activity

1 Base d on the improv ed block di a gra m , de cid e on the

type s of proce ssing req uir ed of your progr am (cyc lic

p roc e ssing, time -c on tro ll ed proc e ssi ng e tc. ) an d sel ect

the OBs required for this.

2 Divi de the typ es of proc essin g into tec hno log ica l

and/or functional units.

3 Che ck whet her the unit s can be assign ed to a progr am

o r func tion b loc k and sele ct th e bl oc ks you re qu ire

(PB x, FB y etc.)

4 Find out which timers, counters and data or results

me m ory yo u re qui re.

5 Sp eci fy the tasks for ea ch of the propose d lo gic bloc ks

an d the da ta for fl ags an d d ata bloc ks which ma y be

required. Create flow diagrams for the logic blocks.

Notes on th e scope of

cyclic processing

Whe n dec iding on the types of proc essin g, kee p the foll owi ng

condit ions in mi nd:

•• The cycl e must run th roug h quick ly enou gh. Th e proc ess sta tuse s

must not change m ore qui ck ly than the CPU c an reac t. Oth erwise

the proce s s can get out of cont rol.

•• The maximum reaction time should be taken as twice the cycle

time.

The cycle time is determined by the cyclic processing of the

system progra m and the type and scope of the user progra m. It is

o ften no t consta nt, sinc e the c ycl ic user progr am may be

int er rupt e d when ti me and in te rru pt- dri ve n prog ra m sectio ns are

called.

How to T ackle Programming

CPU 948 Programming Guide

1 - 16 C79000-G8576-C848-04

Stage 3

Cr eat ing , test ing and st arti ng up the progr am:

Stage Activity

1 Decide on the type of representation for the logic

blocks (LAD, CSF or STL, refer to Chapter 2).

Remember that function blocks can only be created in

the STL method of representation.

2 Pr ogra m all logi c and da t a bloc ks (please ref er to you r

STEP 5 manu al).

3 St a rt up the blo ck s one aft er the other ( you m a y have

to program a different OB for each individual step, to

ca ll the logic bl oc ks):

1a: load the block(s)

1b: test the block(s)

( For more de tail e d inf orm ati on pl ease r efer to your

STEP 5 manual and Chapter 11).

4 W h en you are certain th a t a ll th e logic bl o cks r u n

correctly and all the data can be correctly calculated

and store d, you c an sta rt up your wh o le prog ra m.

Note on test strategies

Whe n you ac tu al ly star t up yo ur pro gra m f or th e fi rst tim e i n ge nui ne

pr ocess operation, i.e . with rea l inpu t and m ore impor ta nt ly outpu t

sig nals, is a dec isio n tha t must b e lef t up to yourse lf or to a tea m o f

experts.

The more com pl ex the process, t he great er the ri sk and there for e the

greater the care required when starting up.

How to Tackle Program ming

CPU 948 Programming Guide

C79000-G8576-C848-04 1 - 17

1.7 Program ming Tools

Suitable PGs

The fol lowing programmer s a re av ai la ble for cre at ing your user

pr ogra m, PG 685, PG 710, PG 730, PG 750 and PG 770. You can

check on the performance and characteristics of these devices in the

catalog ST 59 /9/.

Note

If you wish t o use t he full range of performance of the CPU 948

in your aut om ati on software, (part ic ula rly t he DX 0 scree n, the

"Ou tpu t ISTACK" sc re en , the displ ay with t he "m emor y

conf igu ra ti on" fu nc ti on and the PG funct io ns via the bac kpl an e

bus) you re qui re the PG syste m softwa re "STEP 5/ST" from

versi on 6.3 upwa rd s or "STE P 5/ MT" from version 6.0 upwa rds

pl us the "De lta diske tte CPU 948" a nd a PG 7xx.

Suitable software

You can create user prog ra ms for SIMATIC S5 pr ogr am mable

controllers as follows:

•• In the STEP 5 prog ra mmi ng la ng uage ,

He re you require the STEP 5 prog ra mmi ng pa c ka ge al ong wi th the

system softwar e STE P 5/ST or STEP 5/MT (descri pt ion, refer t o

/3/ in Furt he r Rea din g),

•• In a hi ghe r pro gra m mi ng lan guage:

If you are familiar with programming in higher programming

languages, you can also form ula te your S T EP 5 program for the

CPU 948 as follows:

- SCL (refer to /1 2/ in Furthe r Read ing , the SCL compi le r is

con tain ed in the PG softwar e "S5-DOS/MT " fr om version 6

upwards.)

- C with S5 C compiler (refer to /13/ in Further Reading).

You can a lso c re ate prog rams for seque nc e contr ol syst ems in a

gr ap hic re pre se ntation using t he GRAPH 5 programming package

(d esc ripti on, refe r to /4/ in Furt her Re a din g).

Depending on the task, you can also incorporate "off-the-peg"

sta nd ard func t ion blocks in your use r program. The performanc e and

characteristics of these blocks are described in the catalog ST 57 /11/.

Programming Tools

CPU 948 Programming Guide

1 - 18 C79000-G8576-C848-04

1.8 Converting User Programs of the CPU 928B for the CPU 948

The followi ng section inform s you a bout the point s yo u sh ould

rem e mber when you c onve rt user progr ams writ te n for the CPU 928 B

fo r use on t he CPU 948.

Operations

In the followi ng operat ions, note the difference s i n the exe cuti on a n d

ha nd li ng (a m ong ot her th ing s the diff erent mem ory uti li z ation).

Oper at ions CPU 928B CPU 948

I A/RA (d isa ble/ en ab le

interrupts) All process inte rrupts are disabled or

enabled Onl y the proc ess int errup ts via input

byte IB 0 are disabled or enabled.

Instead of t h ese operations, use the

spe cia l func tion OBs OB 122 or

OB 14 2.

LIR /T IR 16 bit long a ddr esse s are used. 20 bit long a dd re sses are used.

Adapt a tion is nec essa ry.

B lock tra nsfe r ope ra -

tion TNB 16 bit long a ddr esse s are used . The opera ti on do es not ex ist.

Use TN W for bl oc k tr an sf er f rom the

8-bit to the 8-bit area.

B lock tra nsfe r ope ra -

tion TNW - 16 bit long addre sses a re used.

- Blo ck tra nsfe rs from the 8- bit to the

8-bit area and vi ce ve rsa are

possible.

- 20 bi t long a ddr esse s are used .

Adapt atio n is necessar y.

- onl y bloc k transfe rs fro m the

8-b it to th e 8- bit ar ea a nd from the

16- bit to the 16-bi t are a s possi ble

wit h TNW.

- for the block transfer from

th e 8-bit to the 16-bi t are a use

th e op er ation TXB,

- for the block transfer from

th e 16-bi t to the 8-bi t are a u se

th e op er ation TXW.

(T XB a nd T XW do not e xi st on

a CPU 928B)

All operations with the

B R regist er The BR re gist er is 20 b its wide . The BR re gi ste r is 32 bits wide.

Adapt a tion is nec essa ry.

Converting User Programs of the CPU 928B for the CPU 948

CPU 948 Programming Guide

C79000-G8576-C848-04 1 - 19

Timer processing

CPU 928B CPU 948

The timers are updated during

start-up. The timers are only updated in

the RUN m ode

(Reason: compatibility with

CPU 946/947 )

FB 0 as cycle block

CPU 928B CPU 948

If no cyc l e bloc k OB 1 exist s, the

system progr am cal ls FB 0

cyclically, provided it is loaded.

Only OB 1 ca n be used for cyc li c

proc es sing. If yo u ha ve

progra mm ed FB 0, cr eat e an

OB 1 in w hich F B 0 is ca l led.

Default prioritie s

CPU 928B CPU 948

Proc e ss interrupts have highe r

priority than timed interrupts. Timed in terrupts have priori ty

ove r proce ss int er rupt s via IB 0

or syste m inter rupt s. You ca n

ch an ge the pri ori ty w i th t he

parameters in DX 0.

Data block DB 0

(block address list)

CPU 928B CPU 948

The b lock addr ess li st contai n s

th e di rec t start addre sses of the

blocks.

The bl oc k addre ss list contain s

the s egme nt addres ses of the

blo ck s. T o obt ain th e sta rt

ad dre s s of a bl oc k, its segment

address must be shif ted 4 bits to

the left.

Converting User Programs of the CPU 928B for the CPU 948

CPU 948 Programming Guide

1 - 20 C79000-G8576-C848-04

Data block DX 0

You must cre a te a n ew DX 0 data bl ock (see Cha pt e r 7), since the

DX 0 for the CPU 928B has a diff er en t structure a nd setti ngs.

Using the RT area

With th e CPU 928B, the RT ar ea is not used by the syste m progr am ,

with the CPU 948 it is used to some ext ent by the han dling bloc ks.

You ca n onl y use the RT a rea for yo ur use r prog ram whe n you do not

use any standa rd FBs and a ny PG funct ion s via SINEC H1 and the S5

bus.

Organization blocks

The num be r and fun ct io n of th e erro r an d spec i al func t ion OBs are not

the sam e on the CPU 928B and CPU 9 48:

Error OBs

The followi ng e rro r OBs o f the CPU 948 respo nd diffe re ntly fr om

the ir nam e sakes on the CPU 928B:

OB Functio n Error IDs

OB 19

OB 26

OB 27

Sam e as on

CPU 928 Different from

CPU 928B

OB 28

OB 29

OB 30

OB 31

Fu ncti on di ffe rent

from that on

CPU 928B –

Special function OBs

OB Note

OB 110

OB 152

OB 160 to 163

OB 170

OB 190 to 193

OB 216 to 218

OB 220 and 22 1

OB 224

OB 226 to 228

OB 240 to 242

OB 250 and 25 1

The se OBs do not exist on the CPU 948

OB 111

OB 112

OB 113

OB 120

OB 121

OB 122

OB 123

On the CPU 948, the OB is replac ed by :

OB 131

OB 132

OB 133

OB 122

OB 141

OB 142

OB 143

Converting User Programs of the CPU 928B for the CPU 948

CPU 948 Programming Guide

C79000-G8576-C848-04 1 - 21

OB Note

OB 122 Para met er assignme nt is differe nt from that of the

CPU 928 B OB 122

(reason: compatibility with CPU 946/947).

OB 18 0 In cont ra st to the CPU 928B , the ac c ess wind ow of

the CPU 948 can only be shif ted by a multiple of

16.

OB 200

OB 202 to 205

(multiprocessor

communication)

In cont rast to the CPU 928B , these CPU 948 OBs

change the c ontent of ACCU 4.

R64 controller softw are

The R64 cont rol le r soft wa re canno t be run on t he CPU 948.

Stand a rd FBs

Ge nera ll y, the sta nda rd f unc tion bloc ks used on the CPU 928 B (e.g.

for IPs) must be rep la c ed by tho se for the CPU 948. The HDBs are an

exc e ption the se can be taken from the CPU 928B (see Sect io n 1.8.1).

Converting User Programs of the CPU 928B for the CPU 948

CPU 948 Programming Guide

1 - 22 C79000-G8576-C848-04

Cont ents of Ch apter 2

2.1 STE P 5 Progra mming Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4

2.1. 1 The LAD, CSF, STL Me th ods of Re prese ntation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4

2.1.2 Structu re d Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 5

2.1.3 STEP 5 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 6

2.1.4 Number Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 8

2.1.5 STEP 5 Blocks a nd Storing t hem in Memo ry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 12

2.2 P rogr am , Organiza tion and Se quence Block s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 16

2.2.1 Organization Blocks as User Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 18

2.2. 2 Orga ni zat io n Blo cks fo r Spe cia l Funct ion s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 22

2.3 F unc tion Bl ocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 23

2.3. 1 St ructu re of Function Bl oc k s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 24

2.3.2 Programming Function Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 26

2.3.3 Calling Function Blocks and Assigning Parameters to them . . . . . . . . . . . . . . . . . . . . 2 - 28

2.3.4 Special Function Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 33

2.4 Data Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 35

2.4.1 Creating Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 37

2.4.2 Opening Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 38

2.4.3 Sp ec i al Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 41

User Program

CPU 948 Progra mming Gu ide

C79000-G8576-C848-04 2 - 1

Contents

CPU 948 Prog ramming Gu id e

2 - 2 C79000-G8576-C848-04

2User Program

The followi ng cha pter explains the c ompone nts that ma ke up a

ST EP 5 user pr ogra m for the CPU 948 and how i t can be struc tur ed .

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 3

2.1 STEP 5 Programming Language

With the STEP 5 programming language, you convert automation

tasks into programs that run on SIM ATIC S5 programmable

controllers. You can program s imple binary functions, complex

digital functions and arithmetic operations including floating

point arithmetic using STEP 5.

Types of operation

The operations of t he STE P 5 pro grammi ng l an gua ge ar e di vi ded into

the following groups:

Basic operations

•• yo u can use these ope rati ons in all logic block s

•• me tho ds of re pre sentati on: ladder di agram (L AD) , cont rol syste m

f lowcha rt (CSF), statement list (STL ).

Supplem e ntary ope rati ons and system oper at ions:

•• ca n onl y be used i n func tion b lock s

•• on ly stat em e nt l ist (STL) metho d of re pre sentat ion

•• syste m ope ra tions: only exp er ie nce d STE P 5 programmers shoul d

use system ope ra ti ons

2.1.1

The LAD, CSF, STL

Methods of Representation When programming in STEP 5, you can choose between the three

methods of representa tion ladder diagram (LAD), control system

flowchart (CSF) and statement list (STL) for each individual logic block.

You can choose the m ethod of re present ation that best suits your

particular application.

The machi ne code MC5 that the progr amm e rs (PGs) gener ate is the

sa me for al l thre e metho ds of re pre sen tati on.

If you fol low cert ai n rul e s when programming in ST EP 5 (see / 3/), the

pr ogram m er c a n tran slate your user program from one m ethod of

re pr esentat ion into a ny ot her.

Graphic representation or

list of statements

Whi le the la dder dia gram (LAD) an d co ntr ol syste m flo wchart (CSF)

me tho ds of re pre sen tati on re pr ese nt y our ST E P 5 progr am

graphically, statement list (STL) represents STEP 5 operations

indi vidually as m ne mo nic a bbre vi a tions.

STEP 5 Programm ing Language

CPU 948 Programming Guide

2 - 4 C79000-G8576-C848-04

Graphic representation of

sequential controls

GRAPH 5 /4/ is a progra mmi ng lang ua ge for graph ic represen ta tion of

seque ntia l controls. It is at a higher lev el than the LAD, CSF, STL

me thods of repre sen tation. A prog ram writt en in GRAPH 5 as a

graphic representation is automatically converted to a STEP 5

pr ogra m by th e PG.

2.1.2

Structured Prog rammin g Using STE P 5, you ca n struc ture your progr am by divi din g it into

se lf- conta i ned prog ra m sectio ns (blo ck s) . This divi sion of your

pr ogram cl arif ie s t he esse ntia l pro gram struc tures m a king it ea sy to

rec ogn ize the system part s tha t are re lated wi thin the soft wa re.

Ladder diagram Statement list Control system flowchart

Programming with

graphic symbols

like a circuit diagram

Programming with

graphic symbols

IEC 117-15

DIN 40700

DIN 40719

DIN 19239

DIN 19239 DIN 19239

STL CSFLAD A

> = 1

Programming with

mnemonic abbreviations

of function designations

complies with complies with complies with

Fig. 2-1 Me thods o f re pres ent a tion in t he STEP 5 pr ogr amm i ng la ngua ge

STEP 5 Programming Language

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 5

Structured programming offe rs you the fo llowin g adva ntage s:

•• sim pl e and clea r c rea ti on of pr ogra m s, e ve n larg e on es

•• sta nd ardiz ati on of progr am part s

•• simple program organization

•• easy program changes

•• sim ple , sect io n by sect ion progr am test

•• simple system start-up

What is a block?

A bloc k is a part of th e user pro gra m tha t is disti ngui shed by its

fu nction, structure or applicati on. You can d iffer entiat e bet ween

blocks that contain statements (code) i.e. organization blocks,

pr ogram block s, function blo cks or se quenc e block s, and bloc ks that

contain data (da ta bloc ks).

2.1.3

STEP 5 Operations A ST EP 5 operation is the s ma llest independe nt unit of the user program.

It is the work specification for the CPU. A STEP 5 operation consists of

an ope ration a nd an operand as shown in the following exa mple:

Example

Operation code

Operation Operand

Parameter

:O F 54.1

(what is to be done?) (with what is the

operation to be done?)

STEP 5 Programm ing Language

CPU 948 Programming Guide

2 - 6 C79000-G8576-C848-04

Absolute and symbolic

operands

You can enter the operand absolutely or symbolically (u si ng a n

as signm e nt list ) as shown in the follo wing exa m pl e:

Abso lute representation: :A I 1.4

Symbolic represent ation: :A -Motor1

For mo r e infor mat ion on abso lute an d symbo lic pr ogra mm ing , refe r to

yo ur ST EP 5 m a nua l.

Application of STEP 5

operations

The STEP 5 operation set enables you to do the following:

•• se t or re se t a nd c om bin e bi na ry va l ues logi ca l ly

•• loa d and transfe r val ues

•• com pare value s and proce ss the m a ri thm e ti cal ly

•• spe cify tim e r and c ount e r value s

•• co nv ert num be r re p r ese nt at ions

•• call blocks and execute jumps within a block

and

•• infl ue nc e pr ogra m ex ecut ion

Result of logic operation RLO

The central bit for controlling the program is the result of logic

op er at ion RLO . Thi s is ob ta ined a s a res ul t of bi nary logi c op er at ions

and i s influenc ed b y some ope ra t ion s.

Section 3.5 descri bes the whole S T EP 5 operation set and explains how

the RLO is obt ained. Thi s section a lso inc ludes programm ing exa mples

for individual STEP 5 operations.

STEP 5 Programming Language

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 7

2.1.4

Number Representation To all ow the CPU to logi c ally com bine , mod ify or comp are nume ric al

val ues, th ese va lue s mu st be loc ated in t he ac c umul at ors (workin g

registers of the CPU) as binary numbers.

Depending on the operations to be carried out, the following number

re p r es en tations a r e per mitt ed in S TEP 5:

Binar y number s: 1 6-bi t fixe d poi nt num be rs

3 2-bi t fixe d poi nt num be rs

3 2-bi t floa ti ng po int num bers (with a 24-bi t

ma ntissa)

De c imal number s: B CD-c ode d numb er s (sign and 3 digits)

Numerical input on the PG

Whe n you use a programm e r to input or displa y num ber va l ues, you

se t the dat a fo rmat on th e progra m m er ( e.g. KF or fixe d poi nt) i n

whi ch you i nte nd to e nte r or display the values. The pro gra m mer

converts the in te rna l r ep re sent a ti on in to t he form you ha ve re que ste d.

Permitted operat ions

You can carry out all arithm etic oper ation s with the 16-bit fixed

po int num be r s an d flo at ing point number s, in cluding com pa riso n,

addi ti on, subt ra ct io n, mul ti pl ica ti on a nd di visi on.

Note

Do not us e BCD-coded numbers for arithmetical operations, since

thi s leads to incor rect result s.

Use 32-bi t fixe d poi nt num be rs to exe cu te co mp ar ison op er ations.

The se are also ne cessar y as an inte rmed iate leve l when conve rting

nu mber s in BCD code to floati ng po int numbe rs. With t he ope ra ti ons

+ D an d - D they ca n al s o be use d f o r addition and subtr ac t i on .

The STEP 5 programming language also has conve rsion oper ations tha t

enable you to conve rt num bers di rec tly to t he mos t important of the ot her

numerical r epr es en tation s .

STEP 5 Programm ing Language

CPU 948 Programming Guide

2 - 8 C79000-G8576-C848-04

16-bit and 32-bit fixed

point numbers

Fixe d poi nt numb ers are whole bina ry numb er s with a sign.

Coding of fixed point numbers

Fixed poin t number s are 16 b it (= 1 w ord) or 32 bit ( = 2 words ) in

binary repres entation . Bit 15 or bi t 31 con tains the s ign.

•• ’0’ = positive number

•• ’1’ = negati ve number

The two’ s compl em e nt rep re sent a ti on is use d for nega t ive num bers.

PG input

Input of 16-b it fixed po int num ber da ta for mat at the PG:KF

Input of 32-b it fixed po int num ber da ta for mat at the PG:DH

Permitted numer ical range

16 -bi t fixe d point nu mb er

-32768 to +3276 7 (16 bits)

32 -bi t fixe d point nu mb er

-2147483648 to +214 7483 647 (32 bit s)

(8000 0000H to 7FFF FFFFH)

Using fixed point numbers

Use fixe d po int numbe rs for simple ca lc ul a tions an d for c om pa ri ng

nu mber value s. Si nce fixe d poi nt num be rs are alwa ys whol e nu mber s,

rem e mb er tha t the r esul t of divi di ng two fixe d po int num be rs is also a

fixe d poi nt num be r without deci m al plac e s.

Floating point numbers

Floating poin t numbers ar e positive and negative fractions. They

alwa ys oc c upy a double word (32 bit s). A floa ting po int num be r is

repr ese nt ed as an exp one nt ia l numb er . The mant issa is 24 bit s long

and t he e xp one nt is 8 bit s long.

In the CPU 948, the defa ul t m anti s sa is 24 bi ts lo ng (bi ts 0 to 23) for

addi ng, subt ra ctin g, mul ti pl yin g and div idi ng.

The exponent indicates the order of magnitude of the floating point

number. The sign of the exponent tells you whether the value of the

floating point number is greater or less than 0.1.

STEP 5 Programming Language

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 9

Using floating point number s

Use floa t ing point numbe rs for solvi ng e xtensi ve ca lc ula ti ons,

espe ci all y for mul tipli c atio n and div isio n or when you are working

wi th ve r y l a rge or ve ry sm al l nu mbers!

Accuracy

The mant issa indicate s the a cc ura c y of the floa ti ng point num be r as

follows:

•• Accuracy with a 24-bit mantissa:

2-24 = 0. 000000059604 (corresponds t o 7 decimal places)

If the sign of the mant issa i s "0" the nu mb er is p osit ive; if th e sign is

"1" it is a negative number in its two’s complement representation.

The floati ng point value ’0’ is represented as the binary value

80000000H (32 bits, see below) .

Coding floating point numbers

Coding a fl oati ng poi nt numbe r:

31 30 24 23 22 0

6 ... . ... 20V2

-1 .... . . . . . ... 2-23

Exponent Mantissa

Specification of the data format for floating point numbers at the

PG: KG

Permissible numerical range

± 0.14 6936 8 x 10-38 to ± 0.17014 12 x 1039

Input/out put on PG

a) in a logic block:

You wa nt to load t he num be r N = 12. 34 567 a s a floa ti ng poi nt

number.

Input:

:LKG1234567+2

STEP 5 Programm ing Language

CPU 948 Programming Guide

2 - 10 C79000-G8576-C848-04

b) in a data block:

You wa nt to defin e the num be r N = - 0.005 as a fl oati ng po int

constant.

Input:

6: KG = - 5 - 2

Numbers in BCD code

Decimal numbers are represented as numbers in BCD code. With their

sign and three digits, they occupy 16 bits (1 word) in an accumulator

as shown in the following example:

15 12 11 8 7 4 3 0

V V V V hundreds tens ones

The individual digits are positive 4-bit binary numbers between 0000 and

1001 (0 and 9 decimal).

The left bits are reserved for the sign as follows:

Sign for a posi tive num be r: 0000

Si gn fo r a negati ve num be r: 11 11

Permissible numerical range

-999 to +999

PG displ ay aft er you e nter the line :

:L KG + 1234567 + 02

Man tissa with sign Expo ne nt (b ase 10)

wi th s ign

Value of the numb er inpu t: +0.123 4567 x 10 +2 = 12.34567

PG displ ay aft er you e nter the line :

6: KG =- 5000 000 - 02

Man tissa with sign Expo ne nt (b ase 10)

wi th s ign

Val ue of the numb er inpu t : - 0.5 x 10-2 = 0.00 5

STEP 5 Programming Language

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 11

2.1.5

STEP 5 Blocks an d Storin g

them in Memory

Identification

A bloc k is ident if ie d as foll ows:

•• the b loc k t ype (OB, PB, SB , FB, FX, DB, DX )

and

•• the block number (number between 0 and 255).

Block types

The STEP 5 programming language differentiates between the

fo llowin g blo ck type s:

Organization blocks (OB)

Organiza ti on bloc ks are th e inte rface be tween the syste m program a nd

the user progra m . The y ca n be divide d in to two grou ps as fol lows:

With OB 1 to OB 39, you can control program execution, the restart

proc ed ure of the CPU and the rea cti on in the eve nt of an erro r. You

pr ogra m the se b locks you rself acc or din g to your a uto ma tion ta sk.

The se OBs are calle d by the system prog ra m.

OBs 40 to 100 a re block s bel ongi ng t o the ope ra ting syst em. You

must no t c all t he se bl oc ks.

OBs 121 to 255 con tain specia l func tions of t he system progra m . You

ca n cal l these blo ck s, if req uir ed , in your user pr ogra m .

Program blocks (PB)

You req uire pr ogram blocks to structure your progr am . Th ey contain

pr ogra m parts di vid ed acc ordi ng t o tec hnol ogical and func t ion al

cri teri a. Progra m blocks re pre sen t the hea rt of the user prog ra m.

Sequence blocks (SB)

Se quenc e block s we re ori ginally spec ia l program bloc ks f or step by

step pr oc essin g of seque ncer s. In the mea ntim e, howe ver, seq uenc er s

ca n be progr amm e d with GRAPH 5/4/. Seque nce bloc ks have

there fore lost thei r original si gnificance in STEP 5 .

Se quenc e blocks no w r epre sent an extension of the program bloc k s

and are used as prog ram bloc ks.

STEP 5 Programm ing Language

CPU 948 Programming Guide

2 - 12 C79000-G8576-C848-04

Function blocks (FB/F X)

You use funct io n blo cks to prog ra m freq ue ntly re curring and/or

complex functions (e.g. digital functions, sequence control systems,

clo se d loop c ont rol s an d signa ll in g func tions) .

A fun ctio n blo ck can be cal led sev er al time s by highe r ord er bloc k s

and supp lied with new op eran ds (assig ned para met ers) at eac h call.

Using block t ype FX doubles the ma ximum num ber of pos sible function

blocks.

Data blocks (DB/ DX)

Da ta bloc ks con ta in the (fi xed or vari ab le ) data with whi ch the user

pr ogra m works. Th is typ e of block c ont a ins no ST EP 5 st ate ment s and

ha s a di sti nc tl y differe nt f u nc ti on fr o m t he o the r bl ocks. Using block

type DX doubles the num ber of possible da ta block s.

Formal stru cture

of the blocks

All blocks consist of the following two parts:

•• a block header

and

•• a block body

Block header

The block header is a lways 5 words long a nd c ontains information for

block mana gem ent in the PG a nd data for t he system progra m.

Block body

De pe ndi ng on the block type, the block body contai ns th e fo llow ing:

•• ST EP-5 ope ra t ion s (in OB, PB, SB, FB, FX),

•• vari able or constan t data (in DB, DX)

and

•• a form al op eran d list (in FB, FX).

STEP 5 Programming Language

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 13

Block preheader

The prog ra mme r also ge ne ra tes a block preheader (DV, DXV, FV,

FXV) for block type s DB, DX, FB and FX. These bloc k preh eaders

cont a in infor ma tion abo ut the dat a form a t (for DB and DX) or th e

jum p labe ls (for FB and FX). Only the PG can evalua te this

infor ma tion. Conseq ue ntly th e block pre he ade rs ar e not tran sf erre d to

the CPU m em ory. You ca nnot influe nc e the cont ents of th e bloc k

he a de r di rect ly .

Maximum length

A ST EP- 5 block can oc c upy a maximum of 32 767 words in the

pr ogra m mem ory of the CPU (1 word corre spond s to 16 bits).

Available blocks

You c an pro gra m t he followi ng bl oc k ty pe s:

Data blocks DB 0, DB 1, DB 2, DX 0, DX 1 and DX 2 contain

parameters. T hese are re served for s pecific functions and you cannot use

them as normal data blocks.

Data block DX 2 is reserved for the 2nd serial interface and you should

not use it.

OB 1 to 39

FB 0 to 255

total 512

FX 0 to 255

PB 0 to 255

SB 0 to 255

DB 2 to 255

total 508

DX 3 to 255

STEP 5 Programm ing Language

CPU 948 Programming Guide

2 - 14 C79000-G8576-C848-04

Block storage

The progra mm er stor es all progr am m ed blo ck s in the pro gra m

me mo ry in the orde r in whic h the y ar e tra nsfe rre d (Fi g. 2-2). Wit h the

PG fun ctio n "tran sf er data blocks A" th e logi c bloc ks are tra nsfe rre d

fi rst fo ll owe d by th e dat a bl oc ks.

The sta rt addr esse s of al l stored bloc ks a re pla ced i n an addre s s list in

da t a bl oc k D B 0.

Correcting and

del eti ng bl o c ks

Whe n you correct blocks, the old block is declared invalid in the

me mory and a n ew bl oc k is e ntered.

Similarly, when blo cks are deleted, they are not really deleted, instead

the y are dec la red i nva lid. The spa ce the y oc cu py is, howe ver, not

released and is not available for blocks loaded later.

Note

You can use the COMPRE SS MEMOR Y online func tion to make

spa ce fo r new bloc ks. Th is func t ion o pti m ize s the uti li zat ion of

the me mory by d ele ti ng bl oc ks ma rke d a s inva l id and shi fti ng

va l id bl ocks toget her.

Location of blocks

in the user memory

Address 0

FB1

OB1

SB10

DB1

PB1

PB2

Fig. 2-2 Example of block storage in the user memory

STEP 5 Programming Language

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 15

2.2 Program, Organization and Sequence Blocks

Progra m bloc ks (PBs), org an izati on blocks (OBs) an d sequen ce

bloc ks (SBs) a re the sam e with respe c t to prog ramm i ng and c al ling.

You can progra m all three type s in the LAD, CSF and STL methods

of repr esenta tio n.

Programming

When programming organization, program and sequence blocks,

proc eed as follows:

Step Action

1 First indi c ate the typ e of block a nd the n the num ber of the

blo ck that you wan t to progr am.

The follo wing numbe rs a re a vailable for t he t ype of

b loc k l iste d:

- progr am bloc ks 0 to 255

- sequence blocks 0 to 255

- organiz ation blocks 1 to 39

2 Ente r you r progra m in the ST EP 5 pr ogra mm ing langua ge .

Whe n pr ogra mm ing PBs, OBs and SBs, yo u can only

use the STEP 5 basic operations!

A STE P 5 bloc k should always be a self-co ntai ne d

p rogram section.

Log ic ope ra tions m ust a lwa ys be com pl e ted

wi thin a blo ck .

3 Compl et e your pr ogra m inp ut wi th the b loc k end

ope ra ti on "B E".

Block cal ls

Wit h the excepti on of OB 1 t o OB 39 you must cal l th e bl oc k s to

pr ocess the m . Use the spe cia l STEP 5 bl oc k call op erat io ns to call the

bloc ks.

You ca n pro gra m bloc k ca lls inside an orga ni z atio n, progr am ,

function or sequence block. They can be compared with jumps to a

subrout ine . Eac h jump ca uses a block change. T he return addre ss

wi thin th e call ing block is buffere d by the system .

Program, Organization and Sequence Blocks

CPU 948 Programming Guide

2 - 16 C79000-G8576-C848-04

Bloc k calls can be unco nditi onal or con dit iona l as foll ows:

Unconditional call

The "JU" state men t belo ngs to the unc ondi tiona l opera ti ons. It has no

effect on the RLO. The RLO is carried along with the jump to the new

bl oc k. With in t he n ew bl oc k, it c an be ev al ua ted bu t no l onge r

combined logically.

The addres sed bloc k is processed regardless of the prev ious result of

logic oper at io n (RL O - see Sec t ion 3 .4).

Example : JU PB 100

Conditional call

The JC stat ement be longs to the conditional opera ti ons. Th e a ddresse d

bloc k is processed only if the prev ious RLO = 1. If th e RLO = 0, the

jump is not executed.

Example: JC PB 100

Note

Aft er the condi ti ona l jum p ope ra t ion is exe c ut ed , the RLO i s set

to "1" regardless of whether or not the jump to the block is

executed.

PB 1 PB 5 PB 10

PB 6

I1.0 I2.0

I3.0

JU PB 5

OI5.3

AI1.5

JC PB 6

AI3.2

JC PB 10

OF1.5

Fig. 2-3 Block calls that enable processing of a program block

Program, Organization and Sequence Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 17

Effect of the BE statement

Afte r the "BE" sta tem ent (block end ), the CPU continue s the use r

pr ogra m in the block i n which t he bloc k ca ll wa s prog ra mme d.

Pro gra m exec ut ion c on tinue s at the STE P 5 state m ent fo llowin g the

bl oc k c al l.

The "BE" statement is executed regardless of the RLO. After "BE",

the RLO c a n no lo nge r be co mb ine d l ogi ca l ly. How e ve r, the RLO o r

ari thm e ti c r esul t occ urr ing dire ctl y be for e exe c uti on of the BE

oper atio n is transfe rr ed to the block whe re the cal l origina ted a nd can

be eva luat ed the re. Whe n program execution re turns from the bloc k

that has been called, the contents of ACCU 1, ACCU 2, ACCU 3 and

ACCU 4, the condition codes CC 0 and CC 1 and the RLO are not

cha nge d. (Re fe r t o Sect ion 3.5 for m ore deta il ed inf orm a ti on a bout the

AC CUs, CC 0/CC 1 and RL O ).

2.2.1

Organization Blocks as

User Interfaces Org an iz ation bloc k s form the interfaces bet ween t he syst em program

and t he u ser pr ogra m. Orga niz ati on bl oc ks OB 1 to OB 39 belong to

yo ur use r progra m just a s progra m blo ck s. By progra m m ing the se

OBs, you ca n influe nc e the be havi or of t he CPU duri ng sta rt -up,

pr ogra m ex ecut ion and in the event of an er ror. The o rga ni za t ion

bloc ks ar e effe c ti ve as soon as they a re loa de d in the PLC mem ory.

This is also possibl e while the PLC is in the run mode .

Onc e the system program has ca ll e d a specifi c orga nizat ion block, the

use r progra m it cont a ins is exe cu te d.

Note

You c an pro gra m blocks OB 1 to OB 3 9 as user int e rfa ces a nd

the y are ca ll ed aut om ati cal ly by the syste m progra m as a reac ti on

to certain events.

For t est pur pose s, you c an a lso c al l the se org an iz ati on bl ocks

from the user progr am (JC/JU OB xx x). It is, however, not

po ssible to t rigger a COLD RE ST ART , e.g. by cal ling OB 20 .

The fol lowi ng t ab le prov ide s you wi th an ove rv iew of th e use r

interfaces (OBs).

Program, Organization and Sequence Blocks

CPU 948 Programming Guide

2 - 18 C79000-G8576-C848-04

Organization blocks for controlling program execution

Bloc k Funct ion and c all cri ter ion

OB 1 Orga ni z atio n of c ycli c progra m ex ecut io n; first c a ll a fte r a start -up , the n cycl ic c all.

OB 2

OB 3

OB 4

OB 5

OB 6

OB 7

OB 8

OB 9

With DX-0 se tti ng "Proc es s interr upt se rvicing via input byte

IB 0 =on":

(inte rr upt ab ilit y at block b ound arie s, ca n be set in DX 0)

Call with signal state change in input byte IB 0 in bit:

I 0. 0

I 0. 1

I 0. 2

I 0. 3

I 0. 4

I 0. 5

I 0. 6

I 0. 7

OB 2

OB 3

OB 4

OB 5

OB 6

OB 9

With DX-0 se tti ng "Proc es s interr upt se rvicing via input byte

IB 0 = off":

(interruptability at operation or block boundaries, can be set in DX 0)

Ca ll via inte r ru pt l ines of the S5 bus:

System interrup t INT X ( INT A, B, C or D, dep en ds o n sl ot )

System inte rrupt INT E

System inte rrupt INT F

System inte rrupt INT G

Delay e d i n terrupt

Cl oc k-c ont rolled i nte rr upt

OB 10

OB 11

OB 12

OB 13

OB 14

OB 15

OB 16

OB 17

OB 18

Orga niz at ion of tim e- contr oll e d progra m exe cuti on (tim e d inte rru pt) with

sel ect a ble basic cl ock rate (default T = 100 ms) and

cloc k distri butor (def ault co r resp onds to 150U) in da ta blo ck DX 0;

Calls as follows:

De fault setti ng 1 50U cloc k distri but or 2n clock distributor

0.1 s

0.2 s

0.5 s

1.0 s

2.0 s

5.0 s

10.0 s

20.0 s

50.0 s

T* 1

T* 2

T* 5

T*10

T*20

T*50

T * 100

T * 200

T * 500

T* 1

T* 2

T* 4

T* 8

T*16

T*32

T*64

T * 128

T * 256

Table 2-1 Over view of the organ iz ati on bloc ks of the CPU 94 8 for program execu tion

Program, Organization and Sequence Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 19

Or gani zatio n bloc ks to contr ol the start-up pr oc edure

Block Function and call criterion

OB 20 Cal l on requ est for COL D RESTAR T (ma nual and aut om ati c)

OB 21 Cal l on requ est for MANUAL WARM REST ART /C OLD REST ART WITH

MEMORY

OB 22 Cal l on requ est for AUTOMATI C WARM REST ART/ COL D RESTART

WITH MEMOR Y

Or gani zatio n bloc ks to contr ol the start-up pr oc edure

Block Function and call criterion

OB 38 Organ iz a tion of t he star t-u p proc e dur e for co mm un ica ti on in the

"soft stop" mode .

OB 39 Organiza tion of the cycl ic prog ram fo r commun ica tion in the

"soft stop" mode .

Or gani za tio n blocks for re ac ti on to devic e or prog ra m error s 1)

Block Function and call criterion

OB 19 Runtime erro r (LZF) : cal led bloc k not loaded (PB , SB, FB, FX)

or attempt to open a data block that is not loaded (DB, DX)

OB 23 Timeout (QVZ) in user pro gra m (duri ng di re ct acc es s to I/O modu les )

OB 24 Timeout (QVZ) whe n updating the process image and tr ansferrin g

interprocessor communication flags.

OB 25 Addressing error (ADF)

OB 26 Cycle time exceeded (ZYK)

Table 2-4 continued:

OB 27 Substitution err or (SUF)

Table 2-2 Over view of the organ iz ati on bloc ks of the CPU 948 for start -up

Table 2-3 Orga ni za tio n block s of the CPU 948 for a SOFT STOP

Table 2-4 Over view of the organ iz ati on bloc ks of the CPU 948 for error handl ing

Program, Organization and Sequence Blocks

CPU 948 Programming Guide

2 - 20 C79000-G8576-C848-04

Or gani za tio n blocks for re ac ti on to devic e or prog ra m error s 1)

Block Function and call criterion

OB 28 Time out inp ut byte IB 0

(p roc ess in terru pts)

OB 29 Time out distributed I/ Os, e xt ende d ad dre s s volum e

OB 30 T imeout and parity e rror (PARE) acce ssing the user m emory

(OB 31) (set cycle monitoring time) 2)

OB 32 Load and transfer error accessing data blocks (TRAF)

OB 33 Collisio n of ti med i nt errupt s ( WEFE S/W E FE H )

OB 34 Error set ti ng up a da ta blo ck (G DB /GX DX)

OB 36 Error in self test

1) If the OB is not programmed, the CPU changes to the stop mode in the event of an error. EXCEPTION: if OB 19

(logic block not loaded), OB 23 or OB 24, OB 29 (timeout) or OB 33 (collision of timed interrupts) do not exist,

there is no reaction!

2) OB 31 only exists in the CPU 948 for the sake of com patibility.

To set the cycle monitoring time, you sho uld use data block DX0 (refer to Chapter 7)

OB 31 is called once during the start-up, if loaded. You can also use it to s et the cycle monitoring time by programming

the following STEP 5 operations in it:

:L KF +nnn

:BE

nnn is a decimal number. The cycle monitoring time is obtained from "nnn * 10 ms".

Ope ra ting system org aniz at ion bl oc ks of the CP U 948

Block Func tion

OB 0 In terna l bloc k bel ongi ng t o ope ra ting syste m

Program, Organization and Sequence Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 21

2.2.2

Organization Blocks for

Special Functions The fol lowi ng or ga niz a tion blocks co ntai n spec i al funct ion s of the

system prog ram. You cannot p rogram these blo cks, but si mply ca ll

the m (thi s applie s to all OBs with num be rs betwe en 121 a nd 255!).

The y do not cont ain a STE P 5 progra m. Spec ial fu ncti on OBs can be

called in all logic blocks.

Integr ate d or gani zati on bloc ks with spe ci al funct ions

Block : Block func tion :

OB 121 Se t/re a d time of day (com pa tibl e with CPU 946/ 947)

OB 122 "Di sab le inte rrup ts" on/ off

OB 124 Delete STEP 5 blocks

OB 125 Generate STEP 5 blocks

OB 12 6 Defi ne /tra nsfe r proce s s images

OB 12 9 Bat tery state

OB 131 De let e ACCU 1 to ACCU 4

OB 132 Roll up ACCU

OB 133 Ro ll down ACCU

OB 14 1 Ena bl e/ di sabl e "disa bl e individua l tim ed int er rupt s"

OB 14 2 Ena bl e/ di sabl e "de lay a ll int er rupt s"

OB 14 3 Enabl e/ disa ble "dela y sing le timed i nterr upt s"

OB 150 Se t/re a d system tim e (co mpat ib le with CPU 928B )

OB 15 1 Set/ re ad cl ock-contro lled inter rupt time

OB 153 Se t/re a d time for del aye d inte rrup t

OB 180 Variable data block access

OB181 Te st data blo ck s (DB/DX)

OB 18 2 Copy da ta are a

OB 200, 202 to 205 Functions for multiprocessor communication

OB 222 Restart cycle monitoring time

OB 22 3 Comp ar e start -up type s of CPUs in mul tiproc e s sor mode

OB 25 4, 255 Co py/ dupl ic a te DB and DX da ta blo ck s from me m ory c a rd to u ser me mo ry

The se spe c ial fu nc tions ar e desc rib ed in de tai l in Cha pter 6.

Table 2-5 Over view of the organ iz ati on bloc ks of the CPU 948 for speci a l func tion s

Program, Organization and Sequence Blocks

CPU 948 Programming Guide

2 - 22 C79000-G8576-C848-04

2.3 Func tion Blocks

Fun ct io n block s (FB /FX) a re also parts of t he user pr ogra m just like

pr ogram block s. FX function bloc ks have the sam e struct ure as F B

function blocks and are programmed in the same way.

You use function blocks to implement frequently recurring or very

compl ex func ti ons. In th e user p rog ram , each fu ncti on block represents a

complex c ompl ete func tion. You can obtain function bloc ks as fol lows:

•• as a softwar e produc t from SIEMENS (stan da r d functio n blocks

o n disket te - see /11 /); wit h thes e f unc tion blocks you c an ge ne ra te

u ser pr ogra m s for fa st a nd sim pl e open loop co n tro l, signa l li ng,

cl osed loop con tro l and lo ggi ng;

•• yo u can progra m func tion b locks you rsel f.

Co mp ar ed with orga niza tion, progra m an d sequ ence bloc ks, functi on

bloc ks ha ve t he followi ng fo ur e sse nt ial differences:

OB, PB, SB FB/FX

1. Range of oper ati on s

onl y ba sic ope ra ti on s - b asi c op er at io ns,

- s upplementar y operations

- system operations

2. Method of repre sentatio n

pro gra m mi ng a nd c a ll

in STL, LAD, CSF p rogr amm in g only in AWL

3. Name

na me e nvi ron me nt not

possible

(only nu mber )

in a ddi ti on to the num be r

a name with max. 8 chars. can

be assigned

4. Operands

non e f orma l operand s (bloc k

parameters).

When the block is called

f ormal opera nds are assigne d

actual operands

Function Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 23

2.3.1

Stru ctu re of Fu n ctio n Bl oc ks The block he ader (five word s) of a functi on block has the same

structure as the headers of the other STEP 5 block types.

The block body on the othe r hand, has a different structure from the

bo die s of th e othe r bl oc k typ es. Th e bloc k bod y co nta i ns the funct ion

to be executed in the form of a statement list in the STEP 5

pr ogram ming langua ge. Betwe en the bloc k head er and the STEP 5

sta t eme nt s, the fu nc ti on bl oc k ne ed s additi ona l me m ory spa c e for it s

na m e and for a list of form a l oper an ds. Since this li st c ont ai ns no

stat eme nts for the CPU, it is skipped wi th an uncon ditio nal jump tha t

the progr am m er ge ne ra te s aut om ati ca l ly. T his ju mp st ate me nt is not

di spla ye d whe n the func ti on bl oc k is di sp laye d on t he PG!

Whe n a f unc ti on bl oc k is cal le d, onl y the bl oc k bod y is proc e s sed.

Absolute or symb olic

operands

You can e nter op eran ds in a func tion bloc k in absol ute form

(e.g. F 2.5 ) or symbol ica lly (e.g. MOTOR1) . You must store the

as signment of the sym bolic opera nds in an assig nme nt list before you

enter the opera nds in a fun ct ion blo ck (see /3/).

Fig. 2-4 shows the struct ure of a funct ion bloc k in the mem or y of a

pr ogram mab le controll er.

Name of the FB/FX

Formal operand 1

Formal operand 2

Formal operand n

5 words

1word

4 words

3 words

Block

header

Block

body

3 words

Skip formal

operand

list

1st STEP 5 user operation

3 words

List of

formal

operands

STEP 5

user

program

Fig. 2-4 Structure of a function block (FB/FX)

Function Blocks

CPU 948 Programming Guide

2 - 24 C79000-G8576-C848-04

The me m ory c ontains all the in formation t hat th e progra mm er nee d s

to represent the function block graphically when it is called and to

che ck the opera nd s durin g para met er assign ment and progra mmi ng of

the func ti on bl oc k. Th e progra m m er r eje ct s i nc orr ect input.

Whe n ha ndl in g func t ion b locks, dist ing uish be t wee n t he foll owing

procedures:

•• programming FB/FX

and

•• calling FB/FX and then assigni ng ac tual value s to the parameters.

Distincti on: "programming"

– "calling and assigning

parameters"

When programming, you specify the function of the block. You must

dec id e whi ch inp ut op er an ds the funct ion req uir es a nd whi ch outp ut

resul ts it should t ransfer to t he cal li ng pro gra m . You def ine the input

op eran ds an d output resul ts as for ma l ope ra nds. The se f unc tion a s

tokens.

When a block is called by a higher order block (OB, PB, SB, FB, FX),

the formal ope rands (bloc k pa ram et ers) a re replace d by actual ope rands;

i.e. parameters a re assigned to the function bloc k.

How to program

IF... THEN...

You wa nt to progra m a fun ctio n

bl oc k "d i re ct ly", i .e. wit ho u t

formal operands.

Pr ogra m it a s you wou ld a

p rogram or sequence block.

You wa nt to use form a l opera nd s

in a functio n blo ck. Proceed as explained on the

f oll ow i ng pa ge s.

Ma ke sure you keep to the

required order:

Fi rst progra m the FB/FX with t he

f orm a l ope ra nd s and ke e p it on

the PG (offl in e) o r in the CP U

me m ory (o nline)

The n progra m the bloc k(s) to be

called with the actual operands.

Function Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 25

2.3.2

Programming

Fu nction Bl ocks You can program a function block only in the "stateme nt list"

me tho d of re pre se nta t ion . Whe n e nteri ng a func t ion b lock a t a

pr ogram m er, perform the follo wing steps:

Step Action

1 Enter the block type (FB/ FX ) and the number of the

function block.

Nu mb er y our fu nc ti on bl oc ks in de scending orde r

starting with FB 255, so that they do not collide with

the sta ndard func ti on bl oc ks. T he sta nda rd functi on

b locks a re num be red from FB 1 to FB 199.

2 Enter the name of the function block.

The name can have a maximum of eight characters

and must start with a letter.

3If the functi on block is to proce s s formal oper ands:

Ente r the form al opera nds you req uir e in the bloc k as

b lock parameter s.

Ent e r the fol lo wing info rm at ion for e a ch form a l

operand:

- t he na me of the b loc k param e te r (m a ximum

4 characters),

- t he typ e of block para m e te r a nd th e da t a t ype of

the block parameter (if applicable)

Yo u ca n define a ma ximum of 40 form a l ope ra n d s.

4 Enter your STEP 5 program in the form of a statement

list (STL). The formal operands are preceded by an

equality sign (e.g. A = X1). They can also be referenced

more tha n once at vario us posit ions in the funct io n block .

5 Term ina te your progr am input with the block end

ope ra ti on "B E".

Function Blocks

CPU 948 Programming Guide

2 - 26 C79000-G8576-C848-04

Note

If you c ha nge the order or the number of form al op er an ds in th e

fo rmal operand list, you must a lso u pdate all ST EP 5 st ate ments

in the function block that reference a formal operand a nd also

the block parameter list in the calling block!

Program or ch an ge f unc ti on bl ocks only on disk et te or har d disk

and the n transfe r the m to your CPU!

Formal operands

The following parameter and data types are permitted as the formal

operands of a function block (also known as block parameters):

Par am e ter type Data type

I = input pa ra met er

Q = output parameter BI/BY/W/D

D = data KM/KH/KY/KS/KF/

KT/KC/KG

B = bloc k ope ra t ion

T = ti mer

C = coun ter

none

(no type can be specified)

I, D, B, T or C are parameters that are indicated to the left of the

fu nc tion symbol in gra ph ic re pre sen ta tion.

Parameters labelled with Q are indicated on the right of the f uncti o n

symbol.

The da ta typ e indi ca t es whe th er you a re worki ng with bits, byte s,

words or doub le words for I and Q param e ters an d which dat a form at

applie s to D pa ra m et e rs (e. g. bi t patt e rn or hexade c im a l pa t te rn).

Table 2-5 Permitted formal operands for function blocks

Function Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 27

2.3.3

Calling Function Blocks

and Ass ignin g Para mete rs

to them

You can cal l every fu ncti on bloc k as often as you want an ywhe re in

yo ur ST EP 5 pr ogra m. You can c a ll func ti on bl oc ks in a state m en t list

or in one of the gra phi c metho ds of represen tati on (CSF or LAD) .

To c all a func t ion block a nd a ssign pa ra m e ters to i t, pe rfor m the

foll owin g steps:

Step Action Reaction on PG

1 Make sure tha t the ca lle d func t ion b lock e xi sts ei the r

in the PG mem ory (offl in e) or in the CPU me mory

(online).

none

2 Enter the call statement for the function block in the

block where the call is to originate.

You ca n prog ram a func t ion b lock ca ll in an

org an iz ation, program or sequenc e block or

in another function block.

Afte r you en te r th e call stat e ment

(e.g. JU FB200), the name of the

re le va nt func ti on block a nd th e fo rm al

ope ra nd l ist a ppe a r automa tic a ll y.

3 Assign the actual o pe ra nd re le va nt to this c al l to ea c h

of the form a l oper ands, i.e. you as sign parameters to

the function block.

These act ual operands ca n be di ffere nt for

separate c alls (e.g. inputs a nd outputs for the

first call of F B 200, fla gs for the second call).

Using the form al operand list, you a ssign the

required ac tual ope rands for each function

block call.

none

Unconditional/conditional call

Uncondi tio nal c al l Condi tio nal c al l

"JU FBn" fo r FB func t ion bloc ks or

"DOU FXn" f or FX ex te nde d functi on bl ocks:

the ref er en ce d fu nc tion block is proc es sed

regard le ss of the previ ous result of logic

op er at io n (RL O).

"JC FBn " for FB fu nc tion bl oc ks or

"DOC FXn" for FX extended function blocks:

th e re fe re nc e d f un ct io n block i s only

proce ssed when the re su lt of logic ope ra ti on

RLO = 1. If RLO = 0 the block call is not

executed. Regardles s of whether the blo ck call

is e xe c ut ed o r no t , t h e R LO is alswa ys set to "1".

Af ter the unco nditiona l or con ditio nal call, th e RLO c an no longer be com bi ned logica lly. Howeve r, it is

carried over to the called function block with the jump and can be evaluated there.

Function Blocks

CPU 948 Programming Guide

2 - 28 C79000-G8576-C848-04

Permitted act ua l operands

Whi ch o pera nds ca n be assi gne d as actua l operands is shown in the

foll owin g table.

Parameter

type Dat a type Actua l oper ands per mitte d

I, Q BI for an oper an d

wit h bit a ddre s s

BY for an oper an d

wit h byte a dd re ss

W for an oper and

with word add ress

D for an op eran d

with double word add re ss

I n.m input

Q n.m output

Fn.mflag

IB n input byte

QB n output byte

FY n flag by te

DL n data byte left

DR n data byte right

PY n peripheral byte

OY n byte from exte nded periphery

IW n input word

QW n output word

FW n flag word

DW n data word

PW n peripheral word

OW n word from extended periphery

ID n input double word

QD n output double word

FD n f lag double word

DD n data double word

DKM for a bi na ry pa tt e rn (1 6 bit s)

KY for two absolute numbers,

one byte each, each in the

ra nge from 0 to 255

KH for a hexadec im a l pa tt e r n

wit h a m a xi mu m of four

digits

KS for two alphanumeric

characters

KT for timer valu e (BCD-

coded) units .0 to .3 and

va lu es 0 to 9 99

KC for a counter value

0 to 999

Constants

Table 2-6 Permitted actual operands for function blocks

Function Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 29

Parameter

type Dat a type Actua l oper ands per mitte d

Table 2-6 continued:

(Cont.) K F for a fi xed poi nt numb er

-32 768 to +3 2767

KG for a floa ting poi nt

number1)

Constants

BData type designa tion no t possible DB n Data block ; the operatio n

C DB n is executed

FB n Function block (permi tted

only without parameters)

called unconditionally (J U . . n)

OB n Organization bl ock called

unconditionally (JU . .n)

PB n Program blocks - c al led

unconditionally (JU . .n)

SB n Sequence blocks - called

unconditionally (JU . .n)

TData type designa tion no t possible T 0 to 255 Timer

CData type designa tion no t possible Z 0 to 255 Counter

1) ±0.1469368 x 10-38 to ±0.1701412 x 1039

Note

S fl ag s are not perm it ted as ac tu al opera nds for func ti on bloc ks.

After the jump to a function block, the actual operands from the block

the n cal led are used in the fun ctio n block progr am in stead of the

fo rm al operands.

Thi s fea tu re of prog ra mm abl e fu nc tion bl oc ks al low t hem t o be used

fo r a wide var iety of purp oses in your user progra m .

When the pr ogram returns from the calle d func ti on block, the li st of

ac tua l ope ra nds in the call in g block is skippe d by a jump o pera ti on

ac ti va ted impl ic i tly by ST EP 5 i n MC-5 code .

Function Blocks

CPU 948 Programming Guide

2 - 30 C79000-G8576-C848-04

Examples

Example 1: the following (complete) example is intended to further clarify

the programming and calling of a function block and the assign-

ment of parameters to it. You yourself can easily try

ou t th e example.

Programming the function block FB 202:

FB 202

SEGMENT 1

NA ME EXAMPLE

DECL : INP1 I/Q/D/B/T/C: I BI/BY/W/D: BI

DECL : INP2 I/Q/D/B/T/C: I BI/BY/W/D: BI

DECL : OUT1 I/Q/D/B/T/C: Q BI/BY/W/D: BI

:A= INP1

:A= INP2

:== OUT1

:BE

Function block FB 202 is called and has parameters assigned

to it in program block PB 25:

STL method of representation CSF/LAD method of representation

PB 25

SEGMENT 1

: JU FB 202 FB 202

NAME : EXAMPLE EXAMPLE

INP1 : I 13.5 I 13.5 INP1 OUT1 Q 23.0

INP2 : F 17.7 F 17.7 INP2 :BE

O UT 1 : Q 23.0

:BE

The following operations are executed after the jump to FB 202

Formal

operand

list

STEP 5

state-

ments

Formal

operands Parameter

type Data

type

Formal

operands Actual

operands

Function Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 31

Example 2: call ing a functi on b lock and assigning param eter s to it with

the STL and CSF/LAD meth ods of repre sentatio n in a progr am block.

STL method of representation

PB 25

SEGMENT 1

:CDB5

: JU F B 201

NAME : REQUEST

DATA : DW 1

RST : I 3.5

SET : F 2.5

MTIM : T2

TIME : KT 010.1

TRAN : DW 2

BEC : Q 2.3

LOOP : Q 6.0

:BE

CSF/LAD method of representation

PB 25

SEGMENT 1

FB 201

REQUEST

DW1 DATA TRAN DW 2

I 3.5 RST BEC Q 2.3

F2.5 SET LOOP Q 6.0

T2 MTIM :BE

KT 010. 1 TIME

Formal

operands Actual

operands

Function Blocks

CPU 948 Programming Guide

2 - 32 C79000-G8576-C848-04

2.3.4

Special Function Blocks Apa rt from the func ti on bl ocks tha t you prog ra m yourse lf, you ca n

orde r standar d functio n block s as a fini sh ed softwa re produc t. Th ese

cont a in sta nd ard func t ion s for gene ra l use (e.g. sign alli ng fu nc tio ns

and s e que nc e con trol).

St anda rd fun ctio n blo cks are assigne d num bers FB 1 to FB 199.

If you order standard function blocks, remember the special

instru ct io ns in the ac co mp an yin g desc ri ption ( i.e . area s as signe d and

conv en tions et c.) .

The standard function blocks for the S5-155U are listed in catalog

ST 57 /11/.

Example

Floating point root extractor RAD:GP FB 6

The functio n block RAD:GP e xtracts the root of a floating point number

(8-bit expo nent and 24-bit mantissa). It forms the square r oot. The

result is a lso a fl oating p oint num ber (8-bit exponent and 24-bit

mantissa). The leas t signif icant bi t of the mantissa is not rounded up or

down.

If applicable, for the rest of the processing, the function block sets the

"radican d nega tive " identifier.

Numerica l rang e:

Radicand - 0.1469368 Exp. -38 to +0.1701412 Exp. +39

Root +0.3833434 Exp. -19 to +0.1304384 Exp. +20

Function: Y = √

Y = SQ RT ; A = RA DI

Calling the function block FB 6:

In the example , th e ro ot i s extrac ted from a floating point nu mber tha t is

located in DD5 of DB 1 7 wi th an 8- bit exponent and a 24-bit ma ntis sa. The

result, anothe r 32 -bit flo ating po int number, is written to DD 10. Pri or t o

this, the appr opri ate data block must be opene d. The param eter VZ (paramet er

type: Q, data type : BI) indica tes the sign of the radicand : VZ = 1 for a

negative radic and.

Function Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 33

"Floating point root extractor" continued:

STL method of representation LAD method of representation

Seg- : C DB 17

ment : SEGMENT 2

1:***

: JU FB 6 FB 6

Seg- NAME : RAD : GP RAD

ment RADI : DD 5 DD 5 RADI VZ F 15.0

2 VZ : F 15.0 SQRT DD 10

*) SQRT : DD 10 :BE

DD= data double word

*) Must be located in separate segments, since the operation "C DB 17" in

segment 1 cannot be converted to LAD/CSF.

Function Blocks

CPU 948 Programming Guide

2 - 34 C79000-G8576-C848-04

2.4 Data Blocks

Data blocks (DB) or e xten ded da ta block s (DX) are use d to store the

fixe d or va ri a ble da ta wit h which the user progr am works. No ST EP 5

operatio ns are processed in data blocks.

The data of a dat a block i nclud es th e foll owin g:

•• vari ous bi t patt e rns (e .g. fo r status of a controlle d proc e ss)

•• numbers (hexadecimal, binary, decimal) for timer values or arith-

metic results

•• alp ha num e ric cha ra ct e rs, e. g. for message te xts.

Structu re of a data block

A data bl ock (DB/ DX) co nsists of the followi ng pa rts:

•• block prehe ade r (DV, DXV),

•• bl oc k heade r

•• bl oc k b ody.

Block preheader

The block pr ehe ade r is created automatically on the hard or floppy

disk of the PG and not transfe rr ed to the CPU. It con ta in s the dat a

form ats of the data words enter ed in the bloc k body. You have no

influence over the creation of the block preheader.

Note

Whe n you transfe r a data bloc k from the PLC to diskette or hard

disk, the co rre spond ing bloc k preh ea der c an be del ete d. For th is

rea son, you m ust ne ve r modi fy a da ta blo ck with diff er en t data

form at s in th e PLC and then tra nsfe r it back to di sket te, oth er wise

all the da ta word s in the DB a re aut om a ti cally as signed t he data

fo rm at you se le cte d in the pre set s scre e n form .

Data Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 35

Block header

The block he ade r oc c upie s five words in the me m ory and con ta ins

the following:

•• th e b loc k i dentifi er

•• the programmer identifier

•• t he bloc k t y pe an d the bl ock num be r

•• the library number

•• the block length (including the length of the block header).

Block body

The block body contains the da ta w ords with whic h t he user program

works. These dat a words a re in ascending order in the bl ock body,

starting with data word DW 0. Each data word occupies one word

(16 b its) in the mem or y.

Maximum length

A data bloc k can occupy a tota l of ma ximu m 32 767 word s (inc ludin g

hea de r) i n the CPU mem or y. Whe n yo u use your programme r to en ter

and tra nsfe r data block s, rem embe r the size of your CPU memor y!

Data Blocks

CPU 948 Programming Guide

2 - 36 C79000-G8576-C848-04

2.4.1

Creating Data Blocks To c reate a da ta bl ock, perform the foll owing steps:

Step Action

1 En ter the block type (DB/DX) and data block number (2

or 3 to 255).

2 Enter in dividual data word s in the data format you

require.

(Do not complet e yo ur in put of the da ta words with a

B E stat em ent!)

Note

Da ta bloc k s DB 0 , DB 1, DX 0, DX 1 a nd D X 2 are re se r ve d f o r

spe cifi c func ti ons and you canno t use the m fre ely for o ther

fu ncti ons (see Se ctio n 2. 4. 3)!

Type Data forma t Exampl e s

KM Bit pat tern 00100110 001111 11

KH Hexadecimal 263F

KY 2 By te s 0 38, 063

KF Fixe d poi nt numb er +09791

KG Fl oati ng point numbe r +135612 3+ 12

KS Character ?!ABCD123-+.,%

KT T im e r va lue 0 55. 2

KC C ounter value 234

Table 2-7 Data formats permitted in a data block

Data Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 37

2.4.2

Opening Data Blocks You can only open a data block (DB/DX) unconditionally. This is

po ssible wit hi n an o rga ni za tion, progra m , seque nc e or funct io n blo ck .

You ca n open a spec ific data bl ock mo re tha n once in a progra m.

To open a da ta block, perform the fol lowing step s:

IF... THEN...

You wa nt to open a DB data block Type in the STEP 5 operation

"C DB.."

You wa nt to open a DX data

block Type in the STEP 5 operation

"CX DX."

Validity of a data block

Aft er you op en a da ta bloc k, al l state m ents that follow wi th t he

op erand area ’D’ refer to the ope ne d data bl oc k.

The ope ned da ta bl ock also re ma ins val id when the progra m is

cont in ue d in a diffe re nt bl ock fol lo wing a bloc k cal l.

If a sec on d da ta block is o pe ne d in this ne w blo ck, the sec ond da t a

bl oc k is only valid in the newly called block from the point at which it

is call ed . After prog ra m exec uti on ret urns to the cal li ng bloc k, the old

da t a bl oc k is onc e ag ai n vali d.

Access

You can access the da ta stored in th e open ed dat a b lock durin g

pr ogram execution using binar y logic oper ati ons, se t/re set

operations, load or transfer operations (refe r t o Cha pter 3 f or m ore

det aile d infor ma t ion ).

With a binar y ope r ati on, the addre ssed dat a word bit is used to for m

the RLO. T he con te nt of the da ta word is not change d.

Wit h a set/re set ope ra tion, the addr esse d da ta word bi t is assigne d the

value of the RLO. The content of the data word may be changed.

A load ope ra tio n transfe rs the conten ts of the refere nce d data word

into ACCU 1. The contents of a data word are not changed.

A transfer operation transfers data from ACCU 1 to the referenced

data wor d. The ol d co ntent s of the da ta word are ove rwritten.

Data Blocks

CPU 948 Programming Guide

2 - 38 C79000-G8576-C848-04

Note

Befo re acc essin g a dat a wor d, you m ust ope n the data b lock yo u

require in your pr ogra m . Thi s is the only way t ha t the CPU c an

find the corre ct data word.

The re fe re nc ed d at a word m ust be co nta i ne d in t he ope ne d blo ck ,

othe rwise th e syste m prog ra m de t ec t s a loa d or transfer e rror.

With load and transfer operati on s, you ca n only acce ss data word

numbers up to 255!

An ope ned dat a block rem ai ns valid until one of the follo wing

events occur:

a) a second data bl ock is opened

b) the bloc k, in whic h t he data block was

opene d, is com ple ted with ’BE’, ’BEC’

or ’BEU’.

Examples

Example 1: transferring data words

You want to transfer the contents of data word

DW 1 from data block DB 10 to data word DW 1 of

data block DB 20.

Enter the fo llow ing st atements:

:C DB 10 (open DB 10)

:L DW 1 (load the contents of DW 1 into

: A CCU 1)

:C DB 20 (open DB 20)

:T DW 1 (transfer the contents of ACCU 1 to

: D W 1)

Data Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 39

Example 2: range of validity of data blocks

(F ig . 2-5)

Data block DB 10 is opened in program block PB 7 (C DB 10). During the

subsequent program execution, the data of this data block are processed.

After the call (JU PB 20) program block PB 20 is processed. Data block

DB 10, however, remains valid. The data area only changes when data block

DB 11 (C DB 11) is opened.

Data block DB 11 now remains valid until the end of program block PB 20

(BE).

After the j ump back to prog ram block PB 7, data block DB 10 is once again

valid.

PB 7

CDB11

PB 20

CDB10

JU PB 20

Range of validity of DB 10

Range of validity of DB 11

Fig. 2-5 Range of vali dity of an open ed dat a block

Data Blocks

CPU 948 Programming Guide

2 - 40 C79000-G8576-C848-04

2.4.3

Special Data Blocks O n the CPU 948 data blocks DB 0, DB 1, DX 0, DX 1 and DX 2 are

reserved for spe cial f unctions. They are man aged b y the system

pr ogra m and you c a nnot use the m fr eel y for ot he r fun ctions.

DB 0

•• Dat a bloc k DB 0 (see Se cti on 8.3.2)

Da ta bloc k DB 0 cont ai ns the a ddre ss list with the start addresses

of all bloc ks that are loca ted in the dat a bloc k RAM of the CPU.

The syste m progr am ge nera te s this add re ss li st during initi aliz ati on

( fol lowi ng ea ch POWE R UP or OVE RAL L RESE T ) and it is up-

dated automatically when you use a programmer to change data

blocks or generate a new data block.

DB 1

•• Dat a bloc k DB 1 (se e Se c ti on 10. 1. 6)

Data block DB 1 contains the list of digital inputs/outputs (P periphe-

ral with re lative byte a ddresses from 0 to 127) and the interproce ssor

communic ation (IP C) fl ag inputs a nd output s that are assigned t o the

CPU. If applicable, the block may also contain a timer field length.

DB 1 can have para me t ers as signed a nd be lo aded as follows:

to reduce the cycle time in single processor operation, since

onl y the inputs, outputs or time rs ente re d in DB1 a re updated.

DB 1 must be assign ed par amete rs and load ed as follows:

a) for multiprocessing

b) whe n IPC fla gs exi st wit h CP s

DX 0

•• Dat a bloc k DX 0 (see Chapter 7)

If you assign parameters to data block DX 0 and load it, you can chan-

ge t he defa ults of ce rtain s ystem program func tions (e .g. the start-up

procedure) and adapt the pe rforma nce of the s ystem program to your

particular application.

DX 1

•• Dat a bloc k DX 1

R ese rve d.

DX 2

•• Data block DX 2

Reserved for the second serial interface.

Data Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 2 - 41

Data Blocks

CPU 948 Programming Guide

2 - 42 C79000-G8576-C848-04

Cont ents of Ch apter 3

3.1 Princ ip le of Progra m Exec uti on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 4

3.2 Program Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 5

3.3 Stori ng Progra m and Data Block s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 10

3.4 Processing the User Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 11

3.4.1 Defi nition of Te rms used in Progra m Exec ution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1 2

3.5 STEP 5 Operati ons with Examp le s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1 5

3.5.1 Basic Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1 9

3.5.2 Programming Examples in the STL, LAD and CSF Methods of Represent ation . . . . . 3 - 34

3.5.3 Supplementary Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 49

3.5.4 Executive Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 59

3.5. 5 Sem ap hore Ope rati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 75

Program Execution

CPU 948 Progra mming Gu ide

C79000-G8576-C848-04 3 - 1

Contents

CPU 948 Prog ramming Gu id e

3 - 2 C79000-G8576-C848-04

3Program Execution

This cha pter is in te nde d f o r re aders who do not ye t ha ve an y gre a t

expe ri e nc e in usin g the pro gra m ming l an gua ge . The cha pte r the re fore

de als with the basi c s of STE P 5 pro gra m mi ng and e xpl a ins i n de ta il

(with exa m pl es) the STEP 5 opera tion s for the CPU 948.

Expe ri e nc ed reade rs w ho req uir e more in form a tion a bou t a spec i fic

STEP 5 operation listed in the Pocket Guide can refer to the reference

section in 3.5.

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 3

3.1 Principle of Progr am Execution

You can pro cess y our STEP 5 user program i n various ways .

Cy clic progra m exe c ut ion is mo st com mo n wit h progra mm a ble

cont rol le rs (PL Cs) . The syste m progra m runs thr ough a pro gra m loop

(t he cy cl e , re fe r t o Sec t ion 3.4 ) and ca l ls organiz a ti on bl ock OB 1

cyc li c al ly in e ach l oop (r ef er to Fig . 3-1).

Call OB1 BE

Call PB 20

PB 20

OB 1

Update inter-

processor comm.

flag outputs

image outputs

(PIQ)

Update process

Trigger cycle time

Update inter-

processor comm.

flag inputs

image inputs

(PII)

Update process

from start-up

System program User program

Fi g. 3 -1 Pri n c iple of c yclic pr o gram e xe c ution

Principle of Program Execut ion

CPU 948 Programming Guide

3 - 4 C79000-G8576-C848-04

3.2 Program Organization

Program orga niz ation a llows you to spe cify w hich conditions a ffec t the

processing of your blocks and the order in whic h t hey are proc ess ed.

Organize your program by programming organization blocks with

conditional or unconditional calls for the bloc ks you require.

You c an c all addi ti ona l p rogr am, func tion and sequ en ce bl oc ks in any

com bi na tion in the progra m of indi vi dua l orga niz a tion, progra m ,

fu nc tion a nd se que nc e b locks. You c a n cal l these one afte r anot he r or

ne st ed i n one anot her.

For m axi mu m effi c ie ncy, you sho uld orga ni ze your prog ra m to

em pha sise th e most im port a nt progra m stru cture s a nd in such a way

tha t you can c lea rly recog niz e parts of the co ntr olle d syste m which are

rel at ed in the softwa re .

Figs. 3-2 a nd 3-3 are exa mp les of a progr am str uc tur e.

Program Organization

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 5

PB ‘B‘

OB 1 PB ’A’ FB

Go to initial

state

Stop to the system

EMERGENCY

OFF

PB ‘D‘

Message output

via standard

peripherals

Message output

via standard

peripherals

Message

texts

PB ‘C‘

Individual

control level

Group

initialization

Interface flags

of the individual

control

elements

Individual

initialization

Individual

initialization

Sequence

control Control of

sequence

cascade

FB SB

Sequence

step

Sequence

step

JU PB ’A’

JU PB ‘B‘

JU PB ‘C‘

JU PB ‘D‘

Operating mode

program

Fig. 3-2 Example of the organization of the user program according to the program structure

Program Organization

CPU 948 Programming Guide

3 - 6 C79000-G8576-C848-04

OB 1

JU PB ‘X‘

JU PB ‘Y‘

Controlled

system part ‘Z‘

PB ‘X‘

Controlled

system part ‘X‘

Individual control

Closed loop control

Signalling

Controlled

system part ‘Y‘

PB ‘Y‘ FB

Sequence control

Signalling

Closed loop control

Arithmetic

JU PB ‘Z‘

Data logging output

FB ‘Z‘

Fig. 3-3 Example of the organization of the user program according to the structure of the controlled system

Program Organization

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 7

Nesting blocks

Fig. 3-4 shows the prin cipl e of nest ed block call s.

Block addresses

A block start address specifies the location of a block in the user

me mo ry. For lo gic bl oc ks, thi s is the addre ss of t he m em ory l oc at io n

cont a ini ng t he first STEP 5 ope ra t ion (wit h FB and FX, t he JU

op er at ion via th e fo rm al ope rand list ); with dat a bl oc ks , it is the

addr ess of the fir st data word .

To ena ble the CPU to loca te the called block in the mem ory, the start

addr esse s of a ll vali d block s are entere d in the bl ock ad dre ss list in

dat a block DB 0. DB 0 is manag ed by the system progra m, you cann ot

call it yourself.

The CPU stores a return address every time a new block is called. After

the new block has been processed, this return address enables the program

to find the block from which the call originated. The return address is the

address of the memory location containing the next STEP 5 stateme nt

after the block call. The CPU also stores the start add ress and length of

the d ata b loc k valid at this location.

OB 1

PB 20

PB 5

DB 20 DB 30

JU PB 5

F 200.5

JU JU

PB 20 FB 30

OF1.5

NAME: KURV

AI 55.0

*) Operation to which the program returns

1st STEP 5 op. 1st STEP 5 op.

Fig. 3-4 Nested logic block calls

Program Organization

CPU 948 Programming Guide

3 - 8 C79000-G8576-C848-04

Nesting depth

You can only nest 40 blocks within one another. If more than 40

bloc ks a re call ed, the CPU sign als an err or a nd goes to the stop mod e.

Example of nesting depth

You can determine the nesting depth of your program as follows:

- Add all the organization blocks you have programmed

(in the example: 4 OBs).

- Add the nesting depth of the individual organization blocks

(in the example: 2 + 2 + 1 + 0 = 5).

- Add the two amounts together to obtain the program nesting depth

(in the example: 4 + 5 = nesti ng dep th 9). I t m u st n ot e xceed a v a lue

of 40.

OB 25

Nesting depth

123456789

OB 1 PB 1 FB 1

OB 13 PB 131 FB 131

OB 2 FB 21

Program

processing

level

Fig. 3-5 Example of block nesting depth

Program Organization

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 9

3.3 Sto ring P rogram and Dat a Blo cks

On the CPU 948, the use r progra m runs sol ely in the inte rna l RAM.

The use r progra m inc lud ing data bloc ks m ust , there fore , be l oade d in

the CPU 948 user memory.

How do I load programs an d

data blocks in the internal

RAM?

You can us e th e fol lowin g metho ds:

•• You can load the individual logic and data blocks in the RAM

using your PG.

•• You can progra m a memor y card (flash EPROM!) with your

com pl e te prog ram inc lud ing data blocks on the PG and the n inser t

the card in the rec e pta c le on the CPU.

If you do an ov er all rese t on the CPU (re fe r to Chapte r 4) the

com pl e te conte nt s of th e me mo ry c ar d ar e loa de d "1:1 " i n the

int erna l RAM.

•• You loade d your prog ram in the interna l RAM with the PG or

from the memory card with an OVERALL RESET. You can then

loa d a ddi tiona l bl oc ks wit h the PG or repl a ce exist in g blo ck s.

Note

You can only program the memory card on the PG. Use the PG

software from version 6 upwards. When programming, the PG must

be in the mod e "WO R D FIELD " (r efer to the S TEP 5 manu al /3 /) .

Caution

I f you ha ve cha nged or added bl oc ks usi ng th e PG a fte r l oa din g

y our pr ogra m from the me mo ry c ar d, t he se cha n g es a re reve rse d

by the next OVERAL L RESET, since the m e mory is

overwritten ag ain wit h th e cont e nts of t he mem ory ca rd.

Storing Program and Data Blocks

CPU 948 Programming Guide

3 - 10 C79000-G8576-C848-04

3.4 Processing the User Program

The co mplete softwa re on the CPU (c onsisting of the system progra m

and the STE P 5 user prog ram) has the followi ng tasks:

•• CPU START - UP

•• Controllin g an aut om a tion pro cess by cont in uousl y repe a ting

ope ra tions (CYC LE).

•• Controlling an automation process by reacting to events occurring

sp ora di ca l ly or at ce rt ain ti m es (i nt er rupt s) a nd rea ct in g to erro rs.

For all thre e task s, you can sele ct spe cia l parts of your pro gra m to run

on the CPU by progra m ming user i nterf ace s (org aniz ati on bloc ks

OB 1 to OB 35 - refer to Section 2.2.3).

START-UP

Befo re the CPU can star t cycli c progra m execut io n, an i nitial iza tion

must b e perf orm e d to establish a de fi ne d ini ti a l stat us for c yc li c

pr ogra m exec ut io n an d, for e xa mp le , to spe cify a ti me ba se for the

execution of certain functions. The way in which this initialization is

perf orm e d depe nds on the eve nt that le d to a START- UP and o n

sett in gs that you can ma ke on your CPU. For mo re deta iled

infor ma t ion , refe r to Cha pt er 4.

You can influ en ce the ST ART-UP pro ce du re of your CPU by

pr ogra mm ing orga ni za t ion bloc ks OB 20 , OB 21 and OB 22 or by

assig ning para met ers in DX 0 (refer to Chapter 7) .

CYCLE

Fol lowing the STAR T- UP, the syste m progr am goe s ove r to cycl ic

pr ocessi ng. It is re sponsi bl e for back grou nd fun ct io ns requi re d for t he

aut om at io n tasks (re fe r to Fig. 3-1 at the be gin nin g of th is se ctio n).

Afte r the system functio ns ha ve been exe cute d at the beginn ing of a

CYC LE, the system progra m c a ll s organi z at ion blo ck OB 1 or

fu ncti on bl oc k FB 0 as the cycl ic user prog ra m. You pr ogra m the

ST EP 5 opera ti ons for cyc lic proce ssin g in this bloc k.

Processing the User Program

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 11

Reactions to interrupts

and errors

To a llow you t o spe cify t he r eac tions t o int errup ts or e rro rs, spec i al

or ganiz a tion bl oc ks (OB 2 t o OB 18 for i nt errupt ser vic ing, OB 19

and OB 23 to OB 34 for rea ctions to errors) a r e a va i la ble on th e

CPU 948. You can store an appropriate STEP 5 program in these blocks.

Whe n inte rru pts or err ors a re to be proc e sse d, the system prog ram

ac ti va tes the c orre sp o ndi ng org an iz a tion bl oc k duri ng c yc li c

proc essi ng. This m ean s that the cyc l ic proc essin g is inte rru pted to

se rvi ce an in terru pt or to rea ct to an error . The nesti ng of the

or ga niz a ti on bl oc ks ha s a fi xe d pri ority ( for fu rth er info rm at io n, ref er

to Chapters 4 and 5).

In addit ion to th e or ga niz a ti on bl oc ks, you c a n also in fluence the

rea c tion of the CPU to inte rru pt servi c ing by assigni ng pa ra me te rs in

da t a bl oc k D X 0.

Org an iz ati on bl oc ks OB 1 to OB 39 ca n be cal led by t he system

pr ogra m as soo n as the y ar e loa de d in the progr am mem or y (also

during operation).

If the OBs are not load ed, there is eith er no react ion from the CPU or

(in the eve nt of errors) it goes to the sto p mode (re fer also to Sec tion

5.4).

You c an a lso l oad da ta block DX 0 into the progra m me mo ry dur ing

op er ation like the orga ni z atio n blo ck s. It i s, howe ve r, only e ffe c ti ve

afte r the ne xt COLD RESTART. If DX 0 is not loaded, the st andard

settings apply (refer to Chapter 7).

3.4.1

Definition of Terms used in

Program Execu ti on

Cycle time

The cy cl e b eg ins whe n t he cyc l e m oni to rin g ti me is trig ge red and en ds

with the nex t trigger . The time that the CPU require s to exec ute the

pr ogra m between two trig ge rs is c al le d the c yc l e tim e. The cy cl e tim e

consi sts of the runt ime of the system pr ogra m an d the runtime of the

use r progra m .

The cy cl e time there fore inclu des the fol lowing:

•• the tim e re qui red to proc ess t he cycl ic prog ra m (syste m and user

program),

•• the tim e requi re d to proc ess i nterrupts (e.g. tim e- contr oll e d

interrupt),

•• the tim e requi re d to process i nte rr upt ion s (er rors) .

Processing the User Program

CPU 948 Programming Guide

3 - 12 C79000-G8576-C848-04

Cycle time monitoring

The CPU monitors the cycle time in case it exceeds a maximum value.

The standa rd set ting for this ma ximum value is 200 m s . You can s e t t he

cycle t ime m onitori ng yoursel f or restart i t during us er program e xec ution

(refer to DX 0/ Chapter 7 and spec ial func tion OB OB 222/Section 6.16).

Process input and output

image (PII and PIQ)

The proc e ss ima ge of the in put s and outp uts i s a mem ory ar ea in t he

internal RAM.

Before cyc l ic exec ut io n of th e use r program begin s, t he syste m

pr ogra m re ad s the sign al state s of the inpu t peri phe ra l modu les an d

tra nsfe rs th em to the proce ss inp ut image . The user pr ogra m evalua te s

the signal states in the process input image and then sets the

appr opri a te signal state s for the out put s in the proc ess ou tpu t ima ge .

Afte r the user pro gram has bee n proce ssed, the system pro gram

tra nsfe rs th e signa l st ate s of the proce ss out put ima ge to the outpu t

p er iph er al mo du les .

Bu ffe ri ng th e I/O sign als in t he proc e ss im ag e of the inp uts a nd

ou tpu ts a voi ds a cha nge in a bi t withi n a progra m cy cle from causi ng

the cor re spond ing outp ut to "flutt er ".

The process ima ge is the re fore a m em ory area whose c onten ts a re

output to the peripherals and read in from the peripherals once per

cycle.

Note

The process image only exists for input and output bytes of the "P"

peripherals wit h byte a ddress es from 0 to 127!

Apart from the proc ess i ma ge integrated i n the s ys tem, you can use

OB 126 to define and transfer further proc ess image s (re fer to

Section 6.6)

Interproces sor communicat i on

(IPC) flags

IPC flags exchange data between individual CPUs (multiprocessing) or

between the CP U and som e com municat ion process ors .

The system program reads the input IPC flags of the CPU before cyclic

execution of the user program begins. After the STEP 5 program is

processed, the system program transfers the output IPC flags to the

co or dinat o r or t o th e c omm uni ca tions pr oce ss or s.

You define the i nput a nd out put IPC flags when you create data block

DB 1 (refe r t o S ection 10.1.6).

Processing the User Program

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 13

Interrupt events

Cy clic pro gra m exe c ut ion ca n be inte rrup ted by the followi ng:

•• time-controlled program execution (delayed interrupt, cyclic timed

interrupts, clock-controlled interrupts),

•• inte rr upt -dri ve n progra m exe c ut ion ( proc ess int e rrup t, syste m

int er rupt ).

The cycl ic pro gra m ca n be int errup te d or eve n aborted comp lete ly by

the following:

•• a de vic e ha rdware fa ult or progra m e rror

•• oper at or interv en ti on (using the PC stop func ti on, or sett ing the

mod e sele cto r to "stop", mu ltipr ocesso r stop MP-STP) ,

•• a stop operation

Processing the User Program

CPU 948 Programming Guide

3 - 14 C79000-G8576-C848-04

3.5 STEP 5 Operations with Examples

A STEP 5 op erat io n consist s of the oper atio n and an ope ra nd. Th e

oper at i o n s peci fies what t he CPU is to do (ope rat ion ). The ope rand

specifies with what an operation is to be executed.

STE P 5 opera tions c an be divi ded into th e followin g grou ps:

•• basic operations (can be use d in all l ogic bl oc ks),

•• supplem entar y ope rations,

•• ex ecuti ve ope rati ons (can only be used in FB/FX fu ncti on bloc ks),

•• se map hore ope ra tion s (ca n on ly be used in FB/FX fun ctio n blo ck s).

Accumulators as working

registers

The CPU 948 has fou r accum ul ators, ACCU 1 to ACCU 4. Most

ST EP 5 ope rati ons use two 32-bit regi ste rs (ACC U 1 and ACCU 2) as

the source of ope ra nds a nd t he destination for results.

The STE P 5 ope ra t ion to be ca rr ie d out affe ct s the a cc um ul a tor s, e . g. :

•• ACCU 1 is al ways the destinati on i n loa d o p er at ions. A loa d

o pera ti on shi fts t he o ld cont e nts of ACCU 1 to ACC U 2 (sta c k

lif t). Accu mu la to rs 3 and 4 ar e not cha nge d by any l oa d ope ra ti ons.

1) analogou s for ACCU 2 to ACCU 4

ACCU-1-H

Hi gh byte Low byt e High byte L ow byt e

ACCU 1

High word Low wor d

31 24 23 1 6 15 8 7 0

ACCU-1-HL ACCU-1-LH ACCU-1-LL

ACCU-1-L

ACCU-1-HH

STEP 5 Operations with Exam ples

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 15

•• Arith me tic opera tions c om bi ne the co ntent s of ACCU 1 with those

o f ACCU 2, write the result to ACCU 1 and tra nsfe r the con te nts

of ACCU 3 to ACCU 2 and the cont en ts of ACCU 4 to ACCU 3

(stack drop). In 16-b it fixed point arit hmet ic, only the low wo rd or

AC CU 3 is tr an sfe rre d to the low wor d of ACCU 2 and t he low

wo rd of AC C U 4 to th e low word of ACCU 3.

•• Whe n a con stant is adde d (ADD BF/KF/DH) to the content s of

AC CU 1, the acc um ul at ors 2, 3 and 4 a re not cha nged.

Condition codes

STEP 5 operations either s e t or eva lua te condi tion codes. T he condition

codes a r e writte n to a condition code byte. T wo groups of condit ion c odes

can be distinguished: condition codes of digital operations (word

condition codes - bits 4 to 7 in the condition code byte) and condition

codes from bi nary and exe cutive opera tions (bi t condition codes - bits 0 to

3 in the condition code byte) . You can see how the various condition

codes are influenced or evaluated by STEP 5 operations be referring to

the operat ion l ist / 1/.

You c an di spla y the c on ditio n co de byte on a prog ra mme r usi ng th e

"ST AT US" online funct ion (re fer to Sec tion 11. 2.3) . The byte has th e

fo llowin g stru cture :

Wor d condi ti on codes Bit condi tion code s

CC 1 CC 0 OV O S OR STA RL O ERAB

Bit 7 6 5 4 3 2 1 0

Bit condition codes

•• ERAB First bit scan

A logic op er at io n s eq uence containi ng bi nary oper at ions always

begins with the first bit scan, followi ng which a new RLO is

f orm e d. The bit conditi on code ERAB = 1 is then set. While the

remaining logic operations i n the sequence are being performed,

ERAB remains set to 1 and the RLO cannot be changed by these

logic operations.

The active sequence of logic operations is terminated by a binary

se t/re se t oper at ion (e .g . S Q 5.0). Th e set/re se t ope rat ion set s

ERAB to 0; the RLO ca n be evalua ted (e.g. by RLO-de pe nd ent

o pera ti ons) bu t can no lon ger be com bi ne d logica ll y. Th e next

b inary logi c ope ra tion fol lo wing a bi na ry se t/re set ope rati on i s

o nc e aga in a first bi t sc a n.

STEP 5 Operations with Examples

CPU 948 Programming Guide

3 - 16 C79000-G8576-C848-04

Example of ERAB

Other bit condition codes

•• RLO Res ult o f l o gic o p era tion

Thi s is th e resul t of bit logi c ope ra ti ons. It is the tru th stat eme nt for

com pa ri son op er at ions (refer to ope ra tions li st, bina ry lo gic

o pera ti ons or c om pa rison operations).

•• STA Status

Fo r bit opera ti ons, this in dic a tes th e logical sta tus of the bit just

sc anned or set . The statu s is updated in bi na ry lo gic ope ra tions -

exc e pt for A(, O(,), O and fo r set/r ese t ope ra tions.

•• OR Or

Inte rn al CPU bit for ha nd ling "AND be fore OR" logic ope ra tion s.

Word condit ion codes

•• OV Overflow

This i ndicate s w hether t he permissible number range w as e xce eded

during the arithmetic operation just completed.

•• OS Stored overflow

The overflow bit is stored. It can be used in several arithmetic

operations to indicate whethe r a n ove rflow occurred a t a ny poi nt

during the operations.

:A I 1.0 ERAB is set to ’1’,

: the new RLO is formed by

: an AN D operation

:O I 6.3 The RLO is influenced by

: an OR operation

:AN I 2.1 The RLO is influenced by

: an AN D NOT operatio n.

:S Q 2.4 ERAB is set to ’0’,

: the sequence is now complete

:JC FB 150 The function block is called

: dependent on the RLO.

STEP 5 Operations with Exam ples

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 17

•• CC 1 and CC 0

These are the result condition codes that you can interpret from the

following table:

Note

To e val uate t he condition c odes directly, compa rison a nd j ump

operations are ava ilable (refer to Sections 3.5.1 and 3. 5.3).

Word

conditi on c ode s Arith-

metical

operations

Digital

logic

operations

Com-

parison

operations

Shift

operations For

SED,

SEE

Jump

operations

executed

CC 1 CC 0

0 0 Result

= 0 Result

= 0 ACCU 2

ACCU 1

Shifted

bit

= 0

Semaphore

set JZ

0 1 Result

< 0 – ACCU 2

ACCU 1 ––

1 0 Result

> 0 Result

≠ 0ACCU 2

ACCU 1

Shifted

bit

= 1

Semaphore

set

enabled

1 1 Division

by 0 – – – – –

Note

When a change of level takes place, e.g. servic ing a timed interrupt,

all ac cum ulators and the bi t a nd word condition codes (RLO etc.) are

saved and loaded again when the interrupted level is resum ed.

Tab le 3-1 Resul t condi ti on co des of STE P 5 opera tion s

STEP 5 Operations with Examples

CPU 948 Programming Guide

3 - 18 C79000-G8576-C848-04

3.5.1

Basic Operatio ns You can use the basic operations in all logic bl ocks and al l m e thods of

repr esent a tion (STL , LAD, CSF).

Binary logic operation s

Operation Operand Function

I 0. 0 to 127. 7

Q 0.0 t o 127. 7

F 0.0 to 255. 7

S 0.0 t o 4095.7

D 0.0 t o 255.15

T 0 to 255

C 0 to 255

AND logi c op erat io n after sc an nin g for si gna l state "1"

OR logic operation after scanning for signal state "1"

of an input in the PII

of an output in the PIQ

of a flag bi t

of an S flag bit

of a data word bit

of a timer

of a counter

I 0. 0 to 127. 7

Q 0.0 t o 127. 7

F 0.0 to 255. 7

S 0.0 t o 4095.7

D 0.0 t o 255.15

T 0 to 255

C 0 to 255

AND logi c op erat io n after sc an nin g for si gna l state "0"

OR logic operation after scanning for signal state "0"

of an input in the PII

of an output in the PIQ

of a flag bi t

of an S flag bit

of a data word bit

of a timer

of a counter

O – C ombine AND opera t ion s t hro ugh logi c OR

)

– ANDing of exp ression s in parenthe ses

OR ing of expressio ns in pare nthe se s

Close pare nthe sis (t o comp lete the br acke ted exp re ssion )

Maximum of 8 levels are permitted, i.e. 7 opened brackets

RLO format i on

The bin ar y logic ope rati ons ge ne ra te the resu lt of log ic opera ti on

(RLO).

At the beginning of a logi c se qu en ce, the RL O onl y depe nds on t he

si gna l stat e sca nne d (f irst sca n) and not on the typ e of logi c ope ra ti on

(O = OR, A = AND).

Table 3-2 Bin ary lo gic ope rat ions

Basic Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 19

Within a s equence of logic ope rations, t he RLO i s forme d from t h e type

of opera tion, pre vious RL O and the s canned signal sta te. A sequence of

logic opera tions i s com ple ted by a n ope rat ion (e.g. s e t/reset operations)

which retains th e RLO ( ERAB = 0). Following this, the RLO can be

evaluated but cannot be further combined.

Example

Set/reset op erations

Operation Operand Function

I 0. 0 to 127. 7

Q 0.0 t o 127. 7

F 0.0 to 255. 7

S 0.0 t o 4095.7

D 0.0 t o 255.15

Set if RLO = 1

R ese t if RL O = 1

an input in the PII

an out put in the PIQ

a flag

an S fla g

a bit in the data word

I 0. 0 to 127. 7

Q 0.0 t o 127. 7

F 0.0 to 255. 7

S 0.0 t o 4095.7

D 0.0 t o 255.15

The RLO is assigned to

an input in the PII

an out put in the PIQ

a flag

an S fla g

a bit in the data word

Program Status RLO ERAB

=Q0.0

AI1.0

AI1.1

AI1.2

=Q0.1

0 RLO retained

1 first bit sca n

0 RLO retained, end of

the logic operati o n s

sequence

Table 3-3 Set/reset operations

Basic Operations

CPU 948 Programming Guide

3 - 20 C79000-G8576-C848-04

Load and transfer

operations

Operation Operand Function

IB 0 to 127

IW 0 to 126

ID 0 to 124

QB 0 to 127

QW 0 to 126

QD 0 to 124

FB 0 to 255

FW 0 to 254

FD 0 to 252

SY 0 to 4095

SW 0 to 4094

SD 0 to 4092

DR 0 to 255

DL 0 to 255

DW 0 to 255

DD 0 to 254

PY 0 to 127

PY 128 to 255

PW 0 to 126

PW 128 to 254

OY 0 to 255

OW 0 to 254

Load

Transfer

an input byte from/to the PII

an input word from/to the PII

an in put d oubl e word fro m/to the PI I

an out put byt e fr om /to the PI Q

an out put word fr om/t o the PI Q

an out put double word fr om/t o the PIQ

a flag by te

a flag word

a fla g d o ubl e wo r d

an S flag byte

an S flag wor d

an S fla g d o ubl e wo r d

the righ t byte of a data wor d from / to DB,D X

the left byte of a data word from/to DB,DX

a da ta word from /t o DB, DX

a da ta double word from /to DB, DX

a peripher al byte of the digital inputs/out puts (P area )

a pe rip he ra l byte of the ana log o r digit al inputs/output s

(P are a )

a perip hera l word of the digital input s/ou tpu ts (P area)

a pe rip he ral word o f the ana log or digit al inputs/ out puts

(P are a )

a byte of the extended I/O area (O area)

a word of the exte nde d I/O ar ea (O are a)

Table 3-4 Loa d and trans fer op erat ions /p art 1

Basic Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 21

Operation Operand Function

KB 0 to 255

KS 2 ASCII

characters

KF -32768 to

+32767

KG 1)

KH 0 to FFFF

DH 0 to

FFFF FFFF

KM 16-bit patt e rn

KY 0 to 255 for

each byt e

KT 0.0 to 999. 3

KC 0 to 999

T 0 to 255

C 0 to 255

Load

a constant, 1 byte

a consta nt, 2 ASC II cha racters

a constant as fixe d point number

a constant as floa ti ng point numbe r

a constant as hexa decima l number

a doub le word const a nt as a hexa de cim a l number

a constant as bit pa tte rn

a constant, 2 bytes

a consta nt time r va lue (in BCD)

a constant counter value

a time r, binary coded

a co unt er, binary code d

T 0 to 255

C 0 to 255

Load

a timer

a counter

in BCD

1) ±0,1469368 x 10-38 to ±0,1701412 x 1039

Load operations

Load operations wr ite the ad dr essed value in to AC CU 1. The

former conten ts of ACCU 1 are saved in ACCU 2 (stack lif t).

Transfer operations

Tra nsfe r oper atio ns writ e the conte nts of ACCU 1 to the addre sse d

me mory loca t ion .

Table 3-5 Loa d and trans fer op erat ions /p art 2

Basic Operations

CPU 948 Programming Guide

3 - 22 C79000-G8576-C848-04

Examples of load and

transfer operat ions

Example 1:

Fig. 3-6 illustrates loading/transferring a byte, word or double word

from/to a memory area organized in bytes (PII, PIQ, flags, I/O).

:L IB i load byte i of the PII into ACCU-1-LL

:L IW j load bytes j and j+1 of the PII into ACCU-1-L

:L FD k load flag bytes k to k+3 in ACCU 1

ACCU 1

j+1

k+1

k+2

k+3

31 23 15 7 0

k+1 k+2 k+3

00jj+1

000i

Addresses

ascending

order

1) 1)

LIBi

TIBi

TIWj

LIWj

TFDk

LFDk

1) only with load operations

Fig. 3-6 Load and transfer operations in a byte-oriented memory area

Basic Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 23

Note

L oad ope rati o ns do not affect the condition c ode s.

Tra nsfe r operati on s cle a r the OS bit.

When a byte or word is loaded the extr a bits are cleared

in ACCU 1.

Example 2:

Fig. 3-7 illustrates the loading/transfer of a byte, word or double word

from/into a memory area organized in words.

:L DR i load the right byte of data word i into ACCU-1-LL

:L DL j load the left byte of data word j into ACCU-1-LL

:L DW k load data word k into ACCU-1-L

:L DD l load data words l and l+1 into ACCU 1

l+1

31 23 15 7 0

31 15 0

ACCU 1

15 0

l+1

000i

000

1) 1) 1)

left byte

Data word j

LDRi

TDRi

LDLj

TDLj

LDWk

TDWk

LDDl

TDDl

right byte

Data word i

Addresses

ascending

order

only with load operations

Fig. 3-7 Loa d and tran sf er oper ati ons in a word -ori ent e d memor y area

Basic Operations

CPU 948 Programming Guide

3 - 24 C79000-G8576-C848-04

Addressing I/Os

You ca n use load and t ra nsfe r ope ra tions to addre ss th e I/O pe rip he ra ls

as fol lows:

•• dire ctl y using the follo wing ope rati ons:

L. . /T . . . .PY, ..PW, ..OY, ..OW

•• using the proce ss im age with the following ope r ations:

L../T.. ..IB, ..IW, ..ID, .QB, ..QW, ..QD

and with logic and set/reset operations

Note

If you use the tr ansfe r ope ra tions T PY 0 to 127 and T PW 0 to

12 6, the proc e ss out put im ag e is upda te d at the sam e time .

Exc e pti on: co mma nd ou tpu t is di sa ble d by the STEP 5 ope ration

BAS (ref er to Sect ion 3.5. 4).

Not e the followi ng point s ab out I/O pe ri phe ra ls:

•• A pro cess in put /ou tpu t ima ge ex ist s for 128 input and 128 outp ut

b yte s of the P peri phe ra l s wi th b yte a ddre ss e s from 0 to 127.

•• No pr ocess i ma ge exist s for t he ent ir e are a o f the O periphe rals a nd

the P periph er al s wit h rela tive byt e addr esse s fro m 128 to 256.

( For more inform a ti on on a ddr ess spa c e al loca ti on se e

Se ction 8. 2.2) .

•• I/O mo dul es wi th addr esse s of t he O peri phe ra l s c an onl y be plu g-

g ed into ex pa nsio n units (no t in the cent ra l cont rol le r) .

•• In one expansion unit, you can use either only P peripherals or

only O peripherals.

Caution

If you use relative addresses of the O peripherals in an expansion

un it, you can no longer use t he se a ddr esse s for I /O modul e s in the

ce ntr al co ntr olle r (th is would re sul t in doubl e add re ssing ).

Basic Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 25

Timer and Counter

operations

To lo ad a tim er using a sta rt opera ti on or a count e r usin g a set

op erat io n, you m ust first load th e val ue in ACCU 1.

The fol lowi ng l oa d ope ra tions a re pre fe rabl e:

For timers: L KT, L IW, L QW, L FW, L DW, L SW.

For counters: L KC, L IW, L QW, L FW, L DW, L SW.

St ar ti ng a timer with th e se lec te d t ime r va lue re qui res an RLO si gna l

change.

A counter is set or started with the selected counter value when a

positive-going RLO signal edge is detec ted.

The followi ng tab le indicate s the signa l e dge ch ange wi th

corr esp ondi ng a rro ws.

Operation Operand RLO

1) Function

T 0 to 255

↑

↓

Start a timer as a pulse

Start a timer as extended pulse

Start a timer as ON delay

Sta rt a timer a s stor ed ON del ay

Sta rt a timer as OFF dela y

Res et a t ime r

C 0 to 255

↑

Se t a count e r (BCD numb er from 0 to 999)

Reset a counter

C ount up

Count down

1) positive-going edge ( ↑ ): signal change from ’0’ to ’1’

negative -goi ng edge ( ↓ ): signal change from ’1’ to ’ 0’

When exe cuting the timer or count er opera tions SP T, SE T, SD T, SS T,

SF T and S C the value in ACCU 1 is transferred to the timer or

coun te r (as wit h the tran sfe r ope ra tion) an d the approp ria te op erat io n

is started.

Tab le 3-6 Tim er and c ount e r opera t io ns

Basic Operations

CPU 948 Programming Guide

3 - 26 C79000-G8576-C848-04

Timer value

With the operation L KT, you can load a timer value directly into

ACCU 1 or indirectly from a flag or data word. The value must have

the following structure (with L KT, you specify the time base after the

period in the operand as shown below):

Example

Note

The start of each timer is liable to an inaccuracy of 1 time base!

Whe n using ti mer s, you shoul d ther ef ore sele ct the smalle st

possible time base (tim e ba se < timer value):

Example:

time value 4s not: 1 s x 4 inaccuracy: 1 s

but : 0.01 s x 40 0 inaccu ra cy : 0. 01 s

You want to set a time of 127 sec.:

Bi t as signment:

Timer value 127

0000000

xx111

Irrelevant

Time base 1 sec

Bit no.

Timer value 0 ... 999 in BCD

012

15 14 13

10 10

These bits are irrelevant

(i.e. they are ignored when

the timer is started)

Time base specified in BCD: 0: 0.01 sec

1: 0.1 sec

2: 1 sec

3: 10 sec

Basic Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 27

Counter value

With the operation L KC, you can load a count er va lue d irectly in

ACCU 1 or indirectly from a flag or a da ta w ord. The value m ust ha ve the

following struc ture:

Example

In the timer or counter itself, the value is in binary code. If you want to

sc an the tim er or co unt er , you can loa d the actua l tim e r or count e r

value int o A C C U 1 directly or in BCD code.

Counter value 127

000000

xxxx11

Irrelevant

Bit no.

Counter value 0 ... 999

specified in BCD

012

15 14 13

These bits are irrelevant,

(i.e. they are ignored when

the counter is set

)

You want to specify a counter value of 127:

Bi t as signment:

Basic Operations

CPU 948 Programming Guide

3 - 28 C79000-G8576-C848-04

Further exam ples of timer

and counter values

Loading timer values directly:

"L T 10": Loads the binary timer value of timer T 10

directly into ACCU 1

The time base is not loaded.

Loading counter values di rect ly:

"L C 10": Loads the binary counter value of counter C 10

directly into ACCU 1

Counter value

Counter C 10

ACCU 1

90’0’

Timer value

Timer T 10

ACCU 1

’0’

Basic Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 29

If you load values in BCD, status bits 14 and 15 of the timer or 12 to

15 of the count e r are not load ed. The y have the value 0 in ACCU 1.

The va lue in the ACCU can now be proc e ssed furthe r.

Timer value

Timer T 10

ACCU 1

901213

1213 0

347811’0’

Time base Timer value

Time base

Binary BCD

Counter value

Counter C 10

ACCU 1

Counter value in BCD

Binary BCD

478

’0’

Loading ti mer valu es in BCD code:

"LC T 10": Loads the timer value and time base of

timer T 10 into ACCU 1 in BCD

The time base is also loaded.

Loading counter values in BCD code:

"LC C 10": Loads the counter value of counter C 10

into ACCU 1 in BCD

Basic Operations

CPU 948 Programming Guide

3 - 30 C79000-G8576-C848-04

Arithmetic operations

Operation Operand Function

-F

-G

– Add two fi xe d poi nt num be rs (16 bi ts)

Subtract one fixed point number from another (16 bits)

Mult ipl y tw o fixe d p o int num bers (16 bit s )

Divide one fixed point number by another (16 bits):

quotie nt in ACCU-1-L, rem aind er in ACCU-1-H

Ad d two fl oa ti ng po int num be rs (32 bit s)

Subtract one floating point number from another (32 bits)

Mu lt ipl y two floa t ing p oin t numbe rs (32 bits)

Divide one floating point number by another (32 bits)

Arithmetic operations logically combine the contents of ACCU 1 and

ACCU 2 (e.g. ACCU 2 - ACCU 1). The re sult i s then contained in

ACCU 1. An arithmetic opera tion changes the ari thmetic re giste rs as

follows (in fi xed point opera tions onl y the low word):

Note

Within the supplem ent ar y operatio n s, there are operations for

subtraction and addition of double wor d fixed point numbe r s.

Ta b le 3-7 Arithm etic operatio ns

ACCU 1 ACCU 2 ACCU 3 ACCU 4

before : <ACCU 1> <ACCU 2> <AC CU 3> <AC C U 4>

after: <resul t> <ACCU 3> <ACCU 4> <ACC U 4>

Basic Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 31

Comparison operations

Operation Operand Function

! =

>< F

> = G

– Com pare f or e qua l to

Compare for not equal to

Compare for greater than

Compare for greater than or equal to

Compare for less than

Compare for less than or equal to

...F: compare two fixed point numbers (16 bits)

...D: compare two fixed point numbers (32 bits)

.. .G: com pa re two fl oati ng poi nt num be rs (32 bi ts)

Block operations

Operation Operand Function

J U

J C

OB 1 to 39 1)

OB 121 to 255

PB 0 to 255

FB 0 to 255

SB 0 to 255

Jump unconditionally

Ju mp con dit io na ll y (onl y whe n RL O = 1)

to an organization block

to a system pr ogra m spe cia l functio n

to a progra m blo ck

to an FB function block

to a se que nc e blo ck

D O U

D O C

FX 0 to 255

Jump unconditionally

Ju mp con dit io na ll y (onl y whe n RL O = 1)

to an FX function block

B E

B E C

B E U

– B loc k e n d

B lock e nd, condi ti ona l ( onl y whe n RLO = 1)

B lock end, unconditional

C X D B 2 to 255

DX 3 to 255 Cal l a DB da ta blo ck

Call a DX data block

GX DB 2 to 255

DX 3 to 255 G e ne rate da t a bl oc k D B

Ge nerat e da t a bl oc k D X

(ACCU 1 must contain the number of data words

– maximum 4091 – tha t the new bloc k is to have )

1) only for test purposes!

Table 3-8 Compariso n operati ons

Ta ble 3 -9 Bl ock oper ation s

Basic Operations

CPU 948 Programming Guide

3 - 32 C79000-G8576-C848-04

G DB/GX DX

Gene rating a data block

The ope ra ti on G DBx ge ne ra tes a DB da ta blo ck with the num be r x

(2 ≤ x ≤ 2 55) i n the use r mem or y of the CPU. The con te nt of the da ta

bl oc k is not assigne d the value 0, i.e. the data word s ca n have any

contents.

Befo re progr amm ing this sta te m ent, you must store the n umbe r of data

words tha t the new DB is to have in ACCU-1-L. The opera tion

"G DB" or "GX DX" creates the block heade r. A data bloc k genera ted

in this way (without blo ck hea de r) ca n occ upy a maxi m um of 4091

wor ds. You can ge ne ra t e longe r dat a bloc ks usi ng OB 125 ( refe r to

Se c ti on 6. 5).

If the data block already exists, the length of the DB is not permitted

or the re is not enough spac e in t he DB -RAM, the system program

calls OB 34. If thi s i s not loa ded, the CPU goe s to the stop mod e.

The GX DXx op eration generates a DX data block i n the D B-RAM

and is otherwise the same as G DBx.

NOP/display/stop operations

Operation Operand Function

N O P 0

N O P 1 – N o operat ion

No operation

B L D 0 to 255

130

131/131/133

255

Di spl ay gen er atio n ope ra tion fo r the PG:

the CPU handles the ope ra tion like a no ope rati on

Create blank line with carriage return

Swi tc h over between ST L, C SF, LA D

S T P – At end of cyc le or at end of OB 1, CPU change s to soft STOP.

Note

Since the operation STP is only effective at the end of the cycle,

the re is no ISTACK e ntr y. The cau se of the stoppa ge is then

di ffi c ult to fi nd a ft erwar ds.

To mak e dia gnosi s easi er , you should se t an identif ier befor e

ca lling the STP op er atio n, e. g. a spec ial bit pattern in a diagnostic

DB or use t he STE P 5 ope ra ti on ST S (re fer to Sec tion 3. 5. 4 ) .

Table 3-10 NOP/display/stop operations

Basic Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 33

3.5.2

Programmi n g Examples in

the STL, LAD and CSF

Methods of Representation

Logic operat ions

I 1.7

I 1.3

I 1.1

Q 3.5

Logical/circuit diagram STEP 5 representation

Ladder Control system

AI 1.1

I 1.3

I 1.7

= Q3.5

I 1.1 I 1.3 I 1.7 Q 3.5

I 1.1 1.3 1.7

Q 3.5

Output Q 3.5 is "1" when all inputs are "1" simultaneously

I 1.1

I 1.3

I 1.7 Q 3.5

Statement

list

AND operation

diagram flowchart

Output Q 3.5 is "0" if any of the inputs has signal state "0"

The number of scans and the sequence of the logic

statements are optional

Programming Exam ples in the STL, LAD and CSF Methods of Representation

CPU 948 Programming Guide

3 - 34 C79000-G8576-C848-04

Logic operations

(continued)

OI 1.2

I 1.7

I 1.5

= Q3.2

I 1.2

I 1.7

I 1.5

Q 3.2

state "0" simultaneously

Output Q 3.2 is "1" when at least one of the inputs is "1"

I 1.5I 1.7I 1.2

Q 3.2

I 1.2 1.7 1.5

Q 3.2

I 1.2

I 1.7

I 1.5 Q 3.2

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

OR operation

diagram flowchart

Output Q 3.2 is "0" when all inputs have the signal state

The number of scans and sequence of programming is optional

I 1.5 I 1.6

I 1.4

Q 3.1

Q 3.1 is "1" when at least one AND condition is satisfied

I 1.1

I 1.7

Q 3.1

I 1.6

I 1.5

Q 3.1

I 1.3

I 1.4

I 1.5 I 1.6

Q 3.1

I 1.4 I 1.3

AI 1.5

I 1.6

I 1.3

= Q3.1

A I 1.4

I 1.3 I 1.1

I 1.7 &

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

AND-before-OR operation

diagram flowchart

Q 3.1 is "0" when no AND condition is satisfied

Program ming Exam ples in the STL, LAD and CSF Met hods of Representat ion

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 35

Logic operations

(continued)

I 6.0

I 6.3

I 6.2

Q 2.1

Output Q 2.1 is "1" when input I 6.0 or input I 6.1 and one

of the inputs I 6.2 or I 6.3 has signal state "1"

Output Q 2.1 is "0" when input I 6.0 has signal state "0"

and the AND condition is not satisfied

I 6.1

I 6.0 I 6.1 I 6.2 I 6.3

Q 2.1

I 6.0 I 6.2 I 6.3

I 6.1

Q 2.1

AI 6.0

O I 6.2

= Q2.1

AI 6.1

O I 6.3

)

I 6.0

I 6.1

I 6.2

I 6.3

Q 2.1

A (

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

OR-before-AND operation /1st example

diagram flowchart

OR-before-AND operation

I 1.4 I 2..0

I 1.5

Q 3.0

Output Q 3.0 is "1" when both OR conditions are satisifed

I 1.4

I 1.5

Q 3.0

I 2.1 I 2.0

I 2.1

I 1.4 I 1.5

Q 3.0

I 2.0 I 2.1

I 2..0

I 1.4

Q3.0

I 2.1

I 1.5

OI 1.4

I 1.5

I 2.1

= Q3.0

)

O I 2.0

)

1 1

A (

Logical/circuit diagram STEP 5 representation

Ladder diagram Control system

Statement

list

/2nd example

flowchart

Output Q 3.0 is "0" when at least one OR condition is not satisfied

Programming Exam ples in the STL, LAD and CSF Methods of Representation

CPU 948 Programming Guide

3 - 36 C79000-G8576-C848-04

Logic operations

(continued)

Set/reset op erations

I 1.5 Q 3.0

I 1.5 I 1.6

Q 3.0

&I 1.6

I 1.5

Q 3.0

AI 1.5

AN I 1.6

= Q3.0

I 1.6 I 1.5

I 1.6 Q 3.0

Output Q 3.0 is "1" only when input I 1.5 has signal state "1"

state "0" (normally closed contact activated)

(normally open contact activated) and input I 1.6 has signal

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

Scan for signal state "0"

diagram flowchart

I 1.4 I 2.7 I 2.7

Q 3.5

I 1.4

Q 3.5

I 2.7 Q3.5

I 1.4

A I 2.7

I 1.4

Q 3.5

AI 2.7

I 1.4

Q3.5

Q RS

Signal state "1" at input I 2.7 sets the flip-flop

(signal state "1" at output Q 3.5).

If the signal state at input I 2.7 changes to "0", the

state of output Q 3.5 is retained (i.e. the signal is latched).

If the signal state at input I 1.4 changes to "0", the

state of Q 3.5 is retained.

Signal state "1" at input I 1.4 resets the flip-flop

(signal state "0" at output Q 3.5).

When the set signal (input I 2.7) and the reset signal

(input I 1.4) are applied at the same time, the scan

operation programmed last (in this case AI 1.4)

remains in effect for the rest of the program (reset priority).

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

RS flip-flop for a latching signal output

diagram flowchart

Program ming Exam ples in the STL, LAD and CSF Met hods of Representat ion

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 37

Set/reset operations

(continued)

I 1.3 I 2.6

I 2.6

F1.7

I 1.3

F 1.7

I 2.6 F 1.7

I 1.3

A I 2.6

I 1.3

F 1.7

AI 2.6

I 1.3

F 1.7

Signal state "1" at input I 2.6 sets the flip-flop.

If the signal state at input I 1.3 changes to "0", the

signal state of the flag is retained.

When the set signal (input I 2.6) and the reset signal

(input I 1.3) are applied at the same time, the scan

operation last programmed (in this case AI 1.3) remains

in effect for the rest of the program (reset priority).

Signal state "1" at input I 1.3 resets the flip-flop.

If the signal state at input I 2.6 changes to "0", the

signal state of the flag is retained, i.e. the signal is latched.

R Q

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

RS flip-flop with flags

flowchartdiagram

Programming Exam ples in the STL, LAD and CSF Methods of Representation

CPU 948 Programming Guide

3 - 38 C79000-G8576-C848-04

Set/reset operations

(continued)

On each leading edge of the signal at input I 1.7,

the AND condition (AI 1.7 and AN F 4.0) is satisfied;

the RLO is "1". This sets flags F 4.0 (edge flag) and

F 2.0 (pulse flag).

Flag F 2.0 is reset.

In the next processing cycle, the AND condition

AI 1.7 and AN F 4.0 is not satisfied, since flag F 4.0

has already been set.

Flag F 2.0 therefore only remains "1" for one program

run.

I 1.7

F 4.0

F 2.0

I 1.7

F2.0

F4.0

I 1.7

F2.0

I 1.7

F 4.0

F 2.0

F 4.0

I 1.7

F 4.0

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

Simulation of a momentary contact relay (one shot)

diagram flowchart

I 1.7

F 2.0

I 1.7

F 4.0

F 2.0

F 4.0

F 2.0

I 1.7 F 4.0

F 4.0

F 2.0

I 1.7

I 1.0

A I 1.0

Q3.0

I 1.0

M1.0

M1.1

F 2.0

Q 3.0

AN F 1.0

= F 1.1

F 1.1AF 1.0SI 1.0AN F 1.0R

A F 1.1

A Q3.0

= F 2.0

A F 1.1

AN Q3.0

Q 3.0S

AN F 2.0

A F 2.0

R Q 3.0

The binary scaler (output Q 3.2) changes its state

to 1 (leading edge). Therefore, only half the input

frequency appears at the output of the memory cell.

each time input I 1.0 changes its signal state from 0

F1.1 Q3.0 F 2.0

F1.1

I1.0

F1.0

I1.0 F1.0 F1.1

F1.1 Q3.0 F2.0 Q3.0

F2.0

I1.0

F1.0

&F1.1

F1.1

I1.0 S

F1.0

F1.1

Q3.0

F2.0

Q3.0

F1.1

Q3.0

&F2.0

Q 3.0

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

Binary scaler (binary divider)

diagram flowchart

Program ming Exam ples in the STL, LAD and CSF Met hods of Representat ion

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 39

Timer operation s

Subsequent scans with an RLO of "1" do not affect the

If the RLO is "0", the timer is reset (cleared).

timer.

KT 10.2:

the time base:

0 = 0.1sec 2 = 1sec

The timer is loaded with the specified value (10).

The number to the right of the decimal point indicates

BI and DE are digital outputs of the timer. The time at

output BI is in binary code. The time at DE is in BCD code

with time base.

I 3.0

Q4.0 T

as the timer is running.

Q4.0

The timer is started during the first scan if the RLO is "1".

I 3.0

T 1

10s

I 3.0

T 1

Q4.0

I 3.0

10.2

Q4.0

QW0

DE QW2

I 3.0

10.2

TV BI

Q4.0

QW0

DE QW2

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

Pulse timer

SP T 1

L KT 10.2

A I 3.0

AN I 3.0

RT1

LT1

TQW0

LC T 1

TQW2

AT1

= Q 4.0

diagram flowchart

The scan AT or OT produces the signal "1" as long

3 = 10 sec1 = 0.1 sec

KT KT

I 3.0

Programming Exam ples in the STL, LAD and CSF Methods of Representation

CPU 948 Programming Guide

3 - 40 C79000-G8576-C848-04

Timer operations (continued)

The timer is started during the first scan if the RLO is

"1".

A I 3.1

L IW 15

SE T 2

T 2AQ 4.1=

I 3.1

IW15

TW BI

Q4.1

I 3.1

IW15

TW BI

Q4.1

I 3.1

T 2

I 3.1

T 2

(IB 15) (IB 16)

An RLO of "0" does not affect the timer.

The scan AT or OT produces a signal "1" as long as

the timer is running.

IW 15:

Set the timer with the value of the operand I, Q, F or

D in BCD code (in this example, input word 15). I 3.1

Q4.1 TT

Timer value

Time

base

5 43 07 43 0

10101

102

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

Extended pulse timer

diagram flowchart

Program ming Exam ples in the STL, LAD and CSF Met hods of Representat ion

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 41

Timer operations (continued)

The timer is started during the first scan if the RLO

is "1". An RLO of "1" during subsequent scans does

KT9.2

TW BI

Q4.2

I 3.5

KT9.2

Q4.2

Q4.2 R

I 3.5

T 3

I 3.5

T 3

9s 0

Q4.2

TO TO

When the RLO is "0", the timer is reset (cleared).

not affect the timer.

KT 9.2:

The timer is loaded with the specified value (9). The

number to the right of the decimal point indicates

0 = 0.1sec 2 = 10 sec

I 3.5

Q4.2 T

The scan AT or OT produces the signal "1" when the

timer has elapsed and the RLO is still applied to the

input.

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

ON-delay timer

3.5

9.2

3.5

4.2

I 3.5

I 3.5 =

diagram flowchart

the time base:

3 = 10 sec1 = 0.1 sec

Programming Exam ples in the STL, LAD and CSF Methods of Representation

CPU 948 Programming Guide

3 - 42 C79000-G8576-C848-04

Timer operations (continued)

TV BI

I 3.3

Q 4.3

I 3.2 I 3.3

Q 4.3 T4

Q 4.3

20s 0

I 3.3

I 3.2 I 3.2

I 3.3

I 3.2

T4 T4

I 3.3

Q 4.3

timer has elapsed. The signal state does not change

to "0" until the R T operation resets the timer.

The timer is started during the first scan if the RLO is "1".

An RLO of "0" does not affect the timer.

= Q 4.3

AI 3.3

L KT 20.2

SS T4

A I 3.2

RT4

AT4

The scan AT or OT produces the signal "1" when the

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

Stored ON-delay timer

20.2 TV

Q 4.3

20.2

diagram flowchart

I 3.4

Q 4.4

I 3.4

Q 4.4 T5

Q 4.4

01 I 3.4

I 3.4

T5 T5

3.4

L KT 10.1

SF T5

AT5

4.3

I 3.4

Q 4.4

TTT

The scan AT or OT produces signal state "1" if

the timer is running

When the RLO is "1", the timer is reset (cleared).

When the RLO at the start input changes from "1" to

"0", the timer is started. It runs for the length of time

programmed.

Logical/circuit diagram STEP 5 representation

Ladder Control systemStatement

list

OFF-delay timer

10.1 TV 10.1

Q 4.4

diagram flowchart

or the RLO at the input is "1".

Program ming Exam ples in the STL, LAD and CSF Met hods of Representat ion

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 43

Counter operati o ns

When the result of logic operation changes at the start input

(I 4.1) from "0" to "1", the counter is loaded with the specified

is incorporated in the counter word.

BI and DE are digital outputs of the counter cell. The

value at BI is in binary code and the value at DE is in

BCD.

I 4.1

binary

16 bits

KC 150

I 4.1

value (150).

Logical/circuit operation STEP 5 representation

Ladder Control system

Statement

list

Set counter

I 4.1

I 4.0

4.0

4.1

150

diagram flowchart

The flag necessary for edge evaluation of the set input

KC 150

I 4.2

RSCI

binary

16 bits

An RLO of "1" (I 4.2) resets the counter to zero.

Q 2.4

CQ I 4.2

CV Q 2.4

=0 /

An RLO of "0" does not affect the counter.

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

Reset counter

4.0

4.2

2.4

I 4.2

I 4.0

diagram flowchart

Programming Exam ples in the STL, LAD and CSF Methods of Representation

CPU 948 Programming Guide

3 - 44 C79000-G8576-C848-04

Counter operations

(continued)

I 4.1

binary

16 bits

Owing to the two separate edge flags for CU and CD,

a counter with two different inputs can be used as an

up/down counter.

The value of the addressed counter is incremented

by "1" to a maximum value of 999. The function CU

is only executed on a positive edge (from "0" to "1")

of the logic operation programmed before CU. The

flags necessary for edge evaluation of the counter

inputs are incorporated in the counter word.

I 4.1

AI 4.1

CU C 1 CD

I 4.1

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

Count up

diagram flowchart

Program ming Exam ples in the STL, LAD and CSF Met hods of Representat ion

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 45

Counter operations

(continued)

I 4.0

RSCI

binary

16 bits

Owing to the two separate edge flags for CU and CD,

a counter with two different inputs can be used as an

up/down counter.

The value of the addressed counter is decremented

by 1 to a maximum counter value of 0. The function

is only executed on a positive edge (from "0" to "1")

of the logic operation programmed before the CD.

The flags necessary for edge evaluation of the

counter inputs are incorporated in the counter word.

I 4.0

AI 4.0

CD C 1 CU

I 4.0

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

Count down

diagram flowchart

Programming Exam ples in the STL, LAD and CSF Methods of Representation

CPU 948 Programming Guide

3 - 46 C79000-G8576-C848-04

Comparison operations

! = F

QQ 3.0

LI B19

L IB20

! = F

= Q 3.0

IB19

IB20 Q 3.0

IB19

IB20

! = F

not equal to ACCU-2-L.

in the list of operations.

ACCU-2-H and ACCU-1-H are not involved in the operation

for a 16-bit fixed point comparison.

In a 32-bit fixed point comparison (! = D) and floating point

comparison (! = G) the entire contents of ACCU 1 and

ACCU 2 (32 bits) are compared with each other.

During the comparison, the numerical representation of the

operands is taken into account, i.e. the contents of ACCU-1-L

The first operand is compared with the second operand

by the comparison operation. The RLO of the comparison

is binary.

Q 3.0

V1 V2

IB19 IB20

The condition codes CC1 and CC0 are set as described

RLO = "0": comparison is not satisfied, when ACCU-1-L is

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

Compare for equal to

RLO = "1": comparison is satisfied if ACCU-1-L = ACCU-2-L

diagram flowchart

and ACCU-2-L are interpreted here as a fixed point number.

Program ming Exam ples in the STL, LAD and CSF Met hods of Representat ion

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 47

Comparison operations

(continued)

Q 3.1

LI B21

L DW3

> < F

= Q 3.1

IB21

DW3

> < F

Q Q 3.1

IB21

DW3

> < F

RLO = "0": comparison is not satisfied if ACCU-1-L

equals ACCU-2-L.

The condition codes CC1 and CC0 are set as described

at the beginning of Section 3.5.

ACCU-2-H and ACCU-1-H are not involved in the operation

for a 16-bit fixed point comparison.

This information also applies to comparison operations for

"greater than", "greater than or equal to", "less than" and

"less than or equal to" (see the operations list). During the

The first operand is compared with the second operand

by the comparison operation.

The RLO of the comparison is binary.

Q 3.1

V1 V2

IB21 DW3

ACCU-2-H and ACCU-1-H are involved in a 32-bit fixed

point comparison and floating point comparison.

RLO = "1": comparison is satisfied if ACCU-1-L is not

equal to ACCU-2-L.

Logical/circuit diagram STEP 5 representation

Ladder Control system

Statement

list

Compare for not equal to

diagram flowchart

comparison, the numerical representation of the operands

is taken into account, i.e. the contents of ACCU-1-L and

ACCU-2-L are interpreted here as a fixed point number.

Programming Exam ples in the STL, LAD and CSF Methods of Representation

CPU 948 Programming Guide

3 - 48 C79000-G8576-C848-04

3.5.3

Suppl ementary Operations You can use the supple m enta ry oper atio ns set on the progra m mer only

in func t ion blocks ( FB a nd FX). Thi s mea ns tha t the tot al ope ra t ion s

se t for func tion bloc ks consi sts of the basic ope ra tions a nd t he

supplementary operations.

The system ope rati ons also belong to the supple me ntary func tions.

You can use the system opera tion s, for example to overwr ite the

me mo ry a t optio na l loca tions or to cha nge the cont e nts of t he worki ng

registers of the CPU. System operations can only be programmed if

the y have been ena bl ed in the prese t s menu of the progra mm er (no

longe r nec e ssar y from S5-DOS Ve rsi on 2.0 upward s).

If you in te nd t o use system ope ra ti ons, you sho uld be fam ilia r wi th

Chap ter 9 "Memory acce ss".

Caution

Only e xpe rien ce d syste m progra m mer s shoul d use the system

operations and then only with extreme caution.

You can only write operations in function blocks in STL. You cannot

program function bloc ks in graphic form (LAD a nd CS F m ethods of

representation).

This section describes the supplementary operations and covers possible

co mb in ations o f sub s titu tion o p eration s w ith actua l o p erand s .

System operat ions

Sy st em o p er a ti on s are marked in the first column of the

tables with S

Supplementary Operat ions

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 49

Binary l ogic op erations

Operation Operand Function

AN =

ON =

AND opera ti on, sca n a form a l oper and for si gna l stat e ’1’

AND opera ti on, sca n a form a l oper and for si gna l stat e ’0’

OR ope rati on, scan a for mal opera nd for signa l sta te ’1’

OR ope rati on, scan a for mal opera nd for signa l sta te ’0’

Insert formal operand

Inputs, outputs, data and flags addressed in binary (parameter

types: I, Q; data type BI) and timers and counters (parameter

type: T , C) are per mitte d as actual o p erands.

Digital log ic operati o ns

Operation Operand Function

XOW

AND operation on the contents of ACCU-1-L and ACCU-2-L

OR operation on the conten ts of ACCU-1-L and ACCU-2-L

Exklusive OR operation on the contents of ACCU-1-L and

ACCU-2-L

ACCUs 2, 3 and 4 are not affected, however, the condition codes

CC 1 a nd CC 0 are affe c ted (se e word cond ition cod es) .

Tab le 3-1 1 Binar y logi c oper at ions wit h forma l oper and s

Table 3-12 Digital logic operations

Supplementary O perations

CPU 948 Programming Guide

3 - 50 C79000-G8576-C848-04

Bit test operat ion s

Operation Operand Function

I 0. 0 to 127. 7

Q 0.0 t o 127. 7

F 0.0 to 255. 7

D 0.0 t o 255.15

T 0.0 t o 255. 15

Z 0.0 t o 255. 15

RI 0.0 to 255.15

RJ 0.0 to 255.15

RS 0.0 to 255.15

RT 0.0 to 255.15

Scan fo r sign al sta te "1"

of an input (PII)

of an output (PIQ)

of a flag

of a data word bit

o f a tim er word bi t

of a counte r word bit

of a bit in RI area

of a bit in RJ area

of a bit in RS area

of a bit in RT area

TBN

I 0. 0 to 127. 7

Q 0.0 t o 127. 7

F 0.0 to 255. 7

D 0.0 t o 255.15

T 0.0 t o 255. 15

C 0.0 t o 255.15

RI 0.0 to 255.15

RJ 0.0 to 255.15

RS 0.0 to 255.15

RT 0.0 to 255.15

Scan fo r sign al sta te "0"

of an input (PII)

of an output (PIQ)

of a flag

of a data word bit

o f a tim er word bi t

of a counte r word bit

of a bit in RI area

of a bit in RJ area

of a bit in RS area

of a bit in RT area

The bit test operat io ns sca n t he sta te of th e bit a nd i ndi ca t e it vi a the

RLO.

Table 3-13 Bit test operations

Supplementary Operat ions

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 51

Set/reset op erations

Operation Operand Function

RB =

RD=

Set a formal operand (binary)

Reset a formal operand (binary)

Reset a formal operand (digital)

for tim ers a nd c ount e rs

Assign the value of the RLO to a

formal operand

Inse rt forma l op eran d

Inp uts, outputs and F f lags a ddre s se d in b ina ry

(parameter type: I, Q; data type BI) are permitted

as actual oper ands.

Operation Operand Function

SU I 0. 0 to 127. 7

Q 0.0 to 127. 7

F 0.0 t o 255.7

D 0.0 to 255. 15

T 0.0 t o 255.15

C 0.0 t o 255.15

RI 0.0 to 255.15

RJ 0.0 to 255.15

RS 60.0 to 63.15

R T 0.0 t o 255.15

Unc onditional setting

of an inp ut ( PII)

of an output (PIQ)

of a flag

of a dat a word bi t

of a timer word bit

of a cou nter wor d bit

of a bit in RI area

of a bit in RJ area

of a bit in RS area

of a bit in RT area

RU I 0. 0 to 127. 7

Q 0.0 to 127. 7

F 0.0 t o 255.7

D 0.0 to 255. 15

T 0.0 t o 255.15

C 0.0 t o 255.15

R I 0. 0 to 255. 15

R J 0. 0 to 255. 15

RS 60.0 to 63.15

R T 0.0 t o 255.15

Unc onditional re setting

of an inp ut ( PII)

of an output (PIQ)

of a flag

of a dat a word bi t

of a timer word bit

of a cou nter wor d bit

of a bit in RI area

of a bit in RJ area

of a bit in RS area

of a bit in RT area

Table 3-14 Set/reset operations with formal operands

Table 3-15 Set and reset operations

Supplementary O perations

CPU 948 Programming Guide

3 - 52 C79000-G8576-C848-04

Timer and counter

operatio ns

Operation Operand Function

SP =

SD =

SEC =

SSU =

SFD =

FR =

Sta rt t im er s pe c ified by th e fo rm al ope ra nd a s a pu lse wit h the

value stored in ACCU-1-L (parameter type T).

Start timer specified by the formal operand as ON delay with the

value stored in ACCU-1-L (parameter type T).

Start timer specified by the formal operand as extended pulse

with the value s tore d i n A CCU-1-L or set counter spec ified

as formal operand with t he counter value store d in A CCU-1-L

(parameter type: T, C).

Start timer specified by the formal operand as stored

ON delay wit h the va lue store d in A CCU-1-L or

increment a counter specified as formal operand

(parameter type: T, C).

Start timer specified by the formal operand as stored

OFF de lay with th e valu e stor ed in ACCU -1-L or

decrement a counter specified as formal operand

(parameter type: D, C).

Enab le forma l oper an d (tim er /coun te r) fo r cold

restart (see FR T or FR R); (parameter type: T, C).

Insert form al operand

FR T 0 to 255

C 0 to 255

En a b le ti mer fo r cold re s t a r t:

Th e op er at io n is only ex ec ut e d on th e lea di ng e dge

of th e RLO (change from 0 to 1). Th e tim e r is

restarted if the RLO is 1 at the time of the start

ope ra ti on. (Se e tim i ng di ag ram bel ow the tabl e ).

Enable a counter for setting or reset ting:

The operation is executed only on th e lea di ng e dge

of th e RLO (change from 0 to 1). Th e co un te r is only

started if the RLO = 1 at the time of the start operation.

RLO

for SP T

RLO

for FR T

Scan

with A T

Tab le 3-1 6 Tim er and c oun ter oper at ions with fo rma l oper and s

Supplementary Operat ions

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 53

Examples

Fun c ti on bloc k c all Pr ogr am in the

function block Program executed

: JU F B 20 3

NAME :EXAMPLE1

ANNA : I 10.3

BERT : T 17

JOHN : Q 18.4

:A =ANNA

:L KT 010.2

:SSU =BERT

:U =BERT

:= =JOHN

:A I 10.3

:L KT 010.2

:SS T 17

:U T 17

:= Q 18.4

: JU F B 20 4

NAME :EXAMPLE2

MAXI : I 10.5

IRMA : I 10.6

E VA : I 10.7

DORA : C 15

EMMA : F 58.3

:A =MAXI

:SSU =DORA

:A =IRMA

:SFD =DORA

:A =EVA

:L KC 100

:SEC =DORA

:AN =DORA

:= =EMMA

:A I 10.5

:CU C 15

:A I 10.6

:CD C 15

:A I 10.7

:L KC 100

:S C 15

:AN C 15

:= F 58.3

: JU F B 20 5

NAME :EXAMPLE3

BILL : I 10.4

JACK : T 18

EG ON : IW 20

YOGI : F 100.7

:A =BILL

:L =EGON

:SEC =JACK

:A =JACK

:= =YOGI

:A I 10.4

:L IW 20

:SE T 18

:A T 18

:= F 100.7

Supplementary O perations

CPU 948 Programming Guide

3 - 54 C79000-G8576-C848-04

Load and transfer

operations

Operation Operand Function

LCD =

LW =

LWD =

Load a formal operand:

The value of the operand specified as a formal

opera nd is loa ded into the ACCU (pa ram e ter

ty pe: I, T, C, Q; da ta type: BY, W, D ).

Loa d a form al opera nd i n BCD c ode :

The value of th e tim er or c ount e r spe cifi ed as a form a l opera nd is

load ed int o the ACCU i n BCD code (pa ram et er typ e: T, C).

Loa d the bi t patt e rn of a forma l op er an d:

The bit pattern of a formal operand is loaded into the ACCU

(pa ram e ter ty pe : D; dat a type : KF, KH, KM, KY, KS, KT, KC).

Loa d the bi t patt e rn of a forma l op er an d:

The bit pattern of a formal operand is loaded into the ACCU

(param e ter type : D; data type : KG).

Tra nsfe r to a formal ope rand:

The contents of the accumulator are transferred to

the operand specified as a formal operand (parameter

ty pe: I, Q; data type: BY, W, D) .

Inse rt forma l op eran d

Actual operands permitted include those of the corresponding basic

operations ex cept fo r S flag s. For the "LW =" oper atio n, permissib le

data types include a bina ry pattern (KM) or a hexade cimal pattern

(KH), two ab solute numbers of 1 byte each (KY), a cha rac ter (KS), a

fixe d point numbe r (KF), a tim er va lue (KT) a nd a cou nte r val ue

(KC). For "LWD= " perm issi ble data is a flo atin g point nu mber .

Table 3-17 Load and transfer operations with formal operands

Supplementary Operat ions

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 55

Operation Operand Function

L RI 0 to 255

RJ 0 to 255

Loa d a wor d from the inte rf ac e data area

into ACCU 1 (RI area)

Load a w ord from the ext ende d interfa ce a rea

into A CCU 1 (RJ ar ea)

L RS 0 to 255

RT 0 to 255

Loa d a word from the system dat a area

in to AC C U 1 ( RS area)

Load a w ord from the ext ende d sys tem da ta

are a into A CCU 1 (RT ar ea)

T RI 0 to 255

RJ 0 to 255

Tra nsfe r th e cont ents of ACCU 1 to a

word in th e inte rface da ta ar ea (RI area)

Tra n s f er the con tents of A C C U 1 to a w or d

in the ex tend ed int erfa ce da ta area ( RJ ar ea)

T RS 60 to 63

RT 0 to 255

Tra nsfe r th e cont ents of ACCU 1 to a

word in the system data are a (RS area)

Tra nsfe r the contents of ACCU 1 to a word

in the extende d syste m dat a area (RT are a)

In contrast to the RI, RJ and RT areas, you can only use words RS 60 to

RS 63 of the RS area. Refer to Section 8.3.4 "RS/RT Area".

You can use the RT area in its complete length (RT 0 to RT 255)

pr ovi din g you do not use any sta ndar d funct ion bloc ks.

Table 3-18 Load and transfer operations with special operands

Supplementary O perations

CPU 948 Programming Guide

3 - 56 C79000-G8576-C848-04

Arithmetic operations

Operation Operand Function

ENT – This causes a stack lift into ACCUs 3 and 4:

AC CUs 1 and 2 are not cha nged. The old conten ts

of ACCU 4 are lost .

Example

ACCU 1 ACCU 2 ACCU 3 ACCU 4

LKF+30 d30 ca

LKF+3 d3c30

Contents of the ACCUs

before the sequence of

arithmetic operations bcd

xF c12 c30

+F c42 c

LKF+4 c4303

ENT 3 30 30 c

c7cc

LKF+6 c

Tab le 3-1 9 Ari t hm e tic oper at i on E NT

T he fol lowing fra ction must be ca lculated: (30 + 3 * 4) / 6 = 7

Supplementary Operat ions

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 57

Operation Operand Function

SADD BN -128 to

+127 Add a byte c ons tant (fixed point) to ACCU -1-L (includes

sign change)/the condition code in CC 0, CC 1, OV and

OS are not affecte d! – ACCU-1-H a nd ACCUs 2 to 4

re m ai n unc ha nged.

SAD D KF -32 768 t o

+32 7 6 7 Add a fixed point constant (word) to ACCU-1-L/ the

condition codes in CC 0, CC 1, OV and OS are not

affected! – ACCU-1-H and A CCUs 2 to 4 remain unchanged.

SADD 1) D H 0000 0000

FFFF FFFF

Add a doub le word fixe d poi nt con sta nt to ACCU 1/th e

condi ti on c ode s in CC 0, CC 1, OV and OS a re not affected! –

ACCUs 2 to 4 remain uncha nged.

S+D 1) Add two double wo rd fixed point con stants

(ACCU 2 + ACCU 1)/the result can be evaluated

in CC 0/CC 1. 2)

S-D 1) S ubtrac t two do uble word fi xed poin t constant s

(ACCU 2 - ACCU 1)/the result ca n be evaluated in CC 0/ CC 1. 2)

STAK Swap the contents of ACCU 1 and ACCU 2

1) Programming is depe ndent on the PG type and the release of the PG system software.

2) For changes in ACCU 2 and ACCU 3: see Section 3.5.1 "Basic Operations/Arithmetic Operations".

Ta b le 3-2 0 Sup plementa r y arit hm etic op e rations

Supplementary O perations

CPU 948 Programming Guide

3 - 58 C79000-G8576-C848-04

3.5.4

Executive O perat ions The execut iv e operat ions al so incl ude syst em opera t ions.

Caution

Syste m oper atio ns shoul d only be used wit h great car e and then

only by exp erie nce d progra mme rs fa mil iar with the syste m.

Sy st em o p er a ti on s are indicated in the table by

Jump op erati o ns

When you use the supplementary jump operations, you indicate the

jum p de sti nati on for unc ondi tiona l jum ps sym bolica ll y. Th e symbo li c

para m e ter of t he jum p ope ra tion is ide nt ic al to the symbol ic addre ss of

the dest in atio n sta tem e nt. W hen prog ra mmi ng, reme m be r that the

absol ut e jum p dist anc e sho uld not exce ed ± 127 words and a STEP 5

st ate ment can consi st of mor e tha n one word. You ca n onl y exec ute

the se j um ps wit hin a bl oc k; j um ps ove r se gm en t bou nda ri es a re not

perm itt ed ("seg ment" = struc tura l elem ent in PBs, SBs, FBs, FXs and

OBs; see PG de scriptio n).

Note

The jump state ment and jump dest inat ion (sym bolic address) m ust

be in the sam e segme nt . A symbo lic addr ess c an onl y be used

once per segment .

Exception: this does not apply to the J U R j ump for w hic h you

spec ify an abs olute ju mp dis tance as the par ame te r.

Operation Operand Function

JU =

JC =

JZ =

addr

( addr =sym bo lic

addr ess wi th

maximum

4 characters)

Jum p uncon dit io nall y:

The j ump is e xe cute d re gardless of c ondi ti ons

Jum p condi ti ona lly:

th e con d it ion al jum p i s exe c uted only i f th e RL O is 1.

If the RLO is 0, the statement is not executed and the RLO

is se t to 1.

Jum p if resu lt is ’0’ :

the jump is executed only if CC 1 is 0 and CC 0 is 0.

The RLO is not changed.

Table 3-21 Ju mp ope ration s

Executive Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 59

Operation Operand Function

Table 3-21 continued:

JN =

JP =

JM=

JO =

JOS =

addr

(add r = symbo lic

addr ess wi th

maximum

4 characters)

Jump i f result is not 0 :

the jump is executed only if CC1

is not equal to CC0.

The RLO is not changed.

Jump if result > ’0 ’ :

the ju mp is o nly execu ted if C C 1 = 1

and CC 0 = O. The RLO is n ot chang ed.

Jump if res ult < ’0 ’:

the ju mp is o nly execu ted if CC 1 = 0 an d CC 0 = 1.

The RLO is not changed.

Jump on overflow:

the jump is executed when the O V conditio n code is 1. If

there is no o verfl ow (OV is 0), the jump is no t executed . The

RLO is not changed.

An o verfl ow occurs w hen an ar ithmetic o peratio n exceeds the

permissible range for a given numerical representation .

Jump when the OS (s tored overflow) con dition co de is set:

the jump is executed when the condition code OS is 1. If

there is no o verfl ow (OS is 0), the jump is no t executed . The

RLO is not changed.

An o verfl ow occurs w hen an ar ithmetic o peratio n exceeds the

permissible range for a given numerical representation .

SJUR -32 768 to

+3 2 767 Relativ e jump within the user memory or wi thin a f un ction

block (e.g. to arr ive in a d ifferen t segmen t). The o peratio n is

always ex ecuted r egardless of con ditio ns .

The operand is the number of words difference betw een the

addr ess o f the jump dest ination - the current des tinatio n. The

jump is executed eit her to a h igher (positi ve oper and) o r

low er (neg ative op erand) address than th e curren t operat ion.

Caution

I f you use JUR inco rre c tly, unde fi ne d sta tu ses ca n oc cu r in the

sy ste m . It should onl y be use d by extr em ely e xp er ienc e d

progr am me rs wit h detaile d knowl edge of the syst em.

Executive Oper ations

CPU 948 Programming Guide

3 - 60 C79000-G8576-C848-04

Shift operations

Ope r ati on O pe r and Function (o per at ion wi th ACCU 1 )

SLW

SRW

SLD

SSW

SSD

R LD

RRD

0 to 15

0 t o 15

0 t o 32

0 t o 15

0 t o 32

Shi ft a word to the left (va c ant posi tions

to the right are padded with zeros)

Shi ft a word to the right (vaca nt posi tion

to the left are pa dde d with ze ros)

Shift a double word t o the le ft (vacant positi ons

to the right are padded with zeros)

Shi ft a word with si gn to the rig ht (vac a nt posit io ns

to the left are padded with the sign - bit 15)

Shift a doub le word wi th sign to the rig ht (vac ant

positi ons t o the left are padd ed with the sign - bit 31)

Rotate to the left

Rotate to the right

Only ACCU 1 is involved in the execution of shift operations. The

parameter part of the s e opera tions spe cifies t he number of positions by

which the accumulator cont ents should be s hifted or rotated. For the

SLW, SRW and SSW operations, only the low word of ACCU 1 is

involved in the shift operations. For SLD, SSD, RLD and RRD

operations, the entire contents of ACCU 1 (32 bits) are involved.

Shift operations are executed regardless of conditions.

You c a n use jum p op eratio ns to sc a n the va lu e of t he la st bi ts sh i ft ed

ou t usi ng CC 1/ CC 0.

Shift: last

bit shifted CC 1 CC 0 Jump ope rati on

000JZ=

1 1 0 JN=

JP=

Ta ble 3 -22 Shift oper ation s

Executive Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 61

Examples

1. You want to shift the contents of data word DW 52 four bits to the left

and write them to data word DW 53.

STEP 5 program: Contents of the data words:

:L DW 52 KH = 14AF

:SLW 4

:T DW 53 KH = 4AF0

2. You w ant to read the input double word ID 0, and shif t th e conten ts o f

ACCU 1 so tha t th e bi t po sitions of t he input double word sho wn i n bo ld

face are reta ined and the remaini ng b it positions are set to defi ned

values (0H or 0FH ).

STEP 5 program: Contents of ACCU 1 (hexadecimal)

ACCU-1-H: ACCU-1-L:

:L ID 0 2348 ABCD

:SLW 4 2348 BCD0

:SRW 4 2348 0BCD

:SLD 4 3480 BCD0

:SSW 4 3480 FBCD

:SSD 4 0348 0FBC

:RLD 4 3480 FBC0

:RRD 4 0348 0FBC

3. Application: Multiplication by the 3rd power, e.g. new value = old

value x 8

:L FW 10

:SLW 3

:T FW 10 Caution: do not exceed the

positive area limit!

4. Application: Division by the 2nd power, e.g. new value = old value : 4

:C DB 5

:L DW 0

:SRW 2

:T DW 0

Executive Oper ations

CPU 948 Programming Guide

3 - 62 C79000-G8576-C848-04

Conversion operati o ns

Operation Function

CFW

CSW

CSD

DEF

DUF

DED

DUD

FDG

GFD

Fo rm the 1’s c omple me nt of ACCU-1- L (16 bits )

Fo rm the 2’s c omple me nt of ACCU-1- L (16 bits )

Fo rm the 2’s com ple m ent of ACCU 1 (32 bi ts)

C onve rt a fixe d poi nt num be r (16 bi ts) f rom BCD to binary

C onve rt a fixe d poi nt num be r (16 bi ts) from bin ar y to BCD

C onve rt a double wor d (32 bits) from BCD to binary

C onve rt a doubl e wor d (32 bi ts) f rom binar y to BC D

C onve rt a fixe d poi nt n um be r (32 bi ts) to a floa t ing poin t num be r (3 2 bit s)

C onve rt a floa ting point num be r to a fixe d poi nt nu mb er (32 bi ts)

DEF

The value in ACCU-1- L (bit s 0 to 15) is inte rpre t ed as a BCD num be r.

Aft er the conve rsion, ACCU- 1-L conta ins a 16 -bi t fixed poi nt

numb er .

DUF

The value i n A CCU -1-L (bits 0 to 15) is interpreted as a 16-bit fixed point

number. A fter the c onversion, ACCU -1-L cont ains a BCD numbe r.

15 14 0

14 . . . . . . . . . . . . . . . 2 0

DUF ↓DEF ↑

15 0

S S S S 10 2 10 110 0

S (si gn): 0 = posi tive

1 = negative

Table 3-2 3 Conv er sion operati ons

Executive Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 63

DED

Th e value in ACCU 1 (b its 0 to 31 ) is in terp r eted as a BCD nu mber . After

the conversion, ACCU 1 contains a 32-bit fixed point number.

DUD

T he va lue in AC CU 1 ( bi t s 0 to 31) is i nte rpreted as a 32-bit fixed

po int num ber. Afte r the con ve rsio n, ACCU 1 conta ins a BC D numbe r.

31 30 0

30 . . . . . . . . . 2 0

DUD ↓DED ↑

31 0

S S S S 10 610 5 10 410 3 10 2 10 110 0

S (sign): 0 = positive

1 = negative

FDG

T he va lue in AC CU 1 ( bi t s 0 to 31) is i nte rpreted as a 32-bit fixed

po int num be r. Afte r the con ve rsio n, ACCU 1 conta i ns a floa ting po int

number (exponent and mantissa).

GFD

The value i n A CCU 1 (bits 0 to 31) is interpreted a s a floa ting point

number. A fter the c onversion, ACCU 1 contains a 32-bit fixed point

number.

31 30 0

30 . . . . . . . . . 2 0

FDG ↓GFD ↑

31 30 ... ... 24 23 0

6 . . . . . . . . . . . . . . 2 0S2

-1 . . . . . . . . . . 2 -23

Exponent Mantissa

The conve rsion is made by multipl ying the (binary) ma ntissa by the value

of the (binary) exponent by shifting the mantissa value to more significant

bits past an im aginary de ci ma l point by the va lue of t he expone nt (ba se

2). Af ter th e m u ltiplicati o n , r emnan ts of th e original mantissa rema in to

the right of the imaginary decimal point. These bit places are cut off from

the w h o le re sult.

Executive Oper ations

CPU 948 Programming Guide

3 - 64 C79000-G8576-C848-04

Thi s con ve rsio n algor ithm produ ces th e followin g result cla sses:

•• Floating point numbers ≥ 0 or ≤ -1 result in the next lower

number.

•• Floating point numbers < 0 and > -1 result in the value ’0 ’.

Conversion examples

Examples of CFW, CSW

F lo at ing point number 32- bit fixed poin t number

GFD

+5 ,7 → 5

-2 ,3 → -3

-0,6 → 0

+0,9 → 0

1. You want the contents of data word DW 64

inverted bit for bit (reversed) and stored in

data word DW 78.

STEP 5 program: Assignment of the data words:

:L DW 64 KM = 0011111001011011

:CFW

:T DW 78 KM = 1100000110100100

2. The contents of data word DW 207 are

interpreted as a fixed point number and stored

in data word 51 with a reversed sign.

STEP 5 program: Assignment of the data words:

:L DW 207 KF = +51

:CSW

:T DW 51 KF = -51

Executive Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 65

Decrement/

increment

Operation Operand Function

1 to 255

De crem ent the low by te (bi ts 0 to 7) of ACCU- 1-L

by the value of the operand 1)

Increm ent the low byte (bits 0 to 7) of ACCU-1 -L

by the value of the operand 1)

1) The contents of the low byte of ACCU-1-L are decremented or incremented by the number specified as the

operand without a carry. The operation is executed regardless of conditions.

Example

Processing operations

Operation Operand Function

DO =

DW 0 to 255

FW 0 to 254

Proce ss da ta word:

the fo llowin g ope ra tion i s com bi ne d wit h

the parameter specified in the address data

word and executed.

Proce ss flag word:

the fo llowin g ope ra tion i s com bi ne d wit h

the param ete r spec ified in the add re ssed

F flag and executed.

Proc ess form a l oper an d (para m ete r typ e B):

Only C DB, JU PB, JU OB, JU FB, JU SB

can be substituted.

Inse rt forma l op eran d

STEP 5 program: Assignment of the data words:

:L DW 7 KH = 1010

:I 16

:T DW 8 KH = 1020

:D 33

:T DW 9 KH = 10FF

Table 3-24 Decrement/increment operation

Tab le 3-25 Pr oce ss ing ope ra tio ns

Executive Oper ations

CPU 948 Programming Guide

3 - 66 C79000-G8576-C848-04

Operation Operand Function

Table 3-25 continued:

SBI 1) Indire c t proc essi ng of a for mal opera nd:

execute an operation whose operation code is

stored in a formal operand. The number of the

formal opera nd m ust be stored in ACCU 1.

B RS 60 to 63 1) Execute an ope rati on whose ope ra t ion cod e

is st ored in the system data ar ea (RS = fre e

system data: RS 60 to 63). In 2-wor d opera tions

the 2nd word m ust be loa de d in RS n + 1.

1) The value in the formal operan d or system data is interpreted as the operation code of a STEP 5

operation and is then executed.

Note

Onl y the foll owin g opera ti ons ca n be combi ne d wit h DO DW, or

DO FW, DI or DO RS:

- A. . , AN.. , O.. , ON. . , S.. , R.. , =..

with areas I, Q, F, S,

- FR T, R T, SF T, SD T, SP T, SS T, SE T,

- F R C, R C, S C, CD C, CU C,

- L.., T.. with areas P, O, I, Q, F, S, D, RI, RJ, RS, RT,

- L T, L C,

- L C T, LC C,

- JU=, JC=, JZ=, JN=, JP=, JM= , JO= ,

- SLW, SRW,

- D, I, SED, SEE,

- C DB, JU.. , JC.., G DB, GX DX, CX DX, DOC FX, DOU FX.

Th e PG do es n o t c h eck th e l eg ality of the combin ation s !

Executive Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 67

Examples of DO operati ons

DO DW /DO FW

Operand substitution

Using the stateme nts "DO DW" and "DO FW" you can ac ces s dat a with a

substitut ion, e.g. in a program loop. The subst ituted acces s consists of the

statement DO DW/DO FW followed immediately by one of the STEP 5

operations listed above.

"Substituted" means that t he opera nd for the operation is not programmed

as a static val ue but i s fixed during the c ourse of the S TE P 5 program.

Select t he opera nd type from the rang e perm itted for the ope ratio n when

you write your program, e.g. PB for the ope ration "J U P B nn":

You mus t fi rst loa d t he opera nd value (nn in the ex amp le) in a data word

or F fla g word (parameter word) before the substituted access w ith

DO DW/DO FW.

1. Principle of substitution:

:L KF +120

:T FW 14 load FW with the value "KF +120"

: DO FW 14

:L IB 0

before the operation "L IB" is executed, the

operand value ’0’ is replaced by the value ’120’;

Operatio n exec uted : L IB 120

2. Data word as index register:

The contents of data words DW 20 to DW 100 are set to signal state ’0’. The

index register for the parameter of the data words is DW 1.

:L KF +20 supply the index register

:T DW 1

M001 : L KF +0 reset

:DO DW 1

:T DW 0

: L DW 1 increment the index register

:L KF +1

:+F

:T DW 1

:L KF +100

:<=F

:JC =M001 jump if the index is within the range

... remaining STEP 5 program

Continued on next page

Executive Oper ations

CPU 948 Programming Guide

3 - 68 C79000-G8576-C848-04

Ope ra nd substi tu tion with bina ry ope ra t ion s

For op erand substitutions with binary operations you can use the

fo llowin g ope ra nd t ype s: i nput s, outp uts, F flags, S fla gs, tim er s an d

counters.

In thi s su bstituti on, the structure of the F fla g word or da ta word

(p aram e ter wor d) de pends on the ope rati on yo u are usi ng.

Parame t er wo rd for i nput s and ou tpu ts

Bit no. 15 11 10 8 7 6 0

no si gni ficanc e Bi t ad dr e ss

from 0 to 7 0 Byte addre ss from 0 to 1 27

Examples of operand subs titu tion continu ed:

3. Jump distributor for subroutine techniques:

:D O F W 5

:JU =M001 Contents of flag word FW 5:

+ :JU =M002

Jump :JU =M003 jump distance

distance :JU =M00 4 (maximum ± 127)

:JU = M005

: .

M001 : .

: .

:BEU

M 002 : . Advantage:

: . all program sections are

: BE U contained in one bl ock.

M003 : .

: .

:BEU

4. Jump distributor for block calls:

:DO FW 10 Contents of flag word FW 10:

:JU PB 0 PB 0

PB 1 Block no. x

PB 2

PB 3

PB x

Executive Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 69

Parame t er word for F flag s

Bit no. 15 11 10 8 7 0

no si gni ficanc e Bi t ad dr e ss

from 0 to 7 Byte addre ss fro m 0 to 255

Parame t er wo rd for S flag s

Bit no. 15 14 12 11 0

0 Bi t addre ss

from 0 to 7 Byte address from 0 to 4095

Parame t er wo rd for t ime rs and c oun ter s

Bi t no. 1 5 8 7 0

no significance Number of timer or

counter cell from 0 to 255

Principle of the substitut io n

with a binary operation

15 8 7 011 10

0DW 27

DO DW

AI0.0

AI4

statement executed

Executive Oper ations

CPU 948 Programming Guide

3 - 70 C79000-G8576-C848-04

Example of DI operatio n

In function block FB 1, STEP 5 operations are executed whose operation

codes were transferred

by a calling block as formal operands FW 10, FW 12 and FW 14.

Which of the operation codes is executed is written by the calling block

as a consecutive number in flag word FW 16.

The result of the executed operation is then entered in ACCU 1 and is

transferred to flag word FW 18.

FB 1

NAME :TEST

DECL :FW10 I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KH

DECL :FW12 I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KH

DECL :FW14 I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KH

:L FW 16 cons. number of formal operand

: with required operation code

:DI transferred operation code is executed

:T FW 16 result from ACCU 1

:BE

FB 2

:L KF +1

: T FW 16 cons. no . of f orma l operand with o peration code

:JU =AUFR

AUFR :

:JU FB 1 call FB TEST

NAME :TEST

FW10 : KH 4A5A op. code "L IB 90", formal operand 1

FW12 : KH xxxx othe r operation code , formal oper and 2

FW14 : KH yyyy othe r operation code , formal oper and 3

:T FW 18 ACCU 1 → FW 18

:BE

FW 10 4A5AH

:L IB 90

0001H

List of actual operands in FB 2 Principle of sequence in FB 1

xxxxH

yyyyH

Operationexecutedwith"DI"

(cons. no. of actual operand)

FW 12

FW 14 FW 16

ACCU 1

:L FW 16

:DI

Executive Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 71

I/O operations

Operation Operand Function

IAE

RAE

BAS

BAF

Disa ble process in terru pt servi cing (via IB 0) (not for syst em

interrupts!)

Ena bl e p roc ess int er rupt ser vic ing (via IB 0) (no t for syste m

interrupts!)

Di sable addre s sing error

Enable addressing error

Di sa ble com ma nd output: PIQ is no longe r infl ue nc ed by the

operations

S Q, R Q, = Q, T PY and T PW.

Enable command output

"Enable/disable process interrupts" can, for example, be used when

process int errupt driven processing is to be suppres sed duri ng

time-controlled processing. In the program section between the IA and

RA state me nts, no proc ess interrupt drive n proc ess ing is pos sible.

Note the s pe cial function OB 122 "dis able i nterrupts", Sec tion 6.3.

Other o peratio ns

Operation Operand Function

SSTS

STW

SIM

LIM

Stop command leadin g di r ectly t o a so ft ST O P .

St o p c ommand lea d in g d irect ly t o a hard ST O P.

(sta te can only be exited with POWER DOWN/ UP).

Set int er rupt mask (UAMW ) (32 bits): before cal ling th e

operation, the bit pattern for the mask must be loaded in ACCU 1

( 32 bi ts )

R ead i nte rr upt m ask: bit p atte rn of the in te rru pt ma sk (32 bi ts) is

loaded in ACCU 1

Table 3-26 I/O operations

Table 3-27 Other operations

Executive Oper ations

CPU 948 Programming Guide

3 - 72 C79000-G8576-C848-04

SIM/LIM – set/read interrupt

condition code mask (UAMW )

The inte rrup t mask "ma sks" inte rru pts in the in terru pt cond ition cod e

wor d until the end of the cyc le, i.e. all interrup ts re m ain pendi ng, but

the progr am is not interru pted by the m .

Bit in the inte rru pt cond ition cod e mask = 0: inte rrup t disab led

Bit in the in terru pt cond ition cod e ma sk = 1: inte rrup t enable d

Mea ning of the bits in UAMW-H or ACCU-1-H:

15 8 7 0

INTX INTE INTF INTG WEFE WA PA BULE PEU HALT ES AV INTAS TAU DARY KZU

Mea nin g of the bits in UAMW-L or ACCU-1- L:

15 8 7 0

– KB KDB STS TL AF SUF STUEBSTUEU NAU ZA QVZ ADF PARE ZYK STOP HOLD

Abbrev. Meaning

High word

INTX

INTE

INTF

INTG

WEFE

BULE

PEU

HALT

INTAS

TAU

DARY

KZU

S5 bus/system inte rrup t A, B, C or D (slot -

dependent)

S5 bus/syste m inte rrup t E

S5 bus/syste m inte rrup t F

S5 bus/syste m inte rrup t G

Col lision of timed i nterr upt s

Timed in terrupt

Process interrupt

Bus lock err or

I/Os not rea dy

Stop instruction from coordinator COR

Sing le step m ode

Address c om pariso n act ive

Interrupt from SPU proce ssor

Clock failu re of SPU processo r

Cont inuous re a dy (a c cess t o fa ulty m emor y)

Bra cke t c ount er ove rfl o w

Ta ble 3-2 8 M eaning of th e abbre vi at i o ns in UAM W

Executive Operations

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 73

Abbrev. Meaning

Table 3-28 continued:

Low word

KDB

STS

TLAF

SUF

STUEB

STUEU

NAU

QVZ

ADF

PARE

ZYK

STOP

HOLD

No blo ck

No data block

Soft stop

Tran sfe r/loa d error

Substit ution erro r

BSTACK ove rflo w

ISTACK ove rfl ow

Power failure

Tim ed int er rupt (de la yed i nte rr upt , clo ck -c ont rol le d

interrupt

Timeout

Addressi ng error

Parit y error

Cyc le ti m e e rror

Mode sel e ctor switc hed to STO P

DMA request fro m SPU processor

Executive Oper ations

CPU 948 Programming Guide

3 - 74 C79000-G8576-C848-04

3.5.5

Semaphore Operati o ns If two or more CPUs in one progr am ma ble cont rol ler (see Chapte r 10)

requ ire a ccess to the same glob al mem ory are a (peri phe ra ls, CPs, IPs),

the re is a da ng er tha t one CPU wi ll overwri te the data of anot her CP U

or tha t one CPU coul d rea d inv alid int er medi a te da ta sta tuses of

anot he r CPU and m isi nte rp re t them . You m ust the re fore coord ina t e

CPU ac cesse s to the common me mory are as.

You can coordinate t he individual CPUs us ing the SED and SEE

operations.

You can, for example, progra m the following coordination between two

CPUs: a CP U invol ved in m ultiproce ssing ca n onl y access the c omm on

memory area a fter it has successfully se t a de cl are d sem aphore (SES). A

semaphore xx can only be set by a single CPU. If a CPU fails to set (i.e.

disable) the semaphore, it cannot access the memory area. In the same

way, a CPU c an no longer access the me mory once i t ha s released the

semaphore again (SEE ).

SED/ SEE disab le/ en abl e

semaphore

(non-system operations)

Operation Operand Function

SED

SEE

0 to 31

Disable (set) a semaphore

Enable (release ) a semap hore

evaluation of the result of the operation via

CC 0/CC 1

Note

The SED xx a nd SEE xx operation s m ust be programmed in al l

CPUs that req uir e syn ch roni z ed ac c ess t o a common gl obal

me mory are a.

Stan dard FBs, handling blocks a nd blocks for multipro ce ssor

comm unication ma nage the coordination inter nally. I f you use

the se bl oc ks, you do not nee d to progr am the oper at ions SEE xx

and S E D xx.

Table 3-29 Disable/enable semaphore

Semaphore Operat ions

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 75

Effect of SED/SEE

The CPU that e xec utes t he opera tion SE D xx (disab le sema pho re )

ac cesse s a spec if ic byt e in the coord inat or (provided that no other

CPU has a cce ss to tha t byte al read y). Once a CPU has rese rv ed ac c ess,

the other CPUs ca n no longe r access the mem ory area pro tec ted by the

se m aphore (number s 0 to 31). The ar ea is t here fore disab le d for a l l

other CPUs.

Ma ke sure that the co ordina ti on func ti ons corre ctly, al l CPUs

re qu iri ng a c ce ss to the sam e area of gl oba l me m ory m ust use t he sam e

semaphore.

The SEE xx (ena bl e sem a phor e) ope rati on rese ts th e byte on the

coor dinat or. The prot ec t ed me m ory a re a is the n on ce aga in ac ce ss i ble

to the othe r CPUs. A semap hore can only be enabl ed by the CPU that

di sabled i t.

Use of SED/SEE

Fi g. 3-8 il lustrates the basi c se qu en ce of coor dinate d acc e ss using a

se m aphore .

START

Operation

successful?

Disable semaphore

Access to sema-

phore protected

global memory

Enable semaphore:

Yes

End

SED

SEE

Fig. 3-8 Coordination of access to the global memory

Semaphore Operations

CPU 948 Programming Guide

3 - 76 C79000-G8576-C848-04

Before disabling or enabling a particular sema phore, the SED and SEE

operations s ca n the s ta tus of the sem aphore . The c onditi on c odes CC 0

and CC 1 are affected a s foll ows:

CC 1 CC 0 Evalua tio n Si gnif icanc e

0 0 JZ Se m aphore wa s d isabled by

anot her CPU and can not be

disabled/enabled.

1 0 JN, JP Semaphore wa s d isabled/

enabled.

Note

The scanning of a particular semaphore (= read procedure) and

the disa bling or enab li ng of the sem aphor e (=wri te proce du re ) are

one unit. No othe r CPU can acc ess t he sem aphor e du rin g these

procedures!

Whe n usi ng sema ph ore s, reme m be r the follo wing poin ts:

•• A se maphore is a glob al variable , i.e. the sema ph ore with num be r

16 exists only once in the enti re sy ste m , eve n if y our controlle r is

using three CPUs.

•• All CPUs that require coordinated access to a common memory area

must use the SED and SEE operations.

•• All partic ipatin g CPUs must execute the same star t-up type. D u-

ring a COLD RE START, all the sem a phore s are c le a re d. Du rin g a

manual or automatic warm restart, the semaphores are retained.

•• Star t-u p in multi proc e ssor op erat ion mu st be sync hro nize d. For

this reason, no t est opera tion is al lowed.

Semaphore Operat ions

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 77

Application example f or

semaphores

Tasks:

Four CPUs are plugged into an S5-155U. They output status messages to a

status signalling device via a common memory area of the O peripherals

(OW 6). A CPU must output each status message for 10 seconds. Only after a

10 second output can a new message be output from the same CPU or a

different CPU overwrite the first message. The use of peripheral word OW 6

(extended I/O area, no process image) is controlled by a semaphore. Only the

CPU that was able to reserve this area for itself by disabling the assigned

semaphore can write this message to OW 6. The semaphore remains disabled for

10 seconds at a time (TIMER T 10). The CPU re-enables the semaphore only

after this timer has elapsed. After the semaphore has been re-enabled, the

other CPUs can access the reserved area. The new message can then be written

to OW 6.

Implementation:

The following program can run in all four CPUs, each with a different

message. The blocks shown below are loaded.

5 flags are used as follows:

F 10.0 = 1: a message was requested or is being processed

F 10.1 = 1: the semaphore was disabled successfully

F 10.2 = 1: the timer was started

F 10.3 = 1: the message was transmitted

F 10.4 = 1: the semaphore was re-enabled

Continued on next page

FB 1:

MAIN PROGRAM FB 10:

REPORT

FB 100:

DISABLE SEMAPHORE

FB 110:

OUTPUT REPORT

FB 101:

ENABL E SEMAPHORE

Semaphore Operations

CPU 948 Programming Guide

3 - 78 C79000-G8576-C848-04

Semaphore application example continued:

FB 1

:A F 10.0

:JC =M001 If no message is active,

:AN I 0.0

:BEC

:L KH 2222 generate message and

:T FW 12

:AN F 10.0

:S F 10.0 set "MESSAGE" flag.

M001 :JU FB10 Call "REPORT" FB

NAME :REPORT

:BE

FB 10

NAME :REPORT

:AN F 10.1 If no semaphore is disabled,

: JC F B 10 0 call "di sable semaphore" FB.

NAME :SEMADIS

:A F 10.1 If the semaphore is disabled

:AN F 10.2 and the timer has not started,

:S F 10.2

: L KT0 10.2 star t the timer.

:S E T 10

:A F 10.2 If the ti mer ha s star ted

:AN F 10.3 and no message is being transmitted,

:JC FB 110 call "output message" FB.

NAME :MSGOUT

:A F 10.2 If the ti mer ha s star ted

:AN F 10.4 and the semaphore is not enabled

:AN T 10 and the timer has elapsed,

:JC FB 101 call "enable semaphore" FB.

NAME :SEMAENAB

:AN F 10.4 If the se maphore is enabl ed,

:BEC

:L KH0000

: T FY1 0 re se t al l flags.

:BE

Continued on next page

Semaphore Operat ions

CPU 948 Programming Guide

C79000-G8576-C848-04 3 - 79

Semaphore application example continued:

FB 100

NAME :SEMADIS

: SE D 1 0 Di sa bl e semaphore no. 10

:JZ =M001

:AN F 10.1 If the semaphore is disabled successfully,

:S F 10.1 set "SEMAPHORE-DISABLED" flag.

M001 :BE

FB 110

NAME:MSGOUT

:L FW12 Transmit a message

:T OW 6 to the peripherals

:AN F 10.3

:S F 10.3 Set "TRANSFER MESSAGE"

:flag

:BE

FB 101

NAME :SEMAENAB

:SEE 10 Enable se maphore no. 10

:JZ =M001

:AN F 10.4

:S F 10.4 Set "SEMAPHORE ENABLED"

: flag

M001 :BE

Semaphore Operations

CPU 948 Programming Guide

3 - 80 C79000-G8576-C848-04

Cont ents of Ch apter 4

4.1 Program Execution Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 4

4.2 STOP Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 9

4.2.1 SOFT ST OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 9

4.2.2 HARD ST O P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 13

4.2.3 OV ERAL L RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 14

4.3 START-UP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 16

4.3.1 MANUAL and AUT O M ATIC COLD RESTART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 17

4.3.2 MANUAL and AUTO MATIC WARM RESTART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 18

4.3.3 Comparison between COLD RESTART and WARM RESTART. . . . . . . . . . . . . . . . . . 4 - 21

4.3.4 RETENTIVE COLD RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 22

4.3. 5 Co mp arison of C OLD RE START and RET ENTIVE COLD RESTART. . . . . . . . . . . . 4 - 23

4.3. 6 Use r Int erfa ce s for Star t-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 24

4.3.7 Extended AUTOMATIC WARM RESTART with the CPU 948 (HOT RESTART ). . . 4 - 27

4.3. 8 Interru pti ons during START-UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2 8

4.4 RUN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 29

4.4.1 Cyclic Progra m Exec ution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 30

4.4. 2 Specif ying T im e and Inte rrupt-Dr ive n Program Exe cu ti o n . . . . . . . . . . . . . . . . . . . . . . 4 - 32

4.4.3 T im e- Controlled Program Exe c ution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 33

4.4. 4 Inte rrupt-Driv en Pr ogram Executio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 4 1

Operating Statuses and Program

Execution Levels

CPU 948 Progra mming Gu ide

C79000-G8576-C848-04 4 - 1

Contents

CPU 948 Prog ramming Gu id e

4 - 2 C79000-G8576-C848-04

4Operatin g Statuses and Program

Execu tion Leve ls

Thi s cha pt e r prov ides a n ove rvi e w of the ope ra t ing sta tuse s an d

pr ogra m ex ecut io n leve ls of the CPU 948. It i nfo rms you in deta il

abou t vari ous ty pe s of start -up a nd the orga ni zat ion blocks a ssoc ia ted

wi th the m, in which you c an pro gra m your own sequ ences for var iou s

situations when restarting.

You will also learn the characteristics of the program execution modes

"c ycli c proc e ssing ", "tim e -cont rol le d pro cessi ng" a nd

"i nterrupt-dri ve n pro cess i ng" a nd wil l see whic h bloc ks ar e ava il a ble

for your user program.

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 3

4.1 Program Execution Levels

Fi g. 4-2 provid es yo u wit h an o vervi ew of the prog ram pr ocessi ng

lev el s in the var iou s m od es. The exp lana ti ons of t he abbre vi at io ns ar e

on the following p age.

Error levels

Program execution levels

Status

SOFT

STOP

START-UP

RUN

KDB

FEDBX

PARE

QVZ

ADF

TRAF

SUF

ZYK

WEFES/WEFEH

FEDBX

KDB

PARE

QVZ

ADF

TRAF

SUF

COMMUNICATION

Cyclic processing

of communication

COMMUNICATION START-UP

Preparing for

communication

START-UP

WARM RESTART

COLD RESTART

PROCESS INTERRUPTS/INTERRUPTS

Interrupt-driven

program execution

CYCLE

Cyclic program

execution

TIMED INTERRUPTS

Time-controlled

program execution

FEDBX

KDB

PARE

QVZ

ADF

TRAF

SUF

ZYK

Fig. 4-1 Program execution levels

Program Execution Levels

CPU 948 Programming Guide

4 - 4 C79000-G8576-C848-04

Level Meaning Priority

Er ror le vels

WEFES/WEFEH

ZYK

SUF

TRAF

ADF

QVZ

PARE

KDB

FEDBX

Coll isi on of time d inte rrup ts

Cycle er ro r

Substitut ion erro r

Transfer/load error

Addressing error

Timeout

Pa rity error

Called code block does not exist

Called data block does not exist

Error generating a data block, DB or DX

Eac h erro r ha ndl ing

routine has the highest

pri ori ty . If a n erro r

occ urs, the

corre s po ndi ng e rror

level is ne ste d in

immediately.

Pr ogram ex ec ution leve l s in SOFT STO P

COMMUNICAT ION ST ART -UP

COMMUNICATION Preparation (start-up) for communication

Cy clic proce ss i ng of c om municat ion –

Pro gram proc essing l evels in START-UP

COLD RE ST ART

WARM RE ST ART

De fi ned start of the us e r pr o gra m

Continuation of the user program at the

point of inte rr uption

–

Program execution levels in RUN

TIME D INT ERRUPT S

PROCESS INTERRUPTS

CYCLE

Tim e -c ont rol le d pr ogra m exec ut io n

In terru pt- dri ve n prog ram exe c ution

Cycl ic program ex ecu tion

Ascen ding 1)

priority

(default)

1) The default can be changed by selecting parameters for DX 0 (refer to Chapter 7).

Processing via the sy stem

program

A spe cifi c syste m progr am is res po nsib le for ea ch leve l.

Interrupt stack (ISTACK)

If an inte rr upt occ ur s, the syste m progr am se ts up a n information fi e ld

in the IST ACK for ea c h leve l, to a llow i t to continue in the int er rupt ed

lev el afte r se rvi cing t he i nt er rupt .

Tab le 4-1 Progra m execution levels

Program Execut ion Levels

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 5

Nesting other levels

Whe n an ev en t occurs, which re qu ires hi ghe r pri ori ty proc essing, the

curr en t leve l is inte rrup ted by the syste m progr am and th e highe r

prior ity le vel is a c tiva te d.

Thi s occur s in the foll owin g situa ti ons:

•• at error levels: always at operation boundaries,

•• all other levels: at block or operation boundaries

( de pe ndi ng on t he set ti ng in DX 0

refer to Chapter 7)

Note

A ma xim um of 5 erro r orga ni z at io n blo ck s ca n be ne ste d. If 5

err or leve l s are act iv ate d sim ulta ne ousl y, this ca use s a n ISTA CK

ove rfl ow and the CPU cha nge s to the HARD STOP .

A spe cifi c prog ram exe cut ion l ev el is assign ed to one or a group of

orga niz ati on bloc ks whi ch are cal led by the system progra m after an

eve nt . If, for exam pl e, OB 9 is c all ed to proc ess a time-c on tro ll ed

inte rr upt , the progr am exe cuti on level TIME D INT E RRUPT S is

activated.

After the syst em pro gra m calls an orga ni zation block, th e CP U

exe c utes the STE P 5 st a tem ents is cont a ins. The c ur re nt re gi ster

rec ord is sav ed in the ISTACK and a new regist er recor d is s et up

(reg ist er : ACCU 1 to 4, bloc k stac k point er, block addr ess re gi ste r,

data block start address, data block length, step address counter, base

addr ess re gi ste r and t he int er rupt co ndi tion c ode words IC MK and

ICRW).

If "n orm al" pro gra m exe c ut ion is int e rrup ted by the occur re nc e of an

eve nt , following the exe cu tion of the OB, the CPU continue s the

pr ogra m execut io n at the point of inte rrup ti on (i nc lud ing al l the bloc k s

nested the re ) as long a s no st op is pr ogra m m ed in th e OB.

Program Execution Levels

CPU 948 Programming Guide

4 - 6 C79000-G8576-C848-04

Sub-levels

The TIMED INT E RRUPT S leve l con ta ins seve ra l sub-l evel s to whic h

a specific pr ogram (OB) i s a ss igne d. Within the T IMED

INTE RRUPT S leve l , the sub-l evel s have the ir own pri ority (ref er to

the f oll ow i ng ta bl e ).

TIMED INTE RRUPT S leve l

Sub-level Priority

Delay e d i n terrupt

cyc lic time d interrup t, shorte st peri od

...

cyc lic tim e d interrup t, longe st peri od

tim e-drive n interrupt

ascending

priority

(default)

Examples

Example of

"Execution by the system program":

At the CYCLE program execution level, the system program updates the

process image of the inputs and outputs, triggers the cycle monitoring time

and calls the PG interface management (system checkpoint).

Program Execut ion Levels

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 7

Ex am ple of

"Interrupt stack":

CYCLE

START-UP

CYCLE

SUF SUF

ADF

STOP

SUF

CYCLE

Depth 3

Depth 4

Depth 2

Depth 1

ISTACK =

Image of the

interrupted levels

Stop switch

WARM RESTART

Fig. 4-2 Principle of changing level and the ISTACK

Ex am ple of

"Interrupting a basic level with interruptability at block

boundaries":

A timed interrupt occurs while a process interrupt is being serviced.

Since the timed interrupt has a higher priority, the servicing of the

PROCESS INTERRUPT is interrupted at the next block boundary and the

TIMED INTERRUPT level nested in. If an addressing error now occurs

while servicing the timed interrrupt, the timed interrupt servicing is

interrupted immediately at the next operation boundary to nest in the

ADF level.

Program Executi on Levels

CPU 948 Programming Guide

4 - 8 C79000-G8576-C848-04

4.2 STOP Mode

The CPU 948 has two di ffe re nt STOP mode s, the "ha rd" STOP a nd

the "soft" STOP (= CPU capa ble of commun ic a tion).

4.2.1

SO FT STOP The SOFT STOP mo de has the fo llowin g feature s:

The CPU ca n c ommunicat e: the system program c al ls organiz a ti on

block OB 38 once after POWE R UP (COMMUNICAT ION

START -UP leve l in SOFT STOP) and the n cal ls OB 39

(COMMUNICAT ION leve l in SOFT STOP).

Initialization of

communication

(OB 38)

To in itia liz e com m uni ca tion , the system program ca lls OB 38 as the

use r inte rfa ce .

OB 38 is only called after POWER UP . The call is not

depende nt on the type of start- up (AUTOMAT IC COLD

/AUTOMAT IC WARM RE STAR T) set in data block DX 0.

Start-up monit oring of

OB 38

The time required for the execution of OB 38 is not monitored by the

system prog ram. You ca n, howe ver, abo rt exe c ution by cha ng ing the

mode selector to STOP.

If an error occurs in OB 38, its execution is aborted and OB 39 is

called if it e xists.

Cyclic communication

(OB 39)

If the cycl ic progra m is int er rupt ed causi ng a cha ng e to the SOFT

STOP mo de, OB 39 is called as the user interface.

If the inte rrup tion of the cyc lic progra m mean s that a handli ng bloc k

(communication) is not completely executed, it is possible and

permitted to re-call the same block or the same block type in OB 39

(e.g. SEND).

STOP Mode

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 9

Monitoring the executi on

time of OB 39

The exec ut io n time of OB 39 is mo n itore d by the system progra m . If

execution takes longer than 2.55 seconds (fixed value), the system

pr ogra m dete c ts a cyc le tim e erro r; it th en c all s the er ror OB, OB 26,

and t he n proc e s ses OB 39 aga in fr om the begin nin g. If a cyc le ti me

erro r occu rs aga i n, an IST ACK dept h > 5 ca use s an ISTACK overf low

(r ea ction: see following para grap h).

Reaction to an

error in OB 39

If an error occurs in OB 39 or in a handling block called in OB 39

(e. g. QVZ), the syst em progra m call s the approp ria t e error

or ga niz a ti on bl oc k. Afte r this has bee n exe c ute d, th e pr ogra m

pr ocessin g is conti nue d in OB 39. If the erro r OB does not exi st,

OB 39 is exe cut ed aga in from th e begi nni ng. (Exc e pti on: wit h QVZ,

KB and errors in the self test there is no reaction).

If furt he r errors oc cur, an ISTAC K depth > 5 cause s an IST ACK

overflow:

the system pro gra m abo rts pro gra m e xec ut ion (OB 39 is no l onge r

ca lled ), the CPU howe ver rem ains in the SOFT STOP mod e.

Data are not reset

If cycl ic execut io n has already ta ken plac e in the RUN mode, the

val ue s of cou nte rs, time rs, flags a nd the pr oc ess ima ge are reta i ned

du rin g the tran sition t o the stop m od e.

Real-time clock

The real-time clock continues to run. It is updated in the RS area at

10 ms intervals.

BASP signal

The BASP (disa ble outp ut comm an d) signal is act ive. This disa bl es all

the digi ta l o utp uts (e xc e pti on: in the te st in mul ti proc e s sor ope ra ti on

and wi th the PG func ti on "forc e outpu ts", BASP is not a cti ve - refe r to

Se c ti on 10. 1. 8) .

ISTACK

If a use r progra m was processed pri or to the stop m od e, information i s

ent ered in th e interr upt stack (I STAC K) prov iding infor ma tion abo ut

the cause of the interruption.

Timer processing in OB 38/3 9

While OB 38/39 is being executed, the processing of timers and

counte r s is stopped. If nece s sary, time r info rmati on must be

proc e ssed from syste m data area RS 96 to RS 99 or with OB 121

or OB 150.

STO P Mode

CPU 948 Programming Guide

4 - 10 C79000-G8576-C848-04

OB 38/OB 39 call

Fi gure s 4-3 a nd 4- 4 illust ra te the pri nc ip le of th e OB 38 an d OB 3 9

calls.

OB 38

OB 39

OB 22

RUN

OB 39

Communication

start-up

Communication

start-up

Initial status: RUN Initial status: SOFT STOP

POWER DOWN/POWER UP

Communication

processed once

AUTOMATIC

WARM RESTART Cyclic processing

of communication

Fig. 4-3 Program execution after POWER UP

OB 1

OB 39

Interruption e.g.

by STS operation

Cyclic processing

of communication

Fig. 4-4 Program execution after a cycle interruption

STOP Mode

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 11

LED displays

The SOFT STOP st atus c an be rec ogn ize d by the LEDs on the front

pane l of the CPU as follows:

LED Status

RUN off

ST OP on (cont in uous or fla sh ing lig ht)

SYSFAULT off

BASP on (except in test mode with multiprocessor mode

or with PG functi on "forc e outpu ts")

The STOP LED signa ls the possi ble c ause s of the curr en t stop st atus,

as follows:

STOP LED lit continuously

The SOFT ST OP mode was trigge re d by the following:

in single processor ope ration:

- by changing the mode selector

from RUN to STOP,

- by the PG functi on PLC STOP,

- by a device fault (PEU),

- following an OVERALL RESET.

in mult ipro cessor ope ration:

- by cha ngi ng the m od e selec tor on the COR to STOP,

- a different CPU has c hange d t o the S T OP mode due to a proble m

(each CPU not causing the error has a constantly lit L ED) or by t he

STOP switch,

- PG function PLC STOP

- PG function "program test end" on a different CPU

STOP LED flashes slowly

(approx. once every 2 sec)

The SOFT STOP was tr igg er ed by the fol lowing :

- STP or STS sta tem e nt in the user pro gra m ,

- ope ra t or error (DB 1/DX 0 erro r, sele cti on of an ill egal start- up

mode etc.) ,

- BSTACK ove rf low (ST UE B) or b rack et count er o verfl ow (KZ U),

- programming errors or de vice fa ults; the following LE D s provide

further informat ion:

- "ADF" LED

- "QVZ" LED

- "ZYK" LE D

- by the PG function "program test end" on this CPU.

STO P Mode

CPU 948 Programming Guide

4 - 12 C79000-G8576-C848-04

Exiting the SOFT STOP status

The SOFT STOP sta tus can be exited as follows:

a) by selecting a restart (refer to Section 4.4),

b) by an OVERAL L RESE T foll owe d by a COLD REST ART .

4.2.2

HARD STOP If the system pr ogra m can no longer be exe cute d pr ope rly, the CP U

cha nge s to the HARD STOP mode to ensure a safe mode in this

situation.

A HARD STOP ca n be cause d by the foll owi ng:

•• sto p opera ti on (ST W) for the syste m pr ogra m

•• ISTACK overflo w (STUE U),

•• time out (QVZ) or parit y error (PARE ) in the system

RAM/EPROM,

•• erro r in system prog ra m

Note

The CPU is stopped . You ca n only exit the HARD ST OP mod e

by switc hi ng the po wer off a nd th en o n ag ai n!

LED displays

The HARD STOP sta tus ca n be reco gni ze d by the fol lowi ng LEDs on

the front pane l of the CPU:

LED Status

RUN off

STOP off

SYSFAULT on

BASP on

STOP Mode

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 13

4.2.3

OVERAL L RESET With an OVERALL RESE T the whole use r memory and ope rand

areas (flags, process images etc.) are deleted.

Requesti n g an

OVERAL L RESET

Be fo re a n OVE RAL L RESE T can be pe rfo rm ed, it must be re que sted.

An OVE RAL L RESE T is re que ste d whe n the ST OP LED fl ashe s

quickly.

Request by the syste m

program

Ea ch tim e you swit ch on th e power , the CPU r uns thr ough an

initialization routine. If an error is detected during the initialization

(bac k-up volta ge failure during POW E R OFF), the syste m progr am

requires an OVERALL RESET.

The ca use of the problem must be elimi nate d (e.g. repla cing the

battery) following which an overall reset of the CPU is necessary.

An OVERALL RESE T is also re que ste d if a CPU or system er ror

occurs. You can rec o gniz e this error because the re quest occurs aga in

foll owin g the OVERAL L RESE T. In thi s case, contac t your local

Siem e ns representa ti v e .

Operator request

Wit h th e ste ps out li ne d in the table, you c an a lso re que st a n

OVE RAL L RESE T (the op er atin g el eme nt s are on the f ront pane l of

the CPU - Fig. 4-1):

Step Action Result

1 Change the m ode sele ct o r

switch from RUN to STOP. The CPU is in the STO P

mode . The STOP LED is lit

continuously.

2 Hol d the rese t switch in the

OVERALL RESET position;

at th e s ame time, ch an ge the

mode selector from STOP t o

RUN and then back to STOP.

An OVERALL RESE T is

re quested. The ST O P LE D

flashes quickly.

Note

I f you do not wa nt to e xe cute the OVE RAL L RE SE T you

req ueste d, carry out a MANUAL COLD REST ART or

MANUAL W ARM RE STAR T.

STO P Mode

CPU 948 Programming Guide

4 - 14 C79000-G8576-C848-04

Performi ng an

OVERAL L RESET

Rega rdles s of wh et her you or the system p rogram re quested the

OVERALL RESE T , you pe rform the OVERALL RE SET as follo ws

(ini ti al status: STOP L ED fl a shing quic kl y):

OVERALL RESET using

contro l elements on the CPU

Action Result

Hold th e reset sw itch in the

OVERALL RESET position. A t

the sam e tim e, c h an g e the m o d e

sele ctor f rom S TOP to RU N and

back to S TOP a gai n (re fer to

Fig. 4-1).

An OVERALL RESET is

p erform e d. The ST OP LED is li t

continuously.

OVERALL RESET from th e

Action Result

Acti vate the PG f uncti on "de lete

blocks". An OVERALL RESET is

p erform e d. The ST OP LED is li t

continuously.

Note

In con trast to the CPU 946/94 7, you can al so initiat e an

OVERAL L RESET on the CPU 948 in the RUN mod e. In this

ca se, the CPU auto mat ica lly chan ges to the STOP mod e and the

OVERALL RESET is then performed.

During the OVERALL RE SE T, all the LEDs ar e un lit a pa rt fr om

the INIT and BASP LEDs.

Once the OVERALL RESET is completed, the only permitted

start-up mode is then a COLD RESTART.

Loading the memory card

and calling OB 39

After pe rforming the OVE RALL RESET, the m em ory card i s loa ded

(p rovi de d it is plu gge d in) fol lowi ng which OB 39 is calle d.

STOP Mode

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 15

4.3 START-UP Mode

The START- UP mod e has the following feat ures:

Mode change

ST ART -UP is the tra nsit ion from the ST OP mod e to the RUN mode .

Start-up ty pe s

The CPU 948 has the fol lo wing start-up mode s:

- COL D RESTAR T ( manual or autom atic)

- WARM RE STAR T (ma nual or automa tic )

(Yo u ca n se lec t th e type of sta rt -up wi th op er at in g el eme nt s and by

as signi ng param e ters in DX 0)

COLD RESTART

The cycl ic user prog ram is pr ocesse d from th e be gi nning.

The syst em pr ogram ca lls OB 20 as the use r interf ace .

WARM REST ART

The ex ec ut io n of th e cyc li c user pr ogra m is co nti nue d fr om the poi nt

at whic h it was inte rrup ted.

The system pr ogram ca l ls the fol lowing OB s a s the user inter fa ce :

-OB 21 for a MANUAL WARM RE ST ART,

-OB 22 for an AUTOMAT IC WARM RESTAR T.

No time monitoring of the

start-up O Bs

The ex ec ut io n ti me of the star t-u p orga ni z at io n blo ck s is not

moni to re d. You can ca ll other bl ocks wit hin these OBs. Mak e sure

you avoid end les s loops!

Counters, timers, flags,

process images

The values of c ounte rs, time rs, flags and proce ss ima ges a re handled

differently in the va rious start-up type s (refer t o Sec tion 4.4.3).

BASP

The BASP signa l (disa bl e outpu t com mand ) is act ive. This disa bl es all

the d igi ta l o utp uts (e xcepti on: in the te st mo de in multiproc e sso r

oper ation, the BASP is not activa ted - refe r to Section 10.1. 8).

Interrupts

The inte rrup ts (nor mal int er rupt s, pr ocess int e rrup ts, tim ed in terru pts)

are disabl ed.

Start-up in the mu ltiprocesso r

mode

Starting up in the multiprocessor mode is described in Section 10.1.7.

START -UP Mode

CPU 948 Programming Guide

4 - 16 C79000-G8576-C848-04

4.3.1

MANUAL and

AUTOMATIC

COLD REST ART

When is a COLD RESTART

permitted?

A COLD RESTAR T is always perm it ted provi de d th e system is not

re qu est ing an OV E RAL L RESET.

When is a COLD RESTART

necessary?

A COLD RESTAR T is necessary a fte r t he foll o wi ng:

- OVE RAL L RESE T ,

- lo ad ing the user me mory with the use r progra m whil e the CP U

is in the stop mode

- IST ACK/ BST ACK overfl ow,

- COL D RESTAR T abor ted (by POWE R OFF or changi ng the

mode selector to "STOP" ),

- stop aft er PG func tion "p rogr am test end"

MANUAL COLD RESTART

You can trigger a MANUAL COLD RE ST ART as follows:

•• Using the ope ra t ing eleme nt s of the CPU:

Hold the re se t sw itch in the RE SET po sition ; at the sam e tim e chan ge

the mode select or from S TOP t o RU N (re fer to Fig. 4-1).

•• From the PG:

Select the PG function PLC START/COLD RESTART.

AUT OMAT IC CO L D

RESTART

An AUTOMAT IC COLD RESTAR T is triggered as f ollows:

At POWER UP, when

- the defaul t "AUTOMAT IC WARM REST ART aft er POWE R UP"

in DX 0 has been chang ed to "AUTOMAT IC COLD RESTAR T

after POWE R UP",

- th e mode sele ctor on a ll CPUs and on the coor din at or must re m ain

set to RUN

and

the CPU was not in the ST OP mod e when the powe r was swit ch ed off.

Note

If the CPU was in the STOP mode when th e power was switche d

off (for exa m ple, follo wing an addr essin g er ror) , an

AUTOMATIC COLD R ESTART is not permi tted. The STOP

mode can only be exited in this case with a MANUAL COLD

RESTART.

START-UP Mode

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 17

Aborting a cold restart

You c an a bort an acti ve COL D REST ART onl y by cha ngi ng t he mod e

se lec tor to ST OP or by swit ch ing off th e po wer . If y ou abort a COLD

RE ST ART you must repea t it.

4.3.2

MANUAL and

AUTOMATIC

WARM RESTART

When is a WARM RESTART

possible and permitted?

A MANUAL WARM RE START is only possible af ter stoppa ge s

caused by the following:

•• the mod e se lec tor was chan ge d from the RUN positi on to the

STOP posi ti on,

•• a stopp ag e in multipr oc essor op er at ion cause d by the HALT signa l

f rom the coord ina tor,

•• POWE R OFF, wi th the app ropr iate setti ng in data block DX 0,

•• PG function PLC STOP.

Note

If the stop pa ge was cause d by an eve nt other th an those listed

above, then no war m resta rt is p o s sibl e. T he system program

will onl y pe rm it a COLD RE STAR T.

A MANUAL or AUTOMATIC WARM REST ART is only

permitted whe n

•• the user pr ogra m was not mo dif ied dur ing the stop mode

and

•• a COL D REST ART is not necessar y for ot he r rea sons (re fe r to

Se ction 4. 4.1) .

START -UP Mode

CPU 948 Programming Guide

4 - 18 C79000-G8576-C848-04

MANUAL WARM RESTART

You trigger a MANUAL WARM RESTART a s follows:

•• using the cont rol eleme nts of the CPU:

ini ti al state : the rese t swit ch is in the mi d setti ng

cha ng e the mod e selec tor from STOP to RUN (refe r to Fig. 4-1)

•• from th e PG:

sele ct the PG function PL C START/W ARM RE STAR T.

AUTOM AT IC WARM

RESTART

An AUTOMAT IC WARM RESTAR T is triggered as follows:

With POWE R UP, when

- the defaul t "AUTOMAT IC WARM REST ART aft er POWE R UP"

is set in data bloc k DX 0 or DX 0 does not exist,

- the mode sele ctor on all CPUs and on the coor din ator rema in

unchanged and set to RUN

and

the CPU was not in the ST OP mod e when the powe r was swit ch ed

off,

- no fu rth er e rr ors ha ve occ ur re d duri ng t he ini ti aliz a tion nor before

the power was switched off,

- no COLD RE ST ART is req uir ed due to the rea sons liste d above .

Follo wing powe r fail ure or switching the powe r off in the RUN mode

foll owe d by the ret urn of power/POWER UP, the CPU runs throug h

an in it ia li z atio n rout ine and t he n au tom a ti c ally p er form s a WA RM

RESTART.

If there is a power failu re on an exp an sion unit , (PEU sign al), the CPU

cha nge s to t he STOP m ode . It rem ai ns in this m ode unt il the PEU

signa l is switch ed inac tive and then perfo rms an AUTOMATI C

WARM RE ST ART or an AUTOMAT IC COLD RE ST ART .

START-UP Mode

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 19

Note

With a WARM RESTART not e the following special sit uation:

The CPU is currently proc e ssi ng a n error OB (e . g. due to an

add ressi ng error ADF) and the n change s to the STOP mo de

owing to POWER OFF, HAL T, stop switch or PG-STP.

Fo llowin g this, a MANUAL or AUTOMATIC WA RM

RESTART is executed.

Rea ction of the CPU:

-Before OB 21/22 i s ca lled , the int er rupted proce s sing of the er ror

OB is completed.

- If t he error OB do es not lea d to a stop op er atio n, the n fol lo wing

the processing of the remainder of the error OB, a WARM

RESTART is exec uted.

- If t he er ror OB se ts the CPU to the stop m ode , then only a

COLD RESTART is possible .

Aborting a

WARM REST ART

You can onl y abort a WARM REST ART afte r it h as start ed by

cha ngi ng the mod e sele ctor to STOP or by POWER OFF. If you ab ort

the warm re sta rt in this way , both a COLD RESTART or WARM

REST ART is then possible .

START -UP Mode

CPU 948 Programming Guide

4 - 20 C79000-G8576-C848-04

4.3.3

Comparison between

COLD RESTART and

WARM RESTART

The followin g table co ntains a comparison of th e star t-up t yp es

COLD RESTART and WAR M RESTAR T..

COLD RESTART WARM REST AR T

Manual

triggering: Mo de selec to r from positi on ST OP to RU N

and rese t switc h set to RE SE T position

PG func tion PLC STAR T (COLD

RESTART)

Mode sele ctor from posit ion STOP to

positi on RUN

PG func tion PLC ST ART (WA RM

RESTART)

Automatic

triggering: Swi tching on the power suppl y, whe n

"AUTOMATIC COLD RESTART after

POWE R UP" is entere d in DX 0

Swit chin g on the po wer supply when the

defa ult is entered in DX 0 or no DX 0 exists

System

program

activities:

Set up block address list in DB 0

De let e p roc e ss ima ge of the input s

Delete process image of the outputs

Bl oc k ad dre s s list re t ai ne d in DB 0

Process image of the inputs re tained

Proc e ss image of t he outputs reta i ned

Delete flags, timers and counters

Delete digital/analog I/Os

(each 2 x 128 bytes)

Delete IPC flags (256 bytes)

Del ete del aye d interrup ts and timed jobs

Delete ISTACK/BSTACK

Delete semaphore

Fla gs, timers a nd c ount e rs reta ine d

IPC fla gs reta ine d

Delete delayed inte rrupts,

timed jobs r etained

ISTACK/ BST ACK re tain ed

Se ma phore retained

I f DB 1 ex ists:

write th e digital I/ Os e nt e red in it in to

the PI lists

I f DB 1 does not exi st:

enter the modules which actually exist

(o nly d igi tal I/O) i nto the PI list s

IPC flags ar e ignored

No e ntries m a de from DB 1

Table 4-2 Characte ristics of COLD RESTART an d WARM RESTAR T

START-UP Mode

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 21

COLD RESTART WARM REST AR T

Table 4-3 continued:

System

program

activities

(continued):

Se t system para m et ers ac c ordi ng t o the

se ttin gs in DX 0 DX 0 not evaluated

Call user interface OB 20

( if it exist s) 1) Call user int er face O B 21/ 22

(i f the y e xist) 1)

Sy nc hron iz e star t-u p in mul tiprocessor

operation Synchr oni ze sta rt -up in mu ltipr oc essor

operation

Transition to the cycle:

- switch BASP inacti ve,

- call OB 1

Tra nsit ion to the cyc le :

- BASP remai ns ac tive

- delete process image of the outputs

- proce s s rem a ini ng c yc le

- switch BASP inactiv e

- ca ll OB 1

1) Follo wing POWER UP, the user interfaces are called in the following order during the START-UP:

OB 38, OB 39, OB 20/OB 22.

4.3.4

RETENTIVE COLD

RESTART If the parameter for a "cold restart with memory" is stored in the

loa ded DX 0 block, the syste m prog ram go es throug h a RET ENTI VE

COL D REST ART inste ad of a WAR M REST ART . How this diff ers

from a "no rmal " COLD RESTAR T ca n be see n in the foll owing

section.

START -UP Mode

CPU 948 Programming Guide

4 - 22 C79000-G8576-C848-04

4.3.5

Comparison of

COLD RESTART and

RETENTIVE COLD

RESTART

The followin g table s hows the di fferences betw een a CO LD

RESTART and R ETENTIVE COLD RESTA RT.

COLD RESTART RE TENTIVE CO LD RESTART

Manual

triggering: Mo de selec to r from positi on ST OP to

p osit ion RUN a nd rese t swit c h set t o

RESET

PG func tion PLC STAR T (COLD

RESTART)

Mode sele ctor from posit ion STOP to

positi on RUN

PG func tion PLC ST ART (WA RM

RESTART)

Automatic

triggering: Swi tching on the power suppl y, whe n

AUTOMAT IC COLD REST ART after

POW E R UP is en tere d in DX 0

Swit chin g on the po wer supply when

AUTOMATI C WAR M REST ART after

POWER UP and COLD RE ST ART WIT H

MEMORY is entere d in DX 0

System

program

activities:

Set up block address in DB 0

De let e p roc e ss ima ge of the input s

Delete process image of the outputs

Del ete del aye d interrup ts and timed jobs

Delete flags, timers and counters

Delete digital/analog I/Os

(each 2 x 128 bytes)

Bl oc k ad dre s s list re t ai ne d in DB 0

Process image of the inputs re tained

Proc e ss image of t he outputs reta i ned

Delete delaye d i n te r rupt s a nd t imer jo b s

Fla gs, timers a nd c ount e rs reta ine d

De lete di git a l I/O (128 bytes )

Analo g I/Os reta ine d (128 byte s)

Delete IPC flags (256 bytes)

Delete ISTACK/BSTACK

Delete semaphore

IPC fla gs reta ine d

Dele te ISTACK/BSTA CK

Se ma phore retained

I f DB 1 ex ists:

ent er the dig it al I/Os and IPC fl a gs it

cont a ins in the PI lists

I f DB 1 does not exi st:

ent er the existi ng m odu le s (onl y dig it al

I/Os) in the PI list s

IPC flags ar e ignored

No entries from DB 1

Table 4-3 Differences betwee n a cold restart and a RETENTI VE COLD RESTART

START-UP Mode

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 23

COLD RESTART RE TENTIVE CO LD RESTART

System

program

activities

(continued)

Table 4-4 continued:

Se t system para m et ers ac c ordi ng t o defa ult

in DX 0 No evaluation of DX 0

Call user interface OB 20

( if it exist s) 1) Call user int erface O B 21/ 22

(if it exi sts) 1)

Sy nc hron iz e star t-u p in mul tiprocessor

operation Synchr oni ze sta rt -up in mu ltipr oc essor

operation

Transition to the cycle:

- switch BASP inacti ve

- call OB 1

Tra nsit ion to the cyc le :

- switch BASP inactiv e

- ca ll OB 1

1) After POWER ON, t he user interfaces are called in the following order during START-UP:

OB 38, OB 39, OB 20/OB 22.

4.3.6

User Interfaces fo r Start-Up The organi z at ion blo ck s OB 20, OB 21 a nd OB 22 serv e as use r

inte rf ac es for th e vari ous ty pe s of star t-u p. You can sto re your ST E P 5

pr ogra m for the t ype of start-up in th ese blo ck s.

OB 20

When the CPU executes a MANUAL or AUTOMATIC COLD

RE ST ART , the syste m progra m cal ls OB 20 once. In OB 20, you can

store a STEP 5 progra m which i s respon si ble fo r preli mina ry step s for

a cold resta rt of cycl ic proce ssing prior to the exe cut ion of the cycli c

program.

You can, for example:

•• set flag s

•• sta rt timers (t he star t is exe cu ted by the system pro gra m when it en-

ters the RUN mode)

•• set default values for data to be output to I/O modules

•• synchronize CPs.

After proces s ing OB 20, the cyclic program begins by calling OB 1 .

If OB 2 0 is not load ed, the C PU b egin s the cycli c program

execution immediately af ter the C O LD RESTART is co mpleted

(following the sys tem activiti es).

START -UP Mode

CPU 948 Programming Guide

4 - 24 C79000-G8576-C848-04

OB 21

If the CPU perfor ms a MANUAL COL D RESTAR T or RETENT IVE

MANUAL COLD RESTART, the system progr am c al ls OB 21 once.

He re, y ou can store a STEP 5 progr am whi ch exe c utes pre l imin ar y

ste ps for a war m rest art of the cyc lic progr am .

MANUAL WARM RESTART

With a MANUAL WARM RE STAR T, the cyclic progr am is

cont in ue d wit h the next state me nt following the poin t at whi ch it wa s

inte rr upt ed aft e r proce s sing OB 21 , the seque nc e is as fol lo w s:

•• The BASP signa l (disa bl e com m an d output ) re mai ns ac tive during

the proc e ssing of the re mai nin g cy cle and is only switche d in ac t ive

at the beginning of the next (complete) cycle.

•• The proce s s i ma ge of the outputs is re set at the end of the

re ma i ning cycle.

•• If OB 21 is not loa de d, the CPU begi ns a gai n at the point at which

the progra m was int errupt e d on completion of the MANUAL

WARM RE ST ART and the system ac tivi ties.

MANUAL RETENTIVE COLD

RESTART

If the parameter "COLD RESTART WITH MEMORY" is entered in

the dat a block DX 0, afte r proce ssing OB 21, the syst em progra m then

goes th roug h a COLD RESTART (the CPU resum es progra m

execution with the first STEP 5 state me nt in OB 1). The signal

sta tes of the flags, IPC flags, sem aphor e and t he block a ddr ess list

(DB 0) ar e re tai ne d.

START-UP Mode

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 25

OB 22

Whe n the CPU execute s an AUTOMAT IC WARM REST ART or

AUTOMAT IC RET ENTIVE COL D RESTAR T, the system program

ca lls OB 22 onc e. He re, yo u can store a ST EP 5 program which

exe c utes pre li m inary step s (gener al ly foll owi ng a powe r fail ure ) for a

warm rest a rt of cyc l ic progra m executi on.

AUTOM AT IC WARM

RESTART

Following POW E R UP, the CPU ex ec utes the system a ct iv it ies l isted

in Sec t ion 4.4 .4 f or a warm restart and at te m pts to resum e the progra m

at the poin t at which i t was int errupted.

OB 22 is called first.

Aft er ex ec ut in g OB 22, the in te rru pte d pr ogra m exec ut io n is re su med

wi th the nex t state me nt fo llowin g the poi nt at which th e progra m was

interrupted.

Follo wing a power fai lur e and the ret urn of powe r:

•• The BASP signa l (disa bl e com m an d output ) re mai ns ac tive during

the remaining cycle and is only switched inactive at the beginning

o f the fi rst complet e cycle .

•• The proce s s i ma ge of the outputs is re set at the end of the

re ma i ning cycle.

•• If OB 22 is not loa ded, the CPU resum es progra m proc essi ng

im me di a te ly at t he point of i nt er rupt io n at the end of t he

AUTOMAT IC WARM RE START .

AUT OMAT IC RET ENT IV E

COLD RESTART

If the parameter "COLD RESTART WITH MEMORY" is entered in

the dat a block DX 0, afte r proce ssing OB 22, the syst em progra m then

goes th roug h a COLD RESTART (the CPU resum es progra m

execution with the first STEP 5 state me nt in OB 1). The signal

sta tes of the flags, IPC flags, sem aphor e and t he block a ddr ess list

(DB 0) ar e re tai ne d.

START -UP Mode

CPU 948 Programming Guide

4 - 26 C79000-G8576-C848-04

4.3.7

Extend ed AUTOM AT IC

WARM RESTART with the

CPU 948 (HOT RESTART)

The "HOT RESTART" mode specified in the IEC 1131 standard, part

1 is also po ssible in the CPU 948. The "HOT REST ART" is a warm

resta rt co ntr oll ed by a bat te ry -ba c ke d cloc k (ac co rdi ng to IEC 1131) .

The clock monitors the time between switching off and switching on

the powe r su ppl y for the CPU. W he th er o r not a warm r est ar t is then

permitted depends on the time elapsed.

The autom ati c "HOT RE ST ART " of the CPU 948 is not su ppor ted

dire c tly by the system progra m, whi ch mea ns that yo u must progra m

this you rsel f.

The basic functions a va ilable are the AUTOMAT IC WAR M

RESTART (OB 22) and the re al time c loc k whic h although int er na l is

backed up by an external battery.

A "HOT RESTAR T" is progr amm ed as shown below:

Mode Activity/block

RUN Save tim e (time of da y and da te ) regu la rl y from the ext er na l cloc k i n defin ed m em ory

cells (e.g. in data words):

- at the end of the cycle in OB 1

- t ime -c ont rol led by tim e d inte rrup ts (e.g . OB 10), if higher accu r acy is nec e ssary

AUTO-

MATIC

WARM

RESTART

OB 22

C al c ula t e do w n ti me :

Tdown = fi rst tim e val ue aft e r retur n of powe r - last time value sav ed bef ore powe r fail ure

IF ... THEN...

Do wn time > def ault ma xi mu m value Stop warm re sta rt

(STP operation)

execute modified warm restart

Do wn time ≤ default maximum value Continue warm restart

START-UP Mode

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 27

4.3.8

Interrup tio ns during

START-UP A sta rt -up pr ogra m can be in terru pted by the fol lowi ng:

•• power failu re in the central controll er (NAU) or in the e xpansio n

u nit (PE U) ,

•• stop switc h, stop com mand, HALT or PG-STPor

•• pr ogra m errors or de vi c e faul ts (re fe r to Sec t ion 5.5 ).

Basic rules for an interrupted

START-UP

The fol lowing ba sic rule s apply to the sta rt-up response of th e

CPU 948:

If the START -UP is interr upt ed, the subsequen t START -UP is

always resta rte d fr om the begi nning.

The last selected type of start-up is selected. Example:

1. POWER DOW N (NAU) in the cyc le

2. Switch set to STOP

3. POWER UP

4. Switch set to RUN

React ion: the CPU exec utes a MANUAL WARM RESTART

An inte rru pted COL D RE ST ART ca nno t be continued with a

WARM RE STAR T, but mu st be repea t ed .

Followi ng a n interru pte d WARM REST ART , both a COL D

RESTART and a new WARM RESTART are possible.

Response of the CPU on the

return of power after power

failure or PEU signal

If the sta rt- up exe cuti on is interru pted by a powe r fai lur e or the PEU

signal, the re sponse of the CPU when po wer returns depends on the

set and interrupted m od e. T he following ta bl e provides a n ov er view.

Mode set in DX 0 Inte rrupte d mo de Interrupte d

start-up O B Reac tion of the CP U

AUTOMATIC

COLD RE ST ART MANUAL

COLD RE ST ART OB 20 Depending on the prior events, an

AUTOMATIC CO LD RESTART is

executed (OB 20 is called and

processed from the beginning).

No "rem aini ng star t-up" is

p roc e ssed, (OB 20 or OB 21 is not

resumed).

MANUAL

WARM RE ST ART OB 21

AUTOMATIC

COLD RE ST ART OB 20

AUTOMATIC

WARM RE ST ART MANUAL

COLD RE ST ART OB 20 S TOP

MANUAL

WARM RE ST ART OB 21 An AUTOMATIC WARM RE ST ART

is executed (OB 22 is called and

processed from the beginning);

no "rem aining star t- u p" is proc e s sed

(OB 21 or OB 22 is not resumed).

AUTOMATIC

WARM RE ST ART OB 22

START -UP Mode

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4 - 28 C79000-G8576-C848-04

4.4 RUN Mode

Whe n the CPU has execut ed a START -UP (and on ly then) it change s

to the RUN mode. This mode is characterized by the following

features:

Execution of the user program

The user progr am in OB 1 is exe c uted cyc lica ll y an d additional

inte rr upt -dri ve n pro gra m secti ons ca n be nested in it.

Timers, counters, process

image

Al l the tim e rs and cou nte rs sta rt ed i n th e progra m co nti nue to r un, the

proc ess image is updated cycli cally.

BASP

The BASP signa l (disa bl e comm an d out put ) is switc he d ina ctiv e. This

enables all the digital outputs.

IPC flags

The IPC fl ags (if pro gra m me d in DB 1) are upda te d cyc lic al ly .

In the RUN mode , the f ollowi ng program exe c ution le ve ls ex ist:

CYCLE

The user progr am in OB 1 is processed cyclica lly.

PROCESS INTERRUP TS/

IN TERRUP TS

The ex ecut io n of th e use r program is int er rupt -dr ive n (4 int er rupt

lev el s or 1 proce s s inte rr upt le ve l with 8 sub-l eve ls).

TIMED INTERRUPTS

The user progr am is processed time-cont rolled (9 cyclic time d

interrupt s, 1 de laye d i nte rr upt , 1 clo ck -c ontrolled in te rru pt) .

The execut ion levels diffe r from ea ch other as follows:

•• they are triggered by different events

•• there are one or more organization blocks serving as user

int erfaces for ea ch le ve l of program exec ut ion.

All the proc essin g levels in a CPU 948 can be prog ramm ed

sim ultaneously. The levels a re called by t he syst e m program

according to the events that occur and the preset priority (refer to

Se c ti on 4. 2).

RUN Mode

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 29

4.4.1

Cyclic Program Execution With programmable controllers, cyclic program execution (progra m

execution level CYCLE) is the main mode.

Triggering

If the CPU ha s c om pleted the start -up program without errors, it the n

be gi ns cycl ic pro gra m e xe c ut ion .

Principle

The principle of cyclic program execution (system activities):

From start-up

Trigger cycle monitoring time

Update IPC input flags

Supply process image of the

inputs (PII)

Call cyclic user program (OB1)

User program

other program

execution levels

including nesting in of

Output process image of the

outputs (PIQ)

Update IPC output flags

System activities e.g.

loading or deleting blocks

compressing blocks . . .

Fig. 4-6 Cyclic program execution

RUN Mode

CPU 948 Programming Guide

4 - 30 C79000-G8576-C848-04

User interf ace OB 1

During cycl ic prog ra m exec ution, organ iza tion bl ock OB 1 is cal le d

regu la rl y as the user inte rfa ce . The STEP 5 use r prog ram in OB 1 is

pr ocesse d from the be ginni ng with the bloc k ca ll s you have

pr ogrammed . Aft e r the system ac ti vities, the CPU starts again from

the beginning with the first STEP 5 statement in OB 1.

In OB 1, you prog ra m the c all s for progra m , func tion a nd seque nc e

bl oc ks to be exe cu te d wit hi n the c yc lic pr ogra m .

Interrupt points

Cy clic pro gra m exe c ut ion ca n be inte rrup ted by the followi ng:

•• time-controlled program execution at block or operation

boundaries,

•• pr ocess int e rrup t-d riv en p rogr am exe cu ti on via input byte IB 0 at

b lock bo unda ri es,

•• inte rr upt -dri ve n pro gra m exe c ut ion (inte rrup ts INT A/B/ C/D, E , F,

G) at block or operation boundaries..

You spec if y the type of inte rrup t (at block or oper at ion boun darie s) in

da t a bl oc k D X 0 (re fer to Chapter 7).

Cyclic program execution can be interrupted or aborted rega rdles s of

the parameter setting in DX 0 as follows:

•• whe n a devic e fault or pro gra m err or oc c urs (a t opera t ion

boundaries,

•• by oper ator interv ent ion:

- st op swit ch , HAL T (at opera ti on bo unda ri e s),

- PG func tion (a t che c kpoi nt s - refe r to Cha pt er 11),

•• by the stop com m an d STS (a t ope ra ti on bou nda ri es),

•• by a power fa i lur e on the cent ra l cont rol le r or in the expa nsi on uni t

( at operation boundari e s).

RUN Mode

CPU 948 Programming Guide

C79000-G8576-C848-04 4 - 31

4.4.2

Specifyi n g Time and

Interrupt-Driven Program

Execution

Wit h tim e and inte rr upt -drive n progra m e xe cut ion , vari ous ty pe s are

available which can at present only be used as alternatives (i.e. not

mix ed ). You deci de which of the typ es of pr oc essin g you wa nt to use

by setting the parameter in data block DX 0 (refer to Chapter 7).

"Process int errupt s via IB 0"

The ex ecut ion mode "proce ss inte rrupts via IB 0" has the followi ng

features:

•• only po ssible in single pr ocessor opera tion,

•• the nest ing o f highe r pri ori ty program leve ls is onl y possib le at

bloc k boundaries ,

•• the del a yed inte rrup t (proc esse d by OB 6) cannot be used,

•• the t ime -c ont rol le d inte rr upt (proc e ssing by OB 9 ) cannot be used.

"System interrupts" mode

The "system interrupts" m ode is characterized by the following

features:

•• single or multiproc essor mode po ssi ble,

•• highe r pr ior it y prog ram lev el s are ne ste d at block or command

boundaries,

•• del ay ed i nter rupt s are pro cessed by OB 6,

•• tim e -c ont rol le d in terrupts are proc e sse d by OB 9.

Interrupt ing time and

interrupt-driven program

execution

Tim e an d inte rrup t-d riv en program exe cu ti on can b e interr upt ed or

aborted regard les s of the para meter setting in DX 0 as follows:

•• whe n a devic e fault or pro gra m err or oc c urs (a t opera t ion

boundaries,

•• by oper ator interv ent ion:

- st op swit ch , HAL T (at opera ti on bo unda ri e s),

- PG func tion (a t che c kpoi nt s - refe r to Cha pt er 11),

•• by the stop com m an d STS (a t ope ra ti on bou nda ri es),

•• by a power fa i lur e on the cent ra l cont rol le r or in the expa nsi on uni t

( at operation boundari e s).

RUN Mode

CPU 948 Programming Guide

4 - 32 C79000-G8576-C848-04

4.4.3

Time-Co n trolled Progr am

Execution T his type of progra m execut ion inc lu des the delaye d int errup t, the

tim e -c ont rol le d in te rru pt and c yc li c tim e d inte rru pts.

Al l these interrup ts ar e time-controlled.

Tim e -cont rolled pr ogra m exec ut ion uses th e TIMED INTERRUPTS

level.

Delayed interrupts

Triggered once after a selected delay time in the millisecond range.

Organ iz ati on bloc k OB 6 is calle d with this inte rrup t.

Clock-controlled interrupt

Tri gge re d at a selec ted i nterv al or once at an absolut e point in time .

Organ iz ati on bloc k OB 9 is calle d with this inte rrup t.

Cyclic timed interrupt

Tri ggere d at 9 differe nt inter vals. Eac h timed interr upt is assign ed an

or ganiz a tion bl oc k (OB 10 to OB 18) . This invol ve s fixed c yc les, i. e.

the int erval be tween two program stops is fixe d.

Priorities

Wit hin time -con trolled progr am exe cu ti on, the follo wing prioritie s are

set:

Delay e d i n terrupt OB 6

cyclic timed int., period 1

cyclic timed int., period 2

cyclic timed int., period 3

cyclic timed int., period 4

cyclic timed int., period 5

cyclic timed int., period 6

cyclic timed int., period 7

cyclic timed int., period 8

cyclic timed int., period 9

tim e-co ntr oll e d inte rrup t

OB 6

OB 10, short est per iod

OB 11

OB 12

OB 13 ascending

OB 14 pri ori ty

OB 15

OB 16

OB 17

OB 18, lon ge st period

OB 9

Note

Tim e -c ont rol le d i nte rr upt servi c ing in OB 6 and in OB 9 is only

possi ble whe n the param e ter "proc ess inte rrup ts via IB 0 = off" is

se t in DX 0. Wit h the defa ul t setting i n DX 0 ("pro cess int er rupt s

via IB 0 = on") th e corr esponding pro cess int er rupt s of IB 0 are

proc esse d using OB 6 and OB 9 (refe r to Secti on 4.5. 4).

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Delayed interrupt

Wit h the del ay ed int er rupt of the CPU 948, sma ll time inte rva ls wit h a

resol uti on of 1 ms ca n be set . Once the sele cte d time has el a psed , the

system prog ram ca ll s OB 6 once.

Resolution

The delayed interrupt is generated by calling the special function

organization block OB 153 (refer to Section 6.14). As soon as the

del ay tim e assig ne d with OB 153 ha s ela psed , the system pro gra m

inte rr upt s the cur re nt pr ogra m execut io n an d cal ls OB 6 (progra m

exe c ution lev el TI MED INT ERRUPT S). Fol lowi ng this, prog ra m

execution is resumed at the point at wh ic h it was interrupted.

The use of t he de la yed inte rrupt is, howe ver, only possib le when

"p roc e ss in te rru pts vi a IB 0 = off " is set in th e da t a bloc k DX 0.

User interf ace

OB 6

OB 6 is c alled as the user interface for a delayed interrupt. In O B 6, you

write a S T EP 5 program t o be e xec uted in this situation. If OB 6 i s not

loaded, program execution is not interrupted.

Interruptions

With the defa ult sett ing, the TIME D INT ERRUPT S leve l has the

hi ghe st pr ior it y of th e ba sic levels (ca n be mo dif ie d by cha nging the

parameter assignment in DX 0).

In time d-contro ll ed progr am e xecu ti on, the servici ng of t he delaye d

interrupt has hi ghe st pri ority.

Owi ng to the dist rib uti on of prio rit ie s, t he proce s sing of t he dela ye d

inte rr upt ca nno t be interrup te d by any other use r prog ram.

Special features

•• A delaye d interr upt is only proc e ssed in the RUN mode . Delaye d

int er rupt s owing in the ST OP mode , durin g power down or

START -UP a re discarded.

•• A gene ra ted del ayed al ar m (= OB 153 c all was processed ) is not

ret a ined in the tr ansiti on to the ST OP mod e and durin g POWE R

OFF.

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•• If yo u generate a new d elayed in terrupt, i.e. call OB 153 with

new parameter s , a previo usly set delayed inter ru pt is cancell ed.

A delay ed inter rupt currently being processed is cont inued. Th is

means t hat only one d elayed interr up t is valid at an y o ne time.

•• If a delayed interrupt occurs without the previous one being

com pl e tely proc e ssed, the new int e rrup t is disca rde d. Delayed

inter rupts are not c hecked for co ll ision s!

•• Not e the spec i al func tions OB 122 and OB 142 wi th whi ch you

ca n disabl e or de lay th e servi cing of dela yed inte rrup ts.

Clock-controlled interrupt

The CPU 948 has a bat te ry- ba ck ed cloc k (c en tral b ack- up vi a the

power supply of the central controller), which you can set and read out

usi ng the STE P 5 progr am. This cloc k allows tim e -cont rolled

execution of a program section.

While the delayed interrupt is used for fast events, time-controlled

interrupt s a re pa rticula rly suita ble for proce ssi ng eve nts which occu r

once or which occur at longe r inte rval s , e. g. hourly, dail y or monthly.

Onc e the poi nt i n ti me i s reac hed, the sy st e m program ca lls OB 9.

Triggering

A cloc k- co ntr oll ed int e rrup t (time d job ) is gene ra ted by ca ll ing the

spe cia l fu nc ti on org an iz a tion bl ock OB 151 (ref er to Se ct io n 6. 13).

Once the time set in OB 151 is reached (a time, a date) the timed job is

executed. The syst em program inter rupts the cu rrent program

exe cuti on and ca lls OB 9 (progr am exe cu tion leve l TIME D

INTE RRUPT S). Fol lowi ng this, prog ram exe c ution is resum e d at the

po int at which i t was inte rrupted .

To use t he clock-con trolled int er rupt, " proce s s interr upts via IB 0 =

of f" m ust be set in da ta bl oc k DX 0 .

User interf ace OB 9

For a clock- co ntr olle d inte rrup t, OB 9 is cal led as the user inte rf ace . In

OB 9, you write a STE P 5 program to be proc e ssed whe n the OB is

ca lled . If OB 9 is not loa de d, progr am exe cu tion is not interrup te d.

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Interruptions

Owing to the defa ult, the TI MED INT ERRUPT S la yer has the highe st

pr ior it y of th e basic laye rs (can be modifie d in DX 0).

In time-controlled program execution, th e execution of

clo ck -c ont rolled in te rru pts ha s the lowe st pr ior it y. Thi s ca n th er ef ore

be in te rru pted by the proc e s sing of a dela ye d inte rr upt or a cycli c

tim ed inte rrup t.

Special features

•• A clock- co ntrolle d interrup t is only processed in the RUN mode .

C lock- co ntr olle d inte rrup ts occu rri ng in the STOP mode , when

there is a power fai lur e or during ST ART -UP are discarded.

•• Once a clock-controlled interrupt has been generated (= OB 151

ca ll has been proce ssed ) it is retaine d in a WARM RE ST ART and

foll owi ng POWER DOWN/ POWE R UP; it is, howeve r, dele ted

d uri ng a COLD RE ST ART .

•• If yo u generate a new cl ock-co ntrolled inter ru pt, i.e. call

OB 151 w ith new t ime values, a previously s et clock- contro lled

interrupt is cancelled. A cl ock-co ntrol led inter ru pt cur rently

being processed is continued. This means that on ly one

clock-co ntrolled int errupt is valid at any one time.

•• If a tim e- controlle d inte rrup t occ urs wit hout the pre vi ous one

bei ng com pl ete ly proc esse d, the cloc k tim e-co ntr oll ed inte rrup t is

d isc arded. Cloc k-c ontr olle d int err upts are not che c ked fo r

collisions!

•• Not e the spec i al func tions OB 122 and OB 142 wi th whi ch you

ca n di sa bl e or de la y th e se rvi ci ng of c l oc k-c ont rolle d i nte rr upts.

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Cyclic timed interrupts

On the CPU 948, you c an proc e s s 9 di ffe re nt time -c on tro ll ed

programs, each being called at a different cyclic interval.

Triggering

The basic cl oc k pulse for time d inte rru pt proc essin g is set to 100 ms.

Using a spec ial para m ete r in dat a block DX 0, you c an ad just thi s in

ste ps of 10 ms (basic cloc k pul se = yy * 10 ms whe re : 01H ≤ yy ≤

FFH).

You can base the sett ing of the clock pulse on the shor test time

requ ire d by your a ppl ica tion fo r cy clic proce ssing .

Time interval

Cycl ic ti m ed int er rupts are processed at fixe d i nte rvals wi th 9 po s sibl e

inte rv al s (pe rio ds). Ea c h inte rva l is assigned to a spec ifi c orga ni za tion

bloc k. You can sele ct be t wee n two set s of i nt erva ls. You selec t the

sets of intervals using a special parameter in data block DX 0.

the followi ng ta ble i llustr at es the two set s of int erva ls wit h th e

assignment of the different intervals to organization blocks.

Inter val set 1

(default ) Interv al set 2 OB call ed

1x basic c lock pulse

2 x ba si c cl oc k p ulse

5 x ba si c cl oc k p ulse

10 x basic cloc k pu lse

20 x basic cloc k pu lse

50 x basic cloc k pu lse

100 x basic clock pulse

200 x basic clock pulse

500 x basic clock pulse

1 x basic clock pulse

2 x basic clock pulse

4 x basic clock pulse

8 x basic clock pulse

16 x basic clock pulse

32 x basic clock pulse

64 x basic clock pulse

1 28 x ba sic cl oc k pul s e

2 56 x ba sic cl oc k pul s e

OB 10

OB 11

OB 12

OB 13

OB 14

OB 15

OB 16

OB 17

OB 18

Note

The first TIME D INTE RR UPT OB c a ll followi ng th e sta rt-up

takes place within the time assigned to the OB.

If , for exam pl e , the int errupt time "50 0 s" is set for OB 18 (ba sic

clo ck pulse set ting in DX 0 = 1 s and t ime base = 1), the n the fi rst

OB 18 ca ll take s plac e aft er app roxi m ate ly 20 s following a

COL D RE ST ART . All fur the r ca ll s are the n at inte rv al s of 500 s.

Table 4-5 Sets of intervals and intervals of the TIM ED INTERRUPTS

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C79000-G8576-C848-04 4 - 37

User interfaces

OB 10 to OB 18

Whe n a time d inte rru pt occurs, the corre spon din g orga ni zat io n block

is call ed as the use r inte rfa ce at the next bloc k boun dary (or opera ti on

bo unda ry ).

For exa mple, you would progr am th e routine to be in se rt e d in c yc li c

pr ogra m exec ut ion ev er y 100 ms in OB 10 (d ef au lt ).

The timed interrupt is only processed if the assigne d organization

block is loaded. If none of the organi z at io n block s OB 10 t o OB 18

are loa ded, ther e i s no tim e-c ontrolle d program execution an d the

cyc li c progr am is not inte rrupted.

You ca n di sabl e the exec ut ion of tim ed int er rupt s b y set ting a

para me ter in data b lock DX 0, e.g. for testin g your progr am.

Interruptions

As defa ult, the TIMED INT E RRUPT S leve l has th e highe st prior it y of

the basic levels (can be modified in DX 0).

Owi ng to t he dist rib uti on of prio rit y withi n ti me-c on tro ll ed progr am

exe c ution, the foll owin g interrup ti ons in the proc e ssing of a cycl ic

tim ed inte rrup t are possibl e:

•• the proce ssi ng of a cy cl ic tim ed inter rupt can be interrupted by the

processing of a delayed interrupt

•• or ga nizati on bl oc ks wit h sh ort er tim e ba ses ha ve h igh er priority

and can in terrupt orga niz a tion bl oc ks wit h lon ge r time ba ses (e .g.

OB 12 can inte r r u pt OB 1 7).

Note

W i th t he thre e short est ti me base s (O B 10 to 12) multiple

p roc e ssing without inte rru pti on i s possi ble . If, for exa m ple , whil e

OB 10 is being proc e sse d, a furth er tim e d inte rru pt for OB 10

occ ur s, the curren tly act ive pro cessing o f OB 10 is first

com pl e te d. Followi ng th is, OB 1 0 is cal led im m edia t el y aga in. If,

however, there are more than thre e tim e d inter rupt s pe nding for

one of the time bases, a colli sion of tim ed interr upts error occurs.

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Collision of timed interrupts

In the CPU 948 the re are two diff eren t ty pe s of col li sions of timed

interrupts:

Type of erro r/c ause ISTACK ID Reacti on of the CPU

Tim ed in terru pt queu e over flo w:

- there are more than three

tim ed int er rupt s pen din g for on e of

th e thre e shorte st t im e base s (OB 10

to 12),

- one of the other OBs (OB 13 to 18)

is called again before it has been

com pletel y processed .

In the "IST ACK output " of

the programmer, the error ID

WE FES i s marke d in the

control bits.

The system progra m ca lls

OB 33 as the user interface.

If this is not loaded, the CPU

ch an ges to the stop mo de.

If the progra m ca n be int er rupt ed at

bl oc k bo u nda ries, the tim ed proc e ssing

is bl oc ked by t he r un ti m e of a bl oc k in

the cyc lic user progr am ; the run time o f

the bloc k is longe r tha n the basic cloc k

rate set in DX 0.

In the "IST ACK output " on

the programmer, the error ID

WE FEH i s marke d in the

control bits.

The system progra m ca lls

OB 33 as the user interface.

If this is not loaded, the

syste m progra m continues

progr am exe cutio n .

Error reaction

OB 33

In OB 33, you can p rogr am the requ ired re ac tion to the interrup t

col li sions liste d a bove . Wh en OB 33 is cal led, the syste m progr am

ent er s a collisio n ID in ACC U-1-L (bit no s. 0 to 9). You can see the

meaning of these bits (bit = ’1’) in the following table.

Bit number Mea ning

Que ue ove rf low i n time d inte rr upt period 1 (mo re tha n th re e time d inte rrup ts ar e

pe nd ing f or OB 10) .

Que ue ove rf low i n time d inte rr upt period 2 (mo re tha n th re e time d inte rrup ts ar e

pe nd ing f or OB 11) .

Que ue ove rf low i n time d inte rr upt period 3 (mo re tha n th re e time d inte rrup ts ar e

pe nd ing f or OB 12) .

Que ue overflow in time d inte rr upt p er iod 4 (OB 13 has been c a lled aga i n be fore the

pr ior ca ll was com plet el y exe cu te d).

Que ue overflow in time d inte rr upt p er iod 5 (OB 14 has been c a lled aga i n be fore the

pr ior ca ll was com plet el y exe cu te d).

Table 4-6 Timed interrupt collision IDs: meaning of the bits in ACCU-1-L

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C79000-G8576-C848-04 4 - 39

Bit number Mea ning

Que ue overflow in time d inte rr upt p er iod 6 (OB 15 has been c a lled aga i n be fore the

pr ior ca ll was com plet el y exe cu te d).

Que ue overflow in time d inte rr upt p er iod 7 (OB 16 has been c a lled aga i n be fore the

pr ior ca ll was com plet el y exe cu te d).

Que ue overflow in time d inte rr upt p er iod 8 (OB 17 has been c a lled aga i n be fore the

pr ior ca ll was com plet el y exe cu te d).

Que ue overflow in time d inte rr upt p er iod 9 (OB 18 has been c a lled aga i n be fore the

pr ior ca ll was com plet el y exe cu te d).

9 T im ed in te rru pt clo ck pulse maske d for too l ong.

Aft er proc e ssing OB 33 , the progr am is resum ed at the inte rrup te d

tim ed inte rrup t OB.

Note

If "interruptability at block boundaries" is set, following a collision

of timed interrupts, the SAC does not point to the block at whose

boundary the collision of timed interrupts took place (BE

statement) but rather to the block which called the block that

ca use d th e e rror (the re t urn address). You can set th e fol lo wing

parameters in data block DX 0 (refer to Chapter 7) for

time-controlled program execution:

- setting the basic clock rate

- setting the clock distributor,

- setting priorities relative to interrupt-driven program execution,

- enabling/disabling timed interrupt processing.

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4.4.4

Interrupt-Driven Program

Execution Depe nding on the s elec ted mode, two different types of interrupt-driven

program exe cution a re possible with the CPU 948:

•• PRO CESS INTERRUP TS

v ia inp ut byte IB 0 (ma x. 8 int errupts),

•• INTERRUPTS

v ia signa l lines of the S5 bus (max. 4 interru pts).

PROCESS INTERRUP TS via

input byte IB 0

To ser vic e proc e s s inte rr upts, th e defa ul t "p roc e ss in te rru pts vi a IB 0 =

on" must not be changed in the data block DX 0.

Program exe cution controlled by proce s s interrupt s m ean s t ha t a

sig nal cha nge in the inpu t byte IB 0 cause s the curre nt progr am

exe c uti on t o be int er rupt e d an d a spec ial pr ogra m secti on t o be

executed.

Note

If you enable "servicing process interrupts via IB 0" you cannot

use the delayed interrupt, the time-controlled interrupt and the

system interrupt.

Triggering

The signal state change of a bit in input byte IB 0 triggers the process

interrupt.

User interf aces

OB 2 to OB 9

If a proce ss int er rupt occu rs, on e of t he OBs list ed in th e foll owin g

table is called as the user interface.

Signal state chang e in IB 0 with bit OB called

I 0. 0

I 0. 1

I 0. 2

I 0. 3

I 0. 4

I 0. 5

I 0. 6

I 0. 7

OB 2

OB 3

OB 4

OB 5

OB 6

OB 7

OB 8

OB 9

Table 4-7 User interfaces for process interrupts

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C79000-G8576-C848-04 4 - 41

In the organizatio n blo cks OB 2 to OB 9, you pro gra m the part of your

ST EP 5 progr am to be exe cute d when on e of the proc e ss interr upt s

occ urs in dica ted by a bi t in inpu t byte IB 0.

If th e corresponding OB is n o t loa ded , program execution is not

inte rr upt ed . No inte rr upt -dri ve n pro gra m proc e ssi ng take s pla c e .

Note

If the I/O module no longer acknowledges when the CPU accesses

IB 0, the system program recognizes a timeout and calls the user

interface OB 28. If OB 28 is not loaded, the CPU changes to the

stop mode.

Priority of process interrupts

The default setting mea ns that PROCESS INT ER RUPT S have a lower

prior ity than the TIME D INT ERRUPT S leve l.

A pa ra m et e r in data bl oc k DX 0 al lo w s yo u to c ha nge th e de fa ul t s o

tha t the PROCESS INT E RRUPT S level has a higher prio rity than the

TIME D INT ERRUPT S leve l.

The fol lowi ng pr ior itie s are set for proc ess int e rrup t proce ssing :

I 0. 0

I 0. 1

I 0. 2

I 0. 3

I 0. 4

I 0. 5

I 0. 6

I 0. 7

OB 2

OB 3

OB 4 asc endi ng

OB 5 pri ori ty

OB 6

OB 7

OB 8

OB 9

Wit h proce ss int errupt s, no ne sted executi on is possible. When a

proc ess int errup t OB has bee n com plet ely pr ocessed and there are

fu rth er proc e ss inte rru pts pe ndi ng, th e system progra m ca lls the OB

with the next lower prio rity and pro cesses it .

The PROCESS INT ER RUPT S le vel is only exit ed whe n eac h signal

cha nge in inpu t byte IB 0 has bee n dealt with and the correspond ing

OB com pl ete ly proc esse d.

Note

Process interrupt-driven program execution cannot be interrupted

by further process interrupt-driven program execution.

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INTERRUPT S via signal

lines o f the S5 bu s

In terru pt- dri ve n prog ra m exe cuti on me an s that an S5 bus signa l from

an I/O module with interrupt capability (e.g. digital inputs, IPs, CPs)

ca uses th e CPU to interrup t pro gra m exec ut ion and t o proce ss a

spe cific se cti on of pr ogra m .

Note

If you want to use interrupt-driven program execution via S5 bus

signal lines on your CPU, you must set "process interrupts via IB 0

= off" in DX 0 and activate the individual interrupts by means of

DX 0 parameters. The interrupts must also be enabled with

jumpers on the module (refer to the Appendix and /2/). In contrast

to the CPU 946/947, you can set "interrupt at block boundaries" or

"interrupt at operation boundaries" as the mode in DX 0.

Jumper settings for system

interrupts

For inter rupt -dr ive n progra m execut io n with the CPU 948 , there are

fo ur syste m int errupts ava ila bl e to you:

- INT A/B/C /D (de pend en t on the slot in the CPU, see the System

Manual (Furt her Re adin g /2/)),

- INT E

- INT F

and

- INT G.

The inte rrup ts you wa nt to use m ust be ena bl ed with the suppl ie d

jumpers. T he jum pe r pl ug i s loc at e d on th e ba sic boa rd a bo ve the

receptacle for the memory card. The exact position can be seen in

Appendix 1.

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Triggering

The active state of an interrupt line on the S5 bus triggers the

inte rr upt . The int errup t sign al is leve l-tri gge re d (low le vel ). To

ac knowledge the interrupt, pl ea se ref er t o th e oper at ing inst ruction s

fo r the modul e which tr igg er s the int er rupt .

User interf aces

OB 2 to OB 5

If an i nte rrupt occu rs, one of t he OBs listed i n the follo wing table is

called as the user interface.

Interr upt tri gger ed by OB called

Int errupt si gnal X

(A, B, C or D, slot-de pe nd en t)

Int errupt si gnal E

Int errupt si gnal F

Int errupt si gnal G

OB 2

OB 3

OB 4

OB 5

If , for exam pl e , the int er rupt signa l ’F’ oc cu rs, t he system pro gra m

calls OB 4.

If the relevant OB is no t loa d ed, program execution is not interrupted.

The re is no in terru pt- dri ve n prog ra m exec uti on.

Priority of process interrupts

The default setting mea ns that PROCESS INT ER RUPT S have a lower

prior ity than the TIME D INT ERRUPT S leve l.

A pa ra m et e r in data bl oc k DX 0 al lo w s yo u to c ha nge th e de fa ul t s o

tha t the pr ocess int e rrup ts leve l has a highe r pr ior it y than the T IME D

INTE RRUPT S leve l.

Wit hin int e rrupt ser vic ing, the pri orities of the individual inter rupts

are speci fie d a s follows:

•• If the re are seve ra l interrupts pe ndi ng, the corr espo ndi ng

organization blocks are called according to the order of priority

you specify in DX 0 (single priority).

Yo u can spe c ify prio rit y le ve l s 1 to 5 for the four i nte rrupts.

Table 4-8 User interfaces for interrupts

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Whe n an inte rrup t OB has been com pl ete ly exe c uted and t here are

fu rth er int er rupt s pen din g, the syste m pr ogra m calls an d proc e s ses the

OB wi th the nex t lowest priority.

The INTER RUPT S proce ssing leve l is only exi ted whe n eve ry acti ve

sig nal sta te (l ow leve l) of an int er rupt line on the S5 bus has been

dea lt wit h and the corre spon din g OB ha s bee n com plet el y processed.

Note

Interrupt-driven program execution cannot be interrupted by the

same interrupt occurring again.

Disablin g interru pt-d riven

processing

An interrupt-driven program i s called at a bl ock or S TE P 5 operation

boundary in the c yclic program . This i nterrupt c an ca use proble ms when

a cyclic section of program must be processed within a certain time (e.g.

to achieve a certain reaction time) or when a serie s of operations must not

be interrupted (e.g. whe n re ading or w riting i nterdepende nt values).

If a program section must not be interrupted by i nter rupt-dr ive n

pr ocessin g, the fol lowi ng str at egie s ar e possi ble:

Interrupts at block boundaries

•• Program thi s pr ogram sec ti on so that it does not c ontain a bloc k

cha nge. Program se ctions that do not contain a block chang e ca n

the n not be int er rupt ed.

•• Use OB 122 wit h which y ou can disa ble th e proc essin g of proces s

int er rupt s for a specif ic progra m se ctio n. Rem e mbe r, howe ve r, t hat

the time d inte rr upts are al so disa bl ed ( re fer to Se c tion 6. 3).

•• Pro gra m t he STE P 5 ope ra tion ’ IA’ (di sab le proc e s s inte rr upt s) .

Wi th the ope ra tion ’RA’ (en ab le proc e ss interr upt s) you c an e nabl e

inter rupt proce s sing aga in.

B etwe en t hese t wo ope ra ti ons, no proce ss int er rupt -dr ive n

p rogram e xecu ti on is pe rmitte d. The program sect ion bet ween

the se t wo ope ra ti ons cannot be in te rrupted.

•• ’I A’ and ’RA’ a re onl y possibl e in funct ion blo ck s (exte nde d

o pe ra ti on set - re fe r to Se c ti on 3. 5. 4) a nd o n ly a ppl y to proc e ss

interrupts via IB 0.

Note

If a process interrupt is disabled using OB 22 or delayed using

OB 142, the RA operation is not effective.

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Interrupts at operation

boundaries

•• Pro gra m the secti on t ha t must not be int er rupt e d in an in terrupt OB

and assign the hig he st priori ty to it .

•• Use the special funct ion OB 122. With t his, you c a n disable

int er rupt s and tim e d in terrupts (refe r to Sec t ion 6.3 ).

•• Using the opera tion LIM and SIM (syst em opera tion s - refer to

Se cti on 3. 5.4) r ead or set the 32-bi t i nterr upt ma sk.

In terru pt servi ci ng ca n be disa bled c om plet ely or se para te ly for

individua l in terrupts in d ata bloc k DX 0. Th is is, howe ve r, only

possi ble follo wing a COLD RE STAR T (refer to Chapt er 7), since

DX 0 is only eva lua ted i n a C OLD REST ART .

Reaction time

The time re qui red to rea c t to a proc ess int errupt/int errup t request

corr espo nds to the proc e ssing ti me of a bloc k (for int er rupt s at bloc k

bo unda ri es) or a STE P 5 ope rati on (fo r inte rrup ts at opera ti on

bo unda rie s) . If, howev er , at the time the cyc lic pr ogra m is inte rrup te d

the re are higher pri ori ty t ime d in te rru pts pe ndi ng, th e inte rrupt-dri ve n

pr ogra m is only ex ecut e d whe n all the pen din g time d inte rr upt s have

bee n complet ely pro cessed .

The maximum reaction time between the occurrence and execution of

a proc e ss inte rr upt /ha rd war e inte rr upt i s inc re a sed i n thi s c ase by the

pr ocessing time of the higher prio rit y tim ed int er rupt s.

Program execution level s

and flag s

If you run your use r pro gra m n ot only cyc li cal ly but also t ime an d

inte rr upt -dri ve n, you ru n the risk o f overwri ti ng fl a gs.

Thi s is the ca se when the sam e flag areas are ac cessed at diff eren t

pr ogram proce ssing lev el s.

It is there fo re adv isable to assign flags to individ ual pro gram

pr oc essin g leve ls or a t the beg inn ing o f time or inte rr upt -dri ve n

pr ogra m ex ecut ion, to "sa ve " the signal state s o f multipl y assigned

fl ags in a data bloc k and t o writ e t he value s ba ck a t the en d of th e

interrupt servicing. The same applies for a warm restart.

To a voi d double use of fla gs, you can a lso u se the S flag s for mo st

appl ic a tions. Spe cia l "savin g" stra t eg ie s for flag s are then no long er

necessary, providing the S flags are assigned exclusively to individual

pr ogra m proce s sing l ev el s (the re a re en o ugh S fl ag s ava il a ble ).

RUN Mode

CPU 948 Programming Guide

4 - 46 C79000-G8576-C848-04

Cont ents of Ch apter 5

5.1 Frequent Error s in the User Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 4

5.2 Erro r Inform atio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 5

5.3 Procedure for Error Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 8

5.4 Control Bits and Interrupt Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 9

5.4.1 Control Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 10

5.4.2 ISTACK Content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 14

5.4. 3 Exa mple of Erro r Dia gno sis using the ISTAC K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 19

5.5 Er ror Ha ndl ing Using Organization B l o ck s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 20

5.6 Causes of E rr or and Reactions o f the C PU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 23

5.6.1 OB 19: Calling a Logic Block That Is Not Loaded (KB) . . . . . . . . . . . . . . . . . . . . . . . . 5 - 24

5.6.2 OB 19: Callin g a Data Bloc k That Is Not Load ed (KDB) . . . . . . . . . . . . . . . . . . . . . . . 5 - 24

5.6.3 OB 23/24 , OB 28/29: T i meout Err or (QVZ ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 25

5.6.4 OB 25: Addressi ng Error (ADF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 26

5.6. 5 OB 26: Cycl e T i me Exce ede d Error (ZYK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 2 7

5.6.6 OB 27: (Substitution Error SUF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 28

5.6. 7 OB 30: Parity Error and Timeout Error in the User Memory (PARE ). . . . . . . . . . . . . . 5 - 28

5.6.8 OB 32: Loa d and T ransf er Error (TRAF ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 29

5.6.9 OB 33: Collision of T i med Interrupt s Error (WEF ES/W EFEH) . . . . . . . . . . . . . . . . . . 5 - 3 0

5.6.10 OB 34: Error with G DB/GX DX (FEDB X ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 32

5.6.11 OB 35 : Communi c at io n Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 32

5.6. 12 OB 36: Error in Se lf- test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 33

5.7 Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 34

5.7.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 34

5.7.2 Description of the Test Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 35

5.7.3 Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 37

5.7.4 Err or Handl ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 3 8

Interrupt and

Error Diagnostics

CPU 948 Programm in g Gui de

C79000-G8576-C848-04 5 - 1

Contents

CPU 948 Programming Guide

5 - 2 C79000-G8576-C848-04

5Interrupt and

Error Diagnostics

Thi s chapt e r expla i ns how to avo id erro rs whe n plann ing a nd

programming your STEP 5 progra ms.

You will see wha t hel p you ca n get from t he system progr am for

dia gnosi ng and rea c ting to err ors and whi ch blocks yo u can use to

pr ogram re ac tions to e rrors.

At the end of the chapter, you will learn how to activate integrated

syste m func ti ons for a self- te st of the CPU 948.

CPU 948 Programming Guide

C79000-G8576-C848-04 5 - 3

5.1 Freq uent Erro rs in the User Program

The system prog ram ca n dete ct effe c ts of erro rs in the user progr am,

faul ty opera ti on of the CPU, or errors in the system prog ram

processing.

The fol lowi ng l ist desc ri be s errors t ha t occ ur m ost fr eq ue ntl y dur ing

the sta rt- up of the user progr am. You can avoid t hese e rro rs by doi ng

the followi ng whe n you writ e you STE P 5 program.

•• Whe n spe cifying byte addre s se s for I/ Os, ma ke sure that t he

cor respond ing mod ules a re plugge d into the ce ntral contr olle r or

the expa nsion unit.

•• Make sure that you have provide d corr ect p aram ete rs fo r all

operands.

•• Be careful when changing function blocks. Check to see that the

FB s/FXs are assi gne d the corr ect opera nds and that the actua l

o pera nds a re speci fied.

•• Ma ke sure that outp uts, fl ag s, t im ers, and cou nters a re not

p roc essed in seve ra l loca tion s in th e progra m with ope ra tions t ha t

counteract each other.

•• Make sure that timers are scanned only once per cycle (e.g., A T1).

•• Make sure that all da ta bloc ks ca lled i n the progra m exi st a nd are long

enough.

•• Check to see if all blocks called are actually in the memory.

•• If req uir ed by oth er bloc ks (e . g. sta nda rd func ti on bl oc ks),

sc rat ch pa d flags s ho uld be save d by inte rr upt -dri ve n a nd

tim e -cont rolled pr ogra m s an d loade d aga in when the se progr am

sec ti ons have bee n comp lete d.

Frequent Error s in the User Program

CPU 948 Programming Guide

5 - 4 C79000-G8576-C848-04

5.2 Erro r Informat ion

If an error occurs during system start-up or during cyclic processing of

your program, the sources of information described in this section can

help you to find the problem. This includes:

•• LEDs on the front panel of the CPU

•• interr upt sta ck ISTAC K and con trol bits

•• bloc k stack BST ACK

The fol lowi ng se c ti ons expl ai n th e ways of e va lu atin g thi s inf orm a tio n

and ho w to use the inform a ti on t o anal yz e p robl e ms.

LEDs on the front

panel of the CPU

If the CPU goes int o the STOP mode when you do not want it to,

che c k the LEDs on the fron t panel. They can i ndi cat e the ca use of the

problem.

LED display Me aning

ST OP LED li t cont inu ousl y T h e v a r i o us s t ates o f

the STOP LED indicate

specific causes of

interruptions a nd e rrors

(see section 4.1).

STOP LED flashes slowly

STOP LED flashes quickly

SYS FAULT LED lit

continuously

ADF LED lit continuousl y Addressin g error

QVZ LE D lit cont inu ousl y Time ou t error

ZYK LE D lit continuousl y Cycle time e xc eede d erro r

Error Inf ormat i o n

CPU 948 Programming Guide

C79000-G8576-C848-04 5 - 5

PG online function OUTPUT

ISTACK

You c an ge t infor ma t ion ab o ut the sta tus of the co ntr ol bits a nd t he

cont e nts of the inte rrup t stac k (ISTACK) by using die PG onl ine

func tion OUT PUT IST ACK.

Wh en the CP U goes into the S TOP mo de, the sys te m prog ram en ters all

the information it requires for a warm restart in the ISTACK. This

information i ncludes:

•• cont e nts of reg ist er s,

•• cont e nts of a cc um ula tors,

•• STEP address counter SAC

and

•• resul ts c ode s

De pending on wher e the int er rupt io n lea din g to the STOP oc c urre d,

the displ aye d inf orm a tion re fe rs to user b locks or blocks of the system

pr ogram (OB 0).

The se ent ri es are a val ua ble a id in error di a gnosi s.

Befo re the act ual IST ACK is outpu t on the progr am me r, the statu s of

the contro l bits is displaye d. The cont rol bit s mark the curre nt

op erat in g sta tu s a nd speci fic cha ra cte rist ic s of t he CPU an d the use r

pr ogra m an d provide addi ti ona l infor ma tion on the c ause of an erro r.

You can cal l the ISTAC K progr amm e r funct ion not on ly when the

CPU is in the STOP mo de , but also whe n it is in the REST ART or

RUN mode . Howe ver, in the REST ART and RUN mode s, you can

on ly di spl ay t he control bi ts (i . e., the first page of IST AC K

information).

The me aning of the control bit s and s tructure of the i nterrupt s ta ck are

described in detail in Section 5.4.

Onl ine fu n c ti o n OU TPU T

BSTACK

You can di spla y the con tent s of the block sta c k (BSTACK - se e

sec tion 3.2 "Ne sti ng bloc ks") usi ng the PG online fu ncti on OUTPUT

BSTACK.

The BSTACK co nta ins a list ing of all blocks (bl oc ks of the user

pr ogra m an d organi z atio n blo ck OB 0 of the system program) called

in sequence and not complet ely pro cesse d when the CPU went int o

the STOP m ode . Sinc e the BSTACK is fi ll ed from the bot to m, th e top

line of the BSTAC K displ ay conta i ns the bloc k that called the block

cont a ini ng an error .

Error Information

CPU 948 Programming Guide

5 - 6 C79000-G8576-C848-04

In the first line, the informa ti on s h own below is available:

Information Meaning

BLOCK N O T yp e a nd nu mbe r of th e block tha t called the

faulty block

BLOC K ADDR Absolute start addre ss of the calling block in

the progra m m e mory

RETURN ADDR Absolute address of t he first STEP 5 ope ra t ion

of th is bl oc k in the user me m ory.

REL ADDR Relative address (= difference "RETURN

ADDR - BLOCK ADDR") of the next

operation to b e proces s ed in th e calling b lock.

(Y ou can display relative add res s es on a

pro gr ammer in the mode " disable in pu t"/key

switch and with S5-DOS from Stage IV

upwards using the function key "addresses").

DB NO Number of the last data block opened in the

cal li ng block

DB ADDR Absolute start address in the progr am memor y

of the last data block opened in the calling

block (addre ss of data word DW 0)

Example

Eva luating the BSTACK funct ion:

BLOCK NO BLOCK ADDR RET URN ADDR RE L ADDR DB NO DB ADDR

PB 3

PB 2

PB 1

OB 1

OB 66 1)

OB 63

OB 62

OB 61

00090

00050

00040

00010

E2B10

E0FC0

E0490

E0010

E2C40

E12FA

E0CBE

E0273

00008

00001

00130

0033A

0082E

00263

1) T he blocks executed before OB 1 are internal blocks belonging to the syst em program (the BSTACK is structured

chronologically).

In the example, PB 3 called the faulty block at relative address

" 00 00 8 - 1 = 00007".

During the jump to this faulty block, no data block was open.

Error Inf ormat i o n

CPU 948 Programming Guide

C79000-G8576-C848-04 5 - 7

5.3 Proced ure for Error Analysis

If the CPU is in an abno rm al stop mod e, mak e use of all the

infor ma tion avai la ble to an alyz e the error, as foll ows:

Step Action

1 Che ck the sta tus of the S TOP and SYS F AUL T

LEDs and the error LE Ds on the front panel. These

indicate causes of c ertain errors and interruptions.

2 Using the PG online function OUTPUT ISTACK,

ana l yze the sta tus of t he co ntr ol bi ts a nd the

con tent of the IST ACK. This will provi de you

wi th furt he r inf orm a ti on a bout the lo cat ion of the

er r or a nd its ca us e .

3 Se l ec t the PG o nli ne funct ion OUTPUT BST ACK:

in the top line of the BSTACK di splay you will

f ind informat io n ab out the blo ck whic h c all ed the

bloc k ca usin g the error .

4 The system data RS 75 (refer to Section 8.3.4) also

con ta in s furt he r de tail ed er ror i nfor mat ion .

Procedure for Error Analysis

CPU 948 Programming Guide

5 - 8 C79000-G8576-C848-04

5.4 Control Bits and Interrupt Stack

You can use the online functions PLC INFO and OUTPUT ISTA CK to

ana ly ze the foll owin g: oper atin g sta tus, c hara c teri sti cs of the CPU,

cha rac teri sti cs of the user prog ram, possibl e cause s of errors a nd

interruptions.

Note

You ca n display the contro l bits in any mode . You can display

the ISTACK on ly i n the STOP mode.

•• The contr ol bi ts indica te the current and pre vious operat ing sta tus

and t he cause of the problem.

If several errors occurred, the control bits indicate all of them.

•• The ISTACK indicates the l oca tion of the interruption in que stion

(addresses) with the current c ondition c odes, the a cc umulator con-

tents, a nd the c ause of the problem.

If s eve ral inte rrup tions o ccu rred, a mu ltipl e level I STA CK is

constructed as follows (m axi mum 5 levels):

DEPTH (leve l) 01 = last c ause of interruption

DEPTH (leve l) 02 = next to la st c ause of interruption, etc.

When an IS TACK ove rflow oc curs, the CP U goe s into the STOP

mode immediately (HARD STOP!). You must then turn the power

off and on again and perform a cold restart.

The mea ni ngs of t he indi vi dua l abbrev iati ons i n the cont rol bit s a nd in

the ISTACK are descr ibed below.

Note

The text on the screen of your programmer depends on the PG

software you are using. It m ay therefore diffe r from the di splay

shown he re. The descri ption of the s c ree n inform ation i s neverthe less

relevant.

Control Bits and Interrupt Stack

CPU 948 Programming Guide

C79000-G8576-C848-04 5 - 9

5.4.1

Control Bits When you displ a y the ISTACK on yo ur progra m me r, the st atus of the

control bits is indica te d on the fir st pa ge (se e Fig. 5-1).

Note

The ISTACK screen form shown in Fig. 5-1 ref lec ts the PG

so ftwa re ST EP 5/ST, Versi on 6. 3 or STE P 5/MT Ver sion 6.0 with

the "Delta diske tt e CPU 948". In older v ersion s of the P G

so ftwa re , the abbreviati ons of t he control bits m ay be diffe re nt .

The mea ning of the contr ol bits, howe ver, is as descr ibe d in the

f oll ow i ng ta bl e s.

You can output the control bits in every mode. They mark the current or

previous sta tus of the CP U and provide inform at ion on s pec ific fe atures

of the CPU and your STEP 5 program.

The contr ol bits l ist ed unde r E RROR IDS ma rk e rror s tha t ca n occu r

in the RESTART (e. g., during an in itia l cold re sta rt) an d RUN (e.g .,

du rin g time-c on tro ll ed program pro ces si ng) m ode s. If se vera l error s

oc c ur, all errors are di splaye d in the cont rol bits.

CONTROL BITS

SYSTEM DESCRIPTION: E0VH GEP BATT EINP MEHRP SYNCR

TEST

STOP CAUSE:

START-UP IDs:

ERROR IDs:

PGSTP

UPROG

NEUDF

AWEG

QVZIN

FE2S

FDX0

BSTG BEFG MCG

HALT STP STS STOPS BEARBE

USYS UANL AFEL SYSFHL

WIEDF URLDF NEUZU WIEZU URLER

ANEG MSEG

PARIN BSTKF BSTEF UMCG MODUN

SRAMF UAFEHL KDB1 KDX0 FDB1

FMODE FEDBX QVZNIO WEFES DB0UN

Fig. 5-1 Examp le of the first screen form page "OUTPUT ISTACK" : contr ol bits

Control Bits and Interrupt Stack

CPU 948 Programming Guide

5 - 10 C79000-G8576-C848-04

The fol lowi ng t ab le s ex plai n the mea ni ng of the ind ivi dua l b its.

SYSTEM DESCRIPTION

Bit Meaning

E0 VH I nput byte IB 0 (proc e ss inte rrup ts) e xi sts, i.e. the digita l

inpu t modul e add re ssed with ’0’ wa s plug ge d in durin g

the last c ol d resta rt and the mo dul e acknowl e dge d.

GE P Program mab le controll er has a cen tral b ac k-up batte ry.

BATT Battery fai lure in the central controlle r (BAU)

EINP Single processor op eration

ME HRP Mu lt ipr ocessi ng op er atio n

SYNCR St art-up of the CPUs in multiproce ssing opera tion is

synchronized

TEST Test operation

BST G DX - 0 setti ng "i nte rr upt s at b lock bo unda ri e s "

BEFG DX-0 setting "interrupts at operation boundaries

MC G Memory card inse rte d

STOP CAUSE (see RS 7)

Bit Meaning

PGSTP STOP m ode set from pro gra m me r

HALT Mu ltiproc esso r STOP mode:

a) Selec tor swit ch on the coordina tor (COR ) is

in the STOP position

b) Stop status caused by command STOP operation

fr om syste m progr am whe n the corr esp ondi ng

erro r OB is not loade d a nd an error occur s

STS ST OP m ode caused by ST EP 5 ope ra ti on ’ST S’ (a fter

executing an operation)

ST OP S STOP m ode cause d by set ti ng th e mode se lec tor t o the

STOP posi ti on

BEARBE STOP mode after the PROGRAM TEST END

p rogr amm e r funct ion

Table 5-1 Meaning of the control bits SYSTEM DESCRIPTI ON

Table 5-2 Meaning of the control bits STOP CAUSE

Control Bits and Interrupt Stack

CPU 948 Programming Guide

C79000-G8576-C848-04 5 - 11

STOP CAUSE (see RS 7)

Bit Meaning

Table 5-2 continued:

UPR O G STOP mode cause d by user progr am

USYS STOP mode caused by system program

(war m rest ar t possible)

UANL STOP m ode caused by illega l start-up type

AFEL STOP m ode cause d by err ors in the start -up bl oc k

SYSFHL STOP mode cause d by system error (may be caused by

user error, e.g. overwriting system RAM with a block

tra nsfe r or simil ar (whe n a syste m erro r is marked, a

four-digit hexadecimal number/error code appears at the

bottom edge of the screen - refer to RS 75 in Chapter 8).

START-UP IDs (see RS 8)

Bit Meaning

NEUDEF COLD RE ST ART was exe cute d as last st ar t-u p type.

WIEDF WARM REST ART was exe c uted as last st ar t-u p type.

URLDF Overall reset was executed or is active.

NE UZ U COLD RE ST ART perm itte d as nex t start -up type .

WIEZU W ARM REST ART pe rmit ted as next start -up type .

URLER Ov er al l re set re quired.

AWE G AUTOMAT IC WARM REST ART is prese t.

ANEG AUTOMAT IC COLD REST ART is prese t.

MSEG Manual start is preset.

Table 5-3 Meaning of the control bits START-UP IDS

Control Bits and Interrupt Stack

CPU 948 Programming Guide

5 - 12 C79000-G8576-C848-04

ERROR IDs

Bit Meaning

QVZI N Ti meou t error in initializ atio n

PARIN Parity error in init ialization

BSTKF Wro ng block ID

BSTEF Wro ng block deli mi te r

UMC G Illeg al mem ory ca rd inse rted

MODUN Content of the mem ory c ard too large for t he av aila bl e

internal user memory

FE2S Error on the second interface

SRAMF System RAM error

UAFEHL Error in the interrup t condi tion code word (UAW)

KDB1 No DB 1 in multiprocessing operation

KDX0 No DX 0 in multiprocessi ng oper ation

FDB1 Error in DB 1

FDX0 Error in DX 0

FMODE No IB 0 proce ss inte rrup ts allowe d in multiproc e ssor

mode

FE DB X E rr or in the STE P 5 ope ra t ion s G DB, GX D X

QVZNIO QVZ test faulty

WEFE S Collision of softwa re -d riv en time d in te rru pts: queue

overflow

DB0UN DB 0 has been changed since the last COLD

RESTART . Th er efore, no WARM REST ART possible.

Table 5-4 Meanin g of the control bits ERROR IDS

Control Bits and Interrupt Stack

CPU 948 Programming Guide

C79000-G8576-C848-04 5 - 13

5.4.2

ISTACK Conten t If the CPU is in the stop sta te, you c an displ a y the cont en t of the

ISTACK on the scr een after the contr ol bit displ ay by pressin g the

ent er key. When the CPU goes into the STOP mode , the system

pr ogra m en ters a ll the inform a ti on it need s in this IST ACK for a warm

restart.

You ca n use the entr ie s in this IST ACK t o see wha t kind of e rr or

occ urr ed a nd wher e it occ urre d in the pro gra m .

If the stop state was c ause d by a sing le er ror, only one level of the

ISTACK i nfor ma tion is displa yed. With several errors, the

cor respo nding nu m ber of ISTACK l evel s are outpu t (DEPT H 01,

DE PTH 02, et c. ). At all le vels, only one error is ma rked as th e

CAUSE OF INTERRUPT.

If se vera l errors ha ve oc cu rre d DEPTH 01 ma rks t he err or de te cte d

immediately before the change to the stop state.

Fi g 5-2 is an exa m ple of a PG displ a y of the IST ACK cont e nt.

ISTACK

Depth 01

OP-REG:

BLK-STP:

PAGE

NUMBER:

BRACKETS:

ACCU1: 0000 31BA

1205

EDEFF

00FD

KE1 000 ACCU2:

SAC (new):

PB-NO.:

REL-SAC:

SAC (old):

KE2 000 KE3 000

0000 0005

000B3

00013

000B2

ACCU3:

DB-ADD:

DB-NO.:

DBL-REG:

ICMK:

KE4 000 KE5 000 KE6 000

0004 0005

00000

09DF3FBF

0000

ACCU4:

BA-ADD:

OB-NO.:

BR-REG:

ICRW:

0004 0005

00108

00000

FFFFFFFF

CONDITION CODE:

CAUSE OF INTERR.: KB

NAU

STS

KDB

QVZ

WEFEH

TRAF

OVFL

ADF

PEU

SUF

PARE

HALT

OVFLS

STUEB

ZYK

ODER

STUEU

STOP

ERAB

RLO

CC0

STATUS

CC1

Fig. 5-2 Examp le of a screen page "OUTPUT ISTACK"

Control Bits and Interrupt Stack

CPU 948 Programming Guide

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Exp lan ation of the IST A CK

screen

DEPTH

In form ati on lev el of the ISTACK whe n m ore than one err or ha s

occurred:

DEPTH 01 = last ca use of stop to occ ur

DEPTH 02 = next to last ca use of stop to oc cur

......

DEPTH05 = .... .. (maxi mu m dept h)

Information about the error

The fol lowi ng tab le co ntai ns inf orm a tion a bout the IST ACK IDs wit h

whi ch the stat eme nt in the use r progra m can be found whi ch c ause d

the CPU to change to the STOP mode.

Informati on about the error

ISTACK I D Meaning

OP-REG Operation register:

Cont a ins ma ch ine c ode (fi rst word of the

inst ruc tion p roc essed last in an i nterr upted

progra m proc essi ng lev el.

SAC (ne w) ST EP addr ess c oun ter (ne w):

Cont ains t he absolute a ddress of the next

ope ra ti on i n the program memory to be

proc ess e d. When a warm rest ar t occ urs,

the CPU cont inu es t he progr am with this

ope ra ti on.

DB-ADD Absolut e start addre ss (DW 0) in the

program memory of the data block currently

opened (= 0000 if no data block was

opened)

BA-ADD Absolut e address i n the program me mory

for the opera tion to be proc essed next in the

block where the last block call was made

BLK-ST P Bloc k stack (BST ACK) po inter:

Cont ains t he 20-bi t offse t addre s s of t he

last BSTACK e nt ry (always Exxxx).

PB-NO

(de pe nd ing on typ e

PB, OB . ..)

Block type and number of the most

recently proce ssed block

Table 5-5 Mean ing of the ISTACK I Ds for errors

Control Bits and Interrupt Stack

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C79000-G8576-C848-04 5 - 15

Informati on about the error

ISTACK I D Meaning

Table 5-5 continued

DB-NO. Number of the data block currently opened

OB-NO.

(de pe nd ing on typ e

OB, PB . ..)

Block type and number of the last calling

block

REL- SA C Rela t ive ST EP addr ess c oun te r:

co nta i ns the relative address (related to

the block start add ress) of the next

operation to be processed in the

la st bloc k pr o cessed.

DBL-REG Length of the data block currently

opened

BS-REG Content of the base address register prior to

the t ra nsit io n to the stop m ode

PAGE

NUMBER Num be r of the cur re nt dual-po rt RAM page

sele cte d (dual-po rt RAM ac cess re fers to thi s

dua l-por t RAM page , you wil l find

in form a tion a bou t page acc e ss in Cha pt e r 9)

SAC (ol d) STEP a ddr ess coun te r (old):

co nta i ns the absolute address of th e last

ope rati on proc esse d i n the progr am

memory o f an int er rupt e d progra m lev el;

if an error occ ur s, SAC (old) indi cat es the

operation which caused the error.

I CMK Int errup t c ondi tion c ode masking word:

ICMK cont ai ns all the cause s of inte rr upt s

whic h have occ urre d a nd no t yet bee n

comple tel y proc e ss e d.

I CRW Int errup t condi ti on code re se t word

BRACKET S Num be r of bracket le vels:

"KEx ab c" where

x = 1 to 7 level s,

a = ’OR’ (ref er to bit codes),

b =’ RLO’ ( result of logic ope ra tion,

re fe r to bit codes),

c = 1: ’A ( ’,

c = 0: ’O ( ’.

ACCU1 to

ACCU4 Contents of the calculation registers

(ac cu mula tors) a t the time of the interru pti on

Control Bits and Interrupt Stack

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CONDITION CODE

see S ection 3.5

CAUSE OF INTERR.

The following abbreviations (IS TACK ID s) indicate the most important

causes of interruptions.

CAUSE OF INTERR.

ISTACK

ID Me an ing (cal led er ror OB )

KB Ca ll ed block not lo aded (OB 19)

KDB Opened da ta blo ck not loa de d (OB 19)

TR AF Load or transf er err or (OB 32 )

SUF Substit ution erro r (OB 27) :

Pr oc esse d STE P 5 opera ti on can not be

substituted

STUEB Block stack overflow:

Ne st ing dep th too gre a t; re qui re d act ion :

COLD RE ST ART

ST UE U Inter rupt sta ck overfl ow:

Ne st ing dep th too gre a t; re qui re d act ion :

POW E R DOW N, POW E R UP,

the n COLD RESTAR T

NAU Power failure in the ce ntral control ler

QVZ T imeout (OB 23/OB 24/OB 28/OB 29)

AD F Addre ss i ng error f or di gita l inputs and o utp uts wi th

proce ss im age (OB 25)

PARE Parit y error (OB 30)

ZYK Cyc le moni toring t im e exceede d (OB 26)

STOP STOP mode cau sed by setting the mod e selec tor to the

STOP po sit ion

STS STOP m ode cau sed by STEP 5 opera tion ’STS’ (after

executing an operation)

Table 5-6 ISTACK I Ds CAUSE OF INTERRUPTION

Control Bits and Interrupt Stack

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C79000-G8576-C848-04 5 - 17

CAUSE OF INTERR.

ISTACK

ID Me an ing (cal led er ror OB )

Table 5-6 continued:

WE FE H Colli sion of time d interr upts ca use d by the har dwa re

cloc k (OB 33):

timed interrupt clock was masked (ignored)

f or to o lon g

PE U I/Os no t rea dy = power fail ure in expansion unit:

After a statically pending PEU signal is removed

(ex pa nsio n uni t is switc he d on), the syste m

progr am always c alls OB 22 (AUTOMAT IC

WARM RE ST ART ).

HALT Mult ip roc e ssor ST OP mod e:

a) sel ect or switc h on the coor din ator (C OR) is

in the STOP posi ti on

b) ano ther CPU ent ered the STOP m ode in

multiprocessing.

Control Bits and Interrupt Stack

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5.4.3

Example of Error Diag n osis

using the ISTACK

Fig. 5-3 illustr ates the str ucture o f th e ISTACK in conjunction with the

interruptions th at h ave occu rred.

- Th e pr ogram execut ion level CYCLE (OB 1) is interrupted by an interrupt.

- Following thi s, t he p rogr am proce ssin g level interrupt is act ivat ed a nd

OB 3 ca lled .

- The occurrenc e of a t imed interru pt m eans that the INTERRUPT leve l is

exited and th e TI MED INTE RRUPT le vel activated and OB 13 pr oces sed.

- An incorrect addressing operation leads to the activaton of the ADF

level where OB 25 is proces sed. In the error handli ng progr am, the user

has programme d a stop ope ration ( STS) the CPU aborts program exec utio n.

B efore the final tr ansition to the st op mode, a total of four differe nt

program execution levels were interrupted. If you now display the ISTACK on

the PG, you will obtain a four-level ISTACK, at the top the ISTACK with

depth 01, with the ID of the last in te rrupted prog ram execution leve l (=

ADF). You can page down through the ISTACK until you reach depth 04,

r epresenting th e CYCLE program ex ecution level, which w as i nter rupt ed first.

STS

ADF

STS

Depth 04

Program execution levels ISTACK

Depth 03

Depth 02

Depth 01

CYCLE

TIMED INTERRUPTS

INTERRUPT

ADF

OB 1

OB 3

OB 13

OB 25

Fig. 5-3 Example of evaluating the ISTACK

Control Bits and Interrupt Stack

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5.5 E rror Hand lin g Usin g Org an izat ion Blocks

When the system progra m detects an error, i t cal ls the a ppropria te

organization block to handle it. You can determine further operation of

the CPU by programming the a ppropria te organi za tion block.

Therefore, the CP U c an do one of the foll owing:

•• continue normal program processing

•• go into the STOP mode

and/or

•• pr ocess a spe cia l "error han dling pr ogra m "

For the fol lowi ng c a use s of error, OBs are a vai la bl e:

Cause of e r ro r Or gani zation

block called Reac ti on of CP U

if O B is not

programmed

Cal l of a bloc k that is not loa de d (KB) OB 19 non e

At tem pt to ope n a data blo ck DB/DX th at is not loade d

(KDB) OB 19 ST O P

Ti meou t in the use r prog ram du rin g acce ss to I/ O periph er al s

(QVZ) OB 23 none

Ti me ou t during upda te of t he proc e ss im ag e tab le an d duri ng

int er proc essor c om m uni cat ion fla g tran sfe r (QVZ) OB 24 none

Ad dressin g error (ADF) OB 25 ST OP 1)

Cycle time exceeded (ZYK) OB 26 STOP

Su bsti tu ti on error ( SUF) OB 27 STOP

Ti me out by re a di ng in put byte IB 0

( proc ess int e rrup ts – QVZ ) OB 28 STO P

Ti me ou t during acc ess t o the di stri but e d I/O pe ripherals (ex te nde d

address area — QVZ) OB 29 none

Pari ty err or and timeo ut in the user mem or y (PARE) OB 30 STO P

Table 5-7 The organization blocks called in case of errors

Error Handling Using Organization Blocks

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5 - 20 C79000-G8576-C848-04

Cause of e r ro r Or gani zation

block called Reac ti on of CP U

if O B is not

programmed

Ta ble 5- 7 co ntinued:

Loa d and tra nsfe r error (TRA F) OB 32 STO P

C ollisi on of tim e d inte rru pts:

a) queue over flow (contr ol bit WEFES)

b) tim ed inte rrup t clock wa s maske d (igno re d) for too long

(WEFEH)

OB 33 STOP

none

Err or during STE P 5 opera tion "G DB/GX DX"

(co ntrol bit FEDBX) OB 34 STO P

Error in self-test (refer to Section 5.7) OB 36 none

1) The CPU chan ges to the STOP mode only if the addressing error is not disabled by the STEP 5 operation "IAE".

Examples of reactions to

organization blocks whic h are

not load ed

a) No react io n; cyc li c program pro ce ssing is not in terrupted.

If a timeo ut erro r occu rs and neit her OB 23 nor OB 25 is load ed, cyc lic progr am processi ng is not

inte rr upt ed ac c ordi ng to the table a bo ve . The CPU doe s not reac t.

If you wa nt the CPU to go into the STOP mode when a tim eout error oc c urs, you must ente r a stop

st ate ment (ST P for ST OP at cyc l e end) in th e appr opri a te organi z at io n block (e.g. OB 23 with QVZ ) a nd

terminate it with the block end statement ’BE’.

Example of OB 23: : QVZ has occurred

:ST P Cyc lic proc essi ng i s abo rte d

:BE CPU changes to the stop mode

b) Rea ction : the CPU change s to the STOP mode .

The CPU chan ges to the STOP mo de im medi ate ly when a corre spo ndi ng error (e.g. cycle or

loa d/t ra nsfe r erro r) oc c urs - if you di d not loa d the appropria te orga ni zat io n blo cks.

If , as an exc e pt ion , you do not wan t one of the se erro rs to inte rr upt cyc l ic prog ram pr ocessing

(e. g. whil e putt ing the syst em in to oper atio n), a bloc k end sta tem e nt in the appr opri a te

or ga nizati on bl oc k is s uffici en t.

Example of OB 25: : ADF occurr ed

:BE Cycli c proc essi ng is con ti nue d, no CPU STOP

Error Handling Using Organization Block s

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Interruptions during

processing of error

organization blocks

After the syst em program ca lls the a ppropriat e orga ni za t ion bloc k, the

use r progra m in tha t bloc k is pro ces se d.

If ano the r erro r oc cu rs whil e tha t orga niz ati on bl ock is be i ng

pr ocesse d, the pr ogra m is interrupted a t the nex t opera t ion b ound ary

and the app ropr ia te organ iza tion bl ock is calle d, just a s in cyc lic

program processin g.

The system prog ram pr ocesses organiz ati on bloc ks in the orde r in

which they are called.

Note

You can nest a maximum of five error organization blocks. With

mor e than 5 errors, the CPU goes into the HARD STOP mode

b eca use of ISTACK ove rflow.

Error Handling Using Organization Blocks

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5.6 Cau ses of Error and Reactions of the CPU

Spe c ific even ts can int errupt cyclic , time -con trolled, or inter rupt-

drive n program proce ssin g at opera tion bo unda rie s when the CPU is

in the RUN mode.

During initialization and also in the RESTART mode, interruptions

ca n stop the sta rt -up pr ogra m and put the CPU into th e STOP mo de .

The CPU then cha nge s to the stop mod e and ca lls the organi z atio n

bloc k for thi s parti cu lar error . Inte rru ptions during the start -up

pr ogra m ar e hand led like tho se in the RUN mode .

The reaction depends on the cause of the interruption:

•• immediate change to the STOP mode, without calling the error OB

(e.g. NAU → har d stop, STUE U → hard stop, PEU → soft sto p),

•• befo re cha ng ing t o the STOP mo de , the syste m progr am cal ls an

err or OB whi ch you c an progr am and (de pending on the c ause of

the error) avo id a chan ge to the stop mode (e .g. QVZ/I B 0 →

OB 28, ADF → OB 25) .

If an e rro r oc cu rs, note th e ent rie s in the co ntr ol bi ts un der "Er ror IDs"

and the ent ries in the ISTACK und er CAUSE OF INTE RR.

The fol lowi ng se c tions e xpl ain possi bl e ca use s of error i n gre a ter

detail.

Causes of Error and Reactions of the CPU

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5.6.1

OB 19: Calling a Logic

Blo ck That Is Not Loaded

(KB)

If your pr ogra m jumps t o a bloc k that does not e xist, th e syste m

pr ogra m dete c ts a n er ror. This a ppl ie s to a ll lo gic bl oc ks an d al so for

condit ional and uncond it ional ca l ls.

When th e system program d etects th e call of a l og ic block that is

not lo aded , i t ca l ls OB 19, if this is loaded. In OB 19, you can

specif y how the CPU should proceed.

If OB 19 doe s not exi st, the syst em pr ogra m conti nue s e xecu ti ng the

inte rr upt ed STEP 5 prog ra m at the n ext ope ra tion.

5.6.2

OB 19: Calling a Data Bloc k

That Is Not Load ed (KDB) If you call a data block or an extended data block in your program that

do es no t exist in the me m ory or is ma rk ed as inva li d, the CPU de tec ts

an e rror and the system progra m c a ll s OB 19, if this is load ed. If

OB 19 is not loa ded, the CPU change s to the STOP mode . A zero is

ent ered in th e DBA and DBL regi sters.

Note

OB 19 is called both when a logic or data block is not loaded.

You can read syst em data regi ster RS 75 to determ in e (via the

ST EP 5 prog ra m) which ty pe of er ror oc curr ed . The conte nt s of

R S 75 are as fol lows:

- for a KB error: 0101H,

- for a KDB error: 0904H.

Causes of Error and Reactions of the CPU

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5.6.3

OB 23/24, OB 28/29:

Timeout Error (QVZ) A tim eo ut error oc curs whe n an addre ssab le mem ory are a doe s not

respo nd to write or read accesse s with the ready signa l ("RDY")

wi thin a speci fic tim e aft er b eing a ddr esse d. This t ime is mo nit ore d by

the hardware. A defective module or the removal of a module during

op er atio n of th e pr ogra m mab le controlle r can ca use a tim eo ut erro r.

The fol lowi ng tim e out err ors in te rru pt the u ser progr am , jump to

syst em pr ogra m er ror hand li ng, and cal l the appr opri a te blo cks if they

are loaded:

OB 23

QVZ with direct I/O access:

Cause of error Reacti on to error

Ti m eo ut e r ror in the us er

prog ram du rin g direc t ac cess vi a

the S5 bus to an IP, COR , or

to a perip he ra l modul e (e.g. ,

wit h load and t ra nsfe r ope rat ion s

"L/ T P. .. " or "L/ T Q.. . ").

If OB 23 is not loade d, th e

syst em pr ogra m co ntinue s th e

proc essi ng of the user prog ram.

OB 24

Cause of error Reacti on to error

Tim e out err or during u pda te of

the pr oc ess ima ge input /output

tabl e s or during t ra nsfe r of

interpr oc esso r commun ica tion

flags.

I f OB 24 is not loaded, the

system program continues

proc e ssing of the user pro gram .

Extension of the execution

time

Wit h c alli ng OB 23 or OB 24 a time out er ror i nc re ase s th e e xe cution

tim e of the ST EP 5 op er atio n whic h ca use d the tim eo ut whe n the

pr ogram is re sumed:

ext ension = "a cknowl edgeme nt mo nitoring tim e + tim e of error

hand ling in the system progra m + proce ssin g time if err or OB is

called".

Causes of Error and Reactions of the CPU

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OB 28

Cause of error Reacti on to error

Ti m eo ut e rr o r at input byte IB 0

(proce ss inte rru pts) If OB 28 is not loa de d, th e CPU

cha nges to the STOP mode .

OB 29

Cause of error Reacti on to error

Tim eout error of the di stribute d

periphe ra ls in the fol lowi ng

ad dre ss ar eas:

- F 0000H to F EFFFH

- F F200H to F FFFFH

If OB 29 is not loade d, th e

syste m progra m conti nue s

proc essi ng of the user prog ram.

Error address

Whe n a time out error oc c urs, you can re ad the error add re ss in th e

syste m data area (see Chapte r 8):

RS Contents Address

6 8 QVZ error a ddr ess hi gh E F04 4H

69 QVZ e rror addre ss l ow E F04 5 H

5.6.4

OB 25: Addressi ng

Error (ADF) An addr essi ng erro r occu rs whe n a STEP 5 opera ti on refere nc e s a

pr ocess i ma ge in put or out put to whi ch no I/O m odu le was a ssig ned at

the t ime of th e last COL D REST ART (the mod ule is not pl ugge d i n, it

is def ect ive, or it is not defin ed i n data bloc k DB 1 of the CPU.

The STE P 5 opera t ion at whic h the addr essi ng e rro r occu rre d is

pr ocesse d c ompl et e ly: For bit ope rat ion s, t he bit in the proc ess i mage

is sca nne d and c om bi ned log ic all y or set/ re set . Loa d and tra nsfe r

oper at ions ar e also exe c uted . Conti nue d proc essi ng ca n, howe ve r,

resul t in incor re ct or unwant ed re act ion s.

Causes of Error and Reactions of the CPU

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Whe n an addre ssin g er ror occ urs, the syst em progra m inte rrup ts

fu rth er proc e ssing o f the user pro gra m and call s orga ni zat io n blo ck

OB 25. Aft er runni ng the program cont ai ned in OB 25, the progra m i s

resumed at the next operation.

If OB 25 is not loade d, th e CPU change s to the STOP mode with an

addr essi ng erro r.

The STE P 5 IAE opera ti on di sa ble s addre s si ng e rror m on itoring for

indi vid ua l pro gra m par ts or for the e ntire prog ram. You ca n enab le it

aga in using the RAE ope ra tion (se e Sec tion 3.5. 4 and List of

Operations).

5.6.5

OB 26: Cycle Tim e

Exceeded Erro r (ZYK) The cycle time is the time between the start of one OB 1 and the next.

It inc ludes the entire duration of cy cl ic program p roce ssing including

inte rr upt s, inte rr upt serv ic in g and syste m prog ra m acti vitie s. The cyc le

monitorin g time se t on the CPU ca n, for e xa m ple , be e xc e ede d by

inc orre c t progra m m ing (prog ra m loop) .

Note

Hardware faults a s the cause of cycle ti m e e rrors are extremely

rare . Norma ll y, the error i s in th e user pr ogra m or the pr ogra m s

and cycle monitoring time are incompatible.

Whe n a cyc l e time exc e ede d error (Z YK) oc curs, th e syste m progra m

inte rr upt s the use r progra m and ca lls OB 26 if this is loaded. The

monitoring time is then restarted (triggered). If the monitoring time is

exc eed ed aga in, bef ore OB 26 is com plet ed, the CPU change s to the

st op m ode .

If OB 26 is not loade d, th e CPU change s to the STOP mode .

The cycle monitoring time is variable (10 to 2550 msec ) and is

retriggerable (see above ).

You can specify the cycle monitoring time individually by making an

entry in DX 0 (refer to Chapter 7) or by programming OB 31. The default

monitoring time is 200 ms.

In the cyclic program, the cycle monitoring time can be retriggered by

ca ll ing the spe cia l funct io n OB 222.

Causes of Error and Reactions of the CPU

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C79000-G8576-C848-04 5 - 27

5.6.6

OB 27: (Substit ut ion

Error SUF) If an op er atio n wit h a form al ope rand i s to be carr ied out in a func tion

bloc k, the CPU replac es (subst itut es) thi s forma l operand with the

actual operand in the block when the block is called during user

program processin g.

If the CPU detec ts an illega l substitutio n, it interr upts the use r

pr ogram and ca l ls OB 27, if this is loa de d. If OB 27 is not loa de d, the

CPU cha nges to the STOP mode .

Apa rt from an ille ga l sub sti tutio n, SUF is al so ind ic ate d in the

foll owin g sit uati ons:

•• illegal operation code,

•• special situation:

you can not ope n data block s DB 0 and DB 1. The CPU handl es the

o pera ti ons "C DB 0" and "C DB 1" li ke subst ituti on errors. A ze ro

is en tere d in the DBA and DBL reg ist er s.

5.6.7

OB 30: Parity Error and

Timeout Error in the User

Memory (PARE)

The user mem ory is prot e cte d by a par ity bit. The syst em progra m

che c ks whe the r the par ity bit is correct each time the use r mem or y is

ac cesse d. If the pari ty bit is incor re ctly set , a parity error is indic ate d.

The system program c a ll s OB 30. If OB 30 is not loaded, the CPU

cha nges to the STOP mode .

The sam e react ion take s pla c e if a time out er r or oc curs in the use r

memory.

PARE accessing th e

operating system RAM

If a parity erro r occu rs whe n acc e ssing the opera ting syst em RAM, th e

syst em pr ogra m doe s not c all OB 30, but change s to a HARD STOP.

Causes of Error and Reactions of the CPU

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Error address

If a pari ty erro r or tim eo ut occ urs, th e addr ess t hat cau sed the er ror c an

be rea d out of the system data are a (refer to Chapt er 8):

RS Contents Address

70 PARE error address high E F046H

71 PARE error addre ss lo w E F047H

5.6.8

OB 32: Load and Tran sfer

Error (TRAF) A lo ad and tra nsfe r error is indica ted in the fol lo wing si tuat ions:

•• Whe n acce ssin g data in dat a blocks or ext ende d data block s, the

CPU compares the length of the opened block to the parameter in

the load or tra nsfe r op erat ion.

If the specified parameter exceeds the actual data block length, the

C PU d oe s not exe c ute the l oa d or tr an sfe r ope ra ti on. T his pr ev en ts

data in the memory from being overwritten by mistake during

tra nsfe r op erat io ns. Wi th loa d errors, the contents of the

accumulator are retained.

•• A load or transf er err or is also dete ct ed if a single bit within a

n on-exi stent data word i s t o be sca nned or chan ged.

•• If no da ta blo ck has ye t bee n open ed (with "C DBn" or

"C X DXn") pri or to ac cess t o a data wor d, thi s also ca use s a

lo ad/tr an s fe r error .

•• Ac cessi ng t he me m ory usi ng i nc orre ct absol ut e addr esse s vi a the

B R regist e r or inco rre c t are a boundari es with the "TNW ", "TXW "

and "TXB" op er atio ns can ca use a load or transf er err or.

Whe n the syste m progra m detec ts a loa d or transfe r e rror , it call s

OB 32, if thi s is loa ded. The ope ra tion that cause d t he load or tra nsfe r

erro r is not proc e sse d.

If OB 32 is not loade d, th e CPU change s to the STOP mode .

Causes of Error and Reactions of the CPU

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C79000-G8576-C848-04 5 - 29

5.6.9

OB 33: Collision of Timed

Interrupts Error

(WEFES/WEFEH)

Tim e-c ont rol le d program proce ssin g (tim ed inter rupt s) is ha nd led by

organization blocks OB 6, OB 9 and OB 10 to OB 18.

The fol lowi ng type s of tim ed err ors c an occ ur on the CPU 948:

Queue overfl ow

Cause:

Que ue ove rf low se rvi c ing time d in terru pts:

•• the re are more tha n t hre e tim e d in terru pts pending for one of the

thre e shorte st peri ods (OBs 10 to 12)

•• on e of the oth er OBs (OBs 13 to 18) ha s be en call e d before the

first cal l was com pl etely processed.

Reaction:

The system program c a ll s OB 33 as the user interface, if this is loaded.

You can program the reaction to this state in this OB.

If OB 33 is not loade d, th e CPU change s to the STOP mode .

PG displa y in "OUTP UT ISTACK ":

The bit WEFES is marked in the control bits.

Masking the timed interrupt

clock

Cause:

The inte rna l time d inte rrup t clock is ma ske d (ignor ed ) too long

(app li es to int errup ti ons at bloc k boun da ries/ proc e ss inte rrup ts).

This situation is related to the basic clock rate of the internal timed

interrupts and the scan time of a block in the cyclic user program. If

the sca n of a cy clic bl oc k runs longe r t ha n the basic cloc k rat e, a

col lision of time d inte rr upt s occur s.

Causes of Error and Reactions of the CPU

CPU 948 Programming Guide

5 - 30 C79000-G8576-C848-04

Reaction:

The system program c a ll s OB 33 as u se r inte rfa c e , if thi s is loaded .

Here , you c an progr am the rea c tion to this sta te.

If OB 33 is not loade d, th e CPU contin ue s proc essing t he prog ram.

PG displa y with "O UTP UT ISTACK" :

The bit WEFEH is marked in the control bits.

Whe n the syste m progra m cal ls OB 33, a code for the coll isi on of

time d interrup ts is transfe rre d to ACCU-1-L (see Sectio n 4.5.3).

Note

In the "proc ess int errup t via IB 0" mod e and "i nterr u ptab il ity at

bloc k bou nda ri es" t he st ep ad dre ss co unt er (SAC) doe s not point

to the block at whose boundary (BE state ment) the collision of

timed interrupts took plac e . It poi nts to th e bl oc k th at ca ll ed t he

block that caused the error (return address).

As long as an error is pending or reoccurs every time the STEP 5

op er atio n in qu est io n is pro ces se d in ea c h sca n, the appropria te

erro r orga ni z atio n blo ck is al wa ys ca lle d.

This ca n in crease the c ycle ti me c onsiderably , de pend ing on the

dura tion of erro r handling by the syst em progra m and of

proc essi ng tim e of the organ iza tion bloc k.

Causes of Error and Reactions of the CPU

CPU 948 Programming Guide

C79000-G8576-C848-04 5 - 31

5.6.10

OB 34: Error wit h

G DB/GX DX

(FEDBX) Causes:

•• with the opera tion G DB/GX DX, an i lle gal bloc k numbe r wa s

sp eci fie d (num be r of a rese rv ed bloc k, num be r > 255) ,

•• with the opera tion G DB/GX DX, an i lle gal bloc k lengt h was

spec ified (> 409 1),

•• the re is no longe r enoug h spa ce in the user mem ory f or the

ope ration GDB/GXDX.

Reaction:

The system program c a ll s OB 34 is this is loaded. If OB 34 is not

loa ded, the CPU chan ge s to the stop mode .

5.6.11

OB 35: Communicat ion

Errors If problems occ ur on t he sec on d ser ial i nterf ac e with an R K 512

comput er li nk, da ta tra n sfer with procedure 3964/3 964R, data transfe r

with an open dr iver or data transfe r with SINE C L1, the system

pr ogra m cal ls org an iza ti on bl oc k OB 35 and e nte rs a ddi ti ona l

infor ma t ion abo ut the err or in ACCU 1.

Reac ti o n if OB 35 is no t l o a de d

If you have not programm e d OB 35, the system pro gram does not

rea ct and the CPU does not change to the STOP mode.

Error informat ion in ACCU 1

The system prog ram che c ks whe ther erro rs ha ve occ ur red on the seri al

inte rf ace ever y 100 m s. If an err or ha s occu rre d, the syst em pro gra m

ent er s err or in form ati on in ACCU 1.

Error num bers for up t o a maximum of three e rrors can be transferre d

wh en OB 35 is call ed . If there are mor e t h an thr ee e r ro r s , this i s in d icat e d

by an overflow identifier.

Causes of Error and Reactions of the CPU

CPU 948 Programming Guide

5 - 32 C79000-G8576-C848-04

Structure of t he error

information in ACCU 1

31 24 23 18 15 8 7 0

AC CU 1 0 0 0 0 F U B 0 Err or num ber 1 Erro r num ber 2 Error numbe r 3

F = ’0’, me a ns no error ent ry

= ’1’, me a ns one or more errors e nt er ed

U = ’0’, me a ns no error ove rfl ow (m ax im um three entr ie s)

= ‘1‘, me a ns er ror overflo w (mo re tha n th re e ent rie s )

B = ’0’, means no BREAK on the interface

= ’1’, mea ns BRE AK on th e inte rf ace

BREAK

If there is a BREAK on the interface, OB 35 is only called at the

beginning of the BREAK state.

Error number 1 to error

number 3

He re, a m axim um of thre e erro r num bers for err ors de tec ted on the

interface are entered in the order in which they were detected by the

system.

Meaning of the error numbers

The meaning of the error numbers and further information about

dea ling wi th inte rf ace errors c a n be found in the com m uni cat ion

manual (Further Reading /14/).

5.6.12

OB 36: Error in Sel f-test OB 36 is ca l led if one of the self-test routine s de te c ts a n er ror whe n it

is r un (fo r de tail e d inf orm a ti on, re fe r to Sec ti on 5. 7).

Causes of Error and Reactions of the CPU

CPU 948 Programming Guide

C79000-G8576-C848-04 5 - 33

5.7 Self-Test

5.7.1

Overview T he CPU 948 cont a ins i ntegr at ed sel f-t e st rou tine s in the syste m

program.

Activating/deactivating

You c an a ctiv at e or de act iva t e the functions of the self-t e st usi ng bi ts

in system data RS 137.

Time slice

To reduc e the cyc le load ca use d by the se lf-test in the RUN mode,

only part of the self-test is carried out within a cycle (time slice). The

time available for the self-test can be set in RS 136 (refer to

Se ction 5. 7.3).

What can be tested?

The sel f-t est rou ti ne s ca n car ry out the fol lo wing te sts:

WH AT IS TESTED? WHE N?

The user memory During OVERALL R ESET

The BASP signal

(disable command output) In the STOP mode

The hardware clock During COLD RESTART

The cycle time monitoring Du rin g START-U P

The add re ss lines C yc lica lly in the RUN mode

The cod e of the system program

(checksum) C yclica lly in the RUN mode

The code of the STEP 5 logic

blocks in the user memory

(checksum)

Cyc lical ly in the RUN m ode

Self-Test

CPU 948 Programming Guide

5 - 34 C79000-G8576-C848-04

5.7.2

Descripti on of the Test

Functions

Testing the user mem ory

(Durin g OVERALL RESE T, withou t tim e slice)

The use r memory is teste d du rin g an OVERAL L RESET . This test

checks the user memory, the byte areas, the flags and process images.

Dur ing the te st, th e who le area (i nc lud ing the byt e are a s) ar e wri tte n

with a test pat tern and t hen chec ked t o make sure that they ma tch. At

the en d of the test , the are a is writt en with ze ros.

Note

T he us e r memo r y test ta kes ti me to comp lete

- CPU 948-1 (64 0 Kbyt es) a pp rox. 5 seco nds

- CPU 948-2 (1 664 Kbytes) app rox. 22 sec onds

Testing the BASP signal

(In the STOP mode, without time slice)

Thi s te st checks whet her a BASP signal is output by the CPU. The test

func tion run s in the stop loop. The BASP signal is the n rea d cyclica lly.

If an e rro r is de te c ted, a n en try is ma de in t he er ror bu ffe r. At th e next

START -UP, OB 36 (e rro r in self -test ) is cal led, if it exists. If OB 36 is

loa de d and contai ns an STP ope ra t ion, the START -UP i s abo rted.

Othe rwise , the CPU cha nge s to the cycl ic mo de.

Testing the hardware clock

(Durin g STAR T- UP, ho wev er, only in CPU COLD RESTART;

wi tho ut tim e sl ice )

This test is made before OB 20 is called and takes one second.

The c urr ent ti me is retaine d; e xi sting tim ed jo bs (cloc k-c ontr olle d

inte rrupts - OB 9) on the othe r hand are dele ted.

Self-Test

CPU 948 Programming Guide

C79000-G8576-C848-04 5 - 35

Testing cycle tim e monitor i ng

(During START- UP, wi tho ut time slice )

With this function, the cycle time monitoring is checked during the

start-up phase. The cycle monitoring time is set to the minimum value

(2 0 ms) an d the n a progr am loop sta rt e d until the cycl e err or occ urs.

Testing the address lines

(Cyc lica lly in RUN mode , with time slice )

In thi s te st, wire bre a ks and shor t circui ts on the addre ss li nes are

det ec t ed by writ in g te st pat te rns vi a the line s, re a di ng th em ba c k and

comparing them.

Testing the syst em program

code

(Cyc li cal ly in the RUN mode, with time slice)

In the opera ting c ode test , the conte nt of the CPU opera ting syste m in

the inter nal RAM is checke d (test area D 0000H to E 7FFDH).

The test is made by adding the content of the test area and then

com pari ng this with the chec ksum in the EPROM.

Testing the block code of

STEP 5 logic blocks

(Cyc li cal ly in the RUN mode, with time slice)

The checksum of each valid STEP 5 logic block is checked.

If a m em ory ca rd is insert e d, t he check sum of the logic block s o f the

CPU 948 is cre ate d followi ng an OVE RAL L RESE T and aft er

copy ing the mem ory ca rd cont e nts t o the in terna l user m em ory. L ogi c

blocks added at a later point in time are also checked.

Note

In the code test of the STEP 5 blocks, an error is detected if one or

more logi c bloc ks we re mod ifi ed dyna m ic all y.

I t is po ssibl e to modi fy bloc ks wit h the PG. If this is th e ca se, the

che c ksum is crea ted by the syste m progr am of the CPU 9 48.

Self-Test

CPU 948 Programming Guide

5 - 36 C79000-G8576-C848-04

5.7.3

Settings

Calculating and setting the

number of time slices

The proc e ssing time for t he self-func ti ons i s d istributed on t im e slices

which are called once per cycle. The number of time slices can be

se lec te d. This m e an s tha t yo u can i nc re ase th e tim e r eq uir ed for th e

se lf-te st f unc tions pe r cyc le.

Calculating the number

Fi rst, you must est ima te the t ime you can le av e for the se lf- test within

the cyc l e: the le ngth of a tim e sl ic e is approx im a te ly 500 µs, i.e. the

se lf -test requires 500 µs in each cycle.

Onc e you have e sti ma t ed h ow mu ch tim e is available, you c an

calculate the number of time slices each taking approximately 500 µs.

Setting the number

You can se t the numb er of time slic es in syste m data word RS 136

(1 6-bi ts wi de ). The de fa ul t is 1 tim e sl ic e (m ini mum v al ue). You c an

set up to a maximum of 10 time slices (5 ms required in the cycle).

The num be r of tim e slice s is de ri ve d from the val ue of syste m data

wor d RS 136 as fol lows:

RS 136 = 0 or 1: 1 time slice

RS 136 = 2: 2 time slices

RS 136 = 3: 3 time slices

etc.

Activating/deactivating the

tests

You can activate the ind ividua l tests, e.g. in a sta rt-up bloc k, by setting

the cor re spond ing bits in RS 137 to ’1’ and deacti vate the tests by

se tt in g the bi ts to ’0’.

Note

Aft er an OVERAL L RE SET on a newly i nse rte d CPU, all the test

func ti ons are switched off.

The next time you make an OVERALL RESET, only the test

func ti ons to be run in the OVERALL RESET are activated. All

othe r test func tions a re deac tiva t ed .

This means that you can only check the user memory of a newly

inse rte d CPU by a cti vati ng the te st funct io n in RS 13 7 followi ng

an OVERALL RESET and then repeating the OVERALL RESET.

Self-Test

CPU 948 Programming Guide

C79000-G8576-C848-04 5 - 37

Assignment of sys tem data

word RS 137

Test func ti on Bit no.

Che ck the c ode of the syste m progra m 2

Check the code of the STEP 5 logic blocks in the

user mem ory 5

Che ck the a ddre ss line s 7

Che c k the cloc k 10

Check the BASP signa l 11

Check the cycle time monitoring 13

Test the user mem ory 15

The bit num be rs not listed in the table are not used.

5.7.4

Error Handling Pro vid ing the test function is not runnin g wit hin an OVE RAL L

RESE T , the te st funct ion cal ls error OB 36 (re fer to Sec tion 5. 6.11 ) if

an error is de tec te d and tran sfe rs the cont en t of RS 137 conta inin g the

bits of the act ivat ed test rou tine s to ACCU 1.

Al l the test rout in es a lso ent e r inf orm a tion a bout the type of test a nd

erro r dete cte d in the system data words RS 75 to RS 78.

For t est c om pone nt s whic h on ly ru n in an OVE RAL L RESET, the

ca use of the error is ind ic ate d in RS 75. The STOP LED then flashes

quickl y, when the tests ar e comple te d wit h an er ror in an

OVERALL RESET.

Erro rs de tec ted by the self-t est comp one nt "BASP signal " in th e STOP

mode are a lso ind ic a ted in RS 75. The follo wing START -UP on ly

leads to cyclic operation if no STP operation is prog ra mme d in

OB 36 .

Self-Test

CPU 948 Programming Guide

5 - 38 C79000-G8576-C848-04

Error information

Testing the user mem ory

System data word Error information

RS 75 error no . 640CH te st ing the word me mo ry

error no . 65 0CH test ing the byt e me mo ry

RS 76 test pat tern in whi ch t he error oc c urr ed

RS 77 inc orr ect address, hi gh

RS 78 incorrect address, low

Testing the BASP signal

System data word Error information

RS 75 er ror no . 6700H

RS 76 FFFFH

RS 77 FFFFH

RS 78 FFFFH

Testing the hardware clock

System data word Error information

RS 75 er ror no . 6800H

RS 76 FFFFH

RS 77 FFFFH

RS 78 FFFFH

Testing cycle tim e monitor i ng

System data word Error information.

RS 75 er ror no . 6600H

RS 76 FFFFH

RS 77 FFFFH

RS 78 FFFFH

Self-Test

CPU 948 Programming Guide

C79000-G8576-C848-04 5 - 39

Testing the address lines

System data word Error information

RS 75 erro r no. 630B H

RS 76 FFFFH

RS 77 inc orr ect address, hi gh

RS 78 incorrect address, low

Testing the syst em program

code

System data word Error information

RS 75 erro r no. 610B H

RS 76 FFFFH

RS 77 actua l chec ksum , high

RS 78 actua l che cksum , low

Testing the block code of

STEP 5 logic blocks

System data word Error information

RS 75 e rro r no. 620AH

RS 76 blo ck type /block no. (IDs from bloc k head er )

RS 77 expected checksum

RS 78 a ctua l che cksum

Self-Test

CPU 948 Programming Guide

5 - 40 C79000-G8576-C848-04

Cont ents of Ch apter 6

6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 4

6.2 OB121: Set/Read System Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 8

6.3 OB 122: "Disab le Int errupt s" On/Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 12

6.4 OB 124: Dele te STE P 5 Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 14

6.5 OB 125: Gener ate STEP 5 Bl ocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1 7

6.6 OB 126: Define , Transfer Process Ima ge s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 20

6.7 OB 129: Battery State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 25

6.8 OB 131: Dele te ACCUs 1, 2, 3 and 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 2 6

6.9 OB 132/133: Roll- Up ACCU/ Roll- Down ACC U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 27

6.10 OB 141: "Disab le Single Cyclic T im e d Inte rrupts" On/Of f . . . . . . . . . . . . . . . . . . . . . . 6 - 29

6.11 OB 142: "Delay All Interrup ts" On/Off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 3 2

6.12 OB 143: "Delay Singl e Cy clic T im ed Interrupt s" On/ Of f . . . . . . . . . . . . . . . . . . . . . . . 6 - 35

6.13 OB 150: Set /Re a d System Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 38

6.14 OB 151: Set/ Rea d Tim e for Clock -Con tro ll ed Int errupt. . . . . . . . . . . . . . . . . . . . . . . . . 6 - 4 3

6.15 OB 153: Set/Re ad T im e for Delayed Inte rrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 5 0

6.16 Ob 180: Vari ab le Da t a Bloc k Acc es s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 53

Integrated Special Functions

CPU 948 Programm in g Gui de

C79000-G8576-C848-04 6 - 1

6.17 OB 181: Te st Data Blocks (DB/DX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 57

6.18 OB 182: Copy Data Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 59

6.19 OB 202 to 205: Multiprocessor Com munication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 62

6.20 OB 222: Restart Cycle Monitoring Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 63

6.21 OB 223: Compar e Start-u p Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 6 4

6.22 OB 25 4/2 55: Copy/ Dupl ica te Data Blo cks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 65

Contents

CPU 948 Programming Guide

6 - 2 C79000-G8576-C848-04

6Integ rated Speci al Functi ons

The fol lowi ng c ha pter desc ri be s the spec ia l func ti ons inte gra t ed in th e

syst em program, wher e you can use th ese funct ions an d how to call

and assig n parame ter s to the spec ial func tion OBs.

You will also lea rn ho w to re cognize erro rs in the exe c ut ion of a

spe cia l func tion a nd possibl e ways of han dli ng the m in the progra m .

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 3

6.1 Introduction

The opera ti ng syste m of the CPU 948 pr ovi de s you with spe c ial

func ti ons whi ch you can ca ll if nec essar y wit h a condit ion al (JC OB x)

or an unco nditi onal (JU OB x) bloc k call . Organiz ati on bloc ks OB 100

to 255 a re reser ve d for the se spe c ia l func ti ons.

The se func tions a re known as inte gra t ed spec i al func tion s, si nc e the y

are a fixe d pa rt of the system progra m . As user, you ca n call these

spe cia l func ti ons bu t cannot read or modify the corre spon din g

program.

The following table provides an overview of the existing special

functions.

Bloc k Funct ion Refe r to

section/page

OB 121 Set/ read syste m time (compa ti ble with CPU 946 /947) 6.2/ 6 - 8

OB 12 2 "Disa ble int er rupt s" on/ off 6.3/6 - 12

OB 12 4

OB 12 5 Delete STEP 5 b loc ks

Genera te STEP 5 block s 6 .4/6 - 14

6 .5/6 - 17

OB 12 6 De fin e/tr an sfe r proc ess im age s 6.6/6 - 20

OB 129 Battery state 6.7/6 - 25

OB 131 Dele te ACCU 1, 2, 3 and 4 6.8/6 - 26

OB 13 2

OB 13 3 Roll-up ACCU

Rol l-down A CC U 6.9/6- 27

6. 9/6- 27

OB 14 1

OB 14 2

OB 14 3

"Disable single cyclic timed interrupts" on/off

"De lay all int er rupt s" on/ off

"Dela y single cyc lic tim ed inte rrup ts" on/ off

6. 10 / 6 - 2 9

6. 11 / 6 - 3 2

6. 12 / 6 - 3 5

OB 15 0

OB 15 1

OB 15 3

Set/read system time

Se t/read tim e for clo ck -c ontrolle d inte rru pt

Set/read time for delayed interrupt

6. 13 / 6 - 3 8

6. 14 / 6 - 4 3

6. 15 / 6 - 5 0

OB 181 Test data block 6. 16/6 - 53

OB 1 8 2 Co p y data ar ea 6. 17 / 6 - 5 5

OB 200, 202

203, 204, 205 Func tion s for m ultip roc e ssor c ommu nic ati on 6.18/ 6 - 58

OB 222 Restart cycle monitoring time 6.19/6 - 59

OB 223 Compa re start -up mod es in mult iproc esso r mode 6.20/6 - 60

OB 254, 255 Copy/duplicate DB and DX data blocks 6.21/6 - 61

Tab le 6-1 Overview of the spec ia l func tio ns avai lab le with the CPU 948

Introduction

CPU 948 Programming Guide

6 - 4 C79000-G8576-C848-04

Interfaces

The fol lowi ng a re avai labl e as in te rfa c es to th e spec ial func ti ons:

Block call

•• Co ndi ti ona l/ uncondit ional bl oc k ca l l JC .. / JU ..

Parameters

•• Pa ram et ers for de fa ul ts vi a AC CU 1 and possi bly ACCU 2 and/o r

me m ory l oc ations

I n the following desc ript ion of the individu al specia l functions, all

the data requi red by the CPU to execut e the spe cial fun ctio n

correctly are listed under the term parameters. Before c al ling the

sp eci al funct ion in the STE P 5 progr am, you must loa d this da ta in

the accum ul ators or in the spec if ied mem or y locati ons.

Writing to ACCUs

Whe n assign ing par ame ters fo r the spec ial func tion org an iza tion

bloc ks, plea se note th e followin g co nve nt ion s for writi ng to the

ACCUs:

ACCU 1: A C CU 1, 32 bi t s

ACCU-1-L: AC CU 1, low word , 16 b i ts

ACCU-1-LL: A C CU 1, low word, low byt e, 8 bits

ACCU-1-LH: AC CU 1, low word , high- byt e, 8 bits

High word Low word

Hi gh byte L ow byt e High byte Low by te

31 24 23 16 15 8 7 0

Introduction

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 5

Error handli ng

An error occurring in the e xec ution of the a ct ive spec ial func tion triggers

a specia l err or r eac tio n in the s ystem p ro g r a m .

In te rm s of this er ror re ac ti on by the syste m progr am , two gr oups of

spe cia l func ti ons c an be dist inguished .

•• Gr oup 1:

ACCU condition code bits

Gro up 1 in clude s a ll t he spe cia l funct ions wit h whic h IDs are

tra nsfe rre d to ACCU 1 if a n erro r occu rs to furth er exp la in the

error.

•• Gr oup 2:

RLO ,

CC0/CC1

Wit h some of the spec ial fu ncti ons, the RLO or th e stat us bi ts

CC 0/C C1 are writ ten to indi c ate e rr ors for speci fic spec ial

functions.

If an erro r occu rs whe n usin g one of th ese spec ial fu ncti ons, the

RLO is se t to "1" in most c ase s. In your ST EP 5 progr am , you ca n

use a JC operation (conditional jump) to evaluate the RLO for

the se spe c ia l functions a nd t he n re act to a n error.

In some spe cia l func ti ons, the resul ts bi ts CC0 a nd CC1 a re

affe c ted by the proc essin g of a speci al funct ion . You ca n sc an

the se bits in your STE P 5 progra m using a comp ar e operat ion an d

on ce aga in pr ogra m a rea c tion to an erro r.

Whi ch of the e rror rea cti ons oc curs fo r the indiv idu al spe cia l funct io n

OBs is exp lain ed in the foll owin g section s.

Introduction

CPU 948 Programming Guide

6 - 6 C79000-G8576-C848-04

Note

Calling a special function OB using the "JU OB 131/132/133" or

"JC OB 13 1/1 32/ 133" op er atio n doe s not hav e the sam e eff ec t as

a "ge nui ne " bloc k cha nge , but func ti ons as a ST EP 5 ope ra ti on

wi tho ut bloc k opera nd . No interrupts are nested (with the default

"interrupts at block boundaries").

Introduction

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 7

6.2 OB 121: Set/Read System Time

Function

With OB12 1 you ca n set or rea d the system tim e (dat e and time ). This

fu nc ti on is com pa ti bl e wi th the CPU 946/947.

Parameters

1. Data field

Four words i n the word -ori ente d memo ry area.

With the "set system time" fu ncti on th e area before the OB121 call

must be loaded with the time val ues to be set. The system progra m

checks these values to ensure they are logically correct.

With the "read syste m time " function, OB121 ent ers the curre nt t ime

values in this area.

St ruc ture of the da ta fi el d

Bit no. 15 12 11 9 8 4 3 0

1st wor d Sec . x 10 Sec. x 1 1 0th Sec . 100 th Se c .

2ndword Ho ur x 10 Hour x 1 Min. x 10 Min x 1

3rd wor d Day x 10 Day x 1 Wee kda y 0

4th word Year x 10 Year x 1 Month x 10 Mont h x 1

Note

The struc ture of the da ta field corre spon ds to the struc ture of

system data RS 96 to RS 99 (current time).

Possibl e time values:

10 0th sec ond s: 0 to 9

10th se conds: 0 to 9

Sec onds x 1: 0 to 9

Sec onds x 10 : 0 to 5

Minutes x 1: 0 to 9

Mi nut es x 10: 0 to 5

Hours x 1: 0 to 9

Hours x 10:

Bit no.

12 /1 3: 0 to 1 wit h 12 ho ur f or ma t

0 to 2 with 24 hour format

Bit no. 14: 0 = AM wit h 12 hou r forma t

1 = PM " "

0 in 24 hour format

Bit no. 15: 0 = 12 ho ur for ma t

1 = 24 hour format

OB 121: Set/Read System Time

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Weekday: 0 to 6 for Mon to Sun

Days x 1: 0 to 9

Days x 10: 0 to 3

Month x 1: 0 to 9

Month x 10: 0 to 1

Year x 1: 0 to 9

Year x 10: 0 to 9

2. BR register (base address r egist er )

St art addre ss of a da ta fiel d in an are a of m em ory or ga niz ed in words,

from which the time values to be set are read or in which the current

tim e v alue s ar e to be store d. The BR register must be loade d wi th t he

addr ess before the OB 121 call .

3. ACCU-1-L

Functio n no.,

Perm itted val ue s: 1 = set syst em time

2 = re a d system time

Result

Afte r corre c t and error -fre e proc essin g, the system prog ram ent er s t he

val ue ’0’ in ACCU-1- L. Aft er the "set " func t ion , the syste m tim e is set

to the values cont a ine d in the data fiel d; aft e r the "re a d" func t ion , the

da t a fie ld c ont a ins t he current tim e val ue s.

Possib le error s

The errors l ist ed in th e following tabl e can oc cur. If one of these e rror s

does oc cur, the syste m progra m enters th e erro r ID shown in the tabl e

in ACCU-1-L .

ID Meaning

F001H

F00FH

F101H

F102H

F103H

F104H

F105H

F106H

F107H

F108H

F109H

Il le ga l fu nc ti on no.

Multi ple bl oc k ca l l

Year specification illegal

Month spe c ific atio n illegal

Day specification illegal

Weekday specification illegal

Hour specification illegal

Minute specification illegal

Seco nds spe c ific atio n illega l

100th to 10th seconds in the data field unequal to 0.

Entr ie s from th e 100th to the 10 th sec ond m ust

equa l 0.

Hour form at diffe rs fro m settin g in OB 151

Table 6-2 Error IDs of OB 121 in ACCU-1-L

OB 121: Set/ Read System Tim e

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 9

Examples

Programming example for "set system time"

FB 13 is programmed for the "set system time" function. The new values are

transferred in data block DB 10 (data word DW 0 to DW 3).

S TE P 5 pr ogram:

FB13

NAME :CLKWR

:C DB 10 Open DB 10

:L KH 1500 15 seconds (10th .. 100th sec. = 0!)

:T DW 0

:L KH 9555 24 hour mode, 15 hours 55 minutes

:T DW 1

: L KH 1010 the 10th, Tu esda y

:T DW 2

: L KH 9308 1993, Augu st

:T DW 3

:MBR EEC00 Load start address of the DB list

: in th e BR

:LRW +10 Load the start address of DB 10 in memory

: (paragraph address) in ACCU 1

:SLD 4 Absolute address of DB 10 (DW 0)

:MAB Load content of ACCU 1 into BR register

:L KB 1 Load function no. ’1’ in ACCU-1-L

:JU OB 121 Set system time

:L KB 0

:> <F Scan er ror bits

:JC =ERRO Jump to error handling

:BEU

ERRO : Error handling

:BE

Data block DB 10 contains the following information when OB 121 is called:

0 : KH = 1500 ;

1 : KH = 9555 ;

2 : KH = 1010 ;

3 : KH = 9308 ;

OB 121 transfers the required time parameters from DB 10 to the system data

area RS 96 to RS 99.

OB 121: Set/Read System Time

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6 - 10 C79000-G8576-C848-04

Programming example for "read system time"

FB 14 is programmed for the "read system time" function. The current values

should be stored in data block DB 11 (data word DW 0 to DW 3).

S TE P 5 pr ogram:

FB14

NAME :CLKRD

:MBR EEC00 Load start address of the DB list

: in BR

:LRW +11 Load start address of DB 11 in memory

: (paragraph address) in ACCU 1

:L KB 0

:!=F Check that OB 11 is loaded

:JC =NIVO Jump to error handling

: if DB start address = 0

:TAK

:SLD 4 Absolute address of DB 11 (DW 0)

:MAB Load contents of ACCU 1 into BR register

:L KB 2 Load function no. ’2’ in ACCU-1-L

:JU OB 121 Read system time

:BEU

NIVO : Error handling

:BE

Data block DB 11 contains the following information after OB 121 is called

(example):

0: KH = 2994; 29 sec., 940 millisec.

1: KH = 9555; 24 hour format, 15 hours, 55 minutes

2: KH = 1010; 10 days, weekday ’1’(Tuesday), 0

3: KH = 9308; 93 years, 8 months

It is Tuesday the 10th of August 1993, 15 hours, 57 minutes, 29 seconds and

940 milliseconds (9 tenths and 4 hundredths of a second).

OB 121: Set/ Read System Tim e

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 11

6.3 O B 122: "Disable Inte rrupts" On/Off

A ST EP 5 progra m can be in terru pte d at bl oc k bou nda ri es or o pera ti on

bo unda ri e s by progra ms a t an e xe cu tion le ve l wi th a higher pri ori ty .

The prog ra m exe cuti on l ev els wit h hig he r pri ori ty inc lud e the

foll owin g:

•• TIME D INT ERRUPT S

and

•• PROCESS INT E RRUPT S.

The time requi re d to run th e interr upt ed progr ams is e xpa nd ed by the

ru n time of the nest e d prog rams.

Function

Using OB 122 , you can pr even t interrupt servi c ing bloc ks be ing

nest ed at one or mo re con sec ut ive bloc k or oper at ion boun da ries.

OB 122 influe nc e s the acc e pt ance of interrupt s :

•• "Di sab le inte rrup ts" on m e an s t he fol lowi ng:

n o interrup ts wil l be regi ste re d fro m now on.

•• "Disable inte rrup ts" off me a ns the fol lowing :

al l inte rru pts oc c urr ing will be reg ist er ed from now on and t he

corresponding blocks will be nested and executed at the next

operation or block boundary (depending on the mode set in DX 0).

In terru pts t ha t have alre a dy be e n registered, a re th en no longe r

se rvi c ed if th e mode "in terruptability at bloc k boundaries" is set in

DX 0.

Parameters

ACCU-1-L

Functio n no.,

Perm itted v a lue s: 1 = disable all int e r rupt s

2 = e nable all inter rupts

OB 122: "Disable Interrupts" O n/Off

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6 - 12 C79000-G8576-C848-04

Result

Afte r corre c t and error -fre e proc essin g, the system prog ram ent er s t he

value ’0’ in ACCU-1-L.

Note

By ca ll in g OB 122, th e RLO (un defined ) is in flu en ce d. The BR

re gi ste r i s not m odi fi ed.

To disable and en able proce ssin g inte rrup ts, you c an also use the

ST EP 5 ope ra tions IA a nd RA in ste a d of OB 122 . The blo ck ing of

inte rr upt s is cl ear ed at the next syste m che ckpoi nt (refe r to

Chap ter 11) .

Possib le error s

The errors l ist ed in th e following tabl e can oc cur. If one of these e rror

does oc cur, the syst em pr ogra m writ e s the error ID sho wn in the ta ble

into ACCU-1-L.

ID Meaning

F001H Illega l functi on numbe r

Example

Table 6-3 Error IDs of OB 122 in ACCU-1-L

Excerpt of a STEP 5 program in which all

interrupts are disabled using OB 122 immediately

before a critical program section following which

t hey are enabled ag ain:

:L KB 1 Load function ID in ACCU-1-L

: JU O B 12 2 Disable al l interrupts

: } Critical program section

:L KB 2 Load function ID in ACCU-1-L

:JU OB 122 Enable all interrupts

OB 122: "Disable Interrupt s" On/Off

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 13

6.4 OB 124: Delete STEP 5 Blocks

Function

With OB 24, you can delete any STEP 5 blocks (logic and data

bloc ks) i n the use r memor y. The de let ed bloc k is rem ov ed from the

addr ess l ist in DB 0.

The gap in memory resulting from deleting a block is used again when

new blocks are loaded.

Parameters

1. ACCU-1-LH

Block type of the block to be deleted

2. ACCU-1-LL

Block numbe r of th e bl oc k to be de l et e d

Permitted block types and numbers:

ACCU-1-LH (bl ock type) ACCU-1-LL (bloc k numbe r)

1 = PB

2 = SB

3 = FB

4 = FX

5 = DB

6 = DX

7 = OB

0 to 255

3 to 255

1 to 39

Result

Afte r corre c t and error -fre e proc essin g, the system prog ram se ts the

RLO to ’ 0’ and c le a rs the condi ti on c ode s CC 1 and CC 0 .

Note

Whi le th e bloc ks a re a ctual ly b eing de l et e d, user int er rupts are

d isa bl ed: no inte rr upt s com e thr ough .

B y ca lli ng OB 124, the con tent s of ACCU 1 to ACCU 4 are

modified. The BR register is retained.

OB 124: Delete STEP 5 Blocks

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6 - 14 C79000-G8576-C848-04

Possib le errors and

warnings

If an erro r or warni ng occ urs, the system progra m stops pr oc essi ng

OB 124 and continues program execution at the next STEP 5

op erat io n. It a lso se ts the RLO t o ’1’ and wri te s a n ID to ACCU-1-LL

(refer to Table 6-5).

If the funct ion is ab orted with a wa rning, it ma y be possi ble to achiev e

corr ec t exe c ut ion of OB 124 by re- ca l ling th e spe cia l f unc tion

(possib ly se vera l time s).

In the fol lowi ng c ase, OB 124 is ab ort ed with a warning:

Dur ing t he la st 10 ms OB 124 , OB 125, OB 254 or OB 25 5 has bee n

ca lled . (Only on e ca ll for these spec ia l func tions is a llowed withi n

10 ms. Th is a voi ds mu lt ipl e c all s for t he OBs list e d ab ove blo ck ing

the interfa ce to the PG so that it can no longer be processed .)

Condition code bits

Aft er cal li ng OB 124 , you can che c k whethe r the spec ial funct ion has

bee n e xe cute d c orre ctl y or wa s ab ort ed with an "e rro r" or "wa rning"

using the result of logic operation and the condition code bits CC 1

and CC 0. The result can be e va luat ed with co n dit iona l ju mp

operations.

Results bits

RL O CC 1 CC 0 Meaning Scan

0 0 0 Spec ial f unc tion wa s

proc esse d corr ec tly JC

1 1 0 Pro cessi ng of special

fu nc tion a bort e d wit h

"warning"

1 0 1 Pro cessi ng of special

fu ncti on abort e d wit h "error" JC

Table 6-4 Resul ts bi ts of OB 124

OB 124: Delete STEP 5 Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 15

IDs in ACCU-1-LL

In AC CU-1-LL, the system pro gram stores IDs about the processing

resul t, with whi ch the cause of a warnin g or error is spe ci fied i n more

detail.

Bit no. 7 6 5 0

W E Cause of erro r/warning

The fol lowi ng gr oup bits are fix ed :

Bi t no. 7 (W) = 1: wa rn ing

Bit no. 6 (E) = 1: err or

ID Meaning

01 H Funct ion was c orre ctl y pro cess e d

45H

47H

4DH

Error:

Bl oc k typ e not pe rm it te d

Bl oc k doe s not e xi st

Online fun ction COMPRE SS MEMOR Y ac tive

8DH

8EH

Warning:

Con fli c t with a n onl ine fun ction (e xc ep t for

"c om pre ss me m ory ")

10 ms wai ti ng t im e not e la ps e d

Example

Tabl e 6-5 Result IDs of OB 124 in ACCU-1-LL

:L KY 6,100 This sequence of operations deletes

:JU OB 124 data block DX 100 in the user

: memory

OB 124: Delete STEP 5 Blocks

CPU 948 Programming Guide

6 - 16 C79000-G8576-C848-04

6.5 OB 125: Generate STEP 5 Blocks

Function

With OB 125, you can generate any STEP 5 blocks (logic and data

bloc ks) i n the use r mem or y. Gene ra t ing logi c blocks s ho uld , howev er ,

be left to s p ecia lists.

The speci fied bloc k is set up in the int er nal RAM with a block hea der

and block bod y an d en tered in DB 0 . The blo ck b ody c ont a ins ra nd om

dat a. For t his rea son, a newl y ge ne rate d bloc k m ust first b e writte n to

before any useful data can be read out of it.

Parameters

1. ACCU-1-LH

Block type of the block to be generated

2. ACCU-1-LL

Block number of the bl oc k to b e ge ne ra t ed

Permitted block types and numbers

ACCU-1-LH (bl ock type) ACCU-1-LL (bloc k numbe r)

1 = PB

2 = SB

3 = FB

4 = FX

5 = DB

6 = DX

7 = OB

0 to 255

3 to 255

1 to 39

3. ACCU-2-L

Num ber of words (re qu ire d bloc k leng th wi tho ut bloc k hea de r). The

ma ximum a ssign able block le ngth is 32762 data word s. At pre sen t,

appr oxi ma tel y 2 K words can be edi te d with a PG.

Result

Afte r corre c t and error -fre e proc essin g, the system prog ram se ts the

RLO to ’ 0’ and c le a rs the condi ti on c ode s CC 1 and CC 0 .

Note

While the bl oc ks ar e a c tua l ly be i ng ge ne ra te d, use r in te rru pts a re

di sa ble d: no in terru pts c om e t hro ugh.

By ca lling OB 125, th e cont e nts of ACCU 1 to ACC U 4 a re

modified. The BR register is retained.

OB 125: Generate STEP 5 Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 17

Possib le errors and

warnings

If an error occurs, the syst em pr ogram stops processing OB 125 a nd

cont in ue s progr am exe cu tion a t the next STEP 5 ope ra t ion . It also se ts

the RLO t o ’1’ and writes a n ID to ACC U-1-L L (re fe r to Ta bl e 6- 7).

If the funct ion is ab orted with a wa rning, it ma y be possi ble to achiev e

corr ec t exe c ut ion of OB 125 by re- ca l ling th e spe cia l f unc tion

(possib ly se vera l time s).

In the fol lowi ng c ase, OB 125 is ab ort ed with a warning:

Dur ing t he la st 10 ms OB 124 , OB 125, OB 254 or OB 25 5 has bee n

ca lled . (Only on e call for these spe c ial func ti ons is a llowe d wit hi n 10

ms. Thi s avoid s mul tipl e calls for the OBs list ed abo ve blocking the

inte rf ace to the PG so that it can no long er be proc esse d.)

Condition code bits

Aft er cal li ng OB 125 , you can che c k whethe r the spec ial funct ion has

bee n e xe cute d c orre ctl y or wa s ab ort ed with an "e rro r" or "wa rning"

using the result of logic operation and the condition code bits CC 1

and CC 0. The result can be e va luat ed with co n dit iona l ju mp

operations.

Result bits

RL O CC 1 CC 0 Meaning Scan

0 0 0 Spec ial f unc tion wa s

proc esse d corr ec tly JC

1 1 0 Pro cessi ng of special

fu nc tion a bort e d wit h

"warning"

1 0 1 Pro cessi ng of special

fu ncti on abort e d wit h "error" JC

Table 6-6 Result bits of OB 125

OB 125: Generate STEP 5 Blocks

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6 - 18 C79000-G8576-C848-04

IDs in ACCU-1LL

In AC CU-1-LL, the system pro gram stores IDs about the processing

resul t, with whi ch the cause of a warnin g or error is spe ci fied i n more

detail.

Bit no. 7 6 5 0

W E Cause of erro r/warning

The fol lowi ng gr oup bits are fix ed :

Bi t no. 7 (W) = 1: wa rn ing

Bit no. 6 (E) = 1: err or

ID Meaning

01H Function correctly processed

42H

43H

44H

45H

4DH

Errors:

Bl oc k alre a dy e xist s

Not enough memory

Bl oc k le ngt h not pe rm it te d

Bl oc k typ e not pe rm it te d

Online fun ction COMPRE SS MEMOR Y ac tive

8DH

8EH

Warnings:

Con fli c t with a n onl ine fun ction (e xc ep t for

"c om pre ss me m ory ")

10 ms wai ti ng t im e n ot ye t el apsed

Example

Table 6-7 Resul t IDs of OB 125 in ACCU-1-L L

:L KF +2000 This sequence of operations

:L KY 5,24 generates DB 24 with a length of

:JU OB 125 2000 data words

: (total length including header:

: 200 5 words)

OB 125: Generate STEP 5 Blocks

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 19

6.6 OB 126: Define, Transfer Process Images

Ea ch time the c ycle is run thro ugh, th e system progra m upda tes t he

pr oc ess ima ge of the digita l inpu ts a nd out put s an d IPC fl ag s. The

input s, o utp uts a nd IPC fla gs in cl ude d in the pro ces s ima ge ar e store d

in syste m da ta blo ck DB 1 (refe r to Chap ter 10) .

Wit h OB 126, you can use addi ti ona l proc ess i mage s.

Function

Usi ng OB 126 , yo u can pr ogra m up to four fu rth er proc e ss im ag es i n

addition to the process image in DB 1 during a COLD RESTART.

The se add it ion al proc e ss ima ge s ca n be re ad in and output with the

STEP 5 program at any pr ogr am ex ecuti on le vel .

Parameters

1. Data field

6 fla gs wit h the fol lo wing struc t ure :

Bit no. 7 0

FY n Functi on no.

FY n+1 Address list no.

FY n+2 Block type

FY n+3 Block number

FY n+4 Data word no. of the first ID word

FY n+5 in the address list

Pa ra m et e r s of th e da t a fi e ld:

Function no.

With the function number, you stipulate which job OB 126 is to

perform (refer to the table).

Permitted values: 1 to 5

Function no. Function

Read in th e proc ess i mage of the digita l inpu ts

Outp ut the proc e ss im ag e of t he dig it al out put s

Read i n the pr ocess i ma ge of the IPC input fla gs

Outp ut the proc e ss im ag e of the IPC out put flags

5 Set up system internal addre ss l ist (a nalog ous to

DB 1)

(only permi tted in COLD RESTART OB 20 )

OB 126: Define, Transfer Process Images

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6 - 20 C79000-G8576-C848-04

Address list number

Num ber of the ad dre s s li st fo r t he ad dit io nally de fin ed proc e ss im ag e;

permitted values: 1 to 4

Block typ e

Type of da t a bloc k cont ai ni ng th e addr ess l ist ;

p ermi tted va lu es: 1 = DB

2 = DX

Block number

Number of the data block containing the address list;

permitted values: 3 to 255

DW no. 1st ID word

Here, you enter the number of the data word in which the first ID

wor d of the address list is loca ted (r ef er to str uc tur e of DB 1,

Se c ti on 10. 1. 6) .

The fol lowi ng ID wor ds are po ssibl e :

KH = DE00 (digital inputs)

KH = DA00 (digita l output s)

KH = CE00 (IPC i nput flags)

KH = CA00 (IPC outp ut fla gs)

The parameter occupies 2 fla g b y te s !

Note

T he co m p lete da ta fi eld only ne e ds to b e set up w hen OB 2 6 is to

genera te the add ress l ist duri ng a COLD RESTART (= funct ion

5) . To exe cu te funct ion s 1 to 4 it is ade quate to sim ply ent e r the

addr ess l ist num ber al ong side the func ti on num be r in the da ta

field. The remaining entries are then not needed.

You must struct ure the dat a block wit h which you want to set up

the a dd re ss list for an a ddi tional proc ess i ma ge (= func t ion 5 )

ana lo gous to DB 1.

You c an sto re t he ad dre ss li st in form a tion for eac h of the

additional process images in this data block by adding an end ID

to eac h fiel d of infor mat ion a s in DB 1.

To se t up the ad d re ss list , you m ust ho wev er call OB 126 fo r eac h

addi ti ona l p roc ess im ag e usi ng fu nc tion "5" sin gly (onl y in COLD

RESTART).

2. ACCU-1-L

No. of the flag byte FY n, at wh ic h th e da t a fi e ld be gins

permitted values: 0 to 250

OB 126: Define, Trans fer Proc ess Images

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 21

Result

Afte r corre c t and error -fre e proc essin g, the system prog ram se ts the

RLO to ’0’ and enters a ’1’ in ACCU-1 -L L.

Note

Whe n pr ocessi ng OB 126, user int er rupt s ar e disa bled: no

int er rupt s co me th roug h.

Cal ling OB 12 6 chan ges the co ntent s of ACCU 1 to ACCU 4.

The BR register is retained.

Du rin g a WARM REST ART the rema inin g cy cle is proc e sse d

wi th BASP a c tivated. All the digita l outputs are di sabled. At t he

end of the cycle, all outp uts (a l so tho se i n ad dre ss lists 1 to 4 ) are

reset.

Possib le error s

If th e sp ecial functio n cannot be execu ted, the system progr am

interrupts process ing of OB 126 and continues program execu tion

with the next STEP 5 op eration. It also s ets the R LO to ’1’ and

writ es an ID to ACC U- 1- LL (refer to the f ollowin g table) .

Spe cia l situ atio n whe n handl ing e rr ors:

If OB 126 is to execut e functi on ’5’ (se t up syste m intern al addres s

list ), the syste m prog ra m che cks the corre c t struc tu re of the addre s s

list . It also c he ck s whet her th e input s an d outputs or IPC flag s

cont a ine d in the a ddre ss list a c knowl e dge the correspondi ng m odul e s.

If an inc orre c t addr ess list has be e n tran sfe rre d, the CPU re act s in the

sa me wa y as t o a DB 1 err or. It cha nge s to the soft stop st ate and t he

STOP LE D fl ash es slowly . A DB 1 error is ind ica ted a s the cause of

th e er ror .

IDs in ACCU-1-L

ID Meaning

01H

02H

03H

04H

05H

06H

07H

Function correctly processed

Function number illegal

Pointer in ACCU-1 -L (flag numb er) illegal

Block type/number illegal or DB/DX block does not

exist

The first ID word is not loc ate d in the spec i fied da ta

word of the data block (wrong DW numb er) or the

addre ss li st cont a ins a n inco rre c t ID word

Address l ist numbe r illega l

The ca ll for the func ti on i s not pe rm i tt ed at the

curre nt prog ra m exe cuti on l ev el

Tabl e 6-8 Result IDs of OB 125 in ACCU-1-LL

OB 126: Define, Transfer Process Images

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6 - 22 C79000-G8576-C848-04

Examples

Creating the address list in DB 5

Using the function keys <input>, <scr form>,

"block: DB 5" program a data block DB 5 on the PG

w it h th e following parame ters:

Digital in puts : 1, 2,

Digital ou tput s: 3,

IPC input flags: 5, 6, 7,

IPC output flags: 20, 22,

If you create DB 5 manually, it must be

structured like a DB 1 (with start ID, ID words

and operand areas, end ID; refer to Section

10.1.6).

Entering the address list in the COLD

RES TART/OB 20:

First, you must set up the data field in the flag

area. This occupies flag bytes FY 20 to FY 25:

:L KB 5 Transfer function no. ’5’

:T FY 20 to FY 20

:L KB 1 Transfer address list no. ’1 ’

:T FY 21 to FY 21

:L KH 0105 Transfer block type DB (’1’) and

:T FW 22 number ’5’ to FY 22 and FY 23

:L KB 3 Trans. DW no. ’3’ (DW 3 in DB 5

:T FW 24 contains 1st ID word) to FY 24 & 25

Once the data field has been correctly set up,

the number of the first flag byte in the data

field must be transferred to ACCU-1-L. Following

this, OB 126 is called which sets up the address

list:

: L KB 20 Data field begins with FY 20

:JU OB 126 Call for address list generation

: poss. evaluation of status bits

Note:

The address lists with numbers 1 to 4 are only

accepted by the CPU using an OB 126 call in OB 20

(COLD RESTART). To do this, OB 126 must be called

with function number ’5’ in OB 20.

OB 126: Define, Trans fer Proc ess Images

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 23

Output the process image of the outputs

The following STEP 5 program sequence can be

located in any program execution level (in OB 1,

i n a timed interrup t OB o r in a process inter rupt

OB etc.) and causes the process image of all

outputs in address list 1 to be output.

:L KB 2 Transfer function no. ’2’

:T FY 50 to FY 50

:L KB 1 Transfer address list no. ’1’

:T FY 51 to FY 51

:L KB 50 Data field begins with FY 50

:JU OB 126 Call for outputting the PIQ

: possibly evaluation of status bits

:...

OB 126: Define, Transfer Process Images

CPU 948 Programming Guide

6 - 24 C79000-G8576-C848-04

6.7 OB 129: Battery State

Function

Wit h OB 129 , you can c he c k the stat e of the ba ck -up ba t te ry wi th a

ST EP 5 progr am (OB 12 9 scans t he BAU signa l). Depend ing on the

result, you could, for example, set a fault indicator (lamp).

How the BAU signal is

formed

The power supp ly cont a ins two ba ck -up ba tte ri es, a lithi um ce ll (MB

fo r mai n ba tt er y) a nd a n acc um ul at or (R B for re se rve ba tt e ry). The

BAU signa l is form ed by ANDing the battery moni toring signal s.

Jumper setti ng in the p owe r

supply

In the powe r supply of the PLC , there are two jum pe rs with whi ch the

monitorin g of the ba t teries ca n be influenc e d. Ju mp er MB -N B

det er mi nes whe n the BAU signa l is gene ra t ed (if this j um pe r is not

inse rted, BAU is genera ted once foll owin g POWER UP). Oth er wise

the signal is monitored cyclically during operation. The monitoring

signa l of the acc umulat or can be disa bled with the jumper MA-NA.

The possible com bin atio ns of jump er set tings a nd the resul ting ba tte ry

moni to rin g by OB 129 are illu stra t ed in th e foll owin g tabl e:

Jumper MB-NB Jum pe r MA-NA Time when BAU signal

generated BAU sig nal ge ne r ate d from

monitor i ng signa l of ...

ope n open af te r PO W ER UP lith ium cel l

open closed after POWER UP lithium cell and accu

closed open cyclic lithium cell

closed closed cyclic lithium cell and accu

Parameters

none

Result

RL O = ’ 0’: ba tt er y O K

RL O = ’1’: batt er y run do wn

OB 129: Battery State

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 25

Example

6.8 OB 1 31: Delete ACCUs 1, 2, 3 an d 4

Function

By ca ll in g speci a l funct io n orga ni z at io n block OB 131 onc e , you can

delete the contents of ACCUs 1 to 4 ext r em e ly si m ply . O B 1 31

overwrites all four registers with ’0’.

Parameters

None

Result

The ACCUs 1 to 4 (eac h 32 bit) are delet ed (’0’).

Possib le error s

None

With the following sequence of operations, you

c an c heck whether o r not the battery is OK and if

it is not, you can energize a lamp:

:JU OB 12 9

:JC =BATL RLO = 1 -> battery run down

:BEU

BATL :SU Q 22 .5 sw itch o n wa rn ing la mp at

: output byte 22, bit 5

:BE

OB 131: Delete ACCUs 1, 2, 3 and 4

CPU 948 Programming Guide

6 - 26 C79000-G8576-C848-04

6.9 OB 132/133: Roll-Up ACCU/Roll-Down ACCU

Function

OB 13 2 and OB 133 ro ll t he ACCU c ont en ts up or down:

•• OB 132 (rol l up) mo ves the content s of ACCU 4 to ACCU1, th e

con tent s of ACCU 1 to ACCU 2, the conte nts of ACCU 2 to

AC CU 3 etc .

•• OB 13 3 (roll do wn) move s the cont en ts of the ACCUs in the

opposite dire ctio n: the con te nts of ACCU 1 to ACCU 4, ACCU 4

to ACCU 3 etc.

Parameters

None

ResultResult

Fi gs. 6-1 a nd 6-2 show the ACCU cont e nts before and after calling

OB 13 2 and OB 133.

Note

Wit h th e STE P 5 ope rati ons E NT (e xt e nde d ope ra tion set) an d

TAK (syst em opera t ion ) the ACCU cont e nts ca n also be shifte d

(r efer to Section 3.4.3).

Possib le error s

None

OB 132/133: Roll-Up ACCU/Roll-Down ACCU

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 27

ACCU 4

ACCU 2

ACCU 3

ACCU 1

31 0 31 0

OB 132

before after

Shift Accu contents

Fig. 6-1 Effect of the "roll-up" function

ACCU 4

ACCU 2

ACCU 3

ACCU 1

31 0 31 0

OB 133

before after

Shift Accu contents

Fig. 6-2 Eff ec t of the "roll -d own" fun cti on

OB 132/133: Roll-Up ACCU/Roll-Down ACCU

CPU 948 Programming Guide

6 - 28 C79000-G8576-C848-04

6.10 OB 1 41: "Disab le Singl e Cyclic Timed Inte rru pt s" On/ Off

Using OB 141, you c an prevent cert ain cyclic timed interrupt O Bs (ti med

interrupts at fixed intervals ) from being called at one or more

consecutive block or operation boundaries. For example, you can prevent

an OB 10 (period 1) and an OB 11 (period 2) from being called in a

particular program s e ction tha t must not be i nterrupted. O n t he other

hand, all re ma ining program me d time d int errupts are proc ess ed as us ua l.

Function

OB 141 affects the reaction to cyclic timed interrupts.

"D is ab le s ing le cy clic timed interr up ts " on me ans that none of the

specified cyclic timed interrupts are registered from this point onwards

and the interrupts that were already registered (e.g. those w ai ting for a

block boundary) are del eted. If a timed interrupt O B (for proces sing a

time d int errupt w ith a fix ed inte rval ) has al read y been st arte d, it is

processed completely.

"D is ab le s ing le cy clic timed interr up ts " off me ans that all cyc lic time d

interrupts are re gistered again a nd a re proce sse d a t t he next block or

operation bounda ry (de pending on t he setting in D X 0).

Parameters

1. Contr ol word

OB 141 re cords th e time d interrup ts to be disa bled i n a syste m- inte rnal

control word:

Bit no. 15 0

C o n t r o l w o r d

The bits of the cont rol word have the foll owin g sign ific an ce:

Bit no. Interrupt

0 to 2 Reserved, these bits must be ’0’

3 = ’1’

4 = ’1’

5 = ’1’

6 = ’1’

7 = ’1’

8 = ’1’

9 = ’1’

10 = ’1’

11 = ’1’

C ycli c tim ed int errupts wit h fixe d inte rva l:

pe ri od 1 (O B 10)

pe ri od 2 (O B 11)

pe ri od 3 (O B 12)

pe ri od 4 (O B 13)

pe ri od 5 (O B 14)

pe ri od 6 (O B 15)

pe ri od 7 (O B 16)

pe ri od 8 (O B 17)

pe ri od 9 (O B 18)

12 to 15 Reserved ; th ese bi ts must be ’0’

As long a s a bit is se t to ’1’ the cor re spond ing int er rupt is disab le d.

OB 141: "Disable Single Cyclic Timed Interrupt s" On/Off

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 29

2. ACCUs

2a) ACCU-2-L

Functio n no.,

Pe rmit te d value s : 1 , 2 or 3 wh er e:

1: The contents of ACCU 1 are loaded in the

con trol word.

2: All the bits marked ’1’ in the mask in

AC CU 1 ar e set t o ’1’ in the control word.

The new contr ol word is load ed in ACCU 1

3: All the bits marked ’1’ in the mask in

AC CU 1 ar e set t o ’0’ in the control word.

The new contr ol word is load ed in ACCU 1

2b) ACCU 1

Ne w co ntrol word or ma sk depend in g o n th e re q u ire d f u nction .

Result

Afte r corre c t and error -fre e proc essin g the syst em pro gra m set s the

RL O to ’0’.

Cal ling OB 141 has the foll owi ng resul ts:

Funct. no.

in ACCU-2-L

Contents of ACCU 1

before after

control word

mask

con trol word

new

con trol word

new

con trol word

OB 141: "Disable Single Cyclic Timed Interrupt s" On/Off

CPU 948 Programming Guide

6 - 30 C79000-G8576-C848-04

Possib le error s

If an erro r oc cu rs, the system prog ra m sets t he RLO t o ’1’.

The errors l ist ed in the fo llowin g tabl e ca n occu r. If an err or oc c urs,

the syste m progr am ente rs the err or ID listed bel ow in ACCU-1-L .

ID Meaning

8D01H

8D02H ille gal functi on no. in ACCU-2-L 1)

one of the reserv ed bits in ACCU 1 is ’1’ 1)

1) the incorrect value is located in ACCU-2-L

Scan control word

•• The sta tu s of the cont rol word c an be sc anned with th e foll owin g

p rogram sequence:

1 . load func t ion no. ’2’ or ’3 ’ in ACC U-2-L ,

2. loa d value ’0’ in ACCU 1,

3. call OB 141,

4. rea d out ACCU 1.

Table 6-9 Error IDs of OB 141 in ACCU-1-L

OB 141: "Disable Single Cyclic Timed Interrupt s" On/Off

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 31

6.11 OB 142: "Delay All Interrupts" On/Off

A ST EP 5 progra m can be interrupted a t bloc k or oper at io n bounda rie s

by progr am s wit h a high er p rio rity. The pr oc ess inte rr upt s and al l

tim e d inte rrup ts belo ng to the se high er p rio rity pro gra m exe c ut ion

lev el s. The run time of the int errupted progra m is ext e nde d by the

ru ntime of t he ne s te d p ro g ra m s. U s i ng O B 14 2 , you can prevent th e

nesting o f highe r pri ori ty pr ogra m exec ut io n leve ls a t on e or mo r e

conse c ut ive bloc k or opera t ion b ound ar ies (de pe ndi ng on the set ting

in DX 0).

Function

OB 14 2 affe cts the se rvi cing of inter rupt s:

"Del ay inte rrup ts" on mea ns tha t a ll interrupts occurring a re registered

and pe nding i nterrupts rem ai n re gistered. The re giste red interrupts a re,

however, initially not servi ced. The ope ration or block boundaries for

serv icin g inte rrup ts are te mpor ar ily mad e ineffe ct ive. If an O B for pr oces s

interrupt servicing or an OB for timed interrupt servicing has already

started , this is pr ocessed comp lete ly .

"Delay interrupts" off means tha t a ll regi stere d interrupts are proc ess ed at

the next block or ope rat ion boundary.

Note

The tim e in whic h the int er rupt s ar e del ay ed must be shorter tha n

thre e time s t he value of the shor test tim e d interrupt per io d . I f

thi s is not the case , a c ollision of tim ed in te rru pts oc curs.

Parameters

1. Contr ol word

OB 142 en ters th e interr upt s to be de laye d in a syst em-i nter na l control

word, as follows:

Bit no. 15 0

C o n t r o l w o r d

OB 142: "Delay All Interrupts" On/O ff

CPU 948 Programming Guide

6 - 32 C79000-G8576-C848-04

The bits in the contro l word hav e the followi ng meaning:

Bit no. Type of interrupt

0 = ’1’ C ycli c time d inte rrup ts, fix ed per iod

1 = ’1’ Clock-controlled i nterrupt

2 = ’1’ Process interrupts

3 = ’1’ Delayed interrupt

4 to 15 Rese rv ed: these bi ts m ust be ’0’

As lo ng a s a bi t is set to ’1’, th e corr esp onding inte rr upt is disable d.

2. ACCUs

2a) ACCU-2-L

Functio n no.,

Pe rmit te d value s : 1 , 2 or 3 wh er e:

1: The contents of ACCU 1 are loaded in the

con trol word.

2: All the bits marked ’1’ in the mask in

AC CU 1 are set to ’1’ in the control word.

The new contr ol word is load ed in ACCU 1

3: All the bits marked ’1’ in the mask in

AC CU 1 are set to ’0’ in the control word.

The new contr ol word is load ed in ACCU 1

2b) ACCU 1

Ne w co ntrol word or ma sk depend in g o n th e re q u ire d f u nction .

OB 142: "Delay All Interrupts" On/O ff

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 33

Result

Afte r corre c t and error -fre e proc essin g the syst em pro gra m set s the

RL O to ’0’.

Cal ling OB 142 has the foll owi ng resul ts:

Funct. no.

in ACCU-2-L

Contents of ACCU 1

before after

control word

mask

con trol word

new

con trol word

new

con trol word

Possib le error s

If an erro r oc cu rs, the system prog ra m sets t he RLO t o ’1’.

The errors l ist ed in the fo llowin g tabl e ca n occu r. If an err or oc c urs,

the syste m progr am ente rs the err or ID listed bel ow in ACCU-1-L .

ID Meaning

8E01H

8E02H

8EFFH

Illega l func tion no. in ACCU-2- L 1)

One of the rese rved bits (n o. 4 to 15) in

ACCU 1 is ’1’ 1)

Inc orre ct mo de (e.g. when the de l ayed int errupt is to

be disa bl e d and DX 0 c on tain s the para me ter

"proce ss inte rru pts via IB 0 = on")

1) the incorrect value is located in ACCU-2-L

Scan control word

The sta tu s of the cont rol word c an be sc anned with th e foll owin g

pr ogram sequence:

1. load functi on no. ’2’ or ’3’ in ACCU-2-L,

2. load value ’0’ in ACCU 1,

3. cal l OB 142 ,

4. read out ACCU 1.

Table 6-10 Error IDs of OB 142 in ACCU-1-L

OB 142: "Delay All Interrupts" On/O ff

CPU 948 Programming Guide

6 - 34 C79000-G8576-C848-04

6.12 OB 143: "Delay S ingle Cyclic Timed Interrupts" On/Off

Using OB 143, you can prevent certain cyclic timed interrupt OBs

(tim ed in terru pt OBs wi th a fixed per iod ) from be ing ca lle d at one or

more c onse cuti ve blo ck or ope ra tion boundari es. Fo r exa m pl e, you

ca n sel e ct a progra m sec tion wh ich can not b e interr upted by an OB 10

(period 1) and an OB 11 (period 2). On the other hand, all the

rem a ini ng pr ogrammed time d in te rru pts a re proce ss e d as usu al .

Function

OB 143 affe cts the proc ess ing of cyc lic t imed i nterrupts:

"D elay s in g le cy clic time d in terr up ts " on mean s that al l interr upt s are

registered a nd pe nding timed interrupts re main re giste red. T h e timed

interrupts specified in the control word are, however, not processed

immediately. Tempora rily, all the operation and block boundaries for

proc es sing th ese tim ed inte rru pts are ma de in eff ective . If a time d inter rupt

OB (for proce ssing a timed int errupt w ith fixed peri od) ha s alrea dy

started, i t is proce ssed completely.

"D elay s in g le cy clic time d in terr up ts " off me ans that all r egiste red

interrupts are serviced at the next block or operation boundary (depending

on the s etting in D X 0).

Parameters

1. Contr ol word

OB 14 3 ente rs the tim e d inte rrup ts to be del ay ed in a syste m -in te rna l

control word:

Bit no. 15 0

C o n t r o l w o r d

The bits in the contro l word hav e the followi ng meaning:

Bit no. Interrupt

0 to 2 Reserved, these bits must be ’0’

3 = ’1’

4 = ’1’

5 = ’1’

6 = ’1’

7 = ’1’

8 = ’1’

9 = ’1’

C ycli c tim ed int errup ts wit h fi xe d perio d

pe ri od 1 (O B 10)

pe ri od 2 (O B 11)

pe ri od 3 (O B 12)

pe ri od 4 (O B 13)

pe ri od 5 (O B 14)

pe ri od 6 (O B 15)

pe ri od 7 (O B 16)

10 = ’1’

11 = ’1’ pe riod 8 (OB 1 7)

pe ri od 9 (O B 18)

12 to 15 Reserved, these bits must be ’0’

As lo ng a s a bi t is set to ’1’, th e corr esp onding inte rr upt is disable d.

OB 143: "Delay Single Cyclic Timed Interrupt s" On/Off

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 35

2. ACCUs

2a) ACCU-2-L

Functio n no.,

Pe rmit te d value s : 1 , 2 or 3 wh er e:

1: The contents of ACCU 1 are loaded in the

con trol word.

2: All the bits marked ’1’ in the mask in

AC CU 1 ar e set t o ’1’ in the control word.

The new contr ol word is load ed in ACCU 1

3: All the bits marked ’1’ in the mask in

AC CU 1 ar e set t o ’0’ in the control word.

The new contr ol word is load ed in ACCU 1

2b) ACCU 1

Ne w co ntrol word or ma sk depend in g o n th e re q u ire d f u nction .

Result

Afte r corre c t and error -fre e proc essin g the syst em pro gra m set s the

RL O to ’0’.

Cal ling OB 143 has the foll owi ng resul ts:

Funct. no.

in ACCU-2-L

Contents of ACCU 1

before after

control word

mask

con trol word

new

con trol word

new

con trol word

OB 143: "Delay Single Cyclic Timed Interrupt s" On/Off

CPU 948 Programming Guide

6 - 36 C79000-G8576-C848-04

Possib le error s

If an erro r oc cu rs, the system prog ra m sets t he RLO t o ’1’.

The errors l ist ed in the fo llowin g tabl e ca n occu r. If an err or oc c urs,

the syste m progr am ente rs the err or ID listed bel ow in ACCU-1-L .

ID Meaning

8F01H

8F02H Il lega l func tion no. in ACCU-2- L 1)

One of the rese rved bi ts in ACCU 1 is ’1’ 1)

1) the incorrect value is located in ACCU-2-L

Scan control word

•• The sta tu s of the cont rol word c an be sc anned with th e foll owin g

p rogram sequence:

1 . load func t ion no. ’2’ or ’3 ’ in ACC U-2-L ,

2. loa d value ’0’ in ACCU 1,

3. call OB 143,

4. rea d out ACCU 1.

Tab le 6-1 1 Er ror IDs of OB 143 i n ACCU-1-L

OB 143: "Delay Single Cyclic Timed Interrupt s" On/Off

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 37

6.13 OB 150: Set/Read System Time

Features o f the

system time

•• The system time is backe d up by the batt ery in the PLC rack. If the

tim e is se t, it t here for e rem a ins corr ec t even fo llowing a power

failure.

•• The resolu tion is 10 ms for rea di ng and 1 s for setti ng.

•• Leap years are taken into account.

•• Hours ca n be repre se nt ed ei ther using t he 24 hour cloc k or the 12

h our c lo ck "am " an d "pm ".

•• The weekday is specified.

•• In put and o utp ut is BCD coded.

Function

Using OB 150, you c an set or read out t he date and time of the CP U 948

in your user program. T he date a nd time are know n a s the "system ti me".

Note

The system tim e is sta rted (ini tially with a defa ult valu e) aft e r the

C PU is plu gge d in.

Parameters

1. Data fie ld for the ti me paramete r s

When setting the system tim e, OB 150 reads i n the va lu es to be set

from a d ata f iel d, when reading the time, OB 150 transfers the current

tim e to th e dat a fie ld. You ca n set up this da ta fi eld in a data block or

in one of th e two flag area s (F or S flags).

The data fiel d consist s of fou r words.

1a ) F o r mat o f the data fi el d f or setting th e system time.

Bit no. 15 12 11 8 7 4 3 0

wo rd 1 Se c onds 0

wo rd 2 Forma t Hours Minutes

word 3 Day of month Weekday 0

wo rd 4 Yea r Month

OB 150: Set/Read System Time

CPU 948 Programming Guide

6 - 38 C79000-G8576-C848-04

1b) Form at of the data field when reading the syst em ti m e

Bit no. 15 12 11 8 7 4 3 0

wo rd 1 Sec ond s 1 /10 0 secon d s

wo rd 2 Forma t Hours Minut es

word 3 Day of month Weekday 0

wo rd 4 Year Month

The time para m ete rs ha ve the fol lowi ng m e an ing , rang e of value s an d

representation:

Parameter Permitted range of values Value in

Seconds

1/100 se c onds

Minutes

Hours

Weekday

Da y of month

Month

Year

0 to 59

0 to 99 (with "set system time" = 0

0 to 59

0 to 23 or 1 to 12, depending on the

"format"

0 to 6 for Mon to Sun

1 to 31

1 to 12

0 to 99

BCD format

Form at F o rm at for t he hour fi e ld with the

f oll owing meaning:

Bit 15 = 0: 12 hour format

("a m" or "pm "

selected in bit 14)

Bit 15 = 1: 24 hour format

(bi t 14 = 0)

Bit 14 = 0: "am"

Bit 14 = 1: "pm"

–

1) After OB 150 is called, the specified value is checked logically for the correct data

taking into account leap y ears.

Data field in the flag area

If you set up the data field in a flag area, you must take into account the

following assignm ent of the data field w ords to the flag bytes. ’x’ i s the

pa ram eter "nu mber of 1st data field word " wh ich mus t be wr itten to

ACCU-1-L when OB 150 is called:

Bit no. 15 8 7 0

Da ta fiel d word 1 Fla g byt e x Flag byt e x+1

Da ta fiel d word 2 Fla g byte x+2 Fla g byte x+3

Da ta fiel d word 3 Fla g byte x+4 Fla g byte x+5

Da ta fiel d word 4 Fla g byte x+6 Fla g byte x+7

OB 150: Set/ Read System Tim e

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 39

2. ACCUs

2a) ACCU-2-L

ACC U-2-L c ont ains informa tion a bou t th e requ ire d fu nc tion a nd th e

data field use d. It must have the following structu re:

Bit no. 15 12 11 8 7 4 3 0

Functio n no. Ad dress ar ea ty pe Data blo ck n o.

Para m ete rs in ACCU-2-L

Functio n no.,

Perm itted val ue s: 1 = se t system time

2 = re a d system time

Address area type,

Pe rmit te d va l ues: 1 = DB da ta bl oc k

2 = DX data block

3 = F flag area

4 = S flag area

Data block no.,

Permitted values: 3 to 255 (only with address area type ’1’ or ’2’;

with address area type ’3’ or ’4’ irrelevant)

2b) ACCU-1-L

Num be r of the 1st da t a fie ld wor d

Permitted values (depending on the address area type):

DB , DX: 0 to 2039

F fla gs: 0 to 248

(= no. of fl a g byt e ’x ’)

S fla gs 0 to 4088

(= no. of fl a g byt e ’x ’)

Result

After correct processing of OB 150, the RLO, the condition code bits

OR, ERAB and OS = 0.

Possib le error s

The errors l ist ed in the fo llowin g tabl e ma y occu r. If an err or oc c urs,

the syste m progr am se ts th e RLO to ’1’ a nd sto re s t he er ror IDs l ist ed

in the table in ACCU 1.

OB 150: Set/Read System Time

CPU 948 Programming Guide

6 - 40 C79000-G8576-C848-04

ID Meaning

9601H

960FH

9611H

9612H

9613H

9614H

9615H

9621H

9622H

9623H

9624H

9625H

9626H

9627H

9628H

9629H

Data block not loaded

Multiple call for the block

I ll egal function no.

Address area type illegal

Data block number illegal

"Numb er of first data field word" illegal

Dat a block leng th < 4 words

Year specification in the data field illegal

Month sp ecifi c atio n in the da ta fi el d ille gal

Day of month specification in the data field illegal

Weekday specification in the data field illegal

Hour specification in the data field illegal

Minut e sp ecifi c atio n i n the data fi el d ille gal

Seco nd sp ecif ication i n th e data fiel d il lega l

1/100 seconds in the data field not equal to 0

Hour format not equal to setting in OB 151

Note

If the para met ers are inco rrec tly assi gned fo r the "se t system tim e"

fu nc ti on a nd if the time ha s al re a dy be e n set co rre c tl y at lea st

once , the e rror IDs listed are tra nsferre d; the pre viousl y set syst em

time, however, continues to run.

Examples

Table 6-12 Error IDs of OB 150 in ACCU-1-L

"Set syst em time":

You want to set the system time to the following values:

"Thurs, 24.10.1993, 11:30 hours 0 seconds, 24 hour clock"

The time parameters are stored in data block DB 10 from data word DW 0

onwards.

DB 10 0: KH = 0 0 0 0 left byte = s econ ds ( BCD) , right byte = 0

1: KH = 9 1 3 0 9 1 = Form at ( =80H ) + hour (=1 1 BC D)

30 = Minutes (BCD )

2: KH = 2 4 3 0 2 4 = Day of m onth (BC D)

30 = Weekday (3 = Thu rsda y) + bit 0 t o 3 = 0

3: KH = 9 3 1 0 9 3 = Year (BC D)

10 = Month (B CD)

Continued on next page

OB 150: Set/ Read System Tim e

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 41

"Read out system time":

You want the c urre nt s yste m time t o be written to data block D B 10 fro m da ta

word DW 4 onwa rds. You mus t theref ore call OB 150 with the fol lowi ng

parameters:

:L KH 2 1 0 A Values for ACCU -2-L :

: DB no . = 10

: Addre ss a rea type = 1 for "da ta f ield in DB"

: Funct ion no. = 2 for "read"

:L KF +4 ACCU- 1-L:

: No. o f 1s t da ta f ield word = 4

:JU OB 150 Call OB 1 50

:C DB 10 Open DB 1 0

: Evalu ate DB 10

After OB 150 is called, the current system time is written to data block DB

10 in the following form ("Thurs, 24.10.93, 11:30 hours 20 seconds, 13/100

of a second, 24 hour clock"):

DW 4: KH = 2 0 1 3 Seconds = 20 (BCD)

1/100 seconds = 13 (BCD)

DW 5: KH = 9 1 3 0 Format = 24 hour (bit 15 = 1, bit 14 = 0),

Hour = 11(BCD), minutes = 30 (BCD)

DW 6: KH = 2 4 3 0 Day of month = 24 (BCD)

Weekday = 3 = Th ursd ay

DW 7: KH = 9 3 1 0 Year = 93 (BCD)

Month = 10 (BCD)

"Set syst em time"

(continued)

STEP 5 operations in OB 1 for calling OB 150:

:L KH 1 1 0 A Values for ACCU-2-L:

: DB no . = 10

: Address area type = 1 for "data field in DB"

: Fun ction no . = 1 for "set"

: L KF +0 ACCU -1-L :

: No. of 1st data field word = 0

:JU OB 150 Call OB 150

OB 150: Set/Read System Time

CPU 948 Programming Guide

6 - 42 C79000-G8576-C848-04

6.14 OB 151: Set/Read Time for Clock-Controlled Interrupt

Function

By ca llin g OB 151 yo u can do the fol lowi ng:

•• cause the CPU 948 to activate the clock-c ontrolled i nterrupt ("timed

job" - O B 9, refe r to S ection 4.5.3) a t a s e lecte d time :

- every minute

- every hour

- every day

- e v ery we ek

- every month

- every yea r

- once,

•• rea d out the curre nt sta tu s of a tim e d job,

•• ca nc el a previously ge ne rated tim e d jo b.

OB 151 ca n be c al led in the START-UP a nd RU N m odes. A generated

clock-controlled interrupt i s retained w he n a WARM RESTAR T

(automatic or manual) is carried out. A COLD RESTART deletes an

ex isting timed jo b.

If you ge nera te a n ew tim e d job , an existing time d job is a ut om at ic a lly

ca nc el le d. T his m eans tha t only one clock- co ntr oll e d interrup t can be

active.

Parameters

1. Data field for job para mete r s

When generating or cancelling a time d job , OB 151 ta ke s the

requ ire d j ob para m et e rs from a data f ield . Whe n rea ding out th e

current status of the job management, OB 151 transfers the current job

pa r a meters to a data field.

You ca n se t up this da t a fi eld i n a dat a block or in one of th e two flag

areas (F or S fl ag s).

The data field co nsist s of four words a nd has th e foll owin g form at

when generating and reading out a timed job:

Bit no. 15 12 11 8 7 4 3 0

Word 1 Seconds 0

Wor d 2 Forma t Hours Minut es

Word 3 Day of month Weekday Job type

Wor d 4 Yea r Month

OB 151: Set/Read Time for Clock- Controlled Int errupt

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 43

The parameters have the following meaning, range of values and

representation:

Parameter Permitted range of values Value in

Job type 0 to 7 where :

0: cancel job or

no job a ct iv e

1: eve ry m inute

2: every hou r

3: every day

4: every week

5: eve ry m onth

6: every year

7: once

BCD format

Seconds

1/100 se c onds

Minutes

Hours

Weekday

Da y of month

Month

Year

0 to59

0 to 59

0 to 23 or 1 to 12, depending on the

format

0 to 6 for Mon to Sun

1 to 31

1 to 12

0 to 99

BCD format

Forma t 2) Fo rm at for t he h our fi e ld with t he

f oll owing meaning:

Bit 15 = 0: 12 hour clock

Bit 15 = 1: 24 hour clock

(bi t 14 = 0)

Bit 14 = 0: "am"

Bit 14 = 1: "pm"

–

1) After calling OB 151, t he specified value is checked logically that the date is correct

taking into account leap y ears.

2) F or the meaning of "am" and "pm": refer to OB 150 in the previous section:

"format" must match the form specified when setting the system time with OB 150.

Data field in the flag area

If you set up the data field in a flag area, you must take into account

the followi ng assign ment of the dat a fie ld words to the flag bytes. "x"

is the pa rame t er ’num be r of the 1st data fi eld word ’ which must be

writt en to ACCU-1-L whe n OB 151 is cal led.

Bit no. 15 8 7 0

Da ta fiel d word 1 Fla g byt e x Flag byt e x+1

Da ta fiel d word 2 Fla g byte x+2 Fla g byte x+3

Da ta fiel d word 3 Fla g byte x+4 Fla g byte x+5

Da ta fiel d word 4 Fla g byte x+6 Fla g byte x+7

OB 151: Set/Read Time for Clock- Controlled Int errupt

CPU 948 Programming Guide

6 - 44 C79000-G8576-C848-04

2. ACCUs

2a) ACCU-2-L

ACC U-2-L c ont ains informa tion a bou t th e requ ire d fu nc tion a nd th e

data field use d. It must have the following structu re:

Bit no. 15 12 11 8 7 4 3 0

Function no. Address area type Data block no.

Para m ete rs in ACCU-2-L

Functio n no.,

Pe rmit te d va l ues: 1 = ge ne rate jo b

2 = read job status

Address area type,

Pe rmit te d va l ues: 1 = DB da ta bl oc k

2 = DX data block

3 = F flag area

4 = S flag area

Data block no.,

Permitted values: 3 to 255 (only with address area type ’1’ or ’2’;

with address area type ’3’ or ’4’ irrelevant)

2b) ACCU-1-L

No. of the 1st data field word,

Permitted values (depending on the address area type):

DB , DX: 0 to 2039

F fla gs: 0 to 248

(= no. of fl a g byt e ’x ’)

S fla gs 0 to 4088

(= no. of fl a g byt e ’x ’)

Note

There is no point in generating a timed job cyclically (e.g. with an

un co ndi ti ona l OB 151 cal l wit h funct io n num be r ’1’ in OB 1).

Result

After correct processing of OB 151, the RLO, the condition code bits

OR, ERAB and OS = 0.

OB 151: Set/Read Time for Clock- Controlled Int errupt

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 45

Note

If, when reading out the timed job, the job type is ’0’ and all the

remaining parameters are ’F’ or ’FF’ (hex) in the data field, no

timed job is active.

Thi s sta tu s ca n oc c ur in the fol lowi ng si tua t ion s:

a) the re was a COLD RE ST ART wit hout a time d job bein g

ge nerated

b ) when a "one-t im e" time d job was du e

c) when you have cancelled a job.

Possib le error s

The errors l ist ed in th e following tabl e can oc cur. If one of these e rror s

occ urs, the syst em pr ogra m set s the RLO to ’1’ an d write s the er ror

IDs list ed in the tab le to ACCU 1.

ID Meaning

9701H

970FH

9710H

9711H

9712H

9713H

9714H

9715H

9721H

9722H

9723H

9724H

9725H

9726H

9727H

9728H

9729H

972AH

Data block not loaded

Multiple call for the block

Wro ng m ode ("pro cess in terru pts vi a IB 0 = on")

I ll egal function no.

Address area type illegal

Dat a block no. il legal

"Number of t he 1st data fi eld word" illegal

Dat a block leng th less tha n 4 words

Year specification in the data field illegal

Month sp ecifi c atio n in the da ta fi el d ille gal

Day of month specification in the data field illegal

Weekday specification in the data field illegal

Hour specification in the data field illegal

Minut e sp ecifi c atio n i n the data fi el d ille gal

Seco nd sp ecif ication i n th e data fiel d il lega l

1/100 seconds in the data field not equal to 0

Ho ur format not equal to setting in OB12 1/OB 150

Job type illegal

Note

If incorrect pa ra me t er s are a ssigned and a valid timed job was

p revio usly gen er at ed, the error IDs l ist ed ab o ve are tran sfe rre d;

t he pre vio usly ge ne r ate d tim e d job, howev er, rem ains ac tive.

Table 6-13 Error IDs of OB 151 in ACCU-1-L

OB 151: Set/Read Time for Clock- Controlled Int errupt

CPU 948 Programming Guide

6 - 46 C79000-G8576-C848-04

Points to no te wi th the time

parameters

Re ga rd le ss of when a c l oc k-c ont rol le d i nte rr upt (ti med j ob) i s to be

triggered, the individual time parameters must be specified in certain

com bi na ti ons. Depen ding on the se lec te d tim e for th e clo ck -c ont rol le d

interrupt , ce rta i n pa ra me t er s must be spec ified, while oth er s are not

eva luat ed by the syste m progra m .

The following tab le shows which time parame ters must be sp ec i fie d

fo r which t ime d job (XXX = must be spe c ifi e d, --- = irre l ev an t).

Interval Seconds Minu-

tes Hours Week-

day Da y of

month Month Year

eve ry m inu te

eve ry hour

every day

every week

eve ry m ont h

every year

once

XXX

---

XXX

---

XXX

---

XXX

---

XXX

---

XXX

---

XXX

When reading out the time parameters, the irrelevant parameters are

assig ned the valu e FFH.

Special situations

•• If the "29t h of February" is selecte d wit h the job typ e "e ve ry yea r"

( = 6), this m e an s tha t OB 9 i s only c all e d ev er y le a p ye ar .

•• If the value "29", "30" or "31" is se le cte d wit h the job ty pe "every

mo n th" (= 5), OB 9 is on ly ca ll ed i n th e mont hs wh i ch hav e the s e

dates.

Table 6-14 Assignment of "timed job - time parameters"

OB 151: Set/Read Time for Clock- Controlled Int errupt

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 47

Examples

Various timed jobs (in 24 hour format):

1. "Job at 29th second of every minute"

(12:44:29, 12:45:29 etc.):

You must specify: Job type = 1 (Function no. in ACCU-2-L = 1)

Seconds = 29

2. "Job every hour at xx:14:15":

You must specify: Job type = 2 (Function no. in ACCU-2-L = 1)

Seconds = 15

Minutes = 14

3. "Job daily at 5:32:47":

You must specify: Job type = 3 (Function no. in ACCU-2-L = 1)

Seconds = 47

Minutes = 32

Format/hour = 85

4. "Job weekly, Tuesdays at 10:50:00":

You must specify: Job type = 4 (Function no. in ACCU-2-L = 1)

Seconds = 00

Minutes = 50

Format/hour = 90

Weekday = 01

5. "Job monthly, on the 14th at 7:30:15":

You must specify: Job type = 5 (Function no. in ACCU-2-L = 1)

Seconds = 15

Minutes = 30

Format/hour = 87

Day of month= 14

6. "Job yearly, on the 1st of May at 00:01:45":

You must specify: Job type = 6 (Function no. in ACCU-2-L = 1)

Seconds = 45

Minutes = 01

Format/hour = 80

Day of month= 01

Month = 05

Continued on the next page

OB 151: Set/Read Time for Clock- Controlled Int errupt

CPU 948 Programming Guide

6 - 48 C79000-G8576-C848-04

Various timed jobs (in 24 hour format),

continued

7. "Job once on the 31.12.1999 at 23:55:00":

You must specify: Job type = 7 (Function no. in ACCU-2-L = 1)

Seconds = 00

Minutes = 55

Format/hour = A3

Day of month= 31

Month = 12

Year = 99

8 . "C an cel job":

You must specify: Job type = 0 (Function no. in ACCU-2-L = 1)

9. "Read out time job":

You must specify: Function no. in ACCU-2-L = 2

If no job is active, you obtain the following result in the data field:

Data field word 0: FFFF H

Data field word 1: FFFF H

Data field word 2: FFF0 H

Data field word 3: FFFF H

OB 151: Set/Read Time for Clock- Controlled Int errupt

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 49

6.15 OB 153: Set/Read Time for Delayed Interrupt

Using OB 153 , you can tra nsfe r so-ca ll ed "de lay jobs" to the syste m

pr ogra m . Afte r a spec i fied de l ay tim e "a de lay ed int er rupt " is th en

pr ocesse d (r ef er to OB 6, Sec t ion 4.5 .3 ).

Function

By ca lling OB 153, you c an do t he f oll owi ng:

•• define and start a delay time,

•• stop an activated delay time (cancel delay job),

•• rea d how l ong the dela y time sti ll has to run .

A delay job can be activate d in the STAR T UP and RUN modes.

Life of a delay job

The delayed interrupt triggered by a delay job is only activated by the

syste m progra m in the RUN mode (OB 6 call).

Jobs wh ich bec om e due in a mode othe r than RUN are disca rde d by

the system program wit hout any m essa ge .

A curre ntly ac ti ve (but not yet due) jo b is a lso di sc ar de d if the CP U

cha nge s to the STOP mode or if the power i s switche d of f.

Parameters

ACCUs

a) ACCU-2-L

ACCU-2-L only nee ds to be supp lied with t he func tion num be r ’1’

("d ef ine dela y t im e") when OB 153 is ca ll e d, as fol lows:

Delay time in milliseconds (max. 65535)

Perm it ted val ue s: 0001H t o FFFFH

b) ACCU-1-L

Functio n no.

Permitted values: 1 = define and start delay time

2 = stop delay time (= cancel job)

3 = read remaining delay time

OB 153: Set/Read Time for Delayed Int errupt

CPU 948 Programming Guide

6 - 50 C79000-G8576-C848-04

Note

If a previ ousl y de fine d dela y tim e is not yet elap sed when a

fu rth er dela y time is define d, the previ ousl y de fi ned time is lost

and the new delay time started.

Result

After correct processing of OB 153, the RLO, the condition code bits

OR, ERAB and OS = 0.

Whe n OB 153 is cal led wit h the func tion no. ’2’ or ’3’, ACCU- 1-L

cont a ins t he r ema in ing tim e to run in milli se co nds.

If no delay job is active when OB 153 is called with function no. ’2’

or ’3’, ACCU-1- L cont a ins t he val ue ’0’.

Possib le error s

The errors l ist ed in th e followin g tabl e ca n occu r. If one of the erro rs

occ urs, the syst em pr ogra m set s the RLO to ’1’ an d write s the er ror

IDs list ed in the tab le to ACCU 1.

ID Meaning

990FH

9910H

9911H

9921H

Multiple call for the block

Wro ng mode ("pro cess in terru pt via IB 0 = on")

I ll egal function numbe r

Delay time illegal

Examples

Table 6-15 Error IDs of OB 153

Def ine and start delay time:

When an AUTOMATIC WARM RESTART is performed, after 5 seconds a certain

STEP 5 operation sequence must be run through once. To do this, the delay

time is defined and started in start-up organization block OB 22.

The STEP 5 operations in OB 22 for calling OB 153:

:L KF +5000 Value for ACCU-2-L: 5000 ms

:L KF +1 Value for ACCU-1-L: function no. = 1 for

: " def ine an d star t delay time"

:JU OB 153 Call OB 153

OB 153: Set/Read Time for Delayed Interrupt

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 51

Stop delay time (cancel job)

STEP 5 operations for calling OB 153:

:L KF +2 Value for ACCU-1-L: function no. = 2 for

: " sto p dela y time "

:JU OB 153 Call OB 153

Read out remaining time of a delay job:

STEP 5 operations for calling OB 153:

:L KF +3 Value for ACCU-1-L: function no. = 3 for

: " rea d out re main ing time"

:JU OB 153 Call OB 153

: ACCU-1-L contains the time the delay job still

: has to run.

OB 153: Set/Read Time for Delayed Int errupt

CPU 948 Programming Guide

6 - 52 C79000-G8576-C848-04

6.16 OB 180: Variable Data Block Access

Using OB 180

You can use OB 180 whe n wor king wit h data blo ck s tha t are lon ge r

tha n 261 words (incl. 5 words he ade r).

Using OB 180 , you can shift an "ac cess win dow" of 256 data words in

step s of 16 words over a data bloc k (at paragr ap h addresse s). Call

OB 180 eac h tim e you wan t to shift the acce ss wind ow furt he r.

In con trast to the CPU 928B, you ca nnot shif t the access win d ow

cont in uousl y but only in st eps tha t are multiples of 16.

Function

Whe n you use OB 18 0, the sta rt addre ss of the curre nt da ta blo ck is

shi fted t owa rds the e nd of the bloc k by the spec if ie d valu e. This t ak es

into acc ount that t he length of DB stil l ava ilab le is reduc e d (DBA and

DBL registers are loaded in keeping with the shift, see Sections 8.3

a nd 9.2.1 ) .

Note

Before calling OB 180, a data block (DB or DX) with an adequate

length must already be open.

Parameters

ACCU-1-L

Shift numbe r S: Numb er of data words, by whic h the data bl ock sta rt

address will be shifted.

Perm itte d val ues: 0 ≤ V < DBL, S = n * 1 6 ( 1 6, 32, 4 8 . . .)

Result

Aft er you ha ve c alle d OB 18 0 succesfully:

•• the relative address of DW 0 is shifted by the value contained in

AC CU-1- L (the DBA and DBL reg ister s are updat ed acc ord ingly) ,

•• the RLO is cleared (RLO = 0),

•• all other bit and word codes are cleared,

•• the content of ACCU-1-L = 0 .

OB 180: Variable Data Block Access

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 53

Possib le error s

The errors l ist ed in th e following tabl e can oc cur. If an err or doe s

occ ur, the syste m progra m set s the RLO to ’1 ’ and ente rs th e erro r IDs

listed in the table in ACCU 1. The other bit and word codes are

cleared.

The val ue s of the DBA and DBL rem ain unc hange d.

ID Meaning

B401H

B410H

B411H

No data block is open

The shift number S is not a multiple of 16

a) The shif t numbe r is too hi gh; the bloc k end is

exceeded by the ne w window position.

b) The shift number is negative.

Settin g the access wind ow

back to the start value

Ope ning t he data b lock a gain with the ope ra tions C DB or C DX

ret urns t he ac cess wi ndow t o its orig ina l posit io n.

Reaction to nesting

If the acc e ss windo w is shif te d by call ing OB 180 in a logic bloc k and

a furt her lo gic bloc k is then ca lle d, the positi on of the ac c ess wi ndow

re ma ins where it is in t he called logic bloc k until OB 180 is called

again (t he DBA/DBL value s do not chang e) .

If, on the other h and, the acce ss windo w is shif ted in a calle d logi c

bloc k by ca lling OB 180, whe n progra m exe c ution ret urns fr om the

called block (block end operation), it is re tur ne d to the positi on it

had when the neste d lo gic block was cal led.

Tabl e 6-16 Er ror IDs of OB 180

OB 180: Variable Data Block Access

CPU 948 Programming Guide

6 - 54 C79000-G8576-C848-04

Example

You want the data block start address (DBA = 4152H in DB 17, length = 256

DW) to be shifted by 32 data words relative to the end of the block.

:C DB 17 open DB 17

:L KB 32 shift value as constant

:JU OB 180 call OB 180: shift access window

After OB 180 has been called, the data word, for example, at address 4

1543H can no longer be addressed with DW 35 but only with DW 3 etc. (see

F ig . 6- 3).

Due to the cha nge made at the same tim e in the DBL register, e rror mon itor ing

is not affecte d: t he o pera tion T D W 22 3 is permitted, while T DW 2 24/L DW 224

causes an erro r.

By calling OB 180 again, the DBA can be increased again (and the DBL

reduced). The operation C DB 17 returns the block to its original settings

(DBA = 4152H, length 256 DW).

If DB 17 had a length of 256 data words for example, you could then no

longer access DW 256 and DW 257 using STEP 5 operations. By shifting the

DBA resgister by 16, data words 256 and 257 can be addressed as "DW 240"

and "DW 241" .

Continued on next page

OB 180: Variable Data Block Access

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 55

Example continued:

4 1520H

4 1530H

4 1540H

4 1541H

4 1542H

4 1543H

4 1544H

4 1545H

4 151FH

4 151BH

DW 0

DW 1

DW 2

DW 3

DW 4

DW 5

DW 6

Address DB 17

DBA

new

5 words

block header

DBA

old

DBL

old

DBL

new

15 0

"32"

"16"

"00"

"33"

"34"

"35"

"36"

"37"

"38"

(4152H)

(4154H)

Fig. 6-3 Shifting the DB start address

OB 180: Variable Data Block Access

CPU 948 Programming Guide

6 - 56 C79000-G8576-C848-04

6.17 OB 1 81: Test Data Blocks (DB/DX)

With the special function organization block OB 181, you can test

dat a blocks a s follows:

•• whe the r or not a partic ul a r DB or DX data block exi sts,

•• the address at which the first data word of the data block is stored,

•• ho w ma ny data wor d s the da ta bl oc k contai ns .

Using OB 181

The func tion "te st DB/DX" is useful bef ore the operations TNB/T NW,

G DB/ GX DX and befo re c all in g spe cia l funct io n orga ni z atio n blo ck s

OB 182, OB 254 and OB 255.

Befo re t ransfe rring dat a words, for exa mple , you ca n call OB 181 to

che c k tha t the de sti na tion da ta bl oc k is vali d a nd lo ng enough for the

transfer.

Function

OB 181 checks whether a specified data block exists and returns the

c hara c teri s tic pa r a meters o f a da ta block .

Parameters

ACCU-1-L

a) ACCU-1-LL

Bl oc k number,

Perm itte d val ues: 1 to 255

b) ACCU-1-LH

Bloc k ID,

Permitted values: 1 = DB

2 = DX

OB 181: Test Data Blocks (DB/DX)

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 57

Result

If the func t ion i s ex ec ut e d wit hout any er ror a nd i f the bl oc k ex ist s on

the CPU, the syste m progr am tran sfe rs the follo wing value s:

- ACCU-1-L: Addre ss of th e 1st data word (DW 0),

2 0-bi t addr ess,

- ACCU-2-L: Lengt h of the d ata bloc k in words (wi th out

b loc k heade r)

Example: ACCU-2-L con tain s the va lue’7’:

T he da ta bloc k consist s of da ta

wo rds DW 0 to DW 6,

- RLO:= 0.

Possib le error s

The er rors list ed in the tab le below c a n occu r. I f an e rr or oc curs, the

syst em pr ogra m set s the RL O to ’1’ and the follo wing con dit io n code

bits as shown i n the tabl e . It also e nters a n error ID in ACCU-1-L .

RLO CC 1 CC 0 AC C U - 1 - L Me ani ng Scan

1 0 1 B501H Bloc k does no t exist JC

1 1 0 B502H Wro ng bloc k numbe r J C

1 1 0 B503H Wro ng bloc k ID JC

Tab le 6-1 7 Er ror cod es of OB 181 a nd t hei r s ca ns

OB 181: Test Data Blocks (DB/DX)

CPU 948 Programming Guide

6 - 58 C79000-G8576-C848-04

6.18 OB 182: Copy Data Area

Function

OB 182 copies a data area of variable length from one data block to

anot he r. The sourc e and dest inat ion blocks c a n be DBs or DXs. The

start of the area in the source and destination blocks can be freely

se lec ted. OB 182 can c opy a maxi m um of 4091 dat a words.

Note

The source and destination block can be the same. The data areas of

the source and destination can overlap. Even if they overlap, the

original data of the source a rea are copi ed uncha nged to t he

destination are a. The are a of the ove rlap in the source is

overwritten a fter the copy function. Y ou c an us e this t o s hift a dat a

area w ithin a bloc k.

Parameters

1st data fi eld with par am e ters fo r copy functi on

Be fo re c a ll in g OB 182 ma ke a da ta fi el d ava il ab le wit h the pa ra m et e rs

fo r the copy fu nc ti on. Th is da ta fi eld c an b e set up in a DB o r DX dat a

bl oc k or i n the F or S fla g are a .

The da ta fiel d ide nt if ie s the source a nd de sti na ti on bl oc ks, the sta rt

addr ess of t he area in both bloc ks and t he num ber of data word s to be

copi e d. It consi sts of five words:

Bit no. 1 5 8 7 0

1st word Sour ce DB type Sourc e DB no.

2nd word No. of 1st tra nsfe rr ed dat a word in sourc e DB

3rd word De stina tion DB ty pe Desti na tion DB no .

4 th word No. of 1st transf er re d data word in the desti na ti on DB

5th word No. of data words

OB 182: Copy Data Area

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 59

The para meters have the following significance and range of value s :

Par ame te r Per m itt ed range of va lue s

Data block type (sourc e and dest ination ) 1 = DB

2 = DX

Da ta block n o. (source an d desti nation) 3 to 255

No. of 1st data word (sourc e and

destination) 0 to 4090

Numbe r of dat a words 1 to 4091

Data field in flag area

If you set up the data field in a flag area, you must take into account the

following assignment of data field words to flag bytes. ’x’ is the

parameter "no. of the 1s t data fie ld word" which you m ust e nter in

ACCU-1-L when OB 182 is called:

Bi t no. 15 87 0

1st data fiel d word Flag by te x Flag byte x+1

2nd data fiel d word Flag byte x+2 Fla g byte x+3

3rd data fiel d word Flag byte x+4 Fl a g byte x+5

4 th da t a fi e ld w ord Fla g byte x+ 6 Flag byte x+ 7

5 th da t a fi e ld w ord Fla g byte x+ 8 Flag byte x+ 9

2. Accum ulators

2a) ACCU-2-L

ACC U-2-L c ont ains in form a ti on about the dat a fie ld used. It must

have the foll owin g stru cture :

Bi t no. 15 8 7 0

Address a re a type Da ta bloc k no.

Para m ete rs in ACCU-2-L

Address area type,

Pe rmit te d va l ues: 1 = DB da ta bl oc k

2 = DX data block

3 = F flag area

4 = S flag area

Data block no.,

Permitted values: 3 to 255 (only with address area type ’1’ or ’2’;

with address area type ’3’ or ’4’ irrelevant)

OB 182: Copy Data Area

CPU 948 Programming Guide

6 - 60 C79000-G8576-C848-04

2b) ACCU-1-L

Num be r of the 1st da t a fie ld wor d,

po ssibl e value s (de pe ndi ng on the

addr ess a re a type : DB , DX: 0 to 2038

F fla gs: 0 to 246

(= No. of flag byte ’x ’ )

S fla gs 0 to 4086

(= No. of flag byte ’x ’ )

Result

Aft er co rre ctl y proce ssin g OB 182: RLO, cond it ion cod e bits OR,

ERAB and OS = 0.

Possib le error s

If an erro r occu rs, an erro r ID is ente red i n ACCU 1 (see table belo w).

ACCU-1-L Meaning

B601H

B60FH

B611H

B612H

B613H

B621H

B622H

B623H

B624H

B625H

B626H

B627H

B628H

B629H

B62AH

B62BH

B62CH

Data block not loaded

Mul ti ple block call

I nc orre c t cont e nt i n the da ta fiel d

Address area type illegal

Da t a bl oc k no. ille gal

"Number of the 1st data field word" illegal

"Source data block type" illegal

"Source data block no." illegal

"No. of the 1st da t a wor d to be transmitt e d in sou rce

DB" illegal

Length of the source data block in the block header

< 5 word s

"Destination data block type" illegal

"Destination data block no." illegal

"No. of 1st data word to wri tten in destinati on

DB" i ll eg al

Le ngth of the dest in at ion block in bl oc k header < 5

words

"Numb er of data words to be tra nsm itted" i lleg al

(= 0 or > 4091)

Source data block too short

Desti n ation data block too short

Tab le 6-1 8 Er ror IDs of OB 182 i n ACCU-1-L

OB 182: Copy Data Area

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 61

6.19 OB 202 to 205: Multiprocessor Communication

A de ta i led de s c rip ti on of t he se s pe c ia l f unc ti on or ganiza ti on bl oc k s

ca n be found in Cha pt er 10.

The spe cia l funct io n orga ni z atio n blo ck s OB 200 and OB 202 to

OB 205 allo w data tra nsfe r betwee n the indi vidua l CPUs using the

coor din at or COR C in mult iproc e ssor opera t ion .

•• OB 200 : ini tia lize

This special function organization block s et s up the me mory in t he

COR C c oordinator in which the bloc ks of data to be tra ns ferred a re

buffered.

•• OB 202: send

Thi s func t ion tra nsfe rs a blo ck of data to the buffe r of the COR C

and speci fie s how m a ny bloc ks of da ta can stil l be se nt.

•• OB 203 : send test

The special function OB 203 checks the number of free memory

fields in the buffer of the COR C.

•• OB 204 : rece ive

Thi s func t ion a cc ep ts a b lock of data from the COR C buffe r a nd

indicates how many blocks of data can still be received.

•• OB 205 : rece ive tes t

The special function organization block OB 205 checks the number

o f occu pied m e mory fi el ds in the COR C buffe r.

OB 202 to 205: Multiprocess or Communic ation

CPU 948 Programming Guide

6 - 62 C79000-G8576-C848-04

6.20 OB 222: Restart Cycle Monitoring Time

The spe ci al fun ction OB 222 ca use s the cy cle mon it ori ng tim e to be

restarted, i.e. the timer for monitoring is started from the beginning.

By calling this special function, the maximum permitted cycle time for

the current cycle is extended by the value selected at the time of the

call.

Parameters

none

Possib le error s

none

OB 222: Rest art Cycle Monitoring Tim e

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 63

6.21 OB 223: Compare Start-Up Modes

Function

By ca ll in g OB 223, you can c he ck whet he r th e star t-up mo de s of all

CPUs invol ve d in multipro ce ssor opera tion are the same and able to

exe c ute a progr am me d reac t ion to error s.

Parameters

none

Result

Aft er cal ling OB 223 , the syste m progr am sets th e RLO to ’0’ and

writes the value 01H to ACCU-1-LL when the start-up modes are the

same.

Possib le error s

•• Start-up modes are not the same

•• Othe r errors, re fer to con ditio n code bits

Condition code bits

If an erro r oc cu rs, the system prog ra m sets t he RLO t o ’1’ and

tra nsfe rs a n error ID to ACCU-1 -L L.

ID Meaning

01H

02H

03H

04H

St art-up mode s the sa me

Inte rnal system er ror

St art-up mode s not the sam e

Si ngl e proc e ssor mode, compa ri son of start- up

mod es not possibl e

Tabl e 6-19 Results IDs of OB 223 in ACCU-1- LL

OB 223: Compare Start-Up Modes

CPU 948 Programming Guide

6 - 64 C79000-G8576-C848-04

6.22 OB 254/255: Copy/Duplicate Data Blocks

Wit h the spe cia l f unc tions OB 25 4/255, you copy individua l dat a

blocks from a memory card to the user memory or duplicate individual

data blocks within the user memory.

The spe cia l funct ion OB 254 a nd OB 25 5 work ide nti cal ly , with

OB 25 4 excl usi ve ly fo r DX dat a blocks and OB 25 5 for DB dat a

blocks.

Note

During the copyi ng or dupli cat io n, the use r interrup ts a re blocke d.

No tim ed int errupts or proc ess i nte rr upt s a re a cce pt ed .

Application

Co pyi ng da ta bloc ks from th e me mo ry c ar d or dup li cat ing dat a bloc k s

in the use r memory and assi gni ng a new bloc k numb er .

Copying

Conditions

By using the "copy" func t ion of the two speci al func t ion OBs

(OB 254 or OB 25 5 cal l), re mem be r the foll owi ng conditions:

•• The mem or y card must be plugge d in befor e the OVERALL

RESET and must not be remov ed afterwa rds

•• The de sti na ti on da ta bl oc k mu st not yet e xist

•• The onl ine fun ctio n "co mpre ss me m ory" must not be act iv e

Function

A data block is copied from the memory card to the user memory and

retains its original block number. The start address is entered in the

addr ess l ist in DB 0.

OB 254/255: Copy/ Duplicate Data Block s

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 65

Parameters

1. ACCU-1-LL

Number of t he blo ck t o be co pie d.

The fol lowi ng bloc k num bers a re possible :

Bloc k type Block num ber

DB (OB 255)

DX (OB 254) 3 to 255

3 to 255

2. ACCU-1-LH

ACC U-1-L H m ust be z ero.

Duplicating

Function

A data bloc k is duplica ted within the user me mory a nd it is assig ned a

different block number. The start address of the new data block is

ent er ed in the addr ess l ist i n DB 0. The star t addre ss of t he old bloc k is

retained, i.e. the original data block remains valid.

The start address is entered in DB 0 only after the transfer is

com plete d an d al l the IDs are corre c tl y e nte re d i n the bl oc k he ad er .

The dupl ic a ted bl oc k is t he re fore onl y de cla re d va li d or exi ste nt b y the

syste m progra m afte r it has been c ompl et ely tra nsfe rre d.

Parameters

1. ACCU-1-LL

Num ber of the blo ck to be duplic a ted (so urc e ).

2. ACCU-1-LH

Number of the new block (destination).

The fol lowi ng bloc k num bers a re possible :

Bloc k type Block num ber

DB (OB 255)

DX (OB 254) 3 to 255

3 to 255

OB 254/255: Copy/Duplic ate Data Blocks

CPU 948 Programming Guide

6 - 66 C79000-G8576-C848-04

Result foll owing copyi ng

and dupli cati ng

Afte r the fun ctio n has been exe c uted corr ec tly and erro r-fr ee , the

syst em pr ogra m sets the RLO to ’0 ’ and cle ar s the co ndi tion c ode bits

CC 1 and CC 0.

Cal ling OB 254 /25 5 chan ges the content s of ACCU 1 to ACCU 4.

The BR register is retained.

Possib le errors and

warnings when copying and

duplicating

If an erro r or warni ng occ urs, the system progra m stops pr oc essi ng

OB 25 4/2 55 a nd c ont inu es pr ogra m ex ecution at the next STE P 5

op erat io n. It a lso se ts the RLO t o ’1’ and wri te s a n ID to ACCU-1-LL

(refer to Table 6-18).

If the funct ion i s abort ed due to a warn ing , it may be possibl e to run

OB 25 4/2 55 c orre ctl y by c all ing t he speci a l funct io n agai n (i f

necessary, repeated several times).

In the fol lowi ng si tua tion, OB 254/2 55 is a bor te d with a warning:

an OB 124 , OB 125, OB 254 or OB 25 5 has bee n ca ll ed duri ng th e

last 10 ms. (Du rin g a peri od of 10 ms, howeve r, only one spe cia l

function OB call is permitted. This prevents multiple calls for the OBs

listed abo ve pre ve nting t he inter fa ce to the PG f rom be ing proc e ssed .)

Condition code bits

fo ll ow i ng copyi ng and

duplicating

Aft er OB 254/ 255 is ca l led, you ca n see wheth er t he spe ci al fun ctio n

has be e n carr ied out corre c tl y or wheth er it was stop pe d by an "error"

or "wa rning" based on the re sult of logic opera t ion a nd t he condition

code bi ts CC 1 and CC 0 . The result can be eva lua t ed by conditi ona l

jum p ope ra tions.

Result codes

RL O CC 1 CC 0 Meaning Scan

0 0 0 Spec ial function c orr ect ly

processed JB

1 1 0 Spec ial function a bor ted

wi th " warni ng " JB

1 0 1 Spec ial function a bor ted

wi th "e r ro r " JB

Table 6-20 Res ul t code s for OB 254/255

OB 254/255: Copy/ Duplicate Data Block s

CPU 948 Programming Guide

C79000-G8576-C848-04 6 - 67

IDs in ACCU-1-LL

The system progra m sets IDs in ACCU-1 -LL whic h speci fy the ca use s

of a warning or erro r in more deta il.

Bit no. 7 6 5 0

W E Cause of erro r/warning

The fol lowi ng gr oup c ode s a ppl y:

Bi t no. 7 (W) = 1:warn ing

Bi t no . 6 (E) = 1:e rr or

ID Meaning

01H Function correctly executed

41H

43H

48H

4AH

4BH

4CH

4DH

4EH

Error:

Bl oc k he ader on me m ory c a rd i nva li d

Not eno ugh m e mo ry spa c e

Source da ta bl oc k does not exist

Block numbe r or type illegal/sour ce DB

Bl oc k num ber or type ille gal/ de sti nati on DB

De sti na tion da ta bloc k al rea dy e xist s in the user

memory

Online fun ction COMPRE SS MEMOR Y ac tive

No memory card plugged in

8DH

8EH

Warnings:

Con fli c t with a n onl ine fun ct io n ex cept "co mp re s s

memory"

10 ms wai ti ng t im e n ot ye t el apsed

Examples

Ta bl e 6-21 R e sul t IDs f or OB 254/255 i n ACCU-1-LL

1. "Cop y":

:L KY 0,120 This sequence of operations copies

:JU OB 254 the data block DX 120 from the

: memory card to the user memory

2. "Dup licate":

:L KY 80,85 This sequence of operations

:JU OB 255 duplicates data block DB 85; the

: new data block has the number 80.

: The contents of DB 80 and DB 85

: are id entical.

OB 254/255: Copy/Duplic ate Data Blocks

CPU 948 Programming Guide

6 - 68 C79000-G8576-C848-04

Cont ents of Ch apter 7

7.1 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4

7.2 S tru cture of DX 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 5

7.2.1 Ex ample of Input in DX 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 7

7.3 Para meters for DX 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 8

7.4 Exam ples of Param ete r Assignm e nt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 12

7.4.1 STEP 5 Programmi ng. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 12

7.4.2 Para m eter Assignm ent using the PG Screen Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 14

Extended Data Block DX 0

CPU 948 Programm in g Gui de

C79000-G8576-C848-04 7 - 1

Contents

CPU 948 Programming Guide

7 - 2 C79000-G8576-C848-04

7Extended Data Block DX 0

The fol lowi ng cha pt er explain s how to use the dat a bloc k DX 0 and

ho w it is st ruc tured. You wil l find i nfor mat ion ab o ut the me a nin g of

the var iou s DX 0 para m e ters a nd wil l lea rn h ow to cre ate and how to

assig n para meter s for a DX 0 dat a block base d on examp les.

CPU 948 Programming Guide

C79000-G8576-C848-04 7 - 3

7.1 Application

You can ada pt certai n syste m prog ram func tions to me et your own

re qu ire m e nts by sel ec t ing a l ternative de fa ul ts in DX 0 com pa red to the

stan da rd defa ul ts (ma rke d in the para me ter ta ble by "D").

The defa ults of th e syste m progra m (D) are aut om ati cal ly set during

ea ch COLD RESTART and DX 0 is the n eva lu ate d. If you ha ve not

assig ned para meter s in DX 0 and loaded it, the defaul ts remain valid;

otherwise the defaults you have selected in DX 0 become the valid

settings.

You c an m ak e sett in gs in DX 0 by progra m m ing the value s ju st a s i n

any normal data block (refer to Section 7.2 to 7.4.1) or using the PG

syste m softwa re S5-DOS from Ve rsion 3.0 onwa rd s, you can ent er the

values as parameters in a special screen form on your PG (refer to

Se ction 7. 4.2).

You ca n m ak e use of t he full ra nge of fun ct ions of the DX 0 sc reen

fo rm if the PG softwa re STE P 5/ST , Ver sion 6.3 or STEP 5/ MT,

Ve rsi on 6.0 pl us the corre sp o ndi ng "De lt a diske tt e CPU 948" is

insta l le d on your PG.

Note

The s ettings or modifications m ade in DX 0 only become effe ct ive

following a CO L D REST ART.

If a modified DX 0 is read during a COLD RESTART, the

unmodified parameter assignments are retained.

Differences com pared with

the CPU 946/947

Co mpar ed with DX 0 para m ete r assign me nt for the CPU 9 46/ 947,

the re are va rious di ffe re nc e s when as si gni ng DX 0 pa ra met er s for th e

CPU 948, as follo ws:

•• Modes:

The re is no long er a 150 U/15 5U mo de , inste ad of t his, ther e is

n ow "inte rr uptabi lity at block boundar ies " an d

"inte r rupt ability at operati on boundarie s".

•• Proce ssing syst em interru pts:

Wi th the CPU 948, you ca n now also c om bi ne "proc e ss int er rupt s

v ia IB 0 = o ff" (= syste m inte rrup t proces si ng) wi th

"inte r ruptabil ity at block boundaries".

Thi s mea ns that multipr ocesso r opera tion i s now also possi ble in

the "int erruptabi li ty at bloc k bou nda ri es" mode.

•• Addit ional ti me d interr upts:

I f you swi tc h off the mo de "proc e ss int er rupt s via IB 0", th e

additional timed interrupts the delayed int er rupt (O B 6) and the

cl oc k-c ontr olle d inte rr upt (O B 9) ar e avail able .

Application

CPU 948 Programming Guide

7 - 4 C79000-G8576-C848-04

7.2 Struc ture of DX 0

DX 0 consi sts of thre e p arts:

•• the start ID for DX 0 (DW 0, 1 and 2) ,

•• se ve ra l fi e lds of d iff er en t lengths (dep en ding on th e numb er o f

parameters)

and

•• th e en d ID .

Start ID

ASCII characters MASKX0 in DW 0 to DW 2

Field

A field in DX 0 consists of on e to n data words. The se cont a in the

foll owin g:

•• the fiel d ID,

•• the fiel d length

and

•• the fiel d parameter s.

Field ID

The field ID specifies the meaning of the parameters following it.

Ea ch fie ld is assigne d t o a spec if ic syste m progra m sec tion or to a

spe c if ic system function (e. g. the fie ld ID "04" ide nt ifi es the pa rameter

fi eld fo r cycl ic pr ogra m execution).

Field length

The f ield length spec ifie s how ma ny dat a words are occup ie d by the

parameters.

Parameters

The possi ble parameters are listed in Section 7.3. The specified

nume ri cal values a re in hexa dec ima l format (KH).

End ID

Thi s indi c ate s the end of DX 0 wit h EEE E H i n the last da ta word.

Structure of DX 0

CPU 948 Programming Guide

C79000-G8576-C848-04 7 - 5

Formal str uctur e

Field ID 1 Field length 1

Field ID 2

Field ID n Field length n

Field length 2

Parameter

ASCII

chars:

Field 1

Field 2

Field n

End ID

15 8 70Bit no.

DW m

EEE E

Parameter

Fig. 7-1 Structure of DX 0

Structure of DX 0

CPU 948 Programming Guide

7 - 6 C79000-G8576-C848-04

7.2.1

Example of Input in DX 0

Whe n assign ing param e ters fo r DX 0, note the follo wing poin ts:

•• Unnece ssa ry fields do not need to be spec ifie d.

•• Ma in tain the orde r of the fiel ds (e .g . spec ify the fiel d with ID ’02 ’

before th e fie ld wi th ID ’05’).

•• A specific field must only occur once in DX 0.

•• The num be r of pa ra m e te rs m ust correspond t o the fiel d length

specified at the beginning of the field.

•• Maintain the order of par am e te rs. Unne cessary pa ra me t er s towards

the beginni ng of the field must be assi gne d th e defa ul t to ensure

that the parameter order is maintained.

•• Close DX 0 after entering the last field with the end identifier

"KH=EEEE".

Start ID DW 0: KH = 4D41

DW 1: KH = 534B

DW 2: KH = 5830

Field ID/length DW 3: KH = 0101

Parameters (occupies 1 DW) DW 4: KH = 1001

Field ID/length DW 5: KH = 0402

Parameters (occupies 2 DW) DW 6: KH = 1000

DW 7: KH = 0040

End ID DW10: KH = EEEE

Field 1

Field 2

Structure of DX 0

CPU 948 Programming Guide

C79000-G8576-C848-04 7 - 7

7.3 Parameters for DX 0

Field ID/length Paramete rs

1st/2nd wor d Meani ng 1)

Modes

01xx 2) 1000

1001

D Interrupts at block boundaries 3)

(CPU 946/ 947 : 150 U mod e)

Interrupts at operation boundaries 4)

(CPU 946/ 947 : 155 U mod e)

Start -up pro gram exe c ution

02xx 1000

1001

1002

D AUTOMAT IC WARM RE ST ART afte r POWER UP

AUTOMAT IC COL D REST ART afte r POWER UP

MANUAL COLD/WARM RE START af ter POW ER UP

2000

2001 D Sy nchron iza tion of START -UP in the mu ltiproc esso r mode

No synchron iz ation of START -UP in the multipr ocesso r

mode

BB00 00yy 5) Number of timers to be updated yy: 6)

Perm i tted value s: 00H t o FF H

D yy = F F (time r T 0 t o T 255)

4000

4001 D Rest art type = WARM REST ART

R est art type = RET E NTI VE COLD RE ST ART

Cycli c progr am exec ution

04 xx 10 00 00yy Se tti ng the cyc le m oni tor ing tim e: 7)

Cycle monitoring time = (yy * 10 ms)

Perm i tted value s: 01H t o FF H

D yy = 14H (200 ms )

4000

4001

D Updating of the process image and IPC flags without

sem a phor e protec tion

Up da ting th e pr oc ess ima ge and IPC fl a gs wit h sem apho re

protection (in the field, refer to Section 10.1.3)

Int err upt se rvic ing : timed inte rrupt s

05xx 1000 000c

1001 0000 D Timed inte rr upt servic ing "on"

Timed interrupt servicing "off"

c = level priority, permitted values: 1 to 5

D c = 1 ( hig he st le ve l prio rit y )

Table 7-1 DX 0 parameters and their meaning

Parameters for DX 0

CPU 948 Programming Guide

7 - 8 C79000-G8576-C848-04

Field ID/length Paramete rs

1st/2nd wor d Meani ng 1)

Table 7-1 continued:

05xx I nt err upt se rv icing : time d inte r rupt s (cont. )

20 00 00yy Basic cloc k ra te for tim e d inte rrup t servi ci ng:

B as i c c l ock rate = (y y * 10 ms )

Perm i tted value s: 01H t o FF H

D yy = 0A (100 ms )

3000

3001 D Clock rat e di s tribu ti on a cc ordin g to i nte r v al 1 (1, 2, 5, 10)

C loc k ra t e distr ibuti on acc or ding to inte rv al 2 (2n)

(Refer to Section 4.5.2)

Inter r upt ser vic ing: proce ss inte rr upts via S5 bus/syste m inte r rupt s

4000 000c

4001 0002 System interrupt X "on"

D System interrupt X "off" c = level priority,

Permitted values: 1 to 5

X = A, B, C or D

V c = 2 (level priority 2)

(The ser vici ng of system

in terru pts c a n also be

combined with

"int erruptability at block

bou nda ri es" wi th the

CPU 948.)

5000 000c

5001 0002 System interrupt E "on"

D System interrupt E "off"

6000 000c

6001 0002 System interrupt F "on"

D System interrupt F "off"

7000 000c

7001 0002 System interrupt G "on"

D System interrupt G "off"

8000 000c

8001 0000 D Proc ess i nterr upt s via IB 0 "off"

Pr oc ess inte rr upt s via IB 0 "on"

c = level priority, permitted values 1 to 2

D c = 2 (level priority 2)

Whe n "pr oc ess inte rr upt s via IB 0 = on":

- on ly single proc esso r mode,

- on ly "i nterr upt ab il ity at blo ck bound ar ie s".

EEEE End ID

1) D = default with DX 0 not loaded or not present.

2) xx = field length (number of data words occupied by the parameters).

3) With t he CPU 948, can also be combined with a system interrupt.

4) Must not be combined with process interrupts via IB 0.

5) When specifying the field length, the value "2" must be t a ken into account for parameters occupying two data words.

6) For updating the timers, please read the explanation on the following page.

7) Set cycle monitoring time with OB 31 or DX 0: If the cycle monitoring time is set both with OB 31 and with DX 0, the system

program uses the setting made in OB 31 since it has already evaluated DX 0. For this reason, you should only use one of these

possibilities. W e reco mmend setting the cycle monitoring time using DX 0.

Parameters for DX 0

CPU 948 Programming Guide

C79000-G8576-C848-04 7 - 9

Updating the timers

•• As sta nd ar d, the time rs T 0 to T 255 are updat ed .

•• If you e nte r the val ue "0" in DX 0, no time rs a re updat ed , eve n if

the y are i nclu de d in the progr am . Th ere is the n also no err or

message output.

•• Updatin g is as follows:

Entry ’0’ ’1’ ’2’ ’3’ ’4’ ....

Upda ting no ne T0 to

T1 T0 to

T2 T0 to

T3 T0 to

T4 ....

Level priorities

You can spe c ify diff er en t pri ori ti es for th e program exec ut io n leve ls.

Thi s i s achie ve d either using the defa ult or by specif yin g DX 0

parameters.

Pr iori ties whe n "proc e ss inte rr upts via IB 0 = on" is sele ct ed

(PRO CESS INTERRUP TS level)

The se prio ritie s ha ve the fol lo wing defau lt val ue s in DX 0:

•• tim e d inte rrup ts: le ve l priori ty 1 ( hig he r priority)

•• Proce ss interru pts

v ia inp ut by te IB 0: leve l pri ori ty 2 (lower pr ior ity)

Yo u ca n s wap ove r the pr i orities in DX 0.

Pr iori ties whe n "proc ess inte r r upts via IB 0 = off" is se lec te d

(= proce ssing of system inte rrupts lev el INTERRUPTS)

In thi s m od e, the fo llowin g de fa ult pri ori ti es are set:

•• tim e d inte rrup ts: le ve l priori ty 1 ( hig he r priority)

•• syst em inte rr upt s:le vel pri ori ty 2 (lowe r pr ior ity)

Parameters for DX 0

CPU 948 Programming Guide

7 - 10 C79000-G8576-C848-04

You ca n modi fy these pri ori tie s for the fo llowin g prog ra m exec uti on

levels individually in DX 0, by specifying the priority value from ’1’

to ’5’ (t he value ’1’ me a ns hig he st priority ):

•• time d inte rrup ts

•• syste m interr upt INT X (X = A, B, C or D),

•• syste m interr upt INT E,

•• syste m interr upt INT F,

•• syste m interr upt INT G.

Example

Assignment of priorities for interrupt servicing

"system in terr upts ":

S ys te m interrupt INT A/B/ C/D

level priority 1

Timed interrupts level priority 2 descending

System interrupt INT E level priority 3 priority

System interrupt INT F level priority 4

System interrupt INT G level priority 5

Parameters for DX 0

CPU 948 Programming Guide

C79000-G8576-C848-04 7 - 11

7.4 Examples of Parameter Assignment

7.4.1

STEP 5 Programmin g

Example A:

You want to use three CPUs in the multiprocessor mode: CPU A, B and C. CPU

A and B work closely with each other, often exchange data and execute a

complicated start-up program.

CPU C executes a short, time-critical program largely independent of A and

As standard, all CPUs operating in the multiprocessor mode start cyclic

program execution together, i.e. the CPUs wait for each other until they

have all completed their start-up and then change to cyclic program

executio n toge ther .

Since CPU C executes its program independently of the other CPUs and has a

very short start-up program, there is no need to synchronize its start-up

with the others. By assigning parameters in DX 0, CPU C can start its

cyclic program immediately after completing the start-up without waiting

for CPU A and B.

The parameter for synchronizing the CPUs in the multiprocessor mode is the

second parameter in the first field. To maintain the order of the

parameters, the first parameter for the start up must have the default

value (AUTOMATIC WARM RESTART after POWER UP).

Program DX 0 for CPU C as follows:

DX 0 Start ID "MASKX0" DW 0: KH = 4D41

D W 1: KH = 53 4B

D W 2: KH = 58 30

1st field ID/length DW 3: KH = 0202

Parameter 1 DW 4: KH = 1000

Parameter 2 DW 4: KH = 2001

End ID DW 5: KH = EEEE

Once you have loaded this DX 0 in the program memory, it becomes effective

at the next COLD RESTART. Since CPU C runs through a very short start-up

program and does not wait for A and B, its green RUN LED lights up

immediately following start-up. The BASP signal (disable command output)

i s, how ever, only deactiv ated when all three CP Us hav e completed their

start-up. This means that CPU C cannot access the digital I/Os.

Examples of Parameter Assignment

CPU 948 Programming Guide

7 - 12 C79000-G8576-C848-04

Example B:

The parameter assignment for DX 0 shown below achieves the following:

- the mode "interrupts at operation boundaries" is set,

- the timer updating is switched off,

- the cy cle time is se t to 2.5 seconds,

- the level priority of timed interrupts is set to ’2’

and

- the system interrupt INT E is activated with level priority ’1’.

DX 0 Start ID "MASKX0" DW 0: KH = 4D41

D W 1: KH = 53 4B

D W 2: KH = 58 30

1st field ID/length DW 3: KH = 0101

Parameters DW 4: KH = 1001

2nd field ID/length DW 5 KH = 0202

Parameters 1) DW 6: KH = BB 00

D W 7: KH = 00 00

3rd field ID/length DW 8 KH = 0402

Parameters 1) DW 9: KH = 10 00

D W10: K H = 00FA

4th field ID/length DW11: KH = 0504

Parameters 1) DW12: KH = 1000

D W13: K H = 0002

Parameters 1) DW14: KH = 5000

D W15: K H = 0001

End ID DW16: KH = EEEE

This parameter assignment in DX 0 has the following effects on program

execution:

Program execution is interrupted by higher priority levels at operation

boundaries instead of at block boundaries.

The runtime of the system program is slightly reduced since no timers are

updated.

A cycle error is only recognized when the runtime of the user program and

the system program together exceeds 2.5 seconds.

No process interrupts from input byte IB 0 are processed, but rather system

interrupt INT E. Owing to its higher priority, this interrupts timed

interrupt servicing, the processing of the delayed interrupt and the

processing of a timed job.

1) Under "field length", specify the number of data words occupied by a

parameter!

Examples of Param eter Assignment

CPU 948 Programming Guide

C79000-G8576-C848-04 7 - 13

7.4.2

Parameter Assign ment

using the PG Screen For m With the PG system softwa re , scree n form s are ava i labl e for assigni ng

para m ete rs in DX 0 for the CPU 948. The PG softwa re auto ma tic a lly

ge ne ra t es data bl oc k DX 0 ac c ording t o th e de fa ul t pa ra m e te r s (va l ues

in bol d face )and par ame ters yo u ha ve spec i fied. To assign pa ra me ter s

to DX 0, two screen forms are required.

How to s elect and complete the PG s c ree n form s is e xpla ined in your

STEP 5 manual.

Structure of the screen forms

Two sc re en forms ar e requ ired for co mple ting para me ter assign me nt

to DX 0:

The first sc re en form (Fig . 7-2) cont ai ns th e pa ram e ter gro ups

- Inter ruptabil ity,

- Resta rt aft e r power up,

- Warm restart proce dure,

- Nu m ber of ti m er c e ll s ,

- Cycle tim e monitorin g,

- Synchro nize multipr ocesso r resta rt,

- Block tra nsfe r of the IPC flag s.

DX 0 - param. ass. (S5-155U CPU 948)

Restart after power up:

Interruptability:

(1 = warm restart

2 = cold restart

2 = cold restart with memory)

(0...256)

DX 0

for "interruptability at operation boundaries"

for "interruptability at block boundaries"

Mode 155U

Mode 150U

with older PG-software versions the following is displayed:

(1...255)

3 = manual start)

Warm restart procedure:

Number of timer cells:

Cycle time monitoring (x 10 ms):

Synchronize multiprocessor restart:

Block transfer of the IPC flags:

F1 F2 F3 F4 F5 F6

Continue

Select F7 F8

at block bounds.

256

YES

Fig. 7-2 PG screen form for assigning parameters to DX 0 / Part 1

Examples of Parameter Assignment

CPU 948 Programming Guide

7 - 14 C79000-G8576-C848-04

If you m ove on to the sec on d scr een fo rm (Fig. 7-3 ) you wi ll find the

foll owin g para met ers:

- Tim e inte rr upt s,

- Hardwa re proc ess int er rupt s,

- Proce ss int errupts input byte 0.

Using the screen forms

The fol lowi ng fl ow c ha rt expl a ins ho w to c om ple t e the scre e n forms

and fi e lds, how to sav e the par ame te rs and l oa d a gene ra t ed DX 0 dat a

block.

DX 0 - parameter assignment (S5-155U CPU 948) DX 0

YES

YES 1

Process interrupts:

Process interrupts input byte 0 (only with interruptability at block boundaries)

Hardware process interrupts:

System interrupt G:

System interrupt F:

System interrupt E:

System interrupt A/B:

Time interrupts:

Time interrupt servicing:

Priority:

( 1 . . . 255 )

2) CPU 948: System interrupts can be serviced with "interruptability at

block boundaries" or "interruptability at operation boundaries"

1) The delayed interrupt and clock-controlled interrupt must, if necessary, be activated extra

by switching off process interrupts (interrupt servicing on)

( 1 = factor 1, 2, 5, 10

2 = factor 1, 2, 4, 8 )

Basic clock ( x 10 ms ):

Clock pulse processing: 1

6Continue

Select F

Fig. 7-3 PG screen form for assigning parameters to DX 0 / Part 2

Examples of Param eter Assignment

CPU 948 Programming Guide

C79000-G8576-C848-04 7 - 15

Flow chart for complet ing the

DX 0 screen forms

Example

NO YES

Repeat the following procedure until you have made all the necessary

changes in the form:

Position the cursor on the parameter field. The display field F3

at the bottom of the screen indicates whether or not you can select

from different alternatives (SELECT displayed) or change the

parameter value (INPUT displayed).

Are there parameters to be changed in the 2nd screen form?

Are there parameters to be changed in the 1st screen form?

NO YES

Press F6 (CONTINUE); the second screen form is displayed.

Change parameters as explained above for screen 1.

Now press the enter key. The PG software accepts all the parameter

settings from the two screens and generates data block DX 0.

DX0isstoredonthePG.YoucanloaditonthePLCwiththePG’s

TRANSFER function.

- Select the input field:

- SELECT:

Press F3 until the alternative you require is displayed.

- INPUT:

Press F3 once; the cursor jumps to the start

of the field. You can now overwrite the field

with a permissible numerical value.

You want to assign parameters in DX 0 to achieve the following system

program response (different from the defaults):

- mode "interrupts at operation boundaries",

- no ti mer up dating,

- cycle monitoring time = 2.5 seconds,

- level priority for timed interrupts = 2

- system interrupt INT E with priority = 1 .

Continued on the next page

Examples of Parameter Assignment

CPU 948 Programming Guide

7 - 16 C79000-G8576-C848-04

Continuation of the example

Complete the screen form as follows to obtain this response:

First DX 0 screen form:

•• For the MODE parameter, select "interruptability at operation boundaries"

with function key F3.

•• For the parameter NUMBER OF TIMER CELLS first press function key F3 and

then type in the number 0 (= no timer) .

•• For the CYCLE MONITORING parameter, first press function key F3 and then

type in the number 250 (= 2.5 seconds).

•• Press function key F6 (CONTINUE). The second DX 0 screen form is

displayed.

Second DX 0 screen form:

•• For the TIMED INTERRUPT/PRIORITY parameter, select the value ’2’ with

function key F3.

•• For the SYSTEM INTERRUPT E parameter, select the setting ’yes’ with

function key F3.

•• For the SYSTEM INTERRUPT E/PRIORITY parameter, select the value ’1’ with

function key F3.

•• For the PROCESS INTERRUPTS parameter, select the setting ’no’ with

function key F3.

•• Press the enter key to confirm your input. Data block DX 0 is then

generated by the system software.

Examples of Param eter Assignment

CPU 948 Programming Guide

C79000-G8576-C848-04 7 - 17

Examples of Parameter Assignment

CPU 948 Programming Guide

7 - 18 C79000-G8576-C848-04

Cont ents of Ch apter 8

8.1 Structure of the Memory Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 4

8.2 Mem ory Assignment in the CPU 948 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 5

8.2.1 Memory Assignment for the Sy stem RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 6

8.2. 2 Mem ory Assign me nt fo r the Periphe ra ls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 8

8.3 User Memo ry Orga nization in the CPU 948. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 10

8.3.1 Blo ck Headers in User Me mory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 12

8.3.2 Blo ck Add r ess List i n Data Block DB 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 13

8.3. 3 RI/RJ Are a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 14

8.3.4 RS /RT A rea. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 15

8.3. 5 Bit Assignment of the System Data Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 18

8.3.6 Addressable Syste m Data Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 42

Memory Assignment and

Memory Organization

CPU 948 Programm in g Gui de

C79000-G8576-C848-04 8 - 1

Contents

CPU 948 Programming Guide

8 - 2 C79000-G8576-C848-04

8Memory Assignment and

Mem ory Org aniz ation

You c a n use thi s ch ap te r a s a re fe re nce sec ti on t o ch ec k on t he

or ganiz a tion of the CPU 948 me mo ry. Th e chapt er a lso inc l ude s

imp ort an t inform a tion c ont a ined i n some of the system data words.

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 3

8.1 Structure of the Memory Area

The memory of the CPU 948 is esse nt ial ly divide d into the followin g

are a s:

Memory area Data width Location

User m emor y for: OBs, FBs, FXs, PBs, SBs, DBs, DXs 16 bits

CPU

internal

Se rial comm un ica tions in te rfa ce are a : RI, RJ

Syste m area : RS, RT

Timers: T

Counters: C

Flags: F

Flag s: S

Pro cess im a ge (PI) i nput s/

ou tpu ts: PII , PIQ

16 bi ts

8 bi ts

8 bi ts 1)

8 bi ts

Pe ri phe ra l a re a,

di vi ded into:

"P" peri phera ls

"O" peri phe ra l s

Inte rp roce ssor com mu nica tion fla gs

Coord ina tor (COR ) (semaph ore , .. .)

Du al-po rt RAM page s (CP, IP, COR 923 C)

Di str ibu ted pe riphe ra ls

Ha rd war e registers

8 bi ts

8/ 16 bi ts

8 bi ts

8/ 16 bi ts

On the

S5 bu s

1) S flags occ upy 8 bits in the 16-bit area. The hi gh byte is undefi ned.

The next sec tion lists t he add resses of the mem ory are as shown.

Note

Whe n usi ng ST EP 5, yo u should not acce ss a mem or y regist e r

wi thin an ope ra nd are a (e.g ., flag s) dir ec tly via t he ab solu te

add re ss of the mem or y regist e r. This ca n resul t in undesi ra ble

o pera ti ng sta t use s. Acc ess i t only re lat ive to the ba se addr ess of its

operand area.

Dire ct acce ss to the are as I, Q and F resul t in ’FFH’ in the high

b yte and th e dat a in the low byte . For di re ct acc e ss to S flags, the

high byte is undefi ned!

Table 8-1 Structure of the memory area

Structure of the Memory Area

CPU 948 Programming Guide

8 - 4 C79000-G8576-C848-04

8.2 Memo ry Assign ment in t he CPU 948

With the CPU 948, the re are two possi ble user mem orie s (RAM)

available:

•• the CPU 948-1 with 640 Kbyt es of use r memory

•• the CPU 948-2 with 1664 K by te s of use r mem or y.

Fi g. 8-1 il lu stra t es t he distributi on of t he addre ss ar ea of the CPU 948

and t he loc a ti on of t he user mem ory ve rsi ons.

Peripheral Area (S5 bus)

System RAM

The last 20 words of the user RAM cannot be used.

640 Kbyte User RAM

(CPU 948-1)

1664 Kbyte User RAM

(CPU 948-2)

Bit no.:

Address:

0 0000H

1 0000H

2 0000H

3 0000H

4 0000H

5 0000H

6 0000H

7 0000H

8 0000H

9 0000H

A 0000H

B 0000H

C 0000H

D 0000H

E 0000H

F 0000H

F FFFFH

15 0

Fig. 8-1 Mem ory assignm ent in CPU 948/ overvie w

Memor y Assignm ent in the CPU 948

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 5

8.2.1

Memory Assignment for the

System RAM

Bit no.:

Address:

D 0000H

E 9FFFH

E A000H

E AFFFH

E B000H

E DEAFH

E DEB1H

E DF6FH

E DF7CH

E DFA1H

E E1F0H

E E1FBH

E E200H

E E400H

E E600H

E E800H

E EA00H

E EC00H

E EE00H

Reserved

DB 0 header

DB 0

(contains the paragraph

addresses of all blocks,

i. e. address bit no. 4

to address bit no. 19)

Address list OB 0 to OB 255

Address list PB 0 to PB 255

Address list SB 0 to SB 255

Address list FB 0 to FB 255

Address list FX 0 to FX 255

Address list DB 0 to DB 255

Address list DX 0 to DX 255

ISTACK entry - 1

ISTACK (16 entries)

BSTACK (60 entries)

S flags

System program and system data

System program data

15 8 7 0

Fig. 8-2 Memory assignment for the system RAM/Part 1

Memory Assignm ent in the CPU 948

CPU 948 Programming Guide

8 - 6 C79000-G8576-C848-04

Bit no.:

Address:

E F000H

E F200H

E F400H

E F600H

E F800H

E FA00H

E FC00H

E FD00H

E FE00H

E FE80H

E FF00H

E FFFFH

Reserved

PII

PIQ

Flags

Counters (256)

Timers (256)

RT Area (Extended System Data, 256 Words)

RJ Area (Extended Serial Comm. Interface, 256 Words)

RI Area (Serial Comm. Interface, 256 Words)

RS Area (System Data, 256 Words)

15 870

Fig. 8-3 Memory assignment of the system RAM/Part 2

Memor y Assignm ent in the CPU 948

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 7

8.2.2

Memory Assignment for the

Periph erals

Bit no.:

Address:

F 0000H

F D000H

F F000H

F F080H

F F100H

F F200H

F F300H

F F400H

F F800H

F FC00H

HW Registers

F FE00H

F FFFFH

reserved

Data Transfer Area for CPs

Additional Data Area for CPs

Distributed Peripherals

Extended Address Set

with IM 304, IM 307 and

IM 308 Interface Module

(Dual-Port RAM Pages) 1 Kbytes or words

1 Kbytes or words

(Extended Dual-Port RAM Pages)

(with PI, 128 I/128 Q)

Digital Peripherals

Parea

Oarea

(without PI, 128 I/128 Q)

Analog Peripherals

Extended Peripherals

IPCs in

Semaphores (32)

in COR

COR and/or CP

(only in Expansion Unit)

Unassigned Peripheral Address Space (52K Words)

15 870

Fig. 8-4 Address areas for peripherals (8 bits) on the S5 bus

Memory Assignm ent in the CPU 948

CPU 948 Programming Guide

8 - 8 C79000-G8576-C848-04

Address Areas for

Periph erals an d

Programmi n g Them

Usi ng ST EP 5 op er at io ns, you c an a cc ess pe ri phe ra l s e ithe r di re ctl y or

via t he process ima ge (PI). Note that a proc ess i ma ge exists only for

input an d out put b ytes of t he "P" peri phe ra l s with b yte a ddre sse s from

0 to 127!

Note

Usi ng the inte r f ac e mo dul es IM 3 0 4, I M 307 a nd IM 308 , yo u can

ac cess di stri but e d addre ss ar ea s usi ng you r prog ram. This a llo ws

access to two new address areas similar to the O area. In contrast

to the O area, however, acc e ss t o these areas is only possib le

using a bsol ut e addressi ng or using FB 196 of the "basi c

func ti ons" soft wa re packa ge (refe r to Cata lo g ST59).

Area

(absolute addr ess) Referenced with Parameter

"P" per iphe r al s with pr ocess i mag e

L IB / T IB 0 to 127

L IW / T IW 0 to 126

L ID / T ID 0 to 124

A I/ AN I / O I / ON I 0.0 to 127.7

S I / R I / = I

L QB / T QB 0 to 127

L QW / T QW 0 to 126

L QD / T QD 0 to 124

A Q / AN Q / O Q / ON Q 0.0 to 127.7

S Q / R Q / = Q

When the op eration is pr ocess ed, onl y the process

image is chan ged. The n ew status of the process

image of the outpu ts is only outpu t to th e I/Os a t

the end of th e cycle.

"P" peripherals

L PY / T PY 0 to 127

L PW / T PW 0 to 1 26

L PY / T PY 128 to 255

L PW / T PW 128 to 254

The input s and out puts a re addressed d irectly in

byt es or words.

"O" peripherals

L OY / T OY 0 to 255

L OW / T OW 0 to 254

The input s and out put s are addressed d irectly in

byt es or words.

PII

(Pr oc ess i mage in put )

PIQ

(Proc ess im age outp ut)

Digit al periphe rals

Inputs/outputs

Digital or analog

peripherals

Inputs/outputs

Extended peripherals

Inputs/outputs

E FE00

E FEFF

E FE80

E FE7F

F F000

F F07F

F F080

F F0FF

F F100

F F1FF

Memor y Assignm ent in the CPU 948

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 9

8.3 User Memory Organization in the CPU 948

Depen ding o n the v ers ion o f the CPU 948 used, the user memory

occupies the memory area from 0 0000H to C FFFFH. When you

load the individ ual blo cks of yo ur program, they are sto red in t he

memory in r andom o rd er (wi th addresses in ascend ing or der).

Block management

When you correct a block, the old block in the memory is declared

inva li d (i .e. , t he sta rt ID is overwritte n) a nd a new bloc k is ent er ed in

the m em ory a nd t he address list . Thi s al so appl ie s whe n you de l et e

blocks. The blocks are not really deleted in the memory but simply

declared invalid. Gaps created by deleting are managed as available

memory locations and are used again when you load new blocks.

Compressing memor y

The online COMPRESS ME MORY PG function pu she s al l vali d

blocks in the mem ory toget her. When you activat e the COMPRE SS

MEMORY whi le the CPU is in the STOP mod e, all bloc ks tha t are not

dire ctl y next to eac h other ar e shifted . However, when you ac tivate

this fu nc ti on whi le the CPU is in the RUN mode , long dat a and

ext ende d data blocks (i.e ., longe r than 512 data words) ar e not shifte d

bec a use o f data lengt h c onsi ste nc y. Com pre ssi ng pro duc e s l arge

available memory areas which you can use for loading new blocks.

If the onl ine COMPRESS ME MORY PG f unc tion is inter rupt ed (e.g .,

when t he powe r is turne d off ), com pr essi ng i s te rm inat ed and does not

re sume au tom a ti c al ly wh en pow e r is tu rned on.

Locatio n of bl ocks in the

user memor y

In the CPU 948, bl ocks ar e stored so that data word DW 0 or the first

STEP 5 statement of each block is located at a paragr aph addr ess.

Paragra ph a ddresses are at 16-word bou ndari es. T here fore, al l bl oc k s

begi n in the mem ory at the address xxxxBH (bi t no. 0 to 3 = BH) and

all block bodi es at the add re ss yyyy0 H (bit no. 0 to 3 = 0H). Th e gaps

tha t resul t betwe e n bl ocks ar e fill e d in by inva l id dat a bloc ks, so that

all blocks continue to exist in consecutive order.

Filler blocks

The se i nva lid da ta bl ocks a re known as "fil le r bloc ks". They are

treated in the same way as the other blocks by the memory

mana gement an d have the following structu re:

Star t ID: 7 070H ;

Bloc k type /bl ock num be r: 01FBH ;DB 251 i nva lid

Programmer ID: 00FFH ;irrelevant

Library number: FFFFH ;irrelevant

Block leng th: 00XXH ;length 5 to 20 words

Data: FFFFH ;according

:;to

: ;length;

FFFFH ;can be left out entirely

User Memory Or ganization in the CPU 948

CPU 948 Programming Guide

8 - 10 C79000-G8576-C848-04

Example

You can calculate the length of a filler block by finding the difference

bet wee n the e nd add re ss of the last block st ore d and th e addr ess be fo re

the next paragraph address.

Difference Calculation for length of filler block (including

header)

0 to 5 Add 10 to the difference

6 No filler block is inserted

7 to 10 Add 10 to the difference

11 to 15 Subtract 6 from the difference

Bit no. Bit no.

Block List in DB 0 Memory

Header 1

Header 2

Header n

Body 1

Filler Block

xxxx0H

Ascending

Addresses

xxxx0H

Body 2

Body n

= Paragraph addresses (16 word boundary)

Start Block 1

Start Block n

15 15

Fig. 8-5 Example: Location of blocks in memory

User Memor y Organiz ation in the CPU 948

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 11

8.3.1

Block Headers in

User Memory Each block in the memory begins with a header that is five words

long. The block hea de r is di vide d as follows:

1st word: Block start ID: 7070H

2nd word: High byte = Bloc k type

Low byte = Block number

The low byte of t he sec on d he ad er word cont ai ns th e

blo ck num be r (0 to 255). It i s co de d as a he xa deci m al

number: 00 to FFH.

3r d word: The high by te of the thir d word c ont ains t he IDs for

the programmer. The low byte contains part of the

libra ry number .

4th word : The fourt h word contains the rest of the libr ar y numbe r.

5th word : The fift h word (low a nd high byt e s) conta i ns the leng th of

the bl oc k, inc luding the bl oc k header. The le ngt h is

ind ica ted in words.

01H Data block DB

02H Sequence block SB

Program block PB

Function block FX

Function block FB

Data block DX

Organization block OB

04H

05H

08H

0CH

10H

00 address list in DB 0.

address list in DB 0.

The block is invalid; it is not entered in the

The block in the RAM is valid; it is entered in the

Bit no. 15 14 13 12 11 10 9 8

User Memory Or ganization in the CPU 948

CPU 948 Programming Guide

8 - 12 C79000-G8576-C848-04

8.3.2

Block Address List in

Data Block DB 0 Data bloc k DB 0 is locat ed in the system RAM of the CPU (begi nning

at addre ss E E20 0H). It cont ains a list wit h th e st ar t addre sse s of a ll

bloc ks in the use r memory of the CPU. The syste m progra m gene rate s

(COLD RE ST ART ) or chec ks (W ARM RESTART) this list after

power up; it update s it autom atica ll y when you use a prog ramm e r to

enter or change blocks.

Address list start addresses

DB 0 has a sepa ra te, rese rve d addre ss li st of 256 word s in e ach type of

bl oc k. Blo cks tha t a re not loaded or ha ve be e n de le te d have th e st ar t

addr ess ’0’ .

The sta rt add resses of eac h blo ck add ress l ist are spec if ied (se e Sec tion

8.2.1).

Block start address es

The blo ck sta rt addr esse s in the addre ss li sts a lwa ys poi nt to the first

word after the block header:

•• wi th data bl oc ks , to da t a word DW 0

•• with logi c blocks, to the first STEP 5 stat eme nt (in FBs to the ’JU’

o pe ra ti on be for e t he n am e an d the pa ra m et e r list).

Si nce ea ch bloc k is loc ate d at a par agra ph a ddre ss (16 word

bo unda ry ), eac h ad dre ss list e ntr y in DB 0 is r est ri cte d to one wor d

with bits number 4 to 19 of the address.

Locatio n of block

addresses in DB 0

n = E E400H (sta rt add re ss of the PB addre ss li st)

Address PB 0

Address PB 1

Address PB 2

Address PB 178

Address PB 179

If ’0’ is entered as

the address, the

block is not

loaded.

DB0

n+1

n+2

n+178

n+179

15 0

Fig. 8-6 Block addresses in DB 0

User Memor y Organiz ation in the CPU 948

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 13

Example of how to obtain a

block address

8.3.3

RI/RJ Area T he RI area is an area tha t is 256 words long in the intern al system

RAM of the CPU. RI occu pies a ddre sse s E F400H to E F4FFH.

The RJ area is an a re a that is 25 6 words long i n the in terna l syste m

RAM of the CPU. RJ occupie s addresse s E F600H to E F6FFH.

You ca n use the entire RI are a (R I 0 to RI 2 55) and t he ent ir e RJ are a

(R J 0 to RJ 255 ) for your own pu rpose s.

The RI/RJ ar ea is on ly fille d with zero s foll owi ng OVERAL L RESE T .

The block start addresses of the prog ram bloc ks

are located in DB 0 and begin at address E E400H.

The start address of PB 22 can therefore be read

out by accessing memory at address E E416H

(= start address of the PB + 16H).

User Memory Or ganization in the CPU 948

CPU 948 Programming Guide

8 - 14 C79000-G8576-C848-04

8.3.4

RS/RT Area The RS and RT areas contain information for the system programmer and

system internal data.

The RS area is an are a that is 256 words long in the intern al syste m

RAM of the CPU. RS occupie s addresse s E F000H to E F0FFH.

Caution

You should only write to syste m data words RS 60 to RS 63:

All other system dat a should only be read:

Writing to the system data area can affect the function al ca pabi li ty

of your program mab le co ntr oll e r an d co nne c ted pro gra m me rs:

se rious di stur ba nc es c a n occu r whic h ma y put both peo ple and

machines in danger.

The RT ar ea is an are a that is 256 wor ds lon g in the inter na l system

RAM of the CPU. RT occupie s addre sses E F200H to E F2FFH.

You can use the whol e RT area (RT 0 to RT 255) for your own

purposes if

1. you d o not u se st andard FB s

and

2. you do not use PG functio ns via SINE C H1 and the para lle l S5 bus.

Onl y a n overall re set ca n c le a r th e RS/ RT ar ea s.

RS/RT Area

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 15

Using th e online func ti on SYSTE M PARAMET E RS, you ca n obtain

the info rmat ion conta ine d in some of the system dat a (abo ut the

inte rnal struct ure of the CPU, t he so ftware re leas e, the CPU ident ifi er

etc.)

Assignment of the RS area

RS Name Address

0 Input byt e IB 0 im ag e tab le

(external process interrupts) E F000 H

1 Ext e rna l proc ess i nte rr upt s in the

processing queue (IB 0) E F001 H

2 to 4 System progr am

5 Current cy cle time E F005H

6 System program

7 STOP m ode ID (ISTACK) E F007H

8 Start/re sta rt IDs (ISTACK) E F008H

9 to15 System program

16 Error are a: output bytes 0 to 15 E F010 H

17 to 23 Err or a re a: output byte s 16 t o 127 E F011H

E F017 H

24 to 31 Err or a re a: inp ut bytes 0 to 127 E F018H

E F01FH

32 to 47 Error area: inte rpro cessor

communication flag bytes 0 to 255

E F020 H

E F02FH

48 to 49 Sy ste m progr am

50 PAFE byte for "bac kplane bus functions" E F032H

51 to 59 Sy ste m progr am

60 to 63 Availabl e to u s e r E F03CH

E F03FH

64 to 67 Sy ste m progr am

68 to 71 Error a ddre ss wit h QVZ and PARE errors E F044H

E F047 H

72 to 74 Sy ste m progr am

Table 8-2 Assignment of the RS area

RS/RT Area

CPU 948 Programming Guide

8 - 16 C79000-G8576-C848-04

RS Name Address

Table 8-2 continued:

75 System me ss a ge , fu nc ti on number E F04 BH

76 System me s sage, parame te r1 E F0 4C H

77 System messa ge, param eter 2 E F04DH

78 Sy ste m m e ss a ge , pa ra m e te r 3 E F04 EH

79 to 95 Sy ste m progr am

96 Current ti me of da y (sec onds) E F060 H

97 Curre nt time of da y (hours) E F061H

98 Current ti me of da y (day s) E F062 H

99 Current time of day (y ea r/ mont h) E F063 H

100 to 119 S y ste m progr am

120 Softwa re protec ti on/password E F078H

121 to 135 S y ste m progr am

136 to 137 L oc a tions fo r sel f-t e st fun ct io n E F088H

E F089 H

138 System program

13 9 Cyc le time used a fter re trigge ring E F08BH

140 to 252 S y ste m progr am

25 3 fre e fo r distri but ed peripher y E F0FDH

254 to 255 S y ste m progr am

As a supplement to the li st ing abo ve, the f ollowing pages pr ovide

the bit assignmen ts of a few system data register s that you can

evaluate via S TEP 5 o peratio ns or with your prog rammer (se e

Section 5.4 f or information on the abbreviations) .

RS/RT Area

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 17

8.3.5

Bit Assign men t of th e

System Data Word s

System data RS 0

Input byte IB 0 Image table (ext ernal process int err upts)

Address E F000H

Hi gh byte

Bit no. Assignment

Occupied by syste m progra m

Low byt e

7 Status of I 0.7

6 Status of I 0.6

5 Status of I 0.5

4 Status of I 0.4

3 Status of I 0.3

2 Status of I 0.2

1 Status of I 0.1

0 Status of I 0.0

Table 8-3 Bits in RS 0 (image of IB 0)

Bit Assignment of the System Data Words

CPU 948 Programming Guide

8 - 18 C79000-G8576-C848-04

System data RS 1

Conditi on code of exter nal pro cess int err upts curr entl y in

proc e ssing queue

Addre ss: E F001H

High byte

Bit no. Assignment

All the bits have the value ’0’

Low byt e

7 Bit = ’1’: ed ge I 0. 7

6 Bit = ’1’: ed ge I 0. 6

5 Bit = ’1’: ed ge I 0. 5

4 Bit = ’1’: ed ge I 0. 4

3 Bit = ’1’: edge I 0.3

2 Bit = ’1’: ed ge I 0. 2

1 Bit = ’1’: ed ge I 0. 1

0 Bit = ’1’: ed ge I 0. 0

Table 8-4 Bits of RS 1 (current process interrupts)

Bit Assignment of the System Data Wor ds

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 19

System data RS 5

Current cycle time

Addre ss: E F005H

High byte and low byte

Bit no. Assignment

The entered binary value * 10 msec. equals the

cycle time of the cycle processed last

Example

Table 8-5 Bits of RS 5 (cycle time)

Bit no.151413121110987543210

Value000000000011000

The time of the last cycle is as follows:

(24 + 23) * 10 ms = (16 + 8) * 10 ms = 240 ms

Bit Assignment of the System Data Words

CPU 948 Programming Guide

8 - 20 C79000-G8576-C848-04

System data RS 7

Pr ogrammable contro ller STOP mode IDs (ISTACK)

Addre ss: E F007H

Hi gh byte

Bit no. Assignment

15 Reserved

12 Fau lty ISTACK le vel

11 Illegal start-up type (UANL)

1 0 Inter rupt io n in st op lo op

9 Illegal call of system block (SYSFHL)

8 Error i n start -up bl oc k (AFE L)

Low byt e

7 Inter rupt ion by system (USYS –warm resta rt

possible)

6 Inter rupt ion by pro gra m ming e rro r

(UPROG – cold resta rt)

5 "End of pro gra m te st" (BE A RB E)

4 Stop switch (STOPS)

3 End of operation s top (STS)

2 End of cyc le stop (STP)

1 Multiprocessing stop (HALT)

0 PG stop (PGSTP)

Table 8-6 Bits of RS 7 (PLC stop I Ds)

Bit Assignment of the System Data Wor ds

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 21

System data RS 8

Start and re star t IDs (ISTACK)

Addre ss: E F008H

Hi gh byte

Bit no. Assignment

15 Defau lt: MANUAL COLD REST ART /

WARM RESTART (MSEG)

14 Defau lt: AUTOMATI C COLD

RESTAR T (ANEG)

13 Defau lt: AUTOMATI C WARM

RESTAR T (AWE G)

12 OVERALL RESE T required (UR LER)

1 1 WAR M R EST AR T pe rm it te d (WIEZ U )

1 0 COLD REST ART perm itte d (NEUZ U )

9 OVERALL RESE T exec uted (URLDF)

8 WARM RESTART executed (WIEDF)

Low byt e

7 COLD RESTART executed (NEUDF)

6 Automa t ic start aft er NA U

5 Manua l start

4 COLD RESTART WITH MEMORY

3 PG overall reset

2 PG system st art

1 PG warm restart

0 PG cold restart

Table 8-7 Bits of RS 8 (start and start-up IDs)

Bit Assignment of the System Data Words

CPU 948 Programming Guide

8 - 22 C79000-G8576-C848-04

System data words

RS 16 to RS 47

Er ror areas

RS xx Address( es) Erro r area

RS 16 E F010 Out put bytes 0 to 15

RS 17 to

RS 23 E F011 to

E F01 7 Out put byt es 16 t o 127

RS 24 to

RS 31 E F018 to

E F01F Input bytes 0 to 127

RS 32 to

RS 47 E F020 to

E F02F Interpr oc esso r commun ica tion flag

by tes 0 to 255

RS 16

Addre ss: E F010H

Hi gh byte

Bit no. Assignment

15 Outp ut byte 0

14 Outp ut byte 1

13 Outp ut byte 2

12 Outp ut byte 3

11 Outp ut byte 4

10 Outp ut byte 5

9 Output byte 6

8 Output byte 7

Low byt e

7 Output byte 8

6 Output byte 9

5 Output byte 10

4 Output byte 11

3 Output byte 12

2 Output byte 13

1 Output byte 14

0 Output byte 15

If err ors a ppe a r duri ng up da te of th e proc ess i mage in put /ou tpu t tabl e s

or int er proc essor c om m uni cat ion flags, the corre spo ndi ng bi ts a re se t

to ’1’. – The syste m data words RS 17 t o 47 a re st ruc t ure d ana log o us

to RS 16.

Table 8-8 Bits of RS 16 (error area output bytes 0 to 15)

Bit Assignment of the System Data Wor ds

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 23

Example of RS 1 6

System data RS 50

PAF E byte for "backplane bus function s"

Syste m data RS 50 conta ins the para met er assi gnm ent erro r byte for

the "backp lane bus fun ctio ns" of a C PU.

15 8 7 0

RS 50 PAFE - E F032H

System data wo rds RS 68

to RS 71

Err or addr esse s of QVZ and PARE err or s

If a QVZ or PARE err or oc curs, the addre ss a t which the error wa s

de t ec t ed is ente re d here.

15 0

RS 68 QVZ error addr . high E F044H

RS 69 QVZ error addr. low E F045H

RS 70 PARE erro r addr. high E F046H

RS 71 PARE error addr. low E F047H

The conten t of s yste m data register RS 16 is

"8020" hexadecimal or "1000 0000 0010 0000"

binary.

The process image for output bytes 0 and 10 has

not been updated correctly.

Bit Assignment of the System Data Words

CPU 948 Programming Guide

8 - 24 C79000-G8576-C848-04

System data words

RS 75 to RS 78

System message

The entrie s in syst em data word s RS 75 to RS 78 refer to the erro r that

occ urr ed last. The message consi sts of four syst e m data words wit h the

fo llowin g stru cture :

15 0

RS 75 Error number Parame ter type E F04BH

RS 76 Pa ram ete r 1 E F04CH

RS 77 Parame ter 2 E F04DH

RS 78 Pa ra m e ter 3 E F04E H

RS 75

The high byte conta ins t he error number whic h classifi es the error.

The er ror nu mb er ass i gns th e erro r to one of the fol lowi ng t hre e are as:

Error groups

•• 01H to 2FH: user error

•• 30H to 3FH: e rr or in DX 0 or DB 1,

•• 40H s ys tem er ro r

Parameter ty pe

The low byt e contains t he parameter type that d escribes the structure

of the succeeding parameter block in RS 76 to RS 78. The parameter

type s from 00H t o 10H exist . The str uctur e of the para me t er field is

de scribed la te r.

The two fo llowin g tabl es l ist the er ror gr oups "ge ne ral e rr ors" an d

"e rro rs in DX 0 or DB 0".

Bit Assignment of the System Data Wor ds

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 25

General errors

Error

number Parameter

type Meaning

01H 01H Block called is not loaded

02 H 01 H Addre ssi ng error

0 3H 0 1H Cycle tim e erro r

04 H 01 H Subst itution erro r

05H 02H Timeout distributed peripherals

06H 03H Timeout user memory

07H 01H Load/transfer error with data blocks

an d ex te nded dat a bl oc k s

0 8H 0 1 H Bra c ke t count e r ove rfl ow

09H 04H Data block to be opened does not exist

0AH 0 5H Er ror wi th i nte rn al time in te rru pts/

other interrupts

0BH 03H Timeout page frame area

0CH 03H Timeout global communication area

0DH 07 H Tim eo ut in proc ess im age upda ting

0EH 03 H Tim eo ut in IPC flag synchron iz ati on error

0F H 03H Tim eout "P"/"O" per ipher als

1 0H 0 3 H Ti meo ut si nc e inte rf ac e module (IM 3/IM 4)

missing

1 1H 0 3H Parity er ror i n user me mory

12 H 0 1H Ti meo ut proc ess i mage tran sfe r

1 3H 0 1H Tim eo ut input byt e IB 0

14 H 01 H BST ACK overfl ow

15 H 0 1H STS op er atio n

16 H 0 1H RUN/ST OP swit ch set to STOP positi on

1 7H 0 1 H Hal t si gna l from the coordi na to r

1 8H 0 1H Not used

19 H 0 1H Lo ad/t ransfe r error with L BY/T BY

(proce ss ima ge updat e)

1AH 0 1H Lo ad /tra nsfe r e rror duri ng a ddre s si ng

via th e BR r eg ist er

1BH 01H I/Os no t ready

1CH 0 8H Ti m eout/parity e rro r during

initialization

Table 8- 9 RS 75: ge neral errors

Bit Assignment of the System Data Words

CPU 948 Programming Guide

8 - 26 C79000-G8576-C848-04

Error

number Parameter

type Meaning

Table 8-9 continued:

1DH 08H AUTOMATIC WARM RESTART n ot

possible; COLD R ESTART required

1EH 00H Illegal start-up type

1F H 01H Load /tra nsfe r error duri ng bloc k tra nsf er

ope rati on (i nc orr ect mem ory a re a bound ar ie s

wit h TNW, TXB , TXW )

20 H 0 9H Ille ga l leng th for G DB/GX D X

21 H 0 9H DB/DX a lrea dy exi sts fo r G DB/GX D X

22 H 0 9H Mem or y spa ce insuffi c ie nt for G DB/GX DX

23H 05H Masked system interrupt is coming through

24H 00H Block function (compress, transfer, input)

requi re d in STOP, COLD RE ST ART

25 H 00 H Batter y failure; no sta rt-up possibl e

26 H 00 H Change from singl e to multiproc esso r

opera tion prev en ts a WARM RE ST ART

27 H 0 1H STOP c ause d by STP ope rati on

2 8H 0 1 H Cont in uous re ady si gnal (I/O m odul e d efec t ))

2 9H 0 8H Er ror i n DB 0 struct. aft e r OVERALL RE SE T

DX 0/DB1 errors

Error

number Parameter

type Meaning

Erro rs in DX 0

30 H 0 0H No DX 0 in multip roc essing

32 H 0 0H Proc . int . and sys. in t. sele cte d sim ulta ne ousl y

3 3H 0 0 H Int er rupt s an d mo de i nc om pa tibl e

34 H 0 6H Inva l id DX 0 heade r

3 5H 07H Error i n DX 0 block ID

3 6H 07H Error i n DX 0 par am e te r

Erro rs in DB 1

38 H 0 6H No DB 1 in multi proc e ssin g

3 9H 0 6H Invalid DB 1 hea de r

3AH 07H DB 1 ID set more than once

3BH 07 H DB 1 byt e offse t withou t ID

Table 8-10 RS 75: Errors in DX 0 or DB 1

Bit Assignment of the System Data Wor ds

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 27

Error

number Parameter

type Meaning

Table 8-10 continued

3CH 07H Peripheral entered in DB 1 is not

plu gge d in

3DH 07H Offse t too big (para met er error)

3EH 07 H Too many offse ts

Error codes of the self test

functions

Error

number Parameter

type Meaning

6 1H 0BH Chec ksum error i n system prog ram code

6 2H 0AH Che c ksum error i n co de of the STEP 5

log ic blocks

63 H 0BH Address de c ode r error

6 4H 0CH Er ror t est in g the use r mem or y orga nized in

words

6 5H 0CH Er ror t est in g the use r mem or y orga nized in

bytes

6 6H 00H Error t est in g cy cl e tim e mo nit ori ng

67 H 0 0H Er ror t est ing the BASP sig na l

6 8H 0 0 H Er ror test in g the hardwa re cloc k

Ta ble 8-11 R S 75: err or code s of th e se lf test fu nctions

Bit Assignment of the System Data Words

CPU 948 Programming Guide

8 - 28 C79000-G8576-C848-04

Structure of the parameter

field (RS 76 to RS 78)

Parameter

type St ructure of the par ameter field

00H No parameter; parameter 1, 2, 3 = 0

01H Pa ra m ete r 1: blo ck type /blo ck num ber (IDs fro m bloc k hea der)

Parameter 2: operation that caused an interruption

02H Para met e r 1: inte rfa c e modu le numbe r (IM 30 2) (di str ibu te d peri phe ry)

Parameter 2: number of the defective interface

Pa ram ete r 3: incor re ct byt e offse t

03H Pa ram ete r 1: not used

Pa ram et e r 2: er ror a ddr ess hi gh

Pa ram et e r 3: er ror a ddr ess lo w

04H Pa ra m ete r 1: blo ck type /blo ck num ber (IDs fro m bloc k hea der)

Para m ete r 2: ope ra tion t hat cau sed the inte rrup tion

Pa ram et er 3: numbe r of the DB/DX to be open ed

05H Pa ra met e r 1: The foll owin g bits are set depe nd ing on the error :

Bit no. 0 = 1 : ti med interrupt/period 1

Bit no. 1 = 1 : ti med interrupt/period 2

: : : :

Bit no. 7 = 1 : ti med interrupt/period 8

Bit no. 8 = 1 : ti med interrupt/period 9

Bit no. 9 = 1: cloc k m ask ed (ign ore d) fo r too l ong

= 0 : que ue overfl o w

Bit no . 10 rese rve d

Bit no . 11 rese rve d

Bit no. 12 = 1: int e rrupt G

Bit no. 13 = 1: interrupt F

Bit no. 14 = 1: interrupt E

Bit no. 15 = 1: interrupt X

06H Para met er 1 data word expe cte d in DX 0 or DB 1 head er

Para met er 2 actua l data word in DX 0 or DB 1 hea der

07H Parameter 1 block ID or code word in DX 0 or DB 1

Parameter 2 incorrect parameter 1 in DX 0 or DB 1

(FFFFH: param eter irre levant)

Parameter 3 incorrect parameter 2 in DX 0 or DB 1

(FFFFH: param eter irre levant)

Tab le 8-1 2 RS 76 to RS 78: Para m eter types

Bit Assignment of the System Data Wor ds

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 29

Parameter

type Structure of the param eter fi el d

Table 8-12 continued:

08H Para met er 1 The foll owin g bits are se t depend ing on the error :

Bit no. 0 = 1: QVZ i n initi a lization

Bit no. 1 = 1: PARE in initializ atio n

Bit no. 2 = 1: content of the memory card too large

Bit no. 3 = 1: opera ti ng syst e m e rror

Bit no. 4 = 1: incorrect block ID

Bit no. 5 = 1: incorrect block delimiter

Bit no. 6 res erved

Bit no. 7 res erved

Bit no.8 = 1: DB 0 chan ge d sinc e last COL D RE ST ART

Bit s no. 9

to 15 reserved

Pa rame t er 2 error a ddr ess hi gh, (whe n bit 2, 4 or 5 of param e ter 1 = ’1’

Pa rame t er 3 error addr ess l ow, (whe n bit 2, 4 or 5 of para m et er 1 = ’1’

09H Para met er 1 Opcode "GX DX" or "G DB" (indi c ates the block type )

Parameter 2 b lock nu mber

Param et e r 3 dat a bl ock len gth

10H internal system error number

0 AH Pa ra met er 1 block t ype /blo ck num ber (IDs fro m bloc k hea de r)

Parameter 2 expected checksum

Parameter 3 actual checksum

0BH Param eter 1 FFFFH

Pa rame t er 2 error a ddr ess hi gh wi th addr ess c ode error ,

act ual che ck sum h igh when testi ng th e syste m progra m code

Pa rame t er 3 er ror addr ess l ow wit h ad dre ss co de err or,

act ual che ck sum low whe n test ing the syste m progra m code

0CH Parameter 1 check pattern when testing the user memory

Pa rame t er 2 error a ddr ess hi gh

Pa rame t er 3 error a ddr ess l ow

Bit Assignment of the System Data Words

CPU 948 Programming Guide

8 - 30 C79000-G8576-C848-04

Example of a system message

RS 75 21 H 09H E F04 BH

RS 76 7804H E F04CH

RS 77 0064H E F04D H

RS 78 0078H E F04E H

RS 75, error number = 21H:The error occurred in the STEP 5 user program when

generating a DB/DX.

R S 75 , pa rameter type=09H :The parameter block in RS 76 to RS 78 contains

3 paramete rs.

RS 76, parameter 1 = 7804H: Opcode = "GX DX", this means block type "DX".

RS 77, parameter 2 = 0064H: Block number = 100 (dec.)

RS 78, parameter 3 = 0078H: Data block length = 120 data words

Information contained in the message:

In the STEP 5 user program, data block DX 100 should be generated with a

length of 120 data words. However, this already exists.

Bit Assignment of the System Data Wor ds

CPU 948 Programming Guide

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System data words

RS 96 to RS 99

Re al-time clock

The current date and time of day are kept in system data areas RS 96

to RS 99 a nd can if nec essa ry be rea d out from th ese loca t ion s.

15 0

RS 96 Seconds 1/10, 1/100 se c onds E F060H

RS 97 Hours Minutes E F061H

RS 98 Day Da y of the week E F062H

RS 99 Yea r Month E F063H

The cloc k is update d by a 10 m sec . pulse.

RS 96

Sec onds a nd 1/100 sec ond s (ad dress: E F060H):

Hi gh byte

Bit no. Assignment

15 Seconds, tens,

perm itte d: 00H to 05 H

11 Seconds, units,

perm itte d: 00H to 09 H

Low byt e

71/10 sec ond,

perm itte d: 00H to 09 H

31/100 second,

perm itte d: 00H to 09 H

Ta ble 8- 13 St r ucture of RS 96 (r eal-t im e cl ock: se co n ds, 1/ 10 0 s ec o nd s)

Bit Assignment of the System Data Words

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8 - 32 C79000-G8576-C848-04

RS 97

Hours an d minut e s (ad dre ss: E F061H) :

Hi gh byte

Bit no. Assignment

1 5 0 = 12 hour fo rm at , 1 = 24 ho ur for ma t

14 0 = AM, 1= PM

1 3 Hours, te ns, pe rmitte d: 00/01H with

12 hou r forma t, 00/ 02H wi th 24 hour fo rm at

11 Hours, units,

perm itte d: 00H to 09 H

Low byt e

7Minutes, tens,

perm itte d: 00H to 05 H

3Minutes, units,

perm itte d: 00H to 09 H

RS 98

Current date and day of the week (address: E F062H):

Hi gh byte

Bit no. Assignment

15 Dat e, ten s,

perm itte d: 00H to 03 H

11 Dat e, un its,

perm itte d: 00H to 09 H

Low byt e

7Day of the week ,

perm it ted: 00H to 06H for Mon. to Sun.

Table 8-14 Structure of RS 97 (real-time clock: hours, minutes)

Table 8-15 Structure of RS 98 (real-time clock: date, day of the week)

Bit Assignment of the System Data Wor ds

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 33

RS 99

Current year and m ont h (addr ess: E F063H):

Hi gh byte

Bit no. Assignment

15 Yea r, te ns,

perm itte d: 00H to 09 H

11 Yea r, uni ts,

perm itte d: 00H to 09 H

Low byt e

7Month, tens,

permitted: 00/01H

3Month, units,

perm itte d: 00 to 09H

Ta bl e 8- 1 6 St r uct ure of RS 99 (r ea l -t i m e clo c k: yea r, m ont h)

Bit Assignment of the System Data Words

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8 - 34 C79000-G8576-C848-04

System data RS 120

Software protection

Syst em dat a RS 120 co ntr ols the syste m func tion "sof twa re

pr otec ti on". Wit h thi s func t ion , you can pr ev en t bloc ks be ing read,

over writ te n or dele ted by the PG (e.g. by unauthorize d personn el ) by

specifying a password.

Password

The "softwar e prote cti on" fu ncti on is link ed to a passwo rd. The

syst em pr ogra m is inform e d of this vi a RS 120.

Specifying th e

password/act ivating prot ection

By specifyi ng a passwo rd in RS 120, the password protection is

automatically activated.

You can spec ify a new password aft er deleti ng the old one.

Deleting the

password/deactivating

protection

If you delete the passwo rd, password pr otec tion is aut oma tical ly

deactivated.

Whe n the passwor d is delet ed , the syste m progr am must be inform ed

via RS 120.

Maximum of fiv e attem pts to

delete

If you attempt to del ete the password a nd specif y the wrong password,

the at tem pt is reje cte d by the syste m progra m and a count sta rte d.

Afte r a maxim um of five unsucc essful atte mpts, th e system pr ogra m

will no longer acce pt passwor d entries. The password c an then only be

del ete d after a COLD RE ST ART .

If the pa ssword i s su cc e ssfully del e ted, the e rror counter is r ese t .

How to specify or delete the

password

The password i s speci fied/ de let ed (and the soft wa re prot ect ion

activated/deactivated) by writing a bit pattern in RS 120 (see

Assignme nt when writing) in one of the following ways:

•• by the STEP 5 program or

•• with a PG job "outpu t addre ss".

Note

Whe n you first re cei ve your CPU a nd fo ll owin g an ove rall r ese t,

the passwo rd is delet ed and the softwa re protect ion switched of f.

Bit Assignment of the System Data Wor ds

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 35

When is the software

protection

activated/deactivated?

A password can be specified at any time. Once it has been specified,

software protection is, howeve r, only act ive at cer ta in times, as shown

below:

•• in the SOFT STOP mode :

o nce aft er calling OB 38 1),

cy c l ic al ly b e fo r e cal li ng OB 39 1),

•• in the START -UP mo de :

once a fter c all ing t he sta rt -up OBs (OB 2 0, OB 21 OB 22),

•• in the RUN mode:

cyclically be fore c a ll ing OB 1.

Assignment of the sys tem

data when writing

To cal l the softwa re pro tec tion fun ctio n, writ e syste m da ta RS 120

wi th a bit patt ern for t he func ti on a s shown in the follo wing t able .

Addre ss: E F078H

Hi gh byte

Bit no. Assignment

1 5 Act io n bit : 1 = ex ecute f unc ti on

14 Function bit: 1 = set passwor d, 0 = delet e PW

Bit nos. 8 to 13 of a 14-bi t password

Low byt e

Bit nos. 0 to 7 of a 14- bit pa ssword

1) Processing a request does not depen d on OB 38 or OB 39 being loaded. This mea ns

tha t software pro tection can b e activated in the STOP mo de.

Ta ble 8-17 As si gnm e nt of RS 1 2 0 (s oftwa re protect i o n) wh en writ i ng

Bit Assignment of the System Data Words

CPU 948 Programming Guide

8 - 36 C79000-G8576-C848-04

Reading system dat a RS 120

By readi ng out system data RS 120 , you can find out wheth er a "job"

was ex ecut e d by writing the syste m data. The syste m progr am enters a

re s ult c ode here.

Assignme nt of the system data whe n readi ng

Aft er ca lli ng th e sof twa re prot e ctio n func t ion , you ca n eva lu at e the

resul t code to find out whethe r the job was suc c essful .

Address: E F07 8H

Hi gh byte

Bit no. Assignment

15 0

1 4 Error bi t: 0 = no error, 1 = erro r

13 0

12 0

11 0

1 0 binary

delete e rror

counter

Low byt e

4 1 = no passwo rd active

3 1 = de letin g not possib le, wrong passwor d

2 1 = software prot ectio n (password ) alre ady

activated

1 1 = illegal password

0 1 = error counter overflow

Table 8-18 Assignment of RS 120 (software protection) when reading

Bit Assignment of the System Data Wor ds

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 37

Valid result codes

Value Explanations

0000H No erro r

4x01 H The maxi m um num ber of de le te att e mp ts ha s be en exc ee de d. The counter ca n only be

re set wi th a co ld re s t art.

4x02H Illega l passwo rd (0000H or 3FFFH)

4x04 H Yo u have at te mpt ed t o spe cif y a new p ass wor d while th e pa sswor d p rotection was a cti ve (x

= n u mber of attempts to delete)

4x08H You at tem pted to delete the existi ng password (deact ivat e protec tion) with an incorre c t

passwor d. The error cou nter for incor rect attem pt s was increme nted . The counter

rea di ng x is tra nsfe rre d in the re sul t code (bi nary num be r i n bits no. 8 to 10).

4010H You at tem pted to dele te a non-e xiste nt password.

The best time to activate

software protection

The mo st e ffe c ti ve p rot ec tion is ac hi e ve d whe n you a c tiva te the

sof twa re prote ctio n in OB 38/OB 39 (SOFT ST OP mode ). Protec tion

is the n activ e imme di ate ly foll owin g an ove rall rese t e ven wi th the

me mo ry c ar d inse rt e d.

Reactions to violations of the

software protection

Once the soft ware prot ec t ion is ac t ive, the system program reac ts t o

viol atio ns of th e protec ti on by PG jobs. The fo llowin g tabl e list s the

rea c tions to v ariou s PG jobs.

PG function Output on PG

Dele te bloc k Messa ge "Bl oc k type and numb er illega l"

Rea d bloc k Outp ut of a dumm y bloc k:

FB/FX: FB numb er

NAME :DUMMY

:BE

DB/DX: DW0 6500

OB/PB/SB: :BE

Overwr it e bloc k

(bloc k does no t yet exist) The block is entered

Overwr it e bloc k

(block a lready exi sts) Message "Bloc k exist s"; a fter c onf irmi ng wit h the ent er key

the messa ge "Bl oc k type and numb er wrong" i s displ a ye d.

Bit Assignment of the System Data Words

CPU 948 Programming Guide

8 - 38 C79000-G8576-C848-04

Examples of writing and

reading RS 120

Act ivating the software protection in t he s tart-up bloc ks:

(If you activate the protection in the program, it is best to activate it

in a start-up OB (OB 20, OB 21, OB 22, OB 38).)

:L KH C0AF KH = bit pattern "specify password"

: (password = 00AFH)

:T RS 120

Evaluate result in RS 120:

Using the following sequence of STEP 5 operations in OB 1 or OB 39, yo u can

react to an error occurring when specifying the password by evaluating the

result.

Note that the result can only be evaluated after certain actions of the

system program (see page 8 - 35).

:L RS 120

:L KB 0

:><F

:JC FB yyy call function block for error processing

NAME : PW-ERROR

Delete and modify the password on the PG using the OUTPUT

ADDRESS function:

Initial status: The CPU is in the RUN or STOP mode.

Go through the following procedure on the PG:

1 . Outpu t the ad dress E F078H.

2. Delete the old password by overwriting the content with 80AFH in

hexadecimal ("00AFH" = old password).

3. Wait at least as long as the cycle time of OB 39 or OB 1.

4 . Outpu t the ad dress E F078H agai n.

5. Enter the new password "1234H" by overwriting the content with the

hexadecimal number D234H.

Bit Assignment of the System Data Wor ds

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 39

System data words

RS 136 to RS 137

For sel f-test function

The system data words RS 136 to RS 137 are used fo r the self- te st.

RS 136

Numbe r of time slice s (addr ess: E F088H)

RS 137

Control bits (add re ss: E F089H)

Using the c ontrol bits, the indivi dual sel f-test funct ions can be

included or excluded (refer to Section 5.7).

Bi t = ’1’: self-t e st function is in cluded

Bi t = ’0’: self-t e st fun ct io n is e xc lud ed

Hi gh byte

Bit no. Assignment

1 5 Memor y test

1 4 Not used

13 Test cycle time monitoring

1 2 Not used

11 Test BASP signal

10 C lock tes t

9 Not used

8 Not used

Low byt e

7 Test address lines

6 Not used

5 Code test o f the ST EP 5 logi c bl oc ks in

the user memory

4 Not used

3 Not used

2 Code test of the system program

1 Not used

0 Not used

Table 8-19 Bits of RS 137 (control bits for self-test functions)

Bit Assignment of the System Data Words

CPU 948 Programming Guide

8 - 40 C79000-G8576-C848-04

System data RS 139

Cycle time used when retriggering

Address E F08AH

This system data word contains the time used for the cycle since the

last syste m chec kp oin t (at the beg inn ing o f OB 1) to the next

re triggerin g wit h OB 222 (i f OB 222 is ca l led m ore tha n on ce wit hi n

the cycle, the time to the last retriggering).

The time value is the content of RS 139 * 10 ms.

System data RS 253

List of inte rf ace m odule s plugge d in

Address: E F0F DH

Hi gh byte

Bit no. Assignment

reserved

1 1 IM numbe r 11

1 0 IM numbe r 10

9 IM numbe r 9

8 IM numbe r 8

Low byt e

7 reser ve d (IM numbe r 8)

6 reser ve d (IM numbe r 7)

5 reser ve d (IM numbe r 6)

4 reser ve d (IM numbe r 5)

3 reserved (IM number 4)

2 reser ve d (IM numbe r 3)

1 reser ve d (IM numbe r 2)

0 reser ve d (IM numbe r 1)

Tab le 8-2 0 Bi ts of RS 253 (li st of inter fa ce modul e s plugg ed i n)

Bit Assignment of the System Data Wor ds

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 41

8.3.6

Addressable System Data

Area The system prog ram use s the me mo ry are a from E 8200H to

E DEF0 H as a n ad dressable syst em da ta a re a.

PLC identification field

At the start of this area there is an informa tion field of 12 words in

which an identifier of the PLC is entered.

This field has the following structure:

Word

0 ’S ’ ’5’ E 8200H

1 ’1’ ’5’ E 8201H

2 ’5’ ’U’ E 8202H

3 ’C’ ’P’ E 8203H

4 ’U’ ’9’ E 8204H

5 ’4’ ’8’ E 8205H

6 ’V’ ’x’ E 8206H

7 ’.’ ’y’ E 8207H

10 0

11 0 E 820BH

For ’x’ and ’y’ the curre nt ver sion num be r is entered.

Addressable System Data Area

CPU 948 Programming Guide

8 - 42 C79000-G8576-C848-04

System param eters

Syst em para m ete rs in the memory are a begin nin g wit h the addre ss

E 8210H:

Word

0 Start ad d. int erfa ce m odule input E 8210H

1 Start add. interface module output E 8211H

2 St art add. proc e ss ima ge inpu t tabl e E 82 12H

3 Start add. proc ess i mage output tabl e E 82 13H

4 Start add. flags E 8214H

5 Start add. timers E 8215H

6 Start add. counters E 8216H

7 Start add. syste m dat a E 8217H

8 Status ID PLC soft wa re version E 8218H

9 User mem ory e nd addr ess E 8219H

10 Syste m prog ram me mo ry E 821 AH

11 Length of DB list E 821BH

12 Le ngt h of SB list E 821CH

13 Le ngt h of PB list E 821 DH

14 Le ngt h of FB list E 821E H

15 Length of OB list E 821FH

16 Lengt h of FX list E 8220H

17 Length of DX list E 8221H

18 Lengt h of DB a ddre ss li st (DB 0) E 8222H

19 Slot ID (see belo w) CPU ID 2 (see bel ow) E 8223H

20 Block header l e ngt h E 822 4H

21 CPU ID 1 (see be low) Progra m m er int er face

softwar e version E 8225H

You can also use the SYSTE M PARAMET E R PG online fun ctio n to

find the information contained in a few system data registers (e.g.,

conc e rni ng the int er na l struc tur e of the CPU, the softwar e versi on, the

CPU ID).

Addressable System Data Area

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 43

Word 19 and word 21

Struc tu re of words 19 and 21:

Word 19

B it no. High byte

15 0

14 0

13 0

12 0

11 Slot ID CPU 4

10 Slot ID CPU 3

9 Slot ID CPU 2

8 Slot ID CPU 1

Low byte

7 CPU typ e:

0010 = CPU 948

(only valid in conjunction with the CPU ID)

3 CPU-ID 2:

1000 = S5-155U

Addressable System Data Area

CPU 948 Programming Guide

8 - 44 C79000-G8576-C848-04

Word 21

B it no. High byte

15 reserved

B it no. Low byte

Rele a se of the PG i nt erfa ce software

in the form "xyH"

Example:

13H corre sp o nds to rel ease "V1. 3"

Addressable System Data Area

CPU 948 Programming Guide

C79000-G8576-C848-04 8 - 45

Addressable System Data Area

CPU 948 Programming Guide

8 - 46 C79000-G8576-C848-04

Cont ents of Ch apter 9

9.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 4

9.2 Memory Acc e ss via Addre sses in ACCU 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 8

9.2.1 LIR/TIR: Loading to or Transferring from a 16-Bit Memory Area Indirectly. . . . . . . . . 9 - 9

9.2.2 Ex amples of Acce ss to DW > 255 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 15

9.2.3 LDI/TDI: Loading to or Transferrin g from a 32-Bit Memory Area Indirectly . . . . . . . 9 - 17

9.3 T r ansferring Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 19

9.4 Operations with the Base Address Register (BR Register). . . . . . . . . . . . . . . . . . . . . . . 9 - 22

9.4.1 Op erat i ons for Transf er betw ee n Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 23

9.4.2 Accessi ng the Loc al Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 24

9.4. 3 Accessi ng the Gl oba l Mem ory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 25

9.4.4 Acc essi ng the Dual-Por t RAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 29

Memory Access Using

Absolute Addresse s

CPU 948 Programm in g Gui de

C79000-G8576-C848-04 9 - 1

Contents

CPU 948 Programming Guide

9 - 2 C79000-G8576-C848-04

9Memory Access Using

Absolute Addresse s

Thi s cha pt er ex plai ns how to use ST E P 5 ope ra ti ons and spe c ia l

ST EP 5 reg ist er s to addre ss da ta in ce rt ain m emor y ar eas usi ng

absol ut e addr esse s.

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 3

9.1 Introduction

The STE P 5 programming l an gua ge conta ins opera tions wi th whi c h

you can access the entire memory area. These operations belong to the

"syste m oper ations".

The ope ra tions de sc ri be d in this cha pt er work wit h 20- bit ab solu te

addr esse s. Conse qu entl y, they are depen de nt on the mem ory siz e and

type, the perip hera ls, CPs, an d IPs of your progr am mable cont roller.

Warning

If the operations described in this chapter are not used properly,

ST EP 5 blo ck s and syste m dat a ca n be ove rwri tte n. The re fo re ,

only exp er ienc ed prog ramme rs shou ld use opera tion s tha t work

with absolute addresses.

Local memor y

Loc al memor y is the me mory are a that is available in eac h CPU. It

inc lud es t he foll owi ng: user subm odul e , RI/RJ a re a , RS/RT ar ea,

counters, timers, flags, pr ocess image s.

Global memory

Gl oba l me mo ry exist s only once for a ll CPUs. You add re ss it vi a the

S5 bu s.

Memory organization

Me mory a re a s are organize d in bytes or in words as follows:

•• Byte s: Ea ch add re ss add resses a byt e.

•• Word s: E ach a ddr ess addresses a 16-bi t wor d

(= 2 byte s).

Organ ization of the local me m ory i s fixed (se e Cha pt er 8 )

Organ ization of the global memory depe nds on t he type of modu le s

tha t a re p lug ge d int o th e progra m m ab le controlle r:

Introduction

CPU 948 Programming Guide

9 - 4 C79000-G8576-C848-04

Pages

1024 byte/words

2048 byte/words

F 0000H

F F000H

F F400H

F FC00H

F FE00H

F FFFFH

F FEFFH

F EFFFH

Page address register

(select register)

The global memory is external

and is available via the S5 bus.

It exists as a common memory

area shared by all CPUs in

one PLC.

The local memory is internal

and is available in each

CPU (acc. to the number

of CPUs plugged)

15 0

0 0000H

E FBFFH

E FC00H

E FFFFH FFH

715 0255

F ig. 9- 1 Glo bal an d local memory

Introduction

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 5

Memory access

Usi ng a bsol ute addre s se s, you can acc ess t he followi ng lo ca l or glo ba l

me mo ry a re as wi th the o pera ti ons in dica te d (ref er t o Fig. 9- 2).

Access to the local and global

area

You can access both the local and global areas:

•• Loc al area (add resses 0 00 00H to E FFFFH) and globa l area

(ad dresse s F 0000H to F FFFFH) with:

LIR, TIR, LDI, TDI, TNW, TXB, TXW,

•• Se cti on of t he loc a l area or ga nize d in wo rds (addre ss e s 0 0000H

to E FBFFH) or in bytes (addresse s E FC000 to E FFFF) with:

LRW, TRW, L RD, T RD.

Access only to the global area

You can acc ess the follo wing parts of the glob al area:

•• Sec ti on of the glob al area organ ize d in bytes (a ddre sse s F 0000H

to F FFFFH) with:

LY GB, LY GW, LY GD, TY GB, TY GW, TY GD, TSG,

•• Sec ti on of the g lob al area org an ize d in words (a ddre sse s F 0000H

to F FFFFH) with:

LW GW, LW GD, TW GW, TW GD, TSG .

Access to the page area

You can acc ess the fol lo wing par ts of the pag e area :

•• Se cti on of t he glob al area organ iz ed in by tes (a ddre ss e s F F400H

to F FBFFH, = dual -por t RAM area) with:

LY CB, LY CW, LY CD, TY CB, TY CW, TY CD, TSC,

•• Se cti on of t he glob al area organ iz ed in wor ds (a ddre ss e s F F400H

to F FBFFH, = dual -por t RAM area) with:

LW CW, LW CD, TW CW, TW CD, TSC

Introduction

CPU 948 Programming Guide

9 - 6 C79000-G8576-C848-04

access not possible access possible

c) LY GB, LY GW, LY GD,

e) LY CB, LY CW, LY CD,

TY CB, TY CW, TY CD, (TSC) f) LW CW, LW CD,

TW CW, TW CD, (TSC)

TY GB, TY GW, TY GD, (TSG) d) LW GW, LW GD,

TW GW, TW GD, (TSG)

b) LRW, TRW, LRD, TRD

a) LIR, TIR, LDI, TDI, TNW, TXB TXW

Access in multiprocessor

mode can lead to errors

Fig. 9-2 Access to local or global areas using absolute addresses

Introduction

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 7

9.2 Memory Acc ess via Addre ss in ACCU 1

Application

The ope rati ons l ist ed in th is se ctio n are sui tabl e p rima ri ly for acc e ss to

da t a bl oc ks a nd other ope rand are a s. Y ou sh oul d, h owever, not access

bloc ks c ont aini ng ST EP 5 progra m s (OBs, FBs, PBs and SBs) wit h

the se o p er at io ns.

To a cce ss the se area s, you c an use var iou s 16 or 32- bit wide regi ste rs.

The se registers inc lu de the acc umul at ors ACC U 1 t o ACCU 4 and

othe r spec ia l re giste rs use d a s resourc e s by the CPU.

Operations

Operation Operand Function

LIR Register

no.

0 to 15

Load the 16-bit r egist er wit h the c ontent

of a mem ory word a ddre s se d by AC C U 1

(20 -bi t addre ss).

TIR Register

no.

0 to 15

Load the content of the 16-bit regi ste r in

the memo ry word add ressed by ACCU 1

(20 -bi t addre ss).

LDI Register

name Load the 32-bit re gist er wit h th e cont e nts

of the me mory w or ds ’n’ a nd ’n +1 ’

addre sse d by ACCU 1 (20-b it add ress).

TDI Register

name Load the contents of the 32-bi t re giste r in

the memo ry words ’n’ and ’n+1’ add re ssed

by ACCU 1 (20-b it add ress).

The absolu te ad dre ss of the memo ry word or the fi rst of the two

me mo ry words is loca te d in ACCU 1 in the followi ng re pr ese nt ati on:

The fol lowi ng pa ge s e xpl ai n which r eg iste r s you c an use with the

operations.

Exa m ples expl ai n how to use the operations.

Ta ble 9- 1 Op e rations for i ndirect mem o ry acc es s using registers

Bit no. ACCU-1-H ACCU-1-L

31 20 19 16 15

0Address bits Address bits 0 to 15

16 to 19

Memory Acces s via Address in ACCU 1

CPU 948 Programming Guide

9 - 8 C79000-G8576-C848-04

9.2.1

LIR/TIR: Loading to or

Transferri n g from a 16-Bit

Memory Area Indirectly

The fol lowi ng tab le shows whi ch reg ist er num be rs you c an use wi th

the CPU 948 for the LI R and TI R opera ti ons a nd ho w thes e are

assig ned.

0 ACCU-1-H (left word of ACCU1, bits 16 to 31)1)

1 ACCU-1-L (right word of ACCU1, bits 0 to 15)1)

2 ACCU-2-H

3 ACCU-2-L

5 Block sta c k poi nter (o ffse t)

6 DBA (da ta blo ck start a ddr ess re gister)

8 DBL (da ta block le ngth re gister)

9 ACCU-3-H

10 ACCU-3-L

11 ACCU-4-H

12 ACCU-4-L

1) Loading the contents of an addressed memory register into register ’0’or ’1

overwrites the address stored in ACCU 1.

Re gi ste rs 4, 7, 13, 14 and 15 do n ot e xi st on t he CPU 9 48. LI R/T IR

op erat io ns wit h the se re gist e r numbe rs m ust no t be use d.

LIR/TI R: with 8-bit

memory areas

If you use the LIR and TIR operations to access memory areas that are

only 8 bits wide , reme mb er that

•• the LIR operation overwrites the high byte of the registers with

no n-de fine d val ue s (ex ce pt for fl a gs, PIQ, PI I ; wit h these are as,

FFH is written in the high byte)

and

•• the TIR operation transfers only the low byte of the register. The

h igh b yte of t he reg ister is lost .

Figs. 9-3 and 9-4 illustrate the diffe re nce when acc essi ng wor d and

byte-oriented memory areas using LIR/TIR.

Tab le 9-2 16-bi t regi s te r for LIR/TIR

Memory Acces s via Address in ACCU 1

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 9

19 0 15 0

19 0

ACCU 1

addressed

memory

location

addressed

memory

location

15 0

LIR n

TIR n

15 0

Fig. 9-3 LIR/TIR with 16-bit memory areas (word-oriented)

19 0 15 0

19 0

ACCU 1

addressed

memory

location

addressed

memory

location

15 0

LIR n

TIR n

Fig. 9-4 LIR/TIR with 8-bit memory areas (byte-oriented)

Memory Acces s via Address in ACCU 1

CPU 948 Programming Guide

9 - 10 C79000-G8576-C848-04

Registers 0 to 3 and 9 to 12:

ACCUs 1, 2, 3 and 4

During program process ing, the accumul a tors are used a s b uffers for

the CPU. T he TI R ope rati on t ra nsfe rs th e cont e nts of the acc um ul ato rs

into a bso lute ly addr esse d me mory re giste rs. The LIR oper at ion load s

the con te nt s of absolu te ly add re ssed me mory re gi ste rs i nto the

ac cu mu lato rs. The a bsol ute a ddre ss of t he mem ory l oc atio ns is in

ACCU 1, bit number 0 to 19.

Examples

Start Address)

When you open a data block or an extended data block using the

C DB or CX DX operations, the address of DW 0 in the opened data

bl oc k is loa de d int o re gi ste r 6. The bl oc k address li st in DB 0 co nta i ns

this a ddr ess.

The DBA regist e r is set to ’0’ be for e each OB 1 ca ll.

The DBA regist e r re m ains the same if one of the fo llowin g occu rs:

•• a jump oper ation (JU/JC ) cause s pro gra m proce ssing to continu e in

a different block,

•• the CPU ac tiva tes a diff eren t progra m proce ssing le vel.

The contents of the memory location with address E F800 are loaded in flag

word FW 100.

:L DH 000E F800 Load address E F800 of the memory location in ACCU 1

:LIR 1 Load the contents of the memory location addressed by

: ACCU 1 in register 1 (= ACCU-1-L)

:T FW 100 Store the contents of address E F800 in flag word FW 100

:BE

The content of the flag word 200 is transferred to the memory location with

address E F8 00.

:L FW 200 Load flag word FW 200 in ACCU 1

:L DH 000E F800 Load address E F800 to which the data will be trans-

: ferred in ACCU 1 (flag word FW 200 to ACCU 2)

:TIR 3 Transfer the contents of register 3 = ACCU-2-L in to

: the memory location addressed by ACCU 1

:BE

Memory Acces s via Address in ACCU 1

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 11

The DBA regist e r changes if one of the followi ng oc c urs:

•• An o the r data bl oc k is opened ,

•• the progr am re turns to a highe r ord er bloc k aft er a new da ta block

is opened in the called block (refer to Section 2.4.3).

Example

Effect of the "CX DX 17" operation on the DBA register:

When DX 17 is called, the address of the memory word in which DW 0 is

stored is entered in the DBA register. In this example, the DBA is 4152H.

Note: In the I STACK, the address enter ed i n th e DB A regist er a ppears under

the heading ’DB- ADD’ .

5 words

Block header

KH = 0000

KH = 0001

4 151BH

4 151CH

4 151DH

4 151EH

4 151FH

4 1520H

4 1521H

4 1522H

DW 0 (at Paragraph address)

DW 1

DW 2

DBA

Addresses DX17

Fig. 9-5 Using the DBA register

Memory Acces s via Address in ACCU 1

CPU 948 Programming Guide

9 - 12 C79000-G8576-C848-04

DBL = Data Block Length

In add ition to the DBA registe r, a DBL registe r is loade d every tim e a

dat a block is ca lled . It contai ns the leng th (in words) of the dat a bloc k

called, without the b loc k he a de r. The DBL re gi ste r is se t t o ’0’ before

each OB 1 call.

DBL re giste r is retained, when

•• pr ogra m exec ut io n is c ont inu ed i n a diff er en t bl oc k following a

jump stat ement (JU/JC)

•• a dif fe re nt pr ogra m exec ut io n leve l i s nest e d in.

It cha nge s when

•• a dif ferent da t a bl ock is opened

•• pr ogra m exec ut io n re tur ns to a hig he r orde r bloc k a fte r a new d ata

block is opened in the called block (refer to Section 2.4.2).

Note

You can cha nge the DBA and DBL regist e rs usin g LIR opera tions

to ad dre ss da ta blo ck add re sses higher tha n 255. The DBA

re gi ste r c ont a ins paragraph addresses. Make sure that a c hange

in the DBA regi ster does not au tomati cal ly ca use a change in the

DBL register and vice - versa. Thi s would me an tha t transfe r

er ror m onit oring i s no longer guarante ed.

On the CPU 9 48, chan ge s in th e DBA/DBL regist e rs are undone,

as soon a s the current blo ck is complete d (BST ACK e nt rie s).

Ma nipul at io ns on the DBA/DBL re gist e rs are the re fore only

effe c ti ve in the block i n whic h the y wer e made .

Memory Acces s via Address in ACCU 1

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 13

Example

Effect of the "CX DX 17" operation on the DBL:

When DX 17 is called, the number of existing data words is entered in the

DBL register. In this example the DBL is 8 (DW 0 to DW 7)

Note: In the I STAC K, t he number en tere d in the DBL reg iste r appears under the

heading "DBL -REG ".

5 words

Block header

eeee

ffff

gggg

aaaa

bbbb

cccc

dddd

hhhh

4 151BH

4 151CH

4 151DH

4 151EH

4 151FH

4 1520H

4 1521H

4 1522H

4 1523H

4 1524H

4 1525H

4 1526H

4 1527H

DW 0

DW 1

DW 2

DW 3

DW 4

DW 5

DW 6

DW 7

DBA

DBL

Addresses DX17

Fig. 9-6 Using the DBL register

Memory Acces s via Address in ACCU 1

CPU 948 Programming Guide

9 - 14 C79000-G8576-C848-04

9.2.2

Examples of Access to

DW > 255

Example 1:

The content of data word DW 300 in DB 100 is read and transferred to flag

word FW 100 (by changing the STEP 5 operation shown in bold face, it can

a ls o be used to read other data blocks (DB or DX)).

FB 5

SEGMENT 1 0000 Reading out DW 300 from DB 100

N AM E :L IR DW

0005 :L DH 000E EC00 Start addr. of the DB list

0008 :L KF +100 plus the DB number

000A :+D = Address list entry of DB 100

000B : (Bits 4 to 19)

000C :LIR 1 Start addr. DB 100 to ACCU 1

000D :SLD 4 Convert addr. to physical addr.

000E :L KF +300 DW 300 is read out

0010 :+D Addr. = start addr. of DB + DW addr.

0011 :LIR 1 Store content of DW 300 to ACCU 1

0012 :T FW 100 in FW 100

0013 :BE

Example 2:

All the data words of a data block will have a constant written to them.

The program shown below writes the constant KH = A5A5 to all data words of

DB 100. After changing the STEP 5 operations shown in bold face, it can

also be used to write values to other data blocks (DB or DX). Non-existent

data blocks are detected and cause a jump to the NIVO marker.

The program uses three accumulators. Within the loop, the accumulator

contents do not change.

ACCU 1 initially contains the address of the first data word and is

incremented by one each time the loop is run through.

ACCU 2 contains the address of the last data word + 1. The loop is

terminated as soon as the content of ACCU 1 is the same as the content of

ACCU 2.

To write the data words, the operation TIR 10 is used which stores the

content of ACCU-3-L (the constant) at the address contained in ACCU 1.

ACCU contents within the loop:

ACCU 1: address of the current data word to be written to

ACCU 2: address of the last data word to be written to + 1

A CC U 3: co ns tant

Continued on the next page

Memory Acces s via Address in ACCU 1

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 15

Example 2 continued:

Flag assignment:

FW 10: Bits 4 to 19 of the start address of the DB/DX (points to DW 0)

FW 12: Length of the DB/DX (number of data words)

FD 14: Address of the last data word in the DB/DX + 1 (physical address)

FB 6

SEGMENT 1 0000 Writing a DB with a constant

NAME :FILL DB

0005 : ! Required flags: FY 10 to FY 17 !

0006 :L DH 000E EC00 Start addr. of the DB list

0009 :L KF +100 plus the DB numbe r

000B :+D = Address list entry of DB 100

000C : (Bits 4 to 19)

000D :LIR 1 Start addr. DB 100 to ACCU 1

000E :T FW 10 Buffer start addr.

000F :L KB 0 (Paragraph address)

0010 :!=F If start addr. = 0, then

0011 :JC =NIVO DB does not exist

0012 :

0013 :L FW 10 Start addr. of DB (1st DW)

0014 :SLD 4 Convert addr. to physical address

0015 :L KB 1 Find out DB length via

0016 :-D 5th word in block header

0017 :LIR 1 Length including block header to ACCU 1

0018 :ADD BN -5 Number of DWs = total length - 5 words (header)

0019 :

001A :T FW 12 Buffer length

001B :

001C :L FW 12 Number of data words +

001D :L FW 10 start address (DW 0 converted to

001E :SLD 4 physical address)

001F :+D produces

0020 :T FD 14 address of the last DW + 1

0021 :

0022 :L KH A5A5 Consta nt, writ ten to all data word s

0024 :

0025 :L FD 14 Address of the last DW + 1

0026 :ENT Shift constant to ACCU-3-L

0027 : (= register 10)

0028 :L FW 10 Convert address of 1st data word (DW 0)

0029 :SLD 4 to physical address

002A :

002B SCHL : Loop:

002C : ACCU 1: address of DW to be written to

002D : ACCU 2: address of last DW + 1

002E : ACCU 3: constant

002F :TIR 10 Store the value of ACCU-3-L in the DW with

0030 : the address in ACCU 1

0031 :

0032 :ADD DH 0000 0001 Increment address by 1

0035 :

0036 :><D Scan whether last DW reached

0037 :JC =SCHL (if not, return to the loop)

0038 :

0039 WEIT : Continue the program ...

003A : after all DWs have been written to ...

003B :

003C :BEU

003D :

003E NIVO : If DB 100 does not exist

003F :BE

Memory Acces s via Address in ACCU 1

CPU 948 Programming Guide

9 - 16 C79000-G8576-C848-04

9.2.3

LDI/TDI: Loading to or

Transferri n g from a 32-Bit

Memory Area Indirectly

The fol lowi ng tab le shows whi ch reg ist er n ame s you ca n use on the

CPU 94 8 for the LDI a nd TDI ope ra t ion s and how the se are assig ne d.

Regi ste r name Re giste r assignme nt (e ach 32 bits wi de)

A1 AC CU 1 (ACCU1, bits 0 to 31) 1)

A2 AC CU 2 (ACCU1, bits 0 to 31)

SA STE P ad dress counter (bit s 0 to 19)

B A BA reg ist er (blo ck sta rt addr ess, bi ts 0 to 19)

BR BR regist e r (ba se add re ss reg ist er , bits 0 to 19)

1) Loading the contents of an addressed memory register into the A1 register overwri tes

the address stored in ACCU 1.

Byte addresses

If you re fe re nc e b yte a ddre sses with the LDI or T DI ope ra ti ons, not e

the following:

•• the LDI op er at io n overwri te s th e high byte of the regi ste r with non-

defined values (exc ept for fla gs, PIQ, PII; with the se area s, FFH is

wr it te n in the hig h byt e)

and

•• the TDI op er at io n tra n sf er s o nly the low by te s of th e re gi ste r (t he

high bytes are lost – refer to the example on the following page

Data storage with LDI/T DI

Tab le 9-3 32-bi t regi s te r for LD I /T DI

High register Low register

31 16 15

DW n

Address

DW n+1

aaaa

bbbb

Memory Acces s via Address in ACCU 1

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 17

SA Register:

SAC = STEP Address

Counter

On com plet ion of the operat ion, the 20-b it abso lut e add re ss of the

operation to be proc esse d ne xt is e ntere d in the SA register.

BA Register:

Block Start Addres s

Dur ing progr am pro ce ssi ng of t he STEP 5 use r prog ra m, a 20-bi t

absol ut e addr ess i s ent e re d in the BA r egist er . Thi s add re ss is in the

highe r orde r block (corre spon ds to the return add re ss). It is the add re s s

of the operati on to be proc essed next.

BR Register:

Available Base Address

The base a ddr ess re gi ste r (2 0 bits) a llows you t o cal cu late addre sses

and t o exec ut e indi re ct lo ad and tra nsfe r op er atio ns wit hout usin g the

ACC Us for th e addr ess. It ca n be use d fre ely du rin g STE P 5 progra m

processing.

Example of TDI in the byte

area

:L DH 1234 5678 Load data

:L DH 000E FC00 Load address of flag

: byte FY 0

:TDI A2 Store content of ACCU 2

E FC00 = 34 (The values ’12H’ and ’56H’ from

E FC01 = 78 ACCU 2 are lost)

Memory Acces s via Address in ACCU 1

CPU 948 Programming Guide

9 - 18 C79000-G8576-C848-04

9.3 Transferring Memory Blocks

Application

Wit h the op erat io ns ex plai ne d in this se c tion, you c an re -sto re dat a

are as with a leng th of up to 255 words locat ed in certa in ad dress ar eas.

Operations

Operation Operand Function

TNW 0 to 255 Fie ld transfe r 0 to 255 word s 1)

( in the 16-bi t me mo ry a re a)

TX B - - Fie ld tra nsfe r from 8- bit to the 16-bi t

memory

TXW - - Fie ld tra nsfe r fro m the 16-bi t to the

8-bit memory

1) Can also be used for transfer from the byte to the byte area.

Parameters

Field length

For TNW: Operan d = number of words (0 to 255)

For TXB/ TXW ACCU 3 = numb er of words (0 to 127 )

End addre ss of the sour ce area

ACC U 2 = end a ddre ss of the source are a (20 bits)

End addre ss of the dest inat ion are a

ACC U 1 = end a ddre ss of t he destination area (20 bit s )

The entire so urc e and d est in at io n ar ea s m ust be lo cat ed in one of the

me mo ry a re as l isted in T ab le 9-5 and cannot overlap.

Permitt ed memory areas

Addre sses Me mory area

0 0000H to C FFFFH User memory:

16 -bi t a re a (d epende nt o n m e m ory

configuration)

Tab le 9-4 Operat i ons for fi el d t rans fe r

Table 9-5 Memory areas permitted for TNW, TXB and TXW

Transf erring Mem ory Block s

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 19

Addre sses Me mory area

Table 9-5 continued:

E 8000H to E 9FFFH

E B000H to E FBFFH

E A000H to E AFFFH

E FC00H to E FFFFH

F 0000H t o F FFFFH

Syste m RAM:

Syste m data, 16 bits

Syste m dat a (RI/RS, t ime rs, cou nters e tc. ),

16 bits

S flag s, 8 bits, low byte in 16-bi t word

(High byte not defined)

Flag s, pr ocess i mage , 8 bits

(High byte = FFH)

I /Os, 8/16 bits

(R efer a l so to Ch apter 8)

Sequence

The field transfer is made in descending order, i.e. it begins with the

highe st add re ss of the sour ce are a (= end addre ss) a nd ends wi th the

lowest.

TNW, TXB and TXW

operations

The ope rati ons T NW , TXB and T XW are lon g-ru nni ng ST EP 5

op er atio ns whic h c a n onl y be i nt errupted by POW ER DOWN a nd

QVZ.

Special features

Interruptions

by POWER DOWN

If one of the opera tion s is inte rrup ted by a power failure (NAU)

followed by a warm restart, the operation does not resume at the point

at whic h it was inte rru pted bu t from the beginning agai n .

Interrupt ions by QVZ

If a timeo ut (QVZ ) occ urs du rin g the tran sfe r, t he ope ra tion is

inte rr upt ed and the approp ria t e erro r OB calle d.

The error a ddr ess i s the ad dre ss at whic h an e rror occ ur re d (re fer to

Se ction 5. 6.3).

Transferring Memory Blocks

CPU 948 Programming Guide

9 - 20 C79000-G8576-C848-04

ADF during execution

If an addr essi ng erro r (ADF) oc curs onc e or more than once during t he

tra nsfe r, all the par t fields a re first trans f erre d an d then OB 25 i s cal led

before the next operation is executed.

Example

TXB and TXW between 8 and 16-bit memory areas:

Transferring bytes 1 to 6 from an 8-bit to a 16-bit area:

:L <field length in words> e.g. :L KH 0003

: L <source address> :L DH EFC1 0

:ENT :ENT

:L <de stination ad dress> :L DH EF208

:TXB :TXB

Transferring bytes 1 to 6 from a 16-bit to an 8-bit area:

:L <field length in words> e.g. :L KH 0003

: L <source address> :L DH EF00 8

:ENT :ENT

:L <de stination ad dress> :L DH EFC10

:TXW :TXW

Ascending

Addresses

Byte 5

Byte 6 TXB

TXW

Byte 4

Byte 3

Byte 2

Byte 1

Source/

Destination

Address

15 70

Ascending

Addresses

Source/

Destination

Address

Byte 4

Byte 2

Byte 5

Byte 6 Byte 3

Byte 1

Fig. 9-7 Transferring memory fields

Transf erring Mem ory Block s

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 21

9.4 Operations with the Base Address Register (BR Register)

Application

The base a ddr ess re gi ste r (2 0 bits) a llows you t o cal cu late addre sses

and use in dir ect reg ist er loa d and tr an sfe r ope ra ti ons wi tho ut using t he

ACCUs.

The memory loca tion whose absol ute addre ss is ca lcul ate d as the sum

of the BR registe r c ont en t plus a const ant is ac cessed.

Absolute addre ss = BR regist e r conte nt + const ant

Operations

Operation Operand Function

MBR

ABR

Constant

(0H to

F FFFFH)

Constant

(- 32 768 t o

+32 7 6 7)

Loa d t he BR re gist e r with a

2 0-bi t const ant

Ad d a 16-bi t const ant to the content s

of the BR register

Changing the BR register

•• The BR register is retained, whe n th e progra m is cont inued in a

di ffe re nt bloc k of the sam e pr ogr am exec uti on leve l due to a

jum p stat eme nt (’JU FB’/ ’JC FB’) .

•• The BR register is retained after nesti ng in a diffe rent pr ogram

ex ec u tion le vel.

•• If a di ffere nt program e xecu ti on le vel is called by the system

p rogram, the BR re giste r is set to ’0’ .

Table 9-6 Load and arithmetic operations with the BR register

Operations with the Base Addres s Register (BR Regist er)

CPU 948 Programming Guide

9 - 22 C79000-G8576-C848-04

9.4.1

Operatio ns for

Transfer b etw een Reg isters

Application

You can use the operations described in this section for the fast

exc ha nge of value s bet we en the re gist e rs ACCU 1 (32 bits), ste p

addr ess c oun ter (SAC - 20 bits) an d BR regi ste r (20 bits).

Operations

Operation Operand Function

MAS

MAB

MSA

MSB

MBA

MBS

---

Tra nsf er the content s of ACCU 1 to

the STE P a ddre ss c ount e r (20 bi ts)

Tra nsf er the content s of ACCU 1 to

the base a ddr ess re gi ste r (2 0 bits )

Transfer the contents of the STEP

address counter (20 bits) to ACCU 1 1)

Transfer the contents of the STEP

address counter (20 bits) to the base

ad d re ss r eg ist er (20 bi ts)

Transfer the contents of the base

add re ss reg ist er (20 bits) t o ACCU 1 1)

Transfer the contents of the base

ad d re ss r eg ist er (20 bi ts) t o the STEP

address counter (20 bits)

1) Bits 220 to 231 are set to ’0’.

The fol lowi ng fi gur e illustr at e s how the re gi ste rs a re chan g ed by the

operations.

Tab le 9-7 Regis te r- regist er ope ra tions

Operat ions with the Base Address Register (BR Register )

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 23

9.4.2

Accessing the Local

Memory

Application

The fol lowi ng op er at io ns al lo w ac cess t o the loca l me m ory or ga niz e d

in words usi ng an a bsol ute mem or y addre ss. The absol ute addre ss is

the sum of the co ntent s of th e BR r egist er and the 16-bit con stant

cont a ine d in the ope ra tion (-327 68 to +32 767) .

Operations

Operation Operand Description

LRW

LRD

Constant

(-32 768 to

+32767)

Constant

(-32 768 to

+32767)

add the specified constant to content 1)

of the BR regi ster and load the word

add ressed in this way in ACCU-1-L

add the specified constant to content 1)

of the BR register and load the double

wo rd addre sse d in thi s way in ACCU 1

TRW Constant

(-32 768 to

+32767)

add the specified constant to content

o f the BR register and tra nsfe r th e

con tent of ACCU-1-L to the word

add ressed in this way

xx 00 00

...... ......

20 19 0

ACCU 1

MAS, MAB MSA, MBA

BR,

SAC BR,

SAC

ACCU 1

31 20 19 0

19 019 0

MSB MBS

SAC

BR BR

SAC

19 0

19 019 0

19 0

Fig. 9-8 T ra nsfer operati ons from one re gi ster to anot her

Table 9-8 Operations for accessing the local memory

Operations with the Base Addres s Register (BR Regist er)

CPU 948 Programming Guide

9 - 24 C79000-G8576-C848-04

Operation Operand Description

Table 9-8 continued:

TRD Constant

(-32 768 to

+32767)

add the specified constant to content

o f the BR register and tra nsfe r th e

con tent of ACCU 1 to the double word

add ressed in this way

1) ACCU 2 new = ACCU 1old

Error reaction

If the cal cula ted a ddr ess of the mem ory loc a ti on is no t betwe e n

0 0000H a nd E FFFFH, the CPU detect s a load/tra nsfe r error (TRAF )

and calls OB 32. If OB 32 is not loade d, th e CPU change s to the stop

mode with the erro r code TRAF (ISTAC K).

9.4.3

Accessing the Global

Memory

Application

Thi s sec tion de sc ribe s the opera tions yo u can use wit h absol ute

me mo ry a ddresse s to ac ce ss th e gl oba l m e mory organiz e d in byte s or

wor ds. The a bsol ute addre ss is t he sum of the co ntent s of th e BR

regi ste r a nd t he con sta nt s con ta in ed in th e oper at io n (-32 768 to 3276 7).

Testing and setting an

"occupied" register in

the global area

You can control access of individual CPUs to commonly used memory

areas by using an "occupied" register. An "occupied" register is assigned

to ea ch com monl y used me mor y are a. Eac h par ticipa ting CPU mus t test

this register before access ing the memory area. The "occupied" register

contains either the value ’0’ or the slot ID of the CPU that is presently

usin g the me mory ar ea. When th e CPU is fin ished using th e memo ry

ar ea, it write s ’0’ to the "occupie d" register to re-enable the memory

area. (N ote the e xpla nations for the opera tions "set s em aphore/SED" and

"enable sem aphore/SEE " in Section 3. 5.5.)

The TSG operation enables testing and setting of "occupied" registers.

Operation Operand Description

TS G -32768 to

+32767 A d d the spe cifi e d constant to the con te nt

o f the BR register a nd t est an d set the

loc a ti on a ddre ssed in thi s way.

Operat ions with the Base Address Register (BR Register )

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 25

Sequence

The loc a ti on use d i s t he low byte of th e wor d ad dre s se d by th e BR

regi ste r plus th e const ant. If the con te nt of the low byte is ’0’, the TSG

op er at ion ente rs th e sl ot I D i n the lo ca t ion .

Te sti ng (re a di ng) a nd po ssibl e occ up at io n of the loc at io n (writi ng)

form a pro gram unit tha t ca nnot be int e rrupted.

Result

You can eva luat e the resu lt of the test using condit ion code s CC 0 and

CC 1:

CC 1 CC 0 De scr i ptio n

The "occ up ie d" re gi ste r c ont ains ’0’ . The CP U

ente rs i ts own sl ot ID.

The slot ID of the CPU is already ent e red

in the "occupied" register.

The "occupied" register contains a

different slot ID.

Note

All CPUs tha t require sync hro nize d access to a comm on glo bal

m e mor y ar e a must use the T SG ope rati on.

Error reaction

The absolute address mu st be betwee n F 0000H and F FFFFH. If the

absol ut e addresse s a re not in the range shown, the CPU detect s a

tra nsfe r error (TR AF) an d calls OB 32. If OB 32 is not loaded, the

CPU cha nges to the STOP m ode with the erro r code TRAF (I STAC K).

Operations with the Base Addres s Register (BR Regist er)

CPU 948 Programming Guide

9 - 26 C79000-G8576-C848-04

Load and transfer

operatio ns on the

global memory organized

in bytes

Operation Operand Description

LY GB

LY GW

LY GD

TY GB

TY GW

TY GD

-32768 to

+32767

-32768 to

+32767

-32768 to

+32767

-32768 to

+32767

-32768 to

+32767

-32768 to

+32767

add the specified constant to content

of the BR register and load the byte

add ressed in this way in ACCU-1-L L 1)

add the specified constant to content

of the BR regi ster and load the word

add ressed in this way in ACCU-1-L 2) 3)

add the specified constant to content

of the BR register and load the double

wo rd addre sse d in thi s way in ACCU 13)

add the specified constant to content

o f the BR register and tra nsfe r th e

con tent of ACCU-1-LL to the byte

add ressed in this way

add the specified constant to content

o f the BR register and tra nsfe r th e

con tent of ACCU-1-L to the word

add ressed in this way

add the specified constant to content

o f the BR register and tra nsfe r th e

con tent of ACCU 1 to the double

wo rd a ddre ss e d in thi s wa y

1) ACCU-1-LH and ACCU-1-H are set to ’0’.

2) ACCU-1-H is set to ’0’.

3) ACCU 2 new : = ACCU 1old

Error reaction

The ra nge of absol ute addre s se s for t he loa d a nd tr an sfe r opera ti on s

fo r the gl obal me mory org an iz e d in by te s

•• betwee n F 0000H and F FFFFH (LY GB, TY GB),

•• bet ween F 000 0H and F FFFEH (LY GW, TY GW)

•• bet ween F 0000H an d F FFFCH (LY GD, TY GD).

Tab le 9-9 Operat i ons for ac cess to t he global mem ory organized

i n byte s

Operat ions with the Base Address Register (BR Register )

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 27

If the absolu te ad dresses are not in the range shown, the CPU detec ts a

loa d/tra nsfe r erro r (TRAF) and c alls OB 32. If OB 32 is not loaded,

the CPU changes to the STOP mode with the error code TRAF

(ISTACK).

Load and transfer

operatio ns for the

global memory

organized in wor ds

Operation Operand Description

LW GW

LW GD

TW GW

TW GD

-32768 to

+32767

-32768 to

+32767

-32768 to

+32767

-32768 to

+32767

add the specified constant to content

of the BR regi ster and load the word

add ressed in this way in ACCU-1-L 1) 2)

add the specified constant to content

of the BR register and load the double

wo rd addre sse d in thi s way in ACCU 1 2)

add the specified constant to content

o f the BR register and tra nsfe r th e

con tent of ACCU-1-L to the word

add ressed in this way

add the specified constant to content

o f the BR register tra nsfe r the

con tent of ACCU 1 to the double

wo rd a ddre ss e d in thi s wa y

1) ACCU-1-H is set to ’0’.

2) ACCU 2 new : = ACCU 1old

Error reaction

The ra nge of absol ute a ddress es must be loc a ted

•• bet ween F 0000H and F FFFFH (LW GW, TW GW)

•• bet ween F 000 0H and F FFFEH (LW GD, TW GD).

If the absolu te ad dresses are not in the range shown, the CPU detec ts a

loa d/tra nsfe r erro r (TRAF) and c alls OB 32. ACCU 1 cont ains t he

erro r ID 1A01H. If OB 32 is not loa de d, the CPU change s to the

ST OP mode with the error c ode TRAF (IST ACK).

Table 9-10 Operations for access to the global memory organized

in words

Operations with the Base Addres s Register (BR Regist er)

CPU 948 Programming Guide

9 - 28 C79000-G8576-C848-04

9.4.4

Accessing the Dual-Port

RAM Memor y

Application

Wit h the foll owin g opera tions, you c an a cce ss page s orga ni zed a s

bytes or words usin g an a bso lut e mem ory a ddr ess. The abs o lute

addr ess i s the sum of the BR re gi ste r cont e nt and t he constant

cont a ine d in the ope ra tion (-327 68 to 32767 ).

Sequence of page access

Betwee n the add resses F F400 H to F FBFFH, the global memor y area

has a windo w for accessin g one of a maxi mu m of 256 memor y area s

ca lled dua l-port RAM p ag es. One dua l-port RAM page ca n occ upy a

ma ximum of 2K addr esse s a nd can be or ganiz e d in ei ther by tes or

words. Bef ore acc ess to th e dual-po rt RAM are a , one of the 256 page s

must be selected by entering its number in the select register (page

addr ess re gi ste r ). The p roc edure of writi ng t o the se lec t regi ste r a nd

the n ac cessing t he dual-port RAM area c annot be i nte rrupted.

Before you c an access the dual -port RAM area (l oad/transfer), you must

select one of the 256 dual-port RAM pa ges. D o this by put ting the

number of the dua l-port RAM page t hat you want to ope n int o

ACC U-1 -L. Us e the AC R ope rati on to ent er this num ber in to the

CPU -inte rnal dual -por t RAM regi ste r. All dual-port RAM opera ti ons

tha t follo w ACR writ e the conte nts of th e dual-port RAM regi ste r into

the sel ect reg ist er o f the corre s po ndi ng m odul e s on the S5 bus be fo re

dual -po rt RAM access.

Changing the page regist er

•• The page re gister is retained when another block is called.

•• If t he pa ge reg ister i s ch an ged in a blo ck , its value i s retained

wh en the progra m returns t o the calli ng bloc k at the end of the

block.

•• The page re gister is retained afte r nesti ng i n another progr am

ex ec u tion le vel.

Operat ions with the Base Address Register (BR Register )

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 29

Open in g a d ual-po rt RAM

page

Operation Parameter Description

ACR Open the dua l-port RA M page w hose

number is located in ACCU-1-L ,

perm issibl e value s: 0 to 255

The dual-port RA M page numbe r m ust be betwee n 0 and 255. If it is not,

the CPU dete cts a subs ti tution err or (S UF) and calls OB 27. If OB 27 is

not loaded, the CP U c hanges to the S TOP mode.

Testing and setting an

"occu pied " register in

the dual-p o rt RAM area

You can control access of individual CPUs to commonly used memory

areas by using an "occupied" register. An "occupied" register is assigned

to ea ch com monl y used me mor y are a. Eac h par ticipa ting CPU mus t test

this register before access ing the memory area. The "occupied" register

contains either the value ’0’ or the slot ID of the CPU that is presently

usin g the me mory ar ea. When th e CPU is fin ished using th e memo ry

ar ea, it write s ’0’ to the "occupie d" register to re-enable the memory

area. (N ote the e xpla nations of the opera tions "set s em aphore/SED" and

"enable sem aphore/SEE " in Section 3.5.5.)

The TSC operation handles the testing and setting of a location on the

open pa ge.

Operation Operand Description

TS C -32 768 to

+32 767 Add the spec ifi e d consta nt to the content

o f the BR register a nd t est an d set the

loc a ti on addressed in t hi s way on the

open page.

Sequence

The low by te of the word addresse d by the sum of the BR re gist e r +

const a nt is used as the "oc cupied" regist e r. If the low byte cont ain s

’0’, the TSC ope rati on enters t he slot ID of the CPU in the "oc cupie d"

Te sti ng (re a di ng) a nd po ssibl e occ up at io n (writi ng) fo rm a pro gra m

unit that cannot be interrupted.

Operations with the Base Addres s Register (BR Regist er)

CPU 948 Programming Guide

9 - 30 C79000-G8576-C848-04

Result

You can evaluate the result of the TSC operation using condition

code s CC 0 a nd CC 1:

CC 1 CC 0 De scr i ptio n

The "occ up ie d" re gi ste r c ont ains ’0’ . The CP U

ente rs i ts own sl ot ID.

The slot ID of the CPU is already ent e red in

the "oc c upi e d" register.

The "occupied" register contains a

different slot ID.

Note

All CPUs th at requi re synchronized access to a common gl obal

memory area (dual-por t RAM area) m ust use the TSC operation.

Error reaction

The loca tion must be on the correspon din g module and on the

com mon page betwee n F F400H a nd F FBFFH. If this is not the case ,

the CPU rec og nizes a tra nsfe r error (TR AF) an d cal ls OB 32. If

OB 32 is not loa de d, the CPU cha nge s to the stop mode with th e error

code TRAF (ISTACK).

Load and transfer

operatio ns for the

dual -port RAM memory

organized in byte s

Operation Operand Description

LY CB

LY CW

LY CD

-32768 to

+32767

-32768 to

+32767

-32768 to

+32767

add the specified constant to content

of the BR register and load the byte

add ressed in this way in the ope n page

into ACCU-1 -LL 1) 3)

add the specified constant to content

of the BR regi ster and load the word

add ressed in this way in the ope n page

into ACCU-1 -L 2) 3)

add the specified constant to content

of the BR register and load the double

wo rd a ddre ss e d in thi s wa y in the open

page into ACCU 1 3)

Tab le 9-1 1 O pe ra ti ons fo r ac ce ss to p age s or ga nized in byt es

Operat ions with the Base Address Register (BR Register )

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 31

Operation Operand Description

Table 9-11 continued:

TY CB

TY CW

TY CD

-32768 to

+32767

-32768 to

+32767

-32768 to

+32767

add the specified constant to content

o f the BR register and tra nsfe r th e

con tent of ACCU-1-LL to the byte

add ressed in this way in the ope n page

add the specified constant to content

o f the BR register and tra nsfe r th e

con tent of ACCU-1-L to the word

add ressed in this way in the ope n

page

add the specified constant to content

o f the BR register and tra nsfe r th e

con tent of ACCU 1 to the double

wo rd a ddre ss e d in thi s wa y in the open

page.

1) ACCU-1-LH and ACCU-1-H are set to ’0’.

2) ACCU-1-H is set to ’0’.

3) ACCU 2 new: = ACCU 1old

Error reaction

The ra nge of absol ute a ddress es must be

•• between F F400H and F FBFFH (LY CB, TY CB),

•• betwee n F F400H and F FBFEH (LY CW, TY CW)

•• between F F400H and F FBFCH (LY CD, TY CD).

If the absolu te ad dresses are not in the range shown, the CPU detec ts a

loa d/tra nsfe r erro r (TRAF) and c alls OB 32. If OB 32 is not loaded,

the CPU changes to the STOP mode with the error bit TRAF

(ISTACK).

Operations with the Base Addres s Register (BR Regist er)

CPU 948 Programming Guide

9 - 32 C79000-G8576-C848-04

Load and transfer

operatio ns for the dual-po rt

RAM memory

org aniz ed in wo r ds

Operation Operand Description

LW CW

LW CD

TW CW

TW CD

-32768 to

+32767

-32768 to

+32767

-32768 to

+32767

-32768 to

+32767

add the specified constant to content

of the BR regi ster and load the word

add ressed in this way in the ope n page

into ACCU-1 -L 1)

add the specified constant to content

of the BR register and load the double

wo rd in t he pa ge add esse d in this way in

t he ope n page int o A CC U 1 2)

add the specified constant to content

o f the BR register and tra nsfe r th e

con tent s of ACCU-1- L to the word in

the ope n pa ge ad dre s se d in this way.

add the specified constant to content

o f the BR register and tra nsfe r th e

con te nt s of ACCU 1 to the doubl e word

in the op en pag e addresse d i n this way .

1) ACCU-1-H is set to ’0’.

2) ACCU 2 new: = ACCU 1old

Error reaction

The ra nge of absol ute a ddress es must be

•• between F F400H and F FBFFH (LW CW, TW CW)

•• betwee n F F400H and F FBFEH (LW CD, TW CD).

If the ab solute ad dre sses are not in the ran ge sh own, the syst em

pr ogra m detec ts a loa d/ tra ns f er err or (T RAF) a nd c all s OB 32. I f

OB 32 is not loa ded, the CPU change s to the STOP mode with the

erro r bit TRAF (IST ACK).

Tab le 9-1 2 O pe ra ti ons fo r access to p age s or ga ni zed as words

Operat ions with the Base Address Register (BR Register )

CPU 948 Programming Guide

C79000-G8576-C848-04 9 - 33

Operations with the Base Addres s Register (BR Regist er)

CPU 948 Programming Guide

9 - 34 C79000-G8576-C848-04

Contents of Chapter 10

10.1 Multiprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4

10.1.1 When to use the Mu ltipr ocesso r Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4

10 .1.2 W h at Co mm un icatio ns Mecha nis ms are Availa ble? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 - 4

10 .1.3 E x chang ing Data via I PC Fla gs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 5

10 .1.4 E x chang ing Data via Handling Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 - 8

10.1.5 Wha t needs to be Pro gra mme d for the Multiproc e ssor Mode? . . . . . . . . . . . . . . . . . . . 1 0 - 9

10.1.6 How to Create Data Block DB 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 9

10.1.7 Star ting up in the Multiproc e ssor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 13

10.1.8 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 14

10.2 Multiprocessor Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 15

10.2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 15

10.2.2 How the Transm it ter and Receiver are Identified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 16

10.2.3 Why Data is Buf fered. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 17

10.2.4 How the Buf fer is Proce sse d and Mana ged. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 18

10.2.5 Syste m Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 21

10.2.6 Calling Communication OBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 22

10.2.7 How to Assign Param ete rs to Comm unic ation OBs . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 23

10.2.8 How to Evalua te the Output Parame ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 24

10.3 Runtimes of the Communication OBs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 31

10.4 INITI ALI ZE Function (OB 200) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 33

10.4.1 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 33

10 .4.2 Call Parame ters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 35

10.4.3 Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 35

10.4.4 Output Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 38

Multiprocessor Mode and

Communication in the S5-155U

CPU 948 Programm in g Gui de

C79000-G8576-C848-04 10 - 1

10.5 SEND Function (OB 202) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 40

10.5.1 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 40

10 .5.2 Call Parame ters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 40

10.5.3 Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 40

10.5.4 Output Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 42

10.6 SEND TEST Function (OB 203) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 45

10.6.1 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 45

10 .6.2 Call Parame ters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 45

10.6.3 Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 45

10.6.4 Output Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 45

10.7 RECE IVE Funct ion (OB 204) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 47

10.7.1 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 47

10 .7.2 Call Parame ters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 47

10.7.3 Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 47

10.7.4 Output Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 48

10.8 RECE IVE TEST Funct ion (OB 205). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 51

10.8.1 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 51

10 .8.2 Call Parame ters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 51

10.8.3 Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 51

10.8.4 Output Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 51

10.9 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 53

10.9. 1 Cal ling the Spec ia l Function OB using Function B loc ks . . . . . . . . . . . . . . . . . . . . . . . 10 - 53

10.9.2 Transferring Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 60

10. 9. 3 Exten ding the IPC Flag Are a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 66

Contents

CPU 948 Programming Guide

10 - 2 C79000-G8576-C848-04

10Multiprocessor Mo de and

Communication in the S5-155U

At the begin nin g of this c hapte r, you will see when you ca n use the

mul tiproc e ssor m ode and which data exc hang e is possib le in this

mode . The cha pt er provi de s you wi th infor ma tion abo ut pr ogra mm ing

for mult iproc esso r operati on (Sec tion 10.1 ).

The sec on d part of the ch ap ter pro vid es yo u wit h deta ile d inst ruc t ion s

and e xa m ple s of e xc ha ngi ng l ar ge r am ou nts of dat a in th e

mul tiprocessor mode (mul ti proc e ssor com m uni cat ion Secti ons 10 .2 to

10.9 ).

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10.1 Multiprocessor Mode

Definitions of terms

The S5-155U is se t up for multipr oc esso r ope rati on as soon as you

plug in a coordin ator modu le, reg ardless of ho w ma ny CPUs or

CP/IPs a re plug ged in. The CPUs must be plugge d in without any

ga ps betwee n t he m.

10.1.1

When to use the

Multipro cessor Mo de •• If your use r pr ogra m is to o large for o ne CPU and the re is not

eno ugh m e mo ry, dist ri but e your pro gra m on sever al CPUs.

•• Whe n a par ticu lar part of your system has to be proc e ssed

espe c ial ly fast , sepa ra te the appr opri a te prog ra m part from the tota l

progr am and run it on its own fast CPU.

•• When your system consists of several parts that you can separate

easily and control independent ly, le t CPU 1 process system pa rt 1,

CPU 2 process s ystem part 2, e tc.

For mo re inform ation on multiprocessing, read the i nforma tion in your

system m anua l. T his w ill he lp you to decide which CP Us are be st s uited

for your problem.

10.1.2

What Co mmun icatio n s

Mechan isms are Availab le? •• "Interprocessor c ommu nicati on flags" are availa b le fo r cyclic

exchange of binary data betwee n CPU s (CPU 948, CP U 946/947,

CPU 928B, CPU 928 and CPU 922) or between CPUs a nd

com m uni cat ions proc e ssors (C Ps).

•• For t he ex ch an ge o f la rge amounts o f da ta (e.g., enti re da ta blocks)

bet ween the CPU 948, CPU 946/947, CPU 9 28B, CPU 928 a nd

CPU 922 you are supp orted by the "special fu nctions for

multiprocessing" OB 200 to OB 205 (for more information refer to

Sec tion 10 .2).

•• "Handl ing bl oc k s" are a vail able for c ommuni ca tion with

intelligent input/output modules (IPs) and with CPs (These

h an dli ng bl ocks must be ord er ed sepa rately).

Multiprocessor Mode

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10.1.3

Exchang i ng Data via IPC

Flags Interprocessor communica tion (IPC) flags are available for cyclic

exchange of binary da ta . They are used mainly for tra nsmitting

information byte by byte.

Da ta is tra nsfe rre d as fol lows:

CPU(s) ↔CPU(s)

CPU(s) ↔Com mu nica tions pr oc esso r(s)

The system prog ram tra nsfe rs IPC fl a gs onc e per cyc l e. For dat a

tra nsfe r betwe en CPUs, the IPC fla gs are buffe re d physic a lly on the

coordinator.

IPC fla gs are bytes th at are tra nsfe rre d. You defi ne them in DB 1 for

ea ch CPU as IPC i nput or output flags. If, for example, you hav e

defi ned fl ag byte 50 on the CPU 1 as an IPC output flag by te, i t s

signa l state is transf erre d cyclica lly via the coo rdi nator to the CPU on

whi c h the fl ag b yte F 50 is de fi ned as an IP C input flag byte.

Note

There is no error m e s sage wh en t he IPC flag byte e xists

ph ysic all y but is only writt en by one CPU and ne ve r read out a nd

vice-versa.

Memory a rea

With th e CPU 948 the memor y area for the IPC flag s in th e

coordinator and the CPs covers the addresses F F200H to F F2 FFH .

On a CPU/c omm uni c atio ns proc e ssor t here are 256 ava ila bl e IPC flag

bytes.

Jumper settings

To a voi d doub le assi gnm e nt s you must group the 256 a va ilab le IPC

fla g byt es on t he COR or CP m odu le s. Fields of 3 2 bytes c a n be

ena bl ed or disa bl e d (your syste m manu al co ntai ns inf orm a ti on about

se tt ing the ju mp ers).

Multiprocessor Mode

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Example

Note

The onl y flag bytes th at you ca n spe cify a s IPC fl ag s are the ones

ena ble d on the coor dinator or on the CP(s) . S flags cannot be

used as IPC flags!

A flag byte tha t is defined on one or more CP Us a s an IP C input

flag byte must be defined as an IPC output flag byte on one other

CPU or CP. An I PC ou tpu t flag b yte is only allowed on one CPU,

but this ma y be us e d a s an IP C input flag in all other CPUs in the

rack.

If you have fla g byte s tha t you have not de fine d a s IPC fla gs in a

CPU, you can use them as normal flags!

In D B 1, indi cate only the numbe r of IPC fla g byt es t hat you a ct ually

need: the s m aller the numbe r of IPC flag bytes, the s horter the

tr ansf er tim e!

CPU 1

IPC output flags:

FY 96 to FY 119

IPC input flags:

FY 120 to FY 125

CPU 2

Coordinator

IPC output flags:

FY 120 to FY 125

IPC input flags:

FY 96 to FY 119

Write

Read

Write

Read

Enabled area

per jumpers:

IPC flag bytes

FY 96 to FY 127

Fig. 10-1 Transferring IPC flags in the multiprocessor mode

Multiprocessor Mode

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Data exchange between

CPUs and communication

processors

If you want to exchange data between one CPU and one CP, you must

enable the necessary number of IPC flags on the CP. You have 256

by tes av aila ble tha t you can di vi de into grou ps of 32 byte s.

If you w ant to tra nsfer da ta from one CP U to s everal CP s, t he areas you

enable i n the CPs a nd the coordinator must not overlap, otherwise the

same address is assigned twice.

If you wa nt to use IPC flags simultaneously on th e coo r din at or a nd i n

one or mor e CPs, you must also preve nt doub le addre ssin g as follows:

Di vid e the IPC flags a m ong t he coo rdi na tor and the CPs in groups of

32 byte s. Remo ve jumpe rs on t he coordina tor to m ask the IPC flag

byte s that you wa nt to use in the CP (r efer to the syste m manua l) .

You can define a speci fic flag byte a s a n IP C out put fl ag in one CPU

only. Howeve r, you c an defi ne a specific fla g byte a s in IP C input fla g i n

several CPUs.

Example

CPU 1

Enabled area:

IPC flag bytes

FY 96 to FY 127

Enabled area:

IPC flag bytes

FY 192 to FY 223

CP 1

CP 2

CP 1

CP 2

CP 1

CP 2

IPC output flags:

CP 1: FY 96 to FY 119

CP 2: FY 201 to FY 205

IPC input flags:

CP 1: FY 120 to FY 125

CP 2: FY 195 to FY 200

Fig. 10-2 Example of IPC flag areas on the CPs

Multiprocessor Mode

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Transmit ting IPC flags in

multiprocessor oper ation

At the en d of eac h pr ogra m cycl e , alo ng wit h th e upda ti ng of t he

pr ocess i mage , the CPU tran smi ts the IPC fla gs spe c ifie d in DB 1

whe n the coo rdi na tor signa l s the CPU that it ca n acc ess t he S5 bus.

The coordi na to r allo ca tes t he bus enab le signal to each CPU in

se que nce . Whe n a CPU has acc ess t o the S5 bus, it can t ransm it o nly

one byt e. Beca use of this inte rleave d tran smissio n, rela ted (by te

groups) IPC flag infor ma tion can be sep ar ated an d subseque ntly

pr ocesse d wi th old or i nc orre ct val ue s.

If you want to transfer information that takes up more than one byt e,

you can pr ev ent corru pti on of data by setti ng a para met er in exte nd ed

dat a bloc k DX 0. Thi s pa rame t er uses se m aphore s to e nsu re tha t all

IPC f lags spe c ifie d in DB 1 are transf erre d in groups (se e Cha pt er 7).

Whi le one CPU is tran smi ttin g IPC fl ags, a not her CPU c annot

interr upt it. Be cau se the nex t CPU has to wait to transm it its da ta,

cyc li c progr am pro ce ssi ng of t his CPU i s dela ye d acc ord ing ly.

Under ce r tain circu m stanc es, the setti ng you ma ke in DX 0 can

incr e ase the cyc l e time consider ably.

Multiprocessor

communication

For tra nsfe rr ing dat a blocks or mor e exa c tly fiel ds of data wit h a siz e

of ma x. 64 byte (= 32 dat a words), the following speci al fun ctio ns ar e

integrated in the CPU:

•• OB 200: INI TIALI ZE : preassi gn

•• OB 202: SE ND: send a data field

•• OB 203: SEND TEST: test sending capacity

•• OB 204: RECEIVE : rec e iv e a da ta fie l d

•• OB 205: RECEIVE TEST: test receiving capacity

10.1.4

Exchang i ng Data via

Handling Blocks Handl ing block s are cap able of multip roce ssing . A specia l para m eter

assig nm ent for the mu ltipr oc esso r mode is not nece ssa ry. For more

infor ma t ion o n handl ing blocks re fe r t o the appro pri at e ma nua l .

Multiprocessor Mode

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10.1.5

What needs to be

Programmed for the

Multipro cessor Mo de?

•• To a llow the coord ina tor to coo rdi na te acce ss by the in div idu al

CPUs to the I/O area , you must prog ra m data block DB 1 . Ev en

if the CPU do es not use I/Os or the IPC flag s, a (emp ty) DB 1

must ex ist (for m ore in form a tion re fe r t o Sec t ion 1 0.1. 6)

•• Data block DX 0 m us t a lso e xist. P rogram t his s o t hat proces s

interrupts via input byte IB 0 are disabled and the system interrupts

are activated.

10.1.6

How to Create Data Bloc k

DB 1 For multi pro cess i ng, you must progr am DB 1 for e ac h CPU. Thi s

esta blishes t he inputs, outputs (b yte a ddre sses 0 to 127) a nd IPC

input and output fl ags wi th whic h each CP U wor ks.

Note

The syste m prog ram recogn iz es only t he inputs and outputs

de fi ned in DB 1 wh en i t up da te s the pro ce s s im a ge!

Inputting or changing DB 1

•• Create/modify DB 1 on the PG using the DB 1 screen form

•• by editing DB 1 as a data block on the PG and then transferring it

to the CPU.

Note

The CPU ac ce pts the entered or c hange d DB 1 only after a cold

restart!

Using the DB 1 screen form

1. Se lec t th e edi tor for th e DB 1 scre e n form on your P G

(re fe r to Fig. 10- 3).

2. E nte r the req uir ed val ue s for "di gi ta l input s" et c . as de ci m al

numbers.

Multiprocessor Mode

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3. Enter the values by pressing the enter key on the PG.

The PG then generates DB 1.

4. Tra nsfe r DB 1 to the CPU.

Note

Entry of the timer field length is ignored! This parameter must be

specified in DX 0 (see Chapter 7).

Example of the DB 1 s creen

form

Editing DB 1 as a data block

1. Write the DB 1 start ID i n data words 0, 1 a nd 2:

DW 0: KH = 4D41 (’M’ ’A’)

DW 1: KH = 534B (’S’ ’K’)

DW 2: KH = 3031 (’0’ ’1’)

DB 1

0, 1, 2, 3, 7, 10,

2, 4, 12,

50, 51, 60,

70, 72,100,

I/O assignment:

Digital inputs:

Digital outputs:

IPC flag inputs:

IPC flag outputs:

Timer field length:

Fig. 10-3 PG screen form for generating DB 1

Multiprocessor Mode

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2. Type i n the individual operand are as (from data w ord 3 onwards).

Before eac h ope rand area, you must spec ify an ID . T he possible ID

words are as follows:

ID word for digital inputs KH = DE00

ID word for digital outputs KH = D A 00

ID word for IPC input flags KH = CE 00

ID word for IPC output flags KH = CA 00

After each ID word, us e fixed-point form at to list the num bers of the

inputs and outputs used.

3. Compl ete the entr ies with the DB 1 end ID "KH = EEEE" a nd

tran sfe r DB 1 to the CPU.

Note

You can make the DB 1 entries in any order. Remember that the

pr oc ess ima ge of the i npu ts a nd out put s is upd at ed in the reverse

order to which you store the addresses in DB 1 (i.e. the last entry

is updated first).

Multiple ent ries of the same bytes (e .g., for te s t purpose s) are

possible. The s ys tem progra m makes multiple updates of the proc ess

imag es of bytes that ar e enter ed more than once .

Example of editing DB 1

DB 1 FD : CPU948ST.S 5D

0: KH = 4D41; DW 0-2:

1: KH = 534B ; St art ID

2: KH = 3031; for DB 1

3: KH = DE00; ID word for digital inputs

4: KF = +00000; Input byte 0

5: KF = +00001; Input byte 1

6: KF = +00002; Input byte 2

7: KF = +00003; Input byte 3

8: KF = +000 07; .

9: KF = +00010; Input byte 10

10: KH = DA00; ID word for digital outputs

11: KF = +00000; Output byte 0

12: KF = +00002; Output byte 2

1 3: KF = +000 04; .

14: KF = +00012; Output byte 12

15: KH = CE00; ID word for IPC flag inputs

1 6: KF = +000 50; F lag byte 50

1 7: KF = +000 51; .

1 8: KF = +000 60; F lag byte 60

19: KH = CA00; ID word for IPC flag outputs

2 0: KF = +000 70; F lag byte 70

2 1: KF = +000 72; .

2 2: KF = +001 00; F lag byte 10 0

2 3: KH = EEEE ; End ID

24:

Multiprocessor Mode

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Entering DB 1

The syste m prog ra m adop ts DB 1 during a c old restart. The syste m

pr ogra m chec ks t o see if the inp uts and outputs or IP C f lags in dicated

in DB 1 ex ist in th ei r corre s po ndi ng m odul e s. If the y a re not pr ese nt

the re , a DB 1 error ca use s the CPU to go int o the ST OP mod e and the

STOP LE D flash es sl owly . The CPU no longe r proce sse s your

program.

Aft er you pr ogra m DB 1 and the CPU acc ept s it durin g a col d resta rt ,

the following rules apply:

•• Only the inputs and outputs indicated in DB 1 can access peripheral

modules via the process i ma ges (L .../T. .. . ..IB, ...IW, ...ID, ...QB,

...QW, . ..QD operations and logic operations with inputs a nd output s).

Acce ss to process image addresses not entered in DB 1 cause

addressing errors.

•• You can load perip he ral byt es dire c tly by bypa ssing t he proc e ss

im ag e using the L PB/ L PY, L PW, L OY, L OW o pera tions for all

ac kno wle dgi ng i nput s, reg ar dle ss of ent rie s in DB 1 .

•• You can transfer directly (T PB/T PY, T PW) to bytes 0 to 127 only

for the outputs indicated in DB 1. This is because the process image is

also writ ten to during di rect t ransfer. Writing to I/O a ddresses not

entered in DB 1 causes an addressing error.

•• Transf er wit hout a proc ess imag e :

Dire c t transfer to byte addre sse s >127 i s possible regardless of the

entries in DB 1.

Dire c t transfe r of byt e a dd resses of the exte nded I/ Os (T OY,

T OW ) is also po ssibl e reg ardle ss of t he ent ri es i n DB 1.

Multiprocessor Mode

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10.1.7

Startin g up in th e

Multipro cessor Mo de You can sta rt the coord inat or for multipro ce ssi ng in one of the

foll owin g ways:

Initia l status: The RUN/STOP switch of each CPU is

in the RUN position. The RUN/STOP switch

on the coordinator is in the STOP position.

Handling: Mo ve the RUN/STOP swit c h on the coor din ator

from STOP to RUN. (Sta rting the S5-155U in

multipro cessor ope ration simply by star ting the

coo rdi na tor is possi ble onl y if t he co ordi na tor

itself caused the controller to change to the STOP

mode).

or:

Initia l status: Th e RU N/ST O P s wi tch of each CPU is i n

the RUN position as well as that of the

coordinator.

Handling: Use th e PG START f un ction to star t the

CP U that ca us ed the STO P in the requ ired

restart type .

Starting up individual CPUs

The resta rt t ype that eac h CPU now use s de pends on what took pla ce

while the CPU was in the STOP m ode. Some CPUs nee d MANUAL

WARM RE ST ART , others, a COLD REST ART .

If the CPU settings were not changed in that ti me , ex ec ute a manual

warm restart.

Note

Due to the va rious resta rt type s, incorre ct signal statu ses c an be

tra nsfe rre d fr om one CPU to anot he r via the IPC flags. Th is coul d

happen if the controller was in cycle prior to entering the STOP

mode . Pre vent t his by progr am m in g the start -up orga ni za tion

bloc ks OB 20, OB 21 and OB 22 ap p ropr iatel y.

You can call special function block OB 223 to check whether the

star t-up types of all the CPUs are the same (refer to Chapt er 6).

Multiprocessor Mode

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Power failure/ret urn of power

Whe n power i s shut off an d then rest ore d, the coord inat or sta rts

autom aticall y. In this case, all CPUs execute an AUTOMATIC

WARM REST A RT or an AUTOMATIC COLD RESTART,

de pe nd ing on the sett ing in DX 0 (se e Chap te r 7).

The sta rt -up of the ind ividua l CPUs in mult ip roc e ssor ope ra tion is

syn ch roni z ed . Ea ch CPU wai ts unt il all othe rs ha ve ende d thei r

init ial iza ti on phase . The n the y be gin the ir cyc l e simu ltan eo usly .

Howeve r, you ca n use a settin g in DX 0 to canc e l start -up

synchronization.

10.1.8

Test Mode Procee d as follows:

1. Ma ke sure tha t the "te st m ode " func tion is en ab le d on the

coordinator.

2. Switc h the mode sel e ctor on the COR from STOP to TE ST.

The BASP LE D goe s off.

3. Go throug h a COLD RE ST ART o r WARM REST ART on the

CPUs you want to cha nge to the RUN mo de .

Special features of test

operation

In test operation, you can run CPUs individually or in any combination.

CPUs in the STOP m ode cannot disable the e ntire PLC.

Star t-up of indiv idual CPUs is not syn chroni zed in te st ope ration. Th e

CPUs begi n their c ycli c oper atio n at diffe rent tim es ac cordi ng t o the

len gth of the sta rt -up organi zat ion blocks OB 20 , OB 21 or OB 22.

If an error occurs in one CPU during test operation, only that CP U goes

into the S T OP mode . The e rror doe s not affe ct the othe r CP Us .

Warning

Sinc e no CP U can output the BASP signal in case of an error

in the test mode, the test mode must be swit ched inact ive after

succ e ssful instal lat ion to avoi d a cr itic al or eve n danger ou s

situat ion ar i sing in the syst em.

Multiprocessor Mode

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10.2 Multiprocessor Communication

Definition

Multiprocessor communication means the exchange of larger

am ount s of data (dat a bloc ks) be twee n CPUs op er atin g in the

mul tiproc e ssor mode . The COR C is ne cessa ry for mult ipr ocesso r

communication.

10.2.1

Introduction To transfer data blocks, or to be more precise, blocks of data with a

ma xim um le ng th of 64 byt es (= 32 dat a wor ds), you c a n use the

foll owin g speci al funct ions tha t are inte grat ed in the CPU:

•• OB 200: INI TIALI ZE : preassi gn

•• OB 202: SE ND: send a fiel d of dat a

•• OB 203: SEND TEST: test sending capacity

•• OB 204: RECEIVE : rec e iv e a da ta fie l d

•• OB 205: RECEIVE TEST: test receiving capacity

The speci al fun ctio n OBs, OB 200 and OB 202 to OB 205 are simpl y

ca lled "com muni c atio n OBs" in the foll owi ng sectio ns.

Required knowledge

To use these func tions, you onl y require basi c knowl ed ge of the

STE P 5 program min g langu ag e and the way in which SIMAT IC S5

pr ogra mm ab le contr oll e rs ope ra te. You can obtai n thi s basic

informat ion from the pub li ca tion s l iste d in t he Further Rea ding.

Basic sequence

To tr an sfe r da ta , you m ust a c ti va te the SE ND func ti on on the

tra nsm itting CPU and the RECE IVE functio n on the rec e iving CPU.

The data words of a DB or DX data bloc k loca ted in the tran smi tt ing

CPU are transp ort ed via the coord ina tor 923 C to the r eceiv ing CPU

one after the other and written to the DB or DX data block with the

sa me numb er and unde r the sam e dat a word addre ss; i .e. this

re pr ese nt s a "1: 1" c opy op er at io n.

Data fields

The amou nt of dat a that ca n be tra nsfe rr ed with the SEND and

RECE IVE fun ctio ns is nor mal ly 32 words.

If the block le ngt h (wit hou t hea de r) is not a m ulti pl e of 32 words, th e

last fiel d of data to be transfe rred is an exc e ption a nd is less tha n 32

words long.

Multiprocessor Communication

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The data blo ck in the rec eivi ng CPU ca n be long er or short e r tha n the

dat a block to be sent . It is, howe ver, impor tant tha t the data words

tra nsfe rre d by the SEND func ti on exist in the rece iv ing bloc k;

ot he rwi se t he REC EI VE fu nc ti on sig nals an error.

Example:

10.2.2

How the Tran smitt er an d

Receiver are Identified Each field of data exchan ged betwee n the CPUs is marked with a

nu mb er t o in dic a te th e source and destination CPU .

The CPUs are number ed so that the leftmost CPU has the numbe r 1

and each subsequent CPU to the right has a number increased by 1.

Example

S5-135U/155U:

D ata to b e

s ent in t he

t rans mitting

CPU:

Data

received

in the

receiving

CPU:

Data block: DB 17 DB 17

Data word address: DW 32 to DW 63 DW 32 to DW 63

IQII Q

F ig. 10 -4 Se nde r/rec eiver identific at ion

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10 - 16 C79000-G8576-C848-04

10.2.3

Why Data is Buffered Gene ra ll y, the m ult ip rocessor mode is used to distrib ute ta sks on

several CPUs. Sin ce th e t asks are not ident ic a l a nd the perform a nce of

the C PUs invo lved ca n be differ en t, the progra m exe cut ion of the

indi vidua l CPs in the mu ltiproc esso r mode is alwa ys asynchronous.

Thi s m ea ns that the data sen t by a CPU cann ot alwa ys be recei ved

imme di ately by anothe r CPU.

For this reason, the data to be transferred is buffered on the

coordinator 923 C. The number of the sender and receiver are always

inc lud ed al ong wi th t he dat a .

Example

Data transfer from CPU 3 to CPU 2:

1st step:

CPU 3 buffers its data on the coordinator.

2nd step:

When CPU 2 is ready to receive, it copies the data from the coordinator

buffer to the destination DB.

SEND, parameter of receiving CPU = 2

QII Q

RECEIVE, parameter of transmitting CPU = 3

QII Q

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10.2.4

How th e Buffer is

Processed an d Man aged

Principle

The buff er is based on the FIFO pri ncip le (first i n - first out , que ue

principle). The data is received in the order in which it is sent. This

applies to each individual link (identified by the transmitting and

receiving CPU) and is independent of other links.

Data protection

The buffer is battery-backed; this means t hat the "automatic war m

rest ar t follo wing a powe r down" is possi bl e witho ut any rest ric tion s. A

loss of powe r durin g a dat a transfe r doe s not cause any lo ss of data in

the programmable controller.

Management

The co ordi nator 923 C ha s a me m ory c apacity o f 48 da ta fi el ds e ac h

wi th a fixed lengt h of 32 wo r ds. The INIT IAL IZ E funct ion a ssi g ns

the se fields to ind ivi dual CPU lin ks.

Each me mor y fi e ld can receive exactly one field of data. The length

of the data can be from 1 data wor d to 32 data words. A da ta fiel d is

entered in a memory fi eld by a SEND function and read out again by a

RE CEIVE f u nct ion.

The number of memory fields assigned to a link is directly related to the

parameters for the tra nsmitting capa ci ty (SE ND, S END T EST function)

and receiving capacity (RECEIVE, RECEIVE TEST function).

The transmi tting c apac it y indic a te s how man y of th e me mo ry fi el ds

reserved for a link are free at any particular time.

The rec eivi ng c apac ity ind ic a tes how m an y of th e me mo ry fi eld s

reserved for a link are occupied at any particular time.

The sum of the transmitting and receiving capacity is always equal to

the num be r of m em or y fie l ds re ser ved for a li nk.

Multiprocessor Com munication

CPU 948 Programming Guide

10 - 18 C79000-G8576-C848-04

Example

Occupation of the buffer by a link

The link between CPU 3 and CPU 2 is initialized. The link is assigned seven

memory fields in the buffer of the coordinator. Following this, the data

transfer shown below would be possible.

Sending/receiving n data fields means that the corresponding functions are

c al le d n times one after the ot her.

To simplify the representation, at any one time, data can either be sent or

received in this example.

It is, however, possible and useful to transmit (CPU 3) and receive (CPU 2)

simultaneously ("Parallel processing in a multiprocessor programmable

controller"). In the example, fields H and I are received while fields K

and L are sent .

The example illustrates the queue organization of the buffer: the fields of

data sent first (A,B,C...) are received first (A,B,C...).

Transmitter: CPU 3

initialize

send

field A send 4 fields

B, C, D, E send 4 fields

F, G, H, I send 2 fields

K, L

Time

receive

fields A, B receive

fields C, D,

E, F, G

receive

fields H, I receive

fields K, L

Transmitting capacity

(no. of free

memory fields)

Receiving capacity

(no. of free

memory fields)

3722

Receiver: CPU 2

Fig. 10-5 Example of the occupation of the COR buffer

Multiprocessor Communication

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 19

Summary

Bu ffe ring da ta on the coo rdi na tor COR 923C al lows the asyn ch rono u s

oper ation of transmi tting and recei ving CPUs and compen sate s for

the ir diffe re nt proce ssin g spe eds.

Sinc e the ca pa cit y of the buffe r is limit ed, the rece ive r shoul d che ck

"of ten" a nd "re gul a rly " whet he r ther e are da ta in the b uffe r (RECEI VE

TE ST fu ncti on, re cei vin g capac it y > 0) and should a ttem pt to fet ch

stored data (RECEIVE function). Ideally, the RECEIVE function

should be repeated until the receiving capacity is zero. This means that

the tra nsm it ted da t a are not buffe re d for a longe r pe riod of tim e an d

that the re c e ive r a lwa ys ha s th e c urr en t da ta . Th is a lso m e an s tha t

memory fields remain free (the transmitting capacity is increased) and

pr ev ents the se nder from b ei ng bl ocked (i .e . whe n the tr an smi tt ing

capacity is zero).

Note

A receiving capacity of zero represents the ideal state (i.e. all

transmitted data have been fetched by the receiver), on the other

hand a transmitting capacity of zero indicates incorre c t planning,

as follows :

- the SE ND f un ct io n is c al le d too often,

- t he RECEI VE fu ncti on is not called of ten enoug h

- t here a re not enough mem ory fi e lds assig ne d to the lin k.

The capac ity of the buffe r is insuf fici en t to com pensa t e tempo -

rary imba la nce s in the freq ue nc y with whic h the CPUs trans-

mit and receive data.

Multiprocessor Com munication

CPU 948 Programming Guide

10 - 20 C79000-G8576-C848-04

10.2.5

System Start-Up If you require multipr ocesso r commun ica tion, then all CPUs involved

must go through the same STOP-RUN tran sition (= REST ART ), i.e.

all the CPUs go throu gh a COLD REST ART or all CPUs go through a

WARM RE ST ART .

You must ma ke sure that the resta rt of a t lea st a ll the CPUs in vol ve d

in the com munica ti on i s uniform ( see Se ction 10 . 1.7), in the

foll owin g ways:

•• dire c t opera tion (front switc h, progr amm e r),

•• param e ter assign ment (DX 0)

and/or

•• pr ogra mm ing (us in g th e spe ci a l func t ion orga n i z ati o n blo c k O B 2 23

"stop if non-uniform restarts occur in the multiprocessor mode")

COLD RESTART

In orga ni za tion bloc k OB 20 (COL D REST ART ) onl y one CPU mu st

set up the buffer (in the COR 923C ) using the INIT IAL IZ E funct ion .

Any existing data is lost.

Fol lowing this, i .e. during t he REST ART, you can cal l the SEND,

SE ND TE ST, RECEI VE, RECE IVE TEST funct ions in the individua l

CPUs. W ith approp riat e progra m m ing , you must make sur e that this

on ly occurs a ft er the buff er in the coor din at or has be e n corre c tly

initialized.

On com plet ion of the REST ART , i.e. in the RUN mode, the user

pr ogram is proces sed from the beginning, i.e . f rom the first operat ion

in OB 1.

WARM REST ART

You must not use the INITIALIZ E function in th e orga niz ation bloc k s

OB 21 (MANUAL WARM REST ART ) and OB 22 (AUTOMATIC

WARM RE ST ART ). Calling the SEND, SEND TE ST, RE CEIVE ,

RECE IVE TEST fun ct ions ca n ca use p robl ems (r ef er to th e following

sections).

On com pl etio n of the WARM RE ST ART , i.e. in the RUN mod e, the

use r program is not proces s ed from th e star t, but from the poi nt at

which it was inte rr upte d. The poi nt of int er rupt io n can, for exa m pl e,

be within the SEND functi on.

Multiprocessor Communication

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 21

10.2.6

Calling Communication OBs

Procee d as follows:

1. Call the INIT IALIZ E function only in th e c ol d re start

organ iza tion bl ock OB 20 on one CPU.

2. Call the SEND, SEND TE ST, REC EIVE, RE CEIVE TEST

fu n ctio n s eith e r only withi n the cycli c progr am or only within the

tim e-drive n progra m.

Double call

De pendi ng on the assi gnm ent of para me ter s in DX 0 ("inte rru pts at

op erat io n bounda ries"), and the type of pro gra m exec ut ion (WAR M

RE ST ART , int er rupt handling, e.g. OB 26 for cyc le tim e erro r) it is

po ssibl e that on e of the func tion s INITIALIZ E , SEN D , SEN D T E ST,

RECEIVE and RECEIVE TEST can be interrupted.

If a use r inte rfa c e inse rt ed at the poi nt of int er rupt io n also c ont ai ns one

of the functions SE ND, SEND TEST, RECEIVE and RECE IVE

TE ST an ille gal ca ll (double call) is re co gni zed and a n error is

si gna lle d (error n umbe r 67, Sect ion 10.2. 8).

Parallel processi ng

Onc e you ha ve c om ple ted the assignm e nt of the buffer (INITIAL IZE

function), you can e xe cu te the functions SEND, SEND TE ST,

RE CE IV E and RECEIVE TES T in any c om binati on a nd wit h a ny

para me ter a ssign ment in all the CPUs sim ulta neou sly a nd para lle l to

each ot her .

Ta king a single link (e.g. fro m CPU 2 to CPU 3) it is possibl e to

exe cute the SEND func t ion (CPU 2) and the RECE IVE funct ion

(CPU 3 ) simul tane ousl y. While CPU 2 is send ing dat a field s to the

coor din ator, CPU 3 can alre ad y recei ve (fetch) bu ffere d data file ds

from the coordinator .

Areas occupied

The communica tion OBs do not requi re a workin g area (fo r buffer ing

vari a bles) a nd do not ca ll data bloc ks. The y do, of course , acc e ss area s

cont a ini ng pa ram e te rs, alth ough o nly the para me t er s ma rke d a s out put

parameters are modified.

Multiprocessor Com munication

CPU 948 Programming Guide

10 - 22 C79000-G8576-C848-04

Results bits

The re sult s bit s (CC 1/CC 0, RLO et c .) are in flu en ce d by the

com m uni cat ion OBs. For mor e detai led i nfor mat ion refer to Se ctio n

10.2.8.

Changes in the ACCUs

•• CPU 922, CPU 928,

C PU 928B: T he co n t en ts o f AC CU 1 t o AC C U 4 an d th e

contents of the registers are not affected by

the communication OBs.

•• CPU 946/9 47,

CPU 948: The contents of a ll registers a nd A CCU 1, 2

and 3 remai n the same, only the contents of

ACCU 4 are affected.

10.2.7

How to Assign Parameters

to Communication OBs The communicat ion OBs have the foll owing types of parame ter:

•• input parameter s,

•• ou tpu t paramete r s

and

•• call pa rameter s.

Input and output parameters are located in a maximum 10 byte long

data field in the F flag area. T he da ta fi el d is di vided int o a n area for

input par amete rs an d an a rea for out put par amete rs .

Input parameters

The inp ut pa ra m e te rs specify how a fu ncti on is ha ndled. All o r pa rt of

the par ame ters a re read out by com m unic atio n OBs and eval uate d, no

write access takes place.

Output param eters

The out put par am ete rs c ont a in all the in form a ti on t ha t the ca ll ing

pr ogra m ne ed s a bo ut the r esu lt of a job, e. g. e rror bit s.

Some or all of the output parameters are written to by the

com m uni ca t ion OBs, t his a re a is not rea d.

Note

You can assign a flag are a w ith 10 flag b ytes for all

communications functions. The functions themse lves require

different numbers of bytes. Refer to the description of the single

functions (Se ction 10. 4ff).

Multiprocessor Communication

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 23

Call parameters

For all commu nicati on OBs the numbe r of the first flag byte in the

data field (= point er to data field) in ACCU-1-L is transf erre d as the

call parameter. Permitted values are 0 to 246.

Example

10.2.8

How to Evalu ate t he

Output Parameters Among other things, the output parameters indicate whether or not a

function could be executed and if not they indicate the reason for the

ter mi na tion of the func t ion .

Condition codes

The INITIAL IZ E , SEND, SEND T EST , RECEIVE and REC EI VE

TE ST fu ncti ons a ffe ct the cond it ion cod es (se e progra mm ing

instr uc tions for your CPUs, gene ral no tes on the STE P 5 opera tions):

•• the OV and OS bits (wor d conditi on codes) a re alway s cleare d,

•• the OR, STA, ERAB bits (bit condition codes) are always cleared,

•• RLO, CC 1 and CC 0 i ndicate w hether a function ha s bee n e xec uted

co rrec tly and co mp letel y.

Dat a field with parameters for the RECE IVE function

(OB 204)

FY x + 0: transmitting CPU input parameter

F Y x + 1: — n ot u sed

FY x + 2: condition code byte output parameter

FY x + 3: receiving capacity output parameter

FY x + 4: block ID output parameter

FY x + 5: block number output parameter

FY x + 6: address of the first output parameter

FY x + 7: received data word output parameter

F Y x + 8: address of the la st outpu t para mete r

FY x + 9: received data word output parameter

This example illustrates that the number of the first F flag byte in the

data field must not be higher than FY 246, since otherwise the parameter

field of up to 10 bytes would exceed the limits of the flag area (FY 255).

Multiprocessor Com munication

CPU 948 Programming Guide

10 - 24 C79000-G8576-C848-04

Condition codes Evaluation Meaning

RL O CC 1 CC 0

0 0 0 JC= F un ction ex ec uted

completely and correctly

1 0 0 JC= Functio n ab orted,

pointer to data field

illegal (> 246)

Functio n ab orted

owing to an initialization

conflict

1 0 1 JC= and

JM= Functio n ab orted

owing to an error

(e rr or number 1 to 9)

1 1 0 JC= and

JP= Functio n ab orted

owi ng to a warni ng

(warning number 1 or 2)

In the fol lowi ng se ct ions, it is assume d that the pointe r to the data

fie ld contai ns a corr ec t value. T he first byt e of the output par am eter

provides detailed information about the cause of termination.

Condition code byte

Bit no.7654 321 0

W E I 0 Number

W = 1: Wa rning

E = 1: Error

I = 1: In i tial iz atio n conf lict

Number: - of a warning

- of an er r or

- of an initialization conflict

Table 10-1 Condition codes of the communication OBs

Multiprocessor Communication

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 25

The first byte in the field of the output parameters (condition code

by te) a lso i ndi ca t es whe t he r or not a fu nc ti on ha s be en c or re ct ly an d

com pl et e ly exe c ute d. This byte co nta i ns de ta ile d inf orm a ti on a bout

the cause of term i na ti on of a func t ion .

Assuming that at least the pointer to the data field contains a correct

value, t his byte is always relevant.

If the func t ion has be e n e xe cu ted c orre c tly a nd c om plet el y, all the bits

are cleared (= 0), and all other output parameters are relevant.

If the func tion is aborted wi th a wa rning (bit number 7 = 1), only the

condition code for the transmitting/receiving capacity is relevant,

ot he r out put pa ra me t er s (if t he y ex ist) are un change d.

If the funct ion is abort ed owing to a n error (b it num be r 6 = 1) or an

initia liz a ti on c onfl ic t (bit num be r 5 = 1), al l ot he r out put p ar ame te r s

re m a in unchanged.

Evaluation of the code byte

The ide nt if ie rs ’W ’, ’E ’ an d ’I’ in dic a te the si gni ficanc e o f the

numbers.

Apa rt from this bi t-b y-bi t eva luat io n, it is al so possi ble to int er pre t the

who le condi ti on c ode byt e as a fixe d point num be r wit hout sign. If

yo u inte rpre t the condi ti on c ode byt e as a byte, the groups of num be rs

have the followin g sign ific an ce:

Number group Significance

33 to 42

65 to 73

129 to 130

Function executed correctly and completely

Funct ion a bo rted owi ng to an initi aliza ti on

conflict

Func tion abo rted owi ng to an err or

Func tion abo rted owi ng to a warni ng

Errors are de te cted a nd indicated in the a scendi ng orde r of the error

numbers. This means that several errors may have occurred although

(currently) only one is indica ted. T he othe r e rrors are then indicated by

further cal ls.

Table 10-2 Code byte for the communication OBs/number groups

Multiprocessor Com munication

CPU 948 Programming Guide

10 - 26 C79000-G8576-C848-04

Example

Initialization conf lict

An init ia l iz a tion c onfl ic t ca n onl y oc cur with th e INI TI ALI ZAT I ON

fu ncti on. If a con fli ct occ urs, you m ust mod ify the progra m or the

parameters.

Initialization conflict numbers (evaluation of the condition code byte

as a byte):

Cond.

code

byte

Significance

33 The pa ges require d for multiproc essor comm unication

(numbe rs 252 to 255) are not or not a ll availa ble .

34 The pag es requ ired for mult iproc esso r commun ica tion

(nu mb er s 252 to 2 55) a re defect iv e.

35 The pa ramet er "autom atic/manual" i s illega l.

The following e rrors a re possible:

- the "auto matic /manu al" I D is less than 1,

- the "auto matic /manual" I D is g reater than 2 .

36 The par amete r "number of CPUs" is illega l .

The following errors are possible:

- the num be r of CPUs is less than 2,

- the numbe r of CPUs is gre ate r than 4.

37 The param et er "bl ock ID" is illega l.

The following e rrors a re possible:

- the block ID is l ess tha n 1,

- the block ID is gre at er than 2.

38 The parameter "block number" is incorrect, since it is a data

block with a special significance.

The following e rrors a re possible:

- if block ID = 1 DB 0, DB 1

- if block ID = 2 : DX 0

39 The pa ramet er "block numbe r " i s incorrec t, s ince t he data

block does not exist.

40 The pa ramet er "start addre ss of the assignment l ist" is too

high or the data block is too short.

T he SEN D function indicat es an er ror and is not

executed. If you then make program and/or

parameter modifications and the SEND function

again indicates an error with a higher number

than previously, you can assume that you have

corrected one of several errors.

Table 10-3 Condition code byte: Initialization conflict numbers

Multiprocessor Communication

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 27

Cond.

code

byte

Significance

Table 10-3 continued:

41 The assignme nt list i n th e dat a bloc k is no t corre c tl y

structured.

42 The sum of the assi gne d me mo ry fields is gr ea ter tha n 48.

Errors

If an error oc cu rs, you must c ha nge th e program/par am e te rs.

Error num be rs (e va lu at io n of th e condit ion code byte as a byt e) :

Cond.

code

byte

Significance

65 The parameter "receiving CPU" (SEND, SEND TEST)

is illegal. The following errors are possible:

- The number of the receiving CPU is greater than 4,

- the number of the receiving CPU is less than 1,

- the number of the receiving CPU is the same as the

CP U’s own num ber .

66 The parameter "transmitting CPU" (RECEIVE, RECEIVE

TEST) is illegal. Th e fo llowi n g errors are possi ble:

- The n umber o f the tran s mitting C P U is greater than 4 ,

- the number of the transmitting CPU is l ess tha n 1,

- the number of the transmitting CPU is t he same a s the

CPU’s own number.

67 The spe cial function organization bloc k c all is wrong

(SEND, RECEIVE, SEND TEST, RECEIVE TEST). The

following errors are possible:

- Secondary error, since the INITIALIZE function could

not be calle d or was te rmi nate d by an initial iza tion

conflict.

- Double call: the call for this function (SEND, SEND

TEST, RECEIVE or RECEIVE TEST) is illegal,

since one of the se func tions INIT IAL IZ E, SEND,

SEND T EST, RE CEIVE or RECEIVE TEST ha s

alre ady be en c alle d in this CPU in a lower

pro cess i ng leve l (i.e . cycli c program e xecu ti on).

- T he CPU’s own num ber i s inc orr ect (system data

corru pte d) ; follo wing powe r down/ powe r up the CPU

num ber i s gen erat e d agai n by the syste m progr am .

Ta ble 10- 4 Co ndi ti on code byte: Error numbe rs

Multiprocessor Com munication

CPU 948 Programming Guide

10 - 28 C79000-G8576-C848-04

Cond.

code

byte

Significance

Table 10-4 continued:

68 The ma nagem ent da ta (qu eue ma nageme nt ) of the

sele c ted links are incor re ct; set up the buffer in the

coord ina t or 923 C agai n using th e INITIAL IZ E funct ion

(SEND, RECEIVE , SEND TEST, R ECEIVE TEST).

69 The parameter "block ID" (SEND) or the block ID provided

by the sender (RECE IV E) is il legal. T he following errors a re

possible:

- The block ID is less than 1,

- the block ID is greater than 2.

70 The parameter "block number" (SEND ) or the block number

sup p lied b y the s end er ( RECEIVE) is ille g al, since it is a data

block with a special significance. The following errors are

possible:

- If the block ID = 1 : DB 0, DB 1

- if the block ID = 2 : DX 0

71 The parameter "block number" (SEND ) or the block number

provided by the sender (RECEIVE) is incorrect. The

specified data block does not exist.

72 The pa ramet er "field number" (S END ) i s incorrec t.

The data bloc k i s too short or the fie ld num ber too high.

73 The da ta bloc k i s not large enough t o re ceive the da ta field

tra nsmitt ed by the se nder ( RECE IVE) .

Multiprocessor Communication

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 29

Warning

The func t ion cou ld no t be ex ecuted; the func ti on c a ll must be

repeated, e.g. in the next cycle.

Warning numbers (evaluation of the condition code byte as a byte):

Cond.

code

byte

Significance

129 The SEND function cannot transfer data, since the

transmitting capacity was already zero when the

function was called.

130 The RECEIVE function cannot a cc ept data, since the

receiving capa ci ty wa s alrea dy z ero when the functi on

was called.

Table 10-5 Condition code bytes: Warning numbers

Multiprocessor Com munication

CPU 948 Programming Guide

10 - 30 C79000-G8576-C848-04

10.3 Runtimes of the Communication OBs

The "runt ime " is the pr ocessing time of the spe c ial fu ncti on

organization blocks; the time from calling a block to its termination

can be much greater if it is interrupted by higher priority activities

(e. g. upda ting time rs, etc.).

Spec ial function OB

Block

name CP U 922 CPU 92 8 CPU 928B CPU 946/

947 CPU 948

OB 200/

initialize 230 ms 13 0 ms 130 m s 128 ms 90 ms

OB 202/

send 806 µs (294 µs

basic time

+ 16 µs/word);

118 µs i f a

warning occu rs

666 µs (250 µs

ba sic time

+ 13 µs/word);

115 µs if a

war ning occu r s

696 µs (280 µs

bas i c t im e

+ 13 µs/word);

145 µs if a

wa rni ng oc c ur s

762 µs ( 426 µs

ba sic time

+ 21 µs/

doub l e wor d) ;

243 µs if a

wa rni ng oc c ur s

542 µs ( 220 µs

ba sic time

+ 19 µs/

double word);

110 µs if a

warning occu rs

OB 203/ send test 72 µs 50 µs 80 µs207µs 115 µs

OB 204/ receive 825 µs (281 µs

ba sic time

+ 17 µs/word);

115 µs i f a

warning occu rs

660 µs (244 µs

ba sic tim e

+ 13 µs/word);

98 µs if a

war ning occu r s

690 µs (274 µs

ba s ic time

+ 13 µs/word);

128 µs if a

wa rni ng oc c ur s

772 µs ( 421 µs

ba sic time

+ 22 µs/

doub l e wor d) ;

243 µs if a

wa rni ng oc c ur s

506 µs ( 218 µs

ba sic time

+ 18 µs/

double word);

132 µs if a

warning occu rs

OB 205/

r ece ive test 70 µs 48 µs78 µs 223 µs 120 µs

The runtim es li ste d in ta ble 10- 6 assume that of four CPUs inse rte d in

a rack , only the CPU whose runt im es are be ing mea sure d acce sse s the

SIMATIC S5 bus. If other CPUs use the bus inte nsiv ely, the run time

inc re ase s pa rt icul ar ly fo r the se nd/ re cei ve functions.

Table 10- 6 Runt imes of the comm unicat i on O Bs

Runtimes of the Communication OBs

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 31

Transfer time

An imp ortan t factor of a link (e.g. from CPU 1 to CPU 2) is the total

dat a tra nsfe r ti me. This i s made up of t he foll owi ng c om pone nt s:

•• time required to send (see runtime),

•• len gth of time the dat a are buffer ed (on th e COR 923C c oor din at or)

and

•• the time required to receive data (see runtime)

The lengt h of tim e that the data are "in transi t" is larg ely

depe ndent on the leng th of time that the data is buffe r ed and

ther e fore on the str uc tur e of the user pro gram (se e "Buffer ing

Dat a").

Runtimes of the Communication OBs

CPU 948 Programming Guide

10 - 32 C79000-G8576-C848-04

10.4 I NITIA LIZ E Function (OB 200)

10.4.1

Function To transfe r data from one CPU to ano the r CPU, th e data must be

tem po ra rily buf fe re d. The INIT IAL IZ E funct ion set s up a buffe r on

the COR 923C coordinator.

The memory is initi a lized i n fields wit h a fixed leng th of 32 words.

Each memory field accepts one data field wit h a le ngth betwe en 1 data

word and 32 data words. A da ta field is entered in a memory field by a

SEND func tion and rea d out by a RECEIVE function.

If you a re u sing two CPUs, there a re two li nk s (t r a nsfe r d i re c t i ons,

"channels"):

If you are using thre e CPUs, the re are six links:

CPU 1 CPU 2

CPU 2

CPU 3

CPU 1

INITIALIZE Function (OB 200)

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 33

If you are using four CPUs, th ere are twe lve link s:

The INITIA LIZE function specifies how t he total of 48 a v ailable memory

fields are assigned to the maximum twelve links.

This m ea ns tha t e ach pos s ible l ink, s pec ified by the parame te rs

"transmitting CPU" a nd "rec eiving CPU " ha s a ce rtain m em ory c apaci ty

available.

Note

Before you can call the SEND / RECEIVE / SEND TEST /

RECEIVE TEST functions, one CPU must have already called the

INITIALIZE function and executed it completely and without errors.

If the INITIAL IZE function i s c a ll e d sever al ti me s, one after the other,

the last a ssignme nt made is val id. While a CPU is processi ng the

INITI ALIZE fun ctio n, no other multiprocessor com m unic ation

fu ncti ons in cluding the INIT IAL IZ E func ti on c an be ca lled on oth er

CPUs.

CPU 3 CPU 4

CPU 1 CPU 2

INITIALIZE Function (OB 200)

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10 - 34 C79000-G8576-C848-04

10.4.2

Call Parameter s

Structure of the (parameter)

data field

Befo re ca ll ing OB 200, you must suppl y the input para met er s in the

da t a fie ld. OB 200 requires e ig ht F fl ag b yte s in t he data fie l d for input

and ou tpu t para met e rs:

FY x + 0: Mode (auto ma tic /

manu al ) input para me t er

FY x + 1: Number of CPUs input pa rameter

FY x + 2: Block ID input pa rame ter

FY x + 3: Block numbe r input para me ter

FY x + 4: Start add re ss of the input para me ter

FY x + 5: assignm e nt list

FY x + 6: Condit ion cod e byte ou tpu t para met e r

FY x + 7: Total capacity output parameter

ACCU-1 -L

Whe n OB 200 is cal le d, you tra nsfe r th e flag byt e numb er at whic h the

pa r a m eter d a ta field be gins to A C C U - 1- L :

ACCU-1-LH: 0

ACCU-1-L L : 0 to 246

10.4.3

Input Parameters

Mode (automatic/manual)

Mode = 1: automatic

Mode = 2: manual

Mo d e = 0 or 3 to 25 5: i ll e gal, ca us e s a n

initialization conflict

Number of CPUs

This parameter is only relevant when you have selected the

"automatic" mode. With the "automatic" setting, the memory fields

are divided evenly acc ordi ng to the num ber of CPUs.

Number of

CPUs Numbe r of

links Memory fields per

link

0; 1; 5 to 25 5 Ille ga l, cau ses a n init iali z atio n co nfl ict

INITIALIZE Function (OB 200)

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 35

Block ID, block number,

address assignment list

The parameters are only relevant if you select the "manual" mode.

You m ust then cre a te an ass i gnm e nt list in a dat a bloc k in whic h t he

48 avai labl e memo ry fields (or le ss) ar e assigne d to the ma ximu m 12

link s. This func tion is par ticula rly use ful when some CPUs tran sfe r

more data than others.

The CPUs not invo lved in the multiproc essor c om munica tion do not

nee d and should not have memory fields assigne d to them .

The parameters

•• bloc k ID,

•• bl oc k number

and

•• st art address of the a ssi gnm e nt list

specify where the assignment list is stored.

Block ID

ID = 1: DB data block

ID = 2: DX da t a bl oc k

ID = 0 or 3 to 255 : ill e gal, ca us e s a n

initialization conflict

Block numbe r

For the block number, you specify the number of the DB or DX data

bloc k in which the assig nm ent list is store d.

Start address of the

assignment list:

Al ong wi th the bloc k ID and number , this spe c if ie s the are a (o r mo re

pr eci sel y, the sta rt addre ss of th e are a ) in the data block i n whic h the

assig nm ent list is stored.

As the addr ess of the assi gnm ent l ist , speci fy the dat a word num be r at

whic h the assign ment list begins in fla g bytes FY x+4 (high byte) and

FY x+5 (low byt e) .

INITIALIZE Function (OB 200)

CPU 948 Programming Guide

10 - 36 C79000-G8576-C848-04

Assignment list

With the assignment list, you specify how many of the existing 48

memory fields are to be assigned to the links.

The li st is not c h anged by the system program. It has the following

structure.

Data word Format Value Significance

DW n + 0

DW n + 1

DW n + 2

DW n + 3

2 , a

3 , b

4 , c

Transmi tt e r = CPU 1

Recei ve r = CPU 2

Recei ve r = CPU 3

Recei ve r = CPU 4

DW n + 4

DW n + 5

DW n + 6

DW n + 7

1 , d

3 , e

4 , f

Transmi tt e r = CPU 2

Recei ve r = CPU 1

Recei ve r = CPU 3

Recei ve r = CPU 4

DW n + 8

DW n + 9

DW n + 10

DW n + 11

1 , g

2 , h

4 , i

Transmi tt e r = CPU 3

Recei ve r = CPU 1

Recei ve r = CPU 2

Recei ve r = CPU 4

DW n + 12

DW n + 13

DW n + 14

DW n + 15

1 , k

2 , l

3 , m

Transmi tt e r = CPU 4

Recei ve r = CPU 1

Recei ve r = CPU 2

Recei ve r = CPU 3

Instead of the l ower c ase letters a to m (in bold fa ce ) num bers between 0

and 48 must be inserted depending on the number of assigned memory

fields. The sum of these numbe rs must not e xce ed 48.

Note

You must keep to the structure shown in table 10-7 even if you have

less than four CPUs.

Tab le 10-7 Assignment li st fo r OB 200 ( in iti al ize )

INITIALIZE Function (OB 200)

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 37

Example

10.4.4

Output Parameters

Condition code byte

Thi s byte in form s you whethe r th e INI TI ALI ZE funct io n was

executed correctly and completely.

Initialization conf lict

The initialization conflicts listed are recognized and indicated by the

function in the ascending order of their numbers.

If an i nit ia liz a ti on c onfl ict occ ur s, yo u mu st c ha nge the

pr ogra m/p ar ame ters.

Al l the numb er s list e d in Ta ble 10- 3 can oc c ur in the condi ti on c ode

byte.

You have three CPUs in your rack, CPU 2 sends a lot of data to the other

two CPUs. The other two CPUs, however, only send a small amount of data

back to CPU 2 as acknowledgements in a logical handshake. There is no data

exchange between CPU 1 and CPU 3.

The assignment list is stored in data block DB 40 from DW 0 onwards and has

the follow ing pa rame ters:

DB40 FD: CPU948ST.S5D

0: KS = S1; Transmitter: CPU 1

1: KY = 2,2; R ec eiver: CP U 2/ 2 fields

2: KY = 3,0; Receiver: CPU 3/no field

3: KY = 4,0; R ec eiver: CP U 4 (d oes not exist)/no fi eld

4: KS = S2; Transmitter: CPU 2

5: KY = 1,22; Receiver: CPU 1/22 fields

6: KY = 3,22;Receiver: CPU 3/22 fields

7: KY = 4,0; Receive r: CP U 4 (does not exist)/n o field

8: KS = S3; Transmitter: CPU 3

9: KY = 1,0; Receiver: CPU 1/no field

1 0: KY = 2,2;Rec eiver: CP U 2/2 fields

1 1: KY = 4,0; Rec ei ver: CPU 4 (d oes not exist) /no field

12: KS = S4; Transmitter: CPU 4 (does not exist)

1 3: KY = 1,0; Receiver: CPU 1/no field

1 4: KY = 2,0; Receiver: CPU 2/no field

15: KY = 3,0; Receiver: CPU 3/no field

16:

INITIALIZE Function (OB 200)

CPU 948 Programming Guide

10 - 38 C79000-G8576-C848-04

Errors

The "error" number group cannot occ ur with the INITI ALIZE

function.

Warning

The "wa rning" number group cannot occ ur with the INITI ALIZE

function.

Total capacity

Thi s par am ete r spe cif ie s how m an y of the 48 ava ila bl e me mo ry fi eld s

are assi gne d to links.

In the "automatic" mode, this parameter always has the value 48. In the

"manual" mode, it can have a value less than 48. This means that existing

memory capacity is not used.

INITIALIZE Function (OB 200)

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 39

10.5 SEND Function (OB 202)

10.5.1

Function The SEND func tion tr ansfe rs a dat a field to the buf fer of the

COR 923C c oor din ator. It al so ind ic ate s how m an y data fiel ds can st ill

be sent or buffered.

10.5.2

Call Parameter s

Structure of the (parameter)

data field

Before calling OB 202 you must specify the input parameters in the data

field. OB 202 requires s ix F fla g byt es i n the da ta fie ld for input a nd

output param eters :

FY x + 0: recei vin g CP U input para met er

FY x + 1: block ID input pa rame t er

FY x + 2: block numbe r input pa rame t er

FY x + 3: field num be r input para me ter

FY x + 4 : condi ti on c ode byt e ou tpu t pa ra m et er

FY x + 5: transmitting capacity output parameter

ACCU-1 -L

Whe n OB 202 is cal led, transf er the flag by te at whic h the p aram ete r

dat a field begi ns to ACCU-1-L:

ACCU-1-LH: 0

ACCU-1-L L : 0 to 246

10.5.3

Input Parameters

Receiving CPU

CPU num ber of the re ce ive r (de stination); the perm itted value is bet ween

1 and 4 but must be different from the CPU’s own number.

SEND Function (O B 202)

CPU 948 Programming Guide

10 - 40 C79000-G8576-C848-04

Block ID

ID = 1: DB data block

ID = 2: DX da t a bl oc k

ID = 0 or 3 to 255 : ill e gal, ca us e s a n

err or messa ge

Block number

The blo ck num be r, al ong wi th t he b loc k ID and t he fie ld n um be r

specifies the area from which the data to be sent is taken (and where it

is to be stor ed in the rece iving CPU).

Remember that certain data blocks have a special significance, for

exa m ple, DB 0, DB 1 or DX 0 (see pro gra m ming instructi ons for your

CPUs). These data blocks must therefore not be used for the dat a

tra nsfe r desc rib ed her e!

If you a tt em pt to use these bl oc k num be rs, the fun ct io n is abort e d wit h

an error me ssa ge.

Field number

The field number indicates the area in which the data to be sent is

located.

Field

number Data ar e a

Fi rst data word L ast data word

DW 0

DW 3 2

DW 6 4

DW 9 6

DW 128

DW 160

DW 192

DW 224

DW 256

DW 288

DW 31

DW 63

DW 95

DW 127

DW 159

DW 191

DW 223

DW 255

DW 287

DW 319

SEND Function (OB 202)

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 41

The following si tua tion s are possi ble:

•• DB is longe r than sour ce area:

If the data bloc k is sufficient ly long , you obtain a 32-wor d long

are a per fie l d as sho wn in the table a bove .

•• DB is too short:

If the end of the data block is within the selected field, in the last

f ield a n are a wi th a leng th be twee n 1 a nd 32 words wil l be

transferred.

•• Fiel d is outsi de the DB:

I f the first data wor d ad dre s s of a f ield is not with in t he le ngt h of

the data blo ck , the SEND funct io n de te c ts a nd in dic a te s a n er ror.

Example

10.5.4

Output Parameters

Condition code byte

Thi s byte in form s you whethe r th e SEND function wa s exe cu te d

correctly and completely.

Initialization conf lict

Has no s ignificance w ith the S END function.

Data block with a length of 80 words: DW 0 to

DW 74, 5 words are required for the block header.

Field no.: First data word: Last data word: Length:

0 DW 0 DW 31 32 words

1 DW 32 DW 63 32 words

2 DW 64 DW 74 11 words

3 and

h ig he r In co rr ect parameter assi gnment

SEND Function (O B 202)

CPU 948 Programming Guide

10 - 42 C79000-G8576-C848-04

Errors

Whe n th e SEND func t ion is ca lle d, the follo wing err or num be rs

(evaluation of the condition code byte) can occur:

Condition

code byte Significance

65 The para me ter "re cei ving CPU" is illeg al.

The foll owin g errors are possible :

- The number of the rec eivi ng CPU is greater tha n 4,

- The number of the re cei ving CPU is less t han 1,

- The number of the rec eiving CPU is the same as

the CPU’s own num be r.

67 The spe cia l func ti on or ga niz a ti on bl oc k c al l is wr ong.

The foll owin g errors are possible :

- Secon da ry error , sinc e the INIT IAL IZ E functi on

could not be called or was terminated by an

i n itializ at i o n conflict.

- Double call: the call for this function, SEND, SEND

TEST, RECEIVE or RECEIVE TEST is illegal,

since one of the functions INITIALIZE, SEND,

SEND TEST, RECEIVE or RECEIVE TEST has

already been called in this CPU in a lower processing

level (e.g. cyclic program processing).

- The CPU’s own number is incorrect (system data

corrupted)

following power down/power up the CPU number

is generated again by the system program.

68 The m a nagement data (queue m anag eme nt) of the

sel ect e d links are incorrect ; set up the buffe r in

the coord inat or 923C again usi ng the INITI ALI ZE

function.

69 The paramete r " blo ck I D " is illegal.

The following errors are possible:

- The bloc k ID is less than 1,

- the bloc k ID is greate r tha n 2.

70 The paramete r " b lock num ber " is illegal, s in ce it is a d ata

block with a special significance.

The following errors are possible:

- If the bl ock ID = 1 : D B 0, D B 1

- If the bl ock ID = 2 : D X 0

71 The pa rame te r "bl ock numbe r" is in co rrect.

The specified data block does not exist.

72 The parameter "fie ld numbe r" is incorrect. The data

block is too s hort or the fi eld number too high.

SEND Function (OB 202)

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 43

Warning

The funct ion could be exe cuted; the function ca ll must be repe at ed,

e. g. i n th e ne xt cy cl e .

The fol lowi ng wa rni ng number s (ev alua ti on of the co ndi ti on c ode

byte) can occur:

Condition

code byte Significance

12 9 The SEND func t ion ca nno t tran sfe r data, sinc e t he

transm i tting ca pa c ity was alr ea dy ze ro whe n t he

function was called.

Transmitting capacity

The "tra nsm i tting ca pac it y" ind ic ate s how m an y data file ds ca n stil l be

sent and buffered.

SEND Function (O B 202)

CPU 948 Programming Guide

10 - 44 C79000-G8576-C848-04

10.6 SEND TEST Fun ction ( OB 20 3)

10.6.1

Function The SEND TE ST func ti on determ i nes the numbe r of free m emor y

fi elds i n the buf fe r of th e COR 923C c oor din at or.

De pending on thi s num be r m, the SE ND func t ion ca n be cal le d m

tim e s to tr an sfe r m da t a fie lds.

10.6.2

Call Parameter s

Structure of the (parameter)

data field

Be fo re ca ll in g OB 203, you must speci fy t he inpu t pa ra m ete rs in t he

da t a fie ld. OB 203 requires 4 F fl ag byte s in t he data fie l d for input

and ou tpu t para met e rs:

FY x + 0: recei vin g CP U input para met er

FY x + 1: — not used

FY x + 2 : condi ti on c ode byt e ou tpu t pa ra m et er

FY x + 3: transmitting capacity output parameter

ACCU-1-L

When OB 203 is called, transfer the flag byte number at which the

pa r a m eter d a ta field be gins to A C C U - 1- L :

ACCU-1-LH: 0

ACCU-1-L L : 0 to 246

10.6.3

Input Parameters

Receiving CPU

The CPU’s own nu mber a nd the numbe r of t he rece iv ing CPU ident ify

the lin k for whi c h the tr an smitt in g capacity is de t er mi ne d.

10.6.4

Output Parameters

Condition code byte

This byte indicates w hether t he SEND TE S T function w as executed

co rrec tly and co mp letely.

SEND TEST Function (OB 203)

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 45

Initialization conf lict

Has no significance for the SEND TEST function.

Errors

Whe n c alli ng t he SEND T EST fun ctio n, t he fol lowi ng e rro r num be rs

(evaluation of the condition code byte) can occur:

Condition

code byte Significance

65 The para me ter "re cei ving CPU" is illeg al.

The foll owin g errors are possible :

- The number of the rec eivi ng CPU is greater tha n 4,

- The number of the re cei ving CPU is less t han 1,

- The number of the rec eiving CPU is the same as

the CPU’s own num be r.

67 The spe cia l func ti on or ga niz a ti on bl oc k c al l is wr ong.

The foll owin g errors are possible :

- Secon da ry error , sinc e the INIT IAL IZ E functi on

could not be called or was terminated by an

i n itializ at i o n conflict.

- Double call: the call for this function, SEND, SEND

TEST, RECEIVE or RECEIVE TEST is illegal,

since one of the functions INITIALIZE, SEND,

SEND TEST, RECEIVE or RECEIVE TEST has

already been called in this CPU in a lower processing

level (e.g. cyclic program processing).

- The CPU’s own number is incorrect (system data

corrupted);

following power down/power up the CPU number

is generated again by the system program.

68 The m a nagement data (queue m anag eme nt) of the

sel ect e d links are incorrect ; set up the buffe r in

the coord inat or 923C again usi ng the INITI ALI ZE

function.

Warning

The "warning" num ber group c annot occ ur wit h the SEND TE ST

function.

Transmitting capacity

The "tra nsm i tt ing ca pa c it y" pa ra me ter indi c ate s how ma ny data fie ld s

ca n be sent and buff ered .

SEND TEST Function (OB 203)

CPU 948 Programming Guide

10 - 46 C79000-G8576-C848-04

10 .7 RECEIVE Functio n (OB 204)

10.7.1

Function The RE CE IVE f unc ti on tak es a da ta fiel d from the bu ffe r of t he

COR 923C c oor din ator. It al so ind ic ate s how m an y data fiel ds are st ill

buffered and can still be received.

The RECEIVE function should be called in a loop until all the

bu ffered da ta fi el ds ha ve be en r ec e iv ed.

10.7.2

Call Parameter s

Structure of the (parameter)

data field

Be fo re ca ll in g OB 204, you must speci fy t he inpu t pa ra m ete rs in t he

da t a fi e ld. OB 204 r eq uires 10 F fla g byt es i n the da ta fi el d fo r in pu t

and ou tpu t para met e rs:

FY x + 0: transm itt ing CPU input para me ter

FY x + 1: — not used

FY x + 2 : condi ti on c ode byt e ou tpu t pa ra m et e r

FY x + 3 : rece iving capacity output pa ra m ete r

FY x + 4 : block I D ou tpu t pa ra m ete r

FY x + 5: block number output parameter

FY x + 6: addre ss of the first ou tpu t param ete r

FY x + 7: recei ved data word output para mete r

FY x + 8: addre ss of the last output param eter

FY x + 9: recei ved data word

ACCU-1 -L

Whe n cal li ng OB 20 4, transfer the flag byt e num be r at whic h the

pa r a m eter d a ta field be gins to A C C U - 1- L :

ACCU-1-LH: 0

ACCU-1-L L : 0 to 246

10.7.3

Input Parameters

Transmit ting CPU

The receive block receives data supplied by the transmitting CPU.

Spec ify the numbe r of the trans mit ting CPU. The per mitte d valu e is

between 1 and 4, but m ust be di ffere nt from t he CPU’s own number.

RECEIVE Function (OB 204)

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 47

10.7.4

Output Parameters

Condition code byte

Thi s byte in form s you whethe r the RECE IVE fun ctio n was exe c uted

correctly and completely.

Initialization conf lict

Has no significance with the RECEIVE function.

Errors

Whe n c alli ng t he REC EI VE fu nc ti on th e foll owin g error nu mb er s

(evaluation of the condition code byte) can occur:

Condition

code byte Significance

66 The para me ter "tr ansmi ttin g CPU" is ille gal .

The foll owin g errors are possible :

- The number of the transmi ttin g CPU is grea ter

tha n 4,

- The number of the transmi tting CPU is less than 1,

- The number of the tran smitt ing CPU is the sam e as

the CPU’s own num be r.

67 The spe cia l func ti on or ga niz a ti on bl oc k c al l is wr ong.

The foll owin g errors are possible :

- Secon da ry error , sinc e the INIT IAL IZ E functi on

could not be called or was terminated by an

i n itializ at i o n conflict.

- Double call: the call for this function, SEND, SEND

TEST, RECEIVE or RECEIVE TEST is illegal,

since one of the functions INITIALIZE, SEND,

SEND TEST, RECEIVE or RECEIVE TEST has

already been called in this CPU in a lower processing

level (e.g. cyclic program processing).

- The CPU’s own number is incorrect (system data

corrupted)

following power down/power up the CPU number

is generated again by the system program.

68 The m a nagement data (queue m anag eme nt) of the

sel ect e d links are incorrect ; set up the buffe r in

the coord inat or 923C again usi ng the INITI ALI ZE

function.

69 The block id enti fiers supplied by the transmitte r a re

illegal.

The following errors are possible:

- The bloc k ID is less than 1,

- The bloc k ID is greater t han 2.

RECEIVE Func tion (OB 204)

CPU 948 Programming Guide

10 - 48 C79000-G8576-C848-04

Condition

code byte Significance

Error numbers continued:

70 The block number supplied by the transmitter is illegal,

since it is a data block with a s pe cial significanc e.

The following errors are possible:

- If the bl ock ID = 1 : D B 0, D B 1

- If the bl ock ID = 2 : D X 0

71 The block numbe r pr ovi de d by th e tra nsm it te r is

incorrect. The specified data block does not exist.

73 The data block is too small to receive the data field

supplie d by the transm i tter .

Warning

The func t ion cou ld no t be ex ecuted; the func ti on c a ll must be

repeated, e.g. in the next cycle.

The fol lowi ng wa rni ng number (ev al ua ti on of the co ndi ti on code byte)

ca n occur:

Condition

code byte Significance

13 0 The RECE IVE fun ct io n cann ot rec e ive data , sinc e

the receiving capacity was already zero when the

function was called.

Receiving capaci ty

The "re cei vin g capa c it y" pa ram et e r indic a tes how m an y data fiel ds ar e

st ill buf fered and can s t ill be re ceive d.

RECEIVE Function (OB 204)

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 49

Block ID:

ID = 1: DB data block

ID = 2: DX da t a bl oc k

ID = 0 or 3 to 255 : ill e gal, ca us e s a n

err or messa ge

Block number

Bloc k num ber of the DB/DX in whic h the rec eiv ed d ata are store d

(and from whic h the y are tak en by the SEND f unc tion i n the

tra nsm itting CPU).

Remembe r tha t the recei ve data bl ocks must be in a random ac ce ss

memory, using read-only memori es (EPROM) might pos sibly serve a

practical purpose for transm it data blocks only.

Address of the first

received data word

Da ta word num be r within t he DB/DX i n which the first

tra nsfe rred/ rec eive d data word was sto red.

Address of the last

received data word

Data word num ber wit hin the DB/DX in whic h the la st

tra nsfe rred/ rec eive d data word was sto red.

Note

The differenc e bet ween the address es of the first and last data

wo rd tr an sferred is a ma xi m um o f 31, sinc e a ma xim um of 32

d ata words can be tra nsfe rre d per fu ncti on cal l.

RECEIVE Func tion (OB 204)

CPU 948 Programming Guide

10 - 50 C79000-G8576-C848-04

10 .8 RECEIVE TEST Function (OB 205)

10.8.1

Function The RECEIVE TEST function determines the number of occupied

me mo ry fields in t he buff er of the COR 92 3C coord ina tor. Depen din g

on this number m, the RECEIVE function can be called m times to

receive m data fields.

10.8.2

Call Parameter s

Structure of the (parameter)

data field

Be fo re ca ll in g OB 205, you must speci fy t he inpu t pa ra m ete rs in t he

da t a fie ld. OB 205 requires 4 F fl ag byte s in t he data fie l d for input

and ou tpu t para met e rs:

FY x + 0: transm itt ing CPU input para me ter

FY x + 1: — not used

FY x + 2 : condi ti on c ode byt e ou tpu t pa ra m et e r

FY x + 3 : rece iving capacity output pa ra m ete r

ACCU-1-L

Whe n cal li ng OB 20 4, transfer the flag byt e num be r at whic h the

pa r a m eter d a ta field be gins to A C C U - 1- L :

ACCU-1-LH: 0

ACCU-1-L L : 0 to 246

10.8.3

Input Parameters

Transmit ting CPU

Th e CPU ’ s o w n numb er and the number of the transm itting CPU id entify

the lin k for wh ich the re ceiv ing ca pac ity is deter min ed.

10.8.4

Output Parameters

Condition code byte

This byte indicates w hether t he RECEIVE T EST function was executed

co rrec tly and co mp letely.

Initialization conf lict

Has no significance with the RECEIVE TEST function.

RECEIV E TES T Function (OB 205)

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 51

Errors

Whe n cal ling the REC EIVE T EST fu nc tion, the fol lowing err or

numbers (evaluation of the condition code byte) can occur:

Condition

code byte Significance

66 The para me ter "tr ansmi ttin g CPU" is ille gal .

The foll owin g errors are possible :

- The number of the transmi ttin g CPU is grea ter

tha n 4,

- The number of the transmi tting CPU is less than 1,

- The number of the tran smitt ing CPU is the sam e as

the CPU’s own num be r.

67 The spe cia l func ti on or ga niz a ti on bl oc k c al l is wr ong.

The foll owin g errors are possible :

- Secon da ry error , sinc e the INIT IAL IZ E functi on

could not be called or was terminated by an

i n itializ at i o n conflict.

- Double call: the call for this function, SEND, SEND

TEST, RECEIVE or RECEIVE TEST is illegal,

since one of the functions INITIALIZE, SEND,

SEND TEST, RECEIVE or RECEIVE TEST has

already been called in this CPU in a lower processing

level (e.g. cyclic program processing).

- The CPU’s own number is incorrect (system data

corrupted);

following power down/power up the CPU number

is generated again by the system program.

68 The m a nagement data (queue m anag eme nt) of the

sel ect e d links are incorrect ; set up the buffe r in

the coord inat or 923C again usi ng the INITI ALI ZE

function.

Warning

The "warning" num ber group c annot occ ur wit h the RE CEIVE T EST

function.

Receiving capaci ty

The "receiving capacity" parameter indicates how many data fields can be

received and buffered.

RECEIVE TEST Funct ion (OB 205)

CPU 948 Programming Guide

10 - 52 C79000-G8576-C848-04

10.9 Applications

Ba se d on exa mp le s, t his sec t ion e xp la in s how to pro gra m

mul ti proc e s sor comm un ic a tion.

Note

If you use the func t ion b locks li ste d be lo w and servi c e inte rr upt s

on your CPU (e . g. wit h OB 2) rem embe r to save the "sc ratc hp ad

fla gs" at the sta rt of inte rrup t servic i ng and to writ e them bac k

whe n the i nter rupt is comp le te d.

Thi s also a ppl ies to the sett in g "inte rru pts a t bloc k bounda rie s",

sin ce th e ca ll of the spe cia l fun ctio n orga ni z at io n block s

represents a block boundar y.

10.9.1

Calling the Special

Fu nction OB us ing

Fu nction Bl ocks

The following five function blocks (FB 200 and FB 202 to FB 205)

contain the call for the c orresponding spec ial func tion organiza tion block

for mult iprocessor comm unic ation (OB 200 and O B 202 to OB 205).

The numbers of the function blocks are not fixed and can be changed.

Th e par ame ter s o f the sp ecial f u nction OBs are transferr ed as actual

parameters w hen the function bl ocks a re called. The dire ct c all of the

special func tion organization bl ocks is fa st er, howeve r, is m ore difficult

to read owing to the absence of formal parameters

FB no. F B name Functi on

FB 200

FB 202

FB 203

FB 204

FB 205

INITIAL

SEND

SEND-TST

RECEIVE

RECV-TST

Set up buffer

Send a data fie ld

Test sending capacity

Receive a data field

Test receiving capacity

The flag area from FY 246 to maximum FY 255 is used by the function

blocks as a pa ram et er field for the speci al funct ion orga nization bloc ks.

The exact significance of the input and output parameters is explained

in the de scriptio n of the spe c ia l fu ncti on organiz a ti on bl ocks.

Applications

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 53

Note

The following examples of applications involve finished applications

that you can program by copying them.

Programming function

blocks

FB 200: initializing the links

FB 200

INITIAL

(1) AUMA INIC (5)

(2) NUMC TCAP (6)

(3) TNAS

(4) STAS

Parameter

name Significance Parameter

type Data

type Parameter

field

AUMA

NUMC

TNAS

STAS

INIC

TCAP

Automatic/manual

Numbe r of CPUs

Type (H byte) and number (L byte )

of the d ata b l ock co ntai ning the

assignm ent list

Start address of the ass ignment list

Initialization conflict

Total capacity

FY 246

FY 247

FW 248

FW 250

FY 252

FY 253

Continued on the next page

Applications

CPU 948 Programming Guide

10 - 54 C79000-G8576-C848-04

FB 200 continued

FB 200 LEN=45

SEGMENT 1 0000

NAME:INITIAL

DECL :A UMA I/Q/D /B/T/C: I BI/BY/ W/D: BY

DECL :N UMC I/Q/D /B/T/C: I BI/BY/ W/D: BY

DECL :T NAS I/Q/D /B/T/C: I BI/BY/ W/D: W

DECL :S TAS I/Q/D /B/T/C: I BI/BY/ W/D: W

DECL :I NIC I/Q/D /B/T/C: Q BI/BY/ W/D: BY

DECL :T CAP I/Q/D /B/T/C: Q BI/BY/ W/D: BY

0017 :L =AUMA Automatic/manual

00 18 :T F Y 246

0019 :L =NUMC Number of CPUs

00 1A :T F Y 247

001B :L =TNAS DB type, DB no.

00 1C :T F Y 248

001D :L =STAS Start address of the assignment list

00 1E :T F W 250

001F :

0020 :L KB 246 SF OB:

0021 :JU OB 200 "Initialize"

0022 :

0023 :L FY 252 Initialization conflict

0024 :T =INIC

0025 :L FY 253 T otal capacity

0026 :T =TCAP

0027 :BE

Applications

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 55

FB 202: Sending a data field

FB 202

SEND

(1) RCPU ERWA (4)

(2) TNDB TCAP (5)

(3) FINO

Parameter

name Significance Parameter

type Data

type Parameter

field

RCPU

TNDB

FINO

ERWA

TCAP

Receiving CPU

Type (H byte) and number (L byte )

of the s ource data block

Field number

Error/warning

Transmitting capacity

FY 246

FW 247

FY 249

FY 250

FY 251

FB 202 LEN=40

SEGMENT 1 00 00

NAME:SEN D

DECL : RCPU I /Q/D /B/T /C: I B I/BY/W/D: BY

DECL : TNDB I /Q/D /B/T /C: I B I/BY/W/D: W

DECL : FINO I /Q/D /B/T /C: I B I/BY/W/D: BY

DECL : ERWA I /Q/D /B/T /C: Q B I/BY/W/D: BY

DECL : TCAP I /Q/D /B/T /C: Q B I/BY/W/D: BY

0014 :L =RCPU Receiving CPU

00 15 :T F Y 246

0016 :L =TNDB DB type, DB no.

00 17 :T F W 247

0018 :L =FINO Field number

00 19 :T F Y 249

001A :

001B :L KB 246 SF OB:

001C :JU OB 202 "Send a data field"

001D :

001E :L FY 250 Error/warning

001F :T =ERWA

0020 :L FY 251 Transmitting capacity

0021 :T =TCAP

0022 :BE

Applications

CPU 948 Programming Guide

10 - 56 C79000-G8576-C848-04

FB 203: Testing the transmitting capacity

FB 203

SEND-TST

(1) RCPU ERRO (2)

TCAP (3)

Parameter

name Significance Parameter

type Data

type Parameter

field

RCPU

ERRO

TCAP

Receiving CPU

Error

Transmitting cap acity

FY 246

FY 248

FY 249

FB 203 LEN=30

SEGMENT 1 0000

NAME:SEND-TST

DECL : RCPU I /Q/D /B/T /C: I B I/BY/W/D: BY

DECL : ERRO I /Q/D /B/T /C: Q B I/BY/W/D: BY

DECL : TCAP I /Q/D /B/T /C: Q B I/BY/W/D: BY

000E :L =RCPU Receiving CPU

00 0F :T F Y 246

0010 :

0011 :L KB 246 SF OB:

0012 :JU OB 203 "Test transmitting capacity"

0013 :

0014 :L FY 248 Error

0015 :T =ERRO

0016 :L FY 249 Transmitting capacity

0017 :T =TCAP

0018 :BE

Applications

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 57

FB 204: Receivin g a data field

FB 204

RECEIVE

(1) TCPU ERWA (2)

RCAP (3)

TNDB (4)

STAA (5)

ENDA (6)

Parameter

name Significance Parameter

type Data

type Pa rameter

field

TCPU

ERWA

RCAP

TNDB

STAA

ENDA

Transmitting CPU

Error/warning

Receiving capacity

Type (H byte) and number (L byt e ) of th e

de sti na ti on data block

Add re ss of t he first r ece iv ed data word

(start address)

Add ress of the la st rece ive d data word

(end address)

FY 246

FY 248

FY 249

FW 250

FW 252

FW 254

Continued on the next page

Applications

CPU 948 Programming Guide

10 - 58 C79000-G8576-C848-04

FB 204 continued:

FB 204 LEN=45

SEGMENT 1 0000

NAME:RECEIVE

DECL : TCPU I /Q/D /B/T /C: I B I/BY/W/D: BY

DECL : ERWA I /Q/D /B/T /C: Q B I/BY/W/D: BY

DECL : RCAP I /Q/D /B/T /C: Q B I/BY/W/D: BY

DECL : TNDB I /Q/D /B/T /C: Q B I/BY/W/D: W

DECL : STAA I /Q/D /B/T /C: Q B I/BY/W/D: W

DECL : ENDA I /Q/D /B/T /C: Q B I/BY/W/D: W

0 01 7 : L =T CPU T ra nsmitting CP U

00 18 :T F Y 246

0019 :

001A :L KB 246 SF OB:

001B :JU OB 204 "Receive a data field"

001C :

001D :L FY 248 Error/warning

001E :T =ERWA

001F :L FY 249 Receiving capacity

0020 :T =RCAP

0021 :L FW 250 DB type, DB no.

0022 :T =TNDB

0023 :L FW 252 S tart address

0024 :T =STAA

0025 :L FW 254 E nd address

0026 :T =ENDA

0027 :BE

FB 205: Testing the rece iving capacity

FB 205

RECV-TST

(1) TCPU ERRO (2)

RCAP (3)

Parameter

name Significance Parameter

type Data

type Parameter

field

TCPU

ERRO

RCAP

Transmitting CPU

Error

Receiving capacity

FY 246

FY 248

FY 249

Applications

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 59

10.9.2

Transferring Data Blocks In thi s example , the fun ctio n block TRAN DAT (FB 110 ) transfe rs a

selectable number of data fields from a data block in one CPU to the

dat a bloc k of the sam e type and same num ber in a diffe rent CPU.

The FB num ber (FB 11 0) ha s bee n sele cte d at random and yo u can

use other numbers.

Pro gramming FB 11 0 is de sc ri be d fi rst fol lo wed b y the appl ic a tion of

FB 110.

Programming FB 110

FB 205 continued:

FB 205 LEN=30

SEGMENT 1 0000

NAME:RECV-TST

DECL : TCPU I /Q/D /B/T /C: I B I/BY/W/D: BY

DECL : ERRO I /Q/D /B/T /C: Q B I/BY/W/D: BY

DECL : RCAP I /Q/D /B/T /C: Q B I/BY/W/D: BY

0 00 E : L =T CPU T ra nsmitting CP U

00 0F :T F Y 246

0010 :

0011 :L KB 246 SF OB:

0012 :JU OB 205 "Test receiving capacity"

0013 :

0014 :L FY 248 Error

0015 :T =ERRO

0016 :L FY 249 Receiving capacity

0017 :T =RCAP

0018 :BE

FB 110: Transferring a data block

Task

The data area to be transferred is stipulated by the input parameter FIRB

(= number of the first data field to be transferred) and NUMB (= number of

data fields to be transferred). A data field normally consists of 32 data

words. Depending on the data block length, the last data field may be less

than 32 data words.

The transfer is triggered by a positive-going edge at the start input STAR.

If the output parameter REST is zero after the transfer, this means that

the function block TRANDAT was able to send all the data fields (according

to the NUMB parameter).

Continued on the next page

Applications

CPU 948 Programming Guide

10 - 60 C79000-G8576-C848-04

FB 110 continued:

If, however, the REST output parameter has a value greater than zero, this

means that the function block must be called again, for example in the next

cycle. This means that you or the user program can only change the set

parameters (i.e. the values of all parameters) when the REST parameter

indicates zero showing that the data transfer is complete.

You can call the function block TRANDAT several times with different

parameters. In this case, various data areas are transferred simultaneously

(interleaved in each other). The special function organization blocks for

multiprocessor communication OB 202 to OB 205 can also be used "directly".

This possibly is illustrated in the application example.

If the SEND fu ncti on ( OB 2 02) is n ot c orrectly executed with t he T RAND AT

function block , th e er ror number i s en tered in the output para mete r ER RO, the

RLO = ’1’ and the outp ut p arameter REST is set to ’0’.

The TRANDAT function block uses flag bytes FY 246 to FY 251 as scratchpad

flags. All other variables whose value is significant as long as the output

p ar am eter REST = ’0’ contin ue to ha ve mem ory assigned t o th em usi ng the

mechanism of formal/actual parameters. This is necessary to allow various

data blocks to be transferred simultaneously.

Implementation

FB 110

TRAN-DAT

(1) STAR ERRO (6)

(2) RCPU REST (7)

(3) TNDB CUBN (8)

(4) NUMB EDGF (9)

(5) FIRB

Continued on the next page

Applications

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 61

FB 110 continued:

Parameter

name Significance Parameter

type Data

type

STAR

RCPU

TNDB

NUMB

FIRB

ERRO

REST

CUBN 1)

EDGF 1)

Start the tra nsfer of the data block on a positive-go ing ed ge

Receiving CPU

Typ e (H byte) and number (L byt e) o f the da ta bl oc k to be

transferred.

Num ber of da t a fie lds to be tra nsfe rre d.

Num ber of t he first data f ield to be transfe rr ed .

Error

Num ber of da t a fie lds sti ll t o be transfe rr ed .

Current field number

Edge flag

1) Internal scratchpad flag, not intended for evaluation

FB 110 LEN=89

SEGMENT 1 0000

NAME:TRAN-DAT

DECL : STAR I /Q/D /B/T /C: I B I/BY/W/D: BI

DECL : RCPU I /Q/D /B/T /C: I B I/BY/W/D: BY

DECL : TNDB I /Q/D /B/T /C: I B I/BY/W/D: W

DECL : NUMB I /Q/D /B/T /C: I B I/BY/W/D: BY

DECL : FIRB I /Q/D /B/T /C: I B I/BY/W/D: BY

DECL : ERRO I /Q/D /B/T /C: Q B I/BY/W/D: BY

DECL : REST I /Q/D /B/T /C: Q B I/BY/W/D: BY

DECL : CUBN I /Q/D /B/T /C: Q B I/BY/W/D: BY

DECL : EDGF I /Q/D /B/T /C: Q B I/BY/W/D: BI

0 02 0 : L =R CPU A ss ign paramete r field for

0021 :T FY 246 SF OB 202

0022 :L =TNDB

00 23 :T F W 247

0024 :

Continued on the next page

Applications

CPU 948 Programming Guide

10 - 62 C79000-G8576-C848-04

FB 110 continued:

0025 :L =REST First send any remaining

0026 :L KB 0 data fields

0027 :><F

0028 :JC =TRAN

0029 :

002A :AN =STAR Positive edge at start

002B :RB =EDGF inpu t ?

002C :ON =STAR

002D :O =EDGF

002E :JC =GOOD

002F :S =EDGF

0030 :

0031 :L =NUMB Initialize the global flags

0032 :T =REST after postive edge at

0033 :L =FIRB START input

0034 :T =CUBN

0035 :

0036 :L =REST As long as REST ><0,

0038 LOOP :L KF+0 continue to attempt to

0039 :!=F send data fields

003A :JC =GOOD

0 03 B TR AN : L =CUB N

00 3C :T F Y 249

003D :L KB 246 SF OB:

003E :JU OB 202 "Send a data field"

00 3F :L F Y 250

0040 :JM =ERRO Abort if error

0041 :JP =GOOD Abort if trans-cap. = 0

0042 :L =CUBN Increment

0043 :I 1 field number

0044 :T =CUBN

0045 :L =REST Decrement number of

0046 :D 1 remaining data fields

0047 :T =REST

0048 :JU =LOOP

0049 :

004A GOOD :A F 0.0 Regular end of program:

004B :AN F 0.0

004C :L KB 0 RLO = 0, ERRO = 0

004D :T =ERRO

004E :BE

004F :

0050 ERRO :T =ERRO Program end if error:

00 51 :L K B 0

0052 :T =REST RLO = 1, ERRO contains error number

0053 :BE

Applications

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 63

Application of FB 110

Application of FB 110 on the S5-155U

Task

You want CPU 1 to tran sfer data bl ocks DB 3 ( data fields 2 to 5) and DB 4

(data fields 1 to 3) t o CP U 2 duri ng t he cyclic user program. The RECE IVE

function (OB 2 04) is a lso called i n th e cyclic user program.

Implementation

Function CPU 1 CPU 2

called in: called in:

Init iali zat ion (OB 200 )

Se nd organiz a ti on ( FB 1)

Rec e ive org an iza tion (FB 2)

OB 20

OB 1

–

OB 1

exists: exists:

Se nd D B

Re ce ive DB

DB 3; DB 4

–

DB 3; DB 4

The user program in function block FB 1 of CPU 1 contains two calls for the

function block TRANDAT in each case with different sets of parameters.

The transfer of the first data block DB 3 begins after a positive edge

after input I 2.0. A positive edge at input I 2.1 starts the transfer of

the second data block.

FB 1 LEN=yy

SEGMENT 1 0000

NAME:S-ORG

0000 :L KB 2 To CPU 2 ..

00 01 :T F Y 0

0002 :L KY 1,3 .. from data block DB 3

00 03 :T F W 1

0004 :L KB 4 .. four data fields

00 05 :T F Y 3

0006 :L KB 2 .. send from 2nd data field

00 07 :T F Y 4

0008 :

Continued on the next page

Applications

CPU 948 Programming Guide

10 - 64 C79000-G8576-C848-04

Application example continued:

0009 :JU FB 110

000A NAME :TRAN-DAT

0 00 B ST AR : I 2. 0

000C RCPU : FY 0

000D TNDB : FW 1

000E NUMB : FY 3

000F FIRB : FY 4

0010 ERRO : FY 5

0011 REST : FY 6

0012 CUBN : FY 7

0 01 3 ED GF : F 8. 0

0014 :

0015 :

0016 :JC =HALT Abor t afte r error

0017 :

0018 :L KB 2 To CPU 2 ..

00 19 :T F Y 10

001A :L KY 1,4 .. from data block DB 4

00 1B :T F W 11

001C :L KB 3 .. three data fields

00 1D :T F Y 13

001E :L KB 1 .. send from 2nd data field

00 1F :T F Y 14

0020 :

0021 :JU FB 110

0023 NAME :TRAN-DAT

0 02 4 ST AR : I 2. 1

0025 RCPU : FY 10

0026 TNDB : FW 11

0027 NUMB : FY 13

0028 FIRB : FY 14

0029 ERRO : FY 5

002A REST : FY16

002B CUBN : FY17

0 02 C ED GF : F 8. 1

002D :

002E :

002F :JC =HALT Abor t afte r error

0030 :BEU

0031 :

0 03 2 HA LT :

0033 : The error handling takes place here

0034 : (e.g. stop , mess age ou tput

0035 : on the printer, ...)

0036 :

00xx :BE

Continued on the next page

Applications

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 65

10.9.3

Extending the IPC

Flag Area

The pro b lem

In the S5-135U/155U progra mmable contro ll ers, eac h of t he 256 fla g

byte s of a CPU can beco me an input or output IPC flag by makin g an

entry in dat a block DB 1. T his, howe ver, reduc es the n umbe r of

"n orm a l" fla g byt es. To transfer a data record (sever al byt es) othe r

me ch an ism s are also re qui re d (sem aphore var ia ble or DX 0 para m e ter

as signm ent "transfe r IPC fla gs as a b lock" ) are nec essa ry to pre vent

the receiver from receiving a fragmented data record.

Application example continued:

In CPU 2, the RECE IVE func tion (OB 204 ) called by FB 2 enters each tra nsmi tted

data field int o th e ap prop riate da ta b lock. It may take

several cycles bef ore a da ta block has been completely receive d.

FB 2 LEN=yy

SEGMENT 1 0000

NAME:RECV-DAT

0000 :L KB 1 Receive data from CPU 1

00 01 :T F Y 246

0002 :

0003 SCHL :L KB 246 SF OB:

0004 :JU OB 204 "Receive"

0005 :JM =ERRO Abort if error

0006 :L FY 249 The RECEIVE function is

0007 :L KB 0 called until there are no

0008 :><F further of data fields in

0009 :JC =LOOP the buffer, i.e. the

000A : receiving capacity = 0.

000B :BEU

0 00 C ER RO :

000D : The error handling takes place here

000E : (e.g. stop , mess age ou tput

000F : on printer, ...)

00xx :BE

Applications

CPU 948 Programming Guide

10 - 66 C79000-G8576-C848-04

The sol u tio n

Co nsec ut iv e dat a wor ds of a DB or DX dat a bloc k a re def ine d fr om

DW 0 onwards a s "IPC data words". Eac h link is assign ed its own

da t a bl oc k a nd is to ta ll y independent of the other links.

At the begi nning of the c ycle bl ock, the IP C data words a re rec eived wit h

the aid of the spec ia l function organi zation blocks for mul tiprocessor

communication. T his is fol lowed by the "re gular" cyclic program , that

evaluates the receive d data and generat es the data to be sent. At the end

of the cycle , this d ata is then s en t w ith the a id o f the s pecial org anization

blocks for m ultiproce ssor comm unication. It can therefore be received by

the other CPUs at t he beginning of their cycles.

The fol lowi ng a ppl ies for e a ch o f the max im um 12 possible link s

r egar dless of th e ot her links:

•• The transmit ting CPU is only acti ve when the receivin g CPU has

r ead ou t all the "ol d" da ta fro m the COR 923C buffe r.

•• The rece ivin g CPU is only act ive when the tra nsmi tt ing CPU ha s

wr itte n all the "ne w" da ta in t he COR 923 C buffer .

Thi s me ans that the rece iving CPU can either receiv e a complete new

da t a re c ord or the ol d data re co rd re m ai ns unc ha nged: no mi xing of

"old" and "new" dat a.

Data structure

Which dat a words (for the da ta word area be low) a re to be transferred

from whic h CPU to wh ich CP U is de sc ribed in the link lis t (see th e table

on the following page). Thi s is located in an additional data bl ock that

must exist in all the CPUs involved.

The data w ord areas a lways be gin from da ta word D W 0, and their

lengths are specified in da ta fields. Rem ember the following points:

•• A comple te dat a field consi sts of 32 data word s.

•• If the last da ta fiel d is "t runc a te d" , i.e. it con ta in s between 1 and 31

dat a wo rds, less data words are tra nsferr ed.

•• If a send data block is longer than the number of fields of data

spec if ied in the link list, the exc ess da ta words can be used in the

cor re spondi ng CPU.

•• If a receive data block is longer than the received data word area,

the excess dat a words can be use d in the cor re spondi ng CPU.

Applications

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 67

Stru ctu re of the

li n k list

SUB-LIST 1 SUB-LIST 2

Li nk DB type DB

number No. of data

fields

from CPU 1

to ... DW 0 S 1 DW 16 S 1

... CPU 2 DW 1 .. . ... DW 17 2...

... CPU 3 DW 2 .. . ... DW 18 3...

...CPU 4 DW 3 ... ... DW 19 4...

from CPU 2

to ... DW 4 S 2 DW 20 S 2

... CPU 1 DW 5 .. . ... DW 21 1...

... CPU 3 DW 6 1 1) 10 1) DW 22 3 2 1)

... CPU 4 DW 7 .. . ... DW 23 4...

from CPU 3

to ... DW 8 S 3 DW 24 S 3

... CPU 1 DW 9 .. . ... DW 25 1...

... CPU 2 DW 10 .. . ... DW 26 2...

... CPU 4 DW 11 .. . ... DW 27 4...

from CPU 4

to ... DW 12 S 4 DW 28 S 4

... CPU 1 DW 13 .. . ... DW 29 1...

... CPU 2 DW 14 .. . ... DW 30 2...

... CPU 3 DW 15 .. . ... DW 31 3...

2 15 2 0 2 15 2 0

1) Refer to the example on the following page

Table 10-8 Link list for extending the IPC flag area

Applications

CPU 948 Programming Guide

10 - 68 C79000-G8576-C848-04

The link consists of two similarly structured s ub-lists, each wit h 16 data

words. For ea ch of the four sender CPUs (S1, S 2, S 3, S4) three entries are

required to describe a link.

•• Number of data fields

The number of data fields specifies the size (= the number of data

wo rds) of the data word are a to be transfe rred. (If lin ks do not exi st

o r you do not re qu ire th em, en te r 0 for t he num be r of da t a fie lds,

and f or th e DB type and DB num be r. )

•• DB type

Typ e of dat a bloc k cont a ini ng the data word are a to be tra nsfe rre d.

•• DB number

Nu mb er of the da ta bl oc k co ntai ning the da ta word area to be tran s-

ferred.

As shown in t he table, the se e ntries ca n be re ad in and com pleted in l ines.

If, for exa mple, you w a nt t o transfer the first two data fi elds in data block

DB 10 from CP U 2 (S 2) to CPU 3, m ake t he following entries:

CPU 2 (S 2) sends ..

Sub-list 2 is identical to the assignment ("manual" mode) required for

the I NIT IAL IZE fu ncti on (OB 200). With in the data b lock, sub-list 2

must oc c upy dat a words 0 to 15 and sub-list 2 data word s 16 to 31.

Yo u m us t not a lt e r the en tr ie s sho w n in bold fac e .

DW 22 3 2 DW 6 1 10

..to CPU 3 2 dat a fields fro m DB 1 0

Applications

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 69

Program structure

During rest art, one of the CPUs calls the INITIALI ZE fun ction (OB

20 0) to rese rve exa ctly the sam e num be r of coord ina tor m emory fiel ds

per link as data fields to be transmitted on this link.

To sen d and rece i ve data word are as, each CPU use s two func tion

blocks:

FB no. Name Funct ion

FB 100

FB 101

SEND-DAT

RECV-DAT

Send data word are as

t o th e other CPUs

Rec ei ve data word areas

from the other CPUs

The se FB number s have be en se l ect ed at random an d you ca n use

others.

The function bloc ks S END -DAT and RECV-DAT rea d t he link list to

de term ine whic h data w ord area s are to be sent f rom or re ceiv ed by whic h

data blocks. The whole da ta word a rea i s alwa ys sent or received. If this

is n ot possibl e owi n g to ins u f f icient transm itting or r eceiving capacit y , the

send or receive funct ion i s not e xec uted.

Note

This example (IPC flag extension using function blocks

SEND-DAT a nd RECV-DAT ) can onl y run corr ect ly when the

spe cia l func ti on or ga niz a ti on bl oc ks for m ul ti proc e s sor

com m uni c at io n OB 202 to OB 205 are not ca ll e d in any of the

CPUs.

The functio n block s SEND-DAT and RE CV-DAT contai n the

spe cia l func ti on or ga niz a ti on bl oc ks for m ul ti proc e s sor

com m uni c at ion OB 202 t o OB 205. You ca nnot cal l these

organization blocks outside SEND-DAT/RECV-DAT.

Applications

CPU 948 Programming Guide

10 - 70 C79000-G8576-C848-04

OB 20

Restart OB to reserve

the buffer on the

923C coordinator JU OB 200

Cyclic user program

extended by the calls for

the RECV-DAT and SEND-DAT

function blocks.

OB 1

JU DB xxx

FB 101

JU DB xxx

FB 100

FB 101

Function block: SEND-DAT

Send data blocks

Function block: RECV-DAT

Receive data blocks

Data block containing

the link list

Maximum three input and

three output blocks

DB xxx

KS = S1

KY = 1,... evalu-

ated

by ...

DB yyy

or/and

DX zzz

OB 200 must

only be called

in one processor.

Fig. 10-6 Overvi ew of the blocks requ ired in e ach CPU

Applications

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 71

Programming function

blocks

FB 100: Sending data word areas

Before you call FB 100, the data block containing the link list must be

open. The function block SEND-DAT requires the number of the CPU on which

it is called in order to evaluate the information contained in the link

list.

If the SEND function (OB 202) is not executed correctly in the function

block, the error or warning number is transferred to the output parameter

ERWA and RLO is set to 1.

If the input parameter CPUN (CPU number) is illegal, ERWA has the value 16

( bi t no . 4 = 1).

The function block SEND-DAT uses flag bytes FY 239 to FY 251 as scratchpad

flags.

FB 100

SEND-DAT

(1) CPUN ERWA (2)

Parameter

name Significance Parameter

type Data

type

CPUN

ERWA

Number of the CPU on whic h FB 100 is ca lle d.

T he number s 1 to 4 a re pe rm itted.

Error/warni ng (se e SEND func t ion /

OB 202)

FB 100 LEN=90

SEGMENT 1 0000

NAME:SEND-DAT

DECL :CPUN I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG:KF

DECL :ERWA I/Q/D/B/T/C: Q BI/BY/W/D: BY

000B :LW =CPUN CPUN = CPUN - 1

000C :L KB 1 Error if:

000D :-F

000E :JM =ERWA CPU no . <1

00 0F :L K B 3

0010 :>F

0011 :JC =ERWA CPU no . >4

0012 :TAK

Continued on the next page

Applications

CPU 948 Programming Guide

10 - 72 C79000-G8576-C848-04

FB 100 continued:

0013 :

0014 : SLW 2 CPUN = CPUN * 4

0015 : T FY 245 Base address

0016 :

0017 : L KB 1

0018 : T FY 244 Link counter

0019 :

001A LOOP : L FY 245 Base ad dres s

001B : L FY 244 + counter

001C :+F

001D : T FW 240

001E : ADD BN+16 + offset

001F : T FW 242

0020 :

0021 : DO F W 24 2

0022 : L DR 0 Number of reser ved

0023 : T FY 239 fields = 0 ?

0024 : L KB 0

0025 :!=F

0026 :JC =EMPT

0027 :

0028 : B FW 242

0029 : L DL 0 No. of the rece ivin g CP U

002A : T FY 246

002B : L KB 246 SF OB:

002C : JU OB 203 "Test sending capacity"

002D :L FY 248 Abort if error

002E :JC =OBER

002F :

0030 :L FY 249 Transmitting capacity >< no.

0031 :L FY 239 of reserved fields?

0032 :><F

0033 :JC =EMPT

0034 :

0035 :L KB 0 Field counter

00 36 :T FY 249

0037 :

00 38 :B FY 240

0039 :L DW 0 Type and number of

003A :T FW 247 the source DB

003B :

003C TRAN :L KB 246 SF OB:

003D :JU OB 202 Send a data field

003E :L FY 250 Abort if error/warning

003F :JC =OBER

0040 :

0041 :L FY 249 Field no. = field no. + 1

0042 :I 1

0043 :T FY 249 All data fields transferred?

00 44 :L FY 239

0045 :<F

0046 :JC =TRAN

0047 :

Continued on the next page

Applications

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 73

FB 100 continued:

0048 EMPT : L FY 244 Increme nt

0049 : I 1 link counter

004A : T FY 244

004B : L KB 4 All links

004C : <F processed ?

004D :JM =LOOP

004E : L KB 0 Regular program end :

004F : T =ERWA RLO = 0 , ER WA = 0

0050 :BEU

0051 :

0052 ERWA : L KB 16 Program end if error:

0053 OBER : T =ERWA RLO = 1 , ERWA contains

0054 : BE error/warning n umbe r

FB 101: Receive data word areas

Before you call FB 101, the data block containing the link list must

already be open. The function block RECV-DAT requires the number of the CPU

in which it is called in order to evaluate the information contained in the

l in k li st.

If the RECEIV E fu ncti on ( OB 204) is n ot correctly processed w ithi n th e

function bloc k, t he c orre sponding err or or warning number is tran sfer red to

the output pa rame ter ERWA and the RLO is set to 1. If the inp ut p aram eter CPUN

is illegal, E RWA has the value 16 (bi t no. 4 = 1).

The RECV-DAT function block uses flag bytes FY 242 to FY 255 as scratchpad

flags.

FB 101

RECV-DAT

(1) CPUN ERWA (2)

Parameter

name Significance Parameter

type Data

type

CPUN

ERWA

Number of the CPU, on which FB 101 is called.

The numbers 1 to 4 are permitted.

Error/warni ng (se e REC EI VE f u nc ti on /

OB 204)

Continued on the next page

Applications

CPU 948 Programming Guide

10 - 74 C79000-G8576-C848-04

FB 101 continued:

FB 101 LEN=88

SEGMENT 1 0000

NAME:RECV-DAT

DECL :CPUN I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KF

DECL :ERWA I/Q/D/B/ T/C: Q BI/BY/ W/D: BY

0 00 B : LW =C PU N Error if:

00 0C :L K B 1

000D :<F

0 00 E : JC =E RW A CP U no . <1

000F :LW =CPUN

00 10 :L K B 4

0011 :>F

0 01 2 : JC =E RW A CPU no. >4

0013 :

0014 :L KB 1 Lin k counter

00 15 :T F Y 242

0016 :

00 17 :L K B 16

0018 :T FW 244 Pointer to sub-list 2

0019 :

001A SRCH :L FW 244 Search sub-list 2 until

001B :I 1 the next entry for the

001C :T FW 244 receiving CPU with the

001D :DO FW 244 number ’CPUN’ is found.

00 1E :L D L 0

001F :LW =CPUN

0020 :><F

0021 :JC =SRCH

0022 :

0023 :DO FW 244

0024 :L DR 0 Num ber of reserved

0025 :T FY 243 memory fields = 0 ?

00 26 :L K B 0

0027 :!=F

0028 :JC =EMPT

0029 :

002A :L FW 244 Determine the number of the

002B :L KM 00000000 00001100 transmitting CPU from the

002D :AW pointer to sub-list 2.

002E :SRW 2

002F :I 1

00 30 :T F Y 246

0031 :

0032 :L KB 246 SF OB:

0033 :JU OB 205 "Test receiving capacity"

00 34 :L F Y 248

0035 :JC = OBER Abort if error

0036 :

Continued on the next page

Applications

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 75

FB 101 continued:

0037 : L FY 249 Receiving capacity = number

0038 : L FY 243 of reserved

0039 : ><F memory fields ?

003A :JC = EMPT

003B :

003C RECV : L KB 246 SF OB:

003D :JU OB 204 "Receive a data field"

00 3E :L F Y 248

003F :JM =OBER Abort if error/warning

0040 :L FY 249 if receiving capacity = 0

0041 :L KB 0 process next

0042 :><F link

0043 :JC =RECV

0044 :

0045 EMPT :L FY 242 Increment

0046 :I 1 link coun ter

00 47 :T F Y 242

0048 :L KB 4 All links

0049 :<F processed ?

004A :JM = SRCH

004B :L KB 0 Regular program end:

0 04 C : T =E RWA RL O = 0, ERWA = 0

004D :BEU

004E :

004F ERWA :L KB 16 Program end if error:

0050 OBER :T =ERWA RLO = 1, ERWA contains

0051 :BE error/warning number

Applications

CPU 948 Programming Guide

10 - 76 C79000-G8576-C848-04

Application example

Application of FB 100/101 on the S5-155U

Task

You want to e xcha nge data between thr ee CPUs:

- From CPU 1 to CPU 2: data block DB 3, DW 0 to DW 127 (= 4 data fields)

- From CPU 1 to CPU 3: data block DX 4, DW 0 to DW 63 (= 2 data fields)

- From CPU 2 to CPU 1

and CPU 3: data block DB 5, DW 0 to DW 95 (= 3 data fields)

Function block FB 1 is the interface for the cyclic user program on all

three CPUs. CPU 1 calls the INITIALIZE function (OB 200) during the cold

restart. The link list is in data block DB 100.

Continued on the next page

DB 5, 3 data fields

DB 3,

4 data

fields

DB 5,

3 data

fields

DX 4, 2 data fields

CPU 2 CPU 3

CPU 1

Fig. 10-7 Data exchange between 3 CPUs

Applications

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 77

Application example continued:

Implementation

1 . Lo ad ing blocks

The following blocks must be loaded in the indivitual CPUs:

Fun c ti on CPU 1 CPU 2 CPU 3

Re st a rt OB

User pr ogra m

FB: SEND- DAT

FB: RE CV-DAT

Link l ist

Input DB

Output DB

OB 20

FB 1

FB 100

FB 101

DB 100

DB 5

DB 3; DX 4

—

FB 1

FB 100

FB 101

DB 10 0

DB 3

DB 5

—

FB 1

FB 100

FB 101

DB 100

DB 5; DX 4

—

2. Creating the link list

The link list is created and entered in data block DB 100:

DB100 LEN=37

PAGE 1

– – Sub-list 1 – –

0: KS = ’S1’; Send from CPU 1 to ..

1: KY = 001,003; .. CPU 2 (DB 3)

2: KY = 002,004; .. CPU 3 (DX 4)

3: KY = 000,000;

4: KS = S2 ; Se nd fro m CPU 2 to ..

5: KY = 001,005; .. CPU 1 (DB 5)

6: KY = 001,005; .. CPU 3 (DB 5)

7: KY = 000,000;

8: KS = ’S3’;

9: KY = 000,000;

1 0: KY = 00 0,000;

1 1: KY = 00 0,000;

1 2: KS = ’S 4’;

1 3: KY = 00 0,000;

1 4: KY = 00 0,000;

1 5: KY = 00 0,000;

Continued on the next page

Applications

CPU 948 Programming Guide

10 - 78 C79000-G8576-C848-04

Application example continued:

– – Sub-list 1 – –

16: KS = ’S1’; Send from CPU 1 to ..

17: KY = 002,004; .. CPU 2 (four data fields)

18: KY = 003,002; .. CPU 3 (two data fields)

1 9: KY = 00 4,000;

20: KS = S2’; Send from CPU 2 to ..

21: KY = 001,003; .. CPU 1 (three data fields)

22: KY = 003,003; .. CPU 3 (three data fields)

2 3: KY = 00 4,000;

2 4: KS = ’S 3’;

2 5: KY = 00 1,000;

2 6: KY = 00 2,000;

2 7: KY = 00 4,000;

2 8: KS = ’S 4’;

2 9: KY = 00 1,000;

3 0: KY = 00 2,000;

3 1: KY = 00 3,000;

Data words DW 16 to DW 31 contain the assignment list required for the

manual INITIALIZATION function (OB 200).

3. Program OB 200 call in the start-up block OB 20 for CPU 1

OB 200 is called by the OB 20 shown below in CPU 1 during the restart.

O B 20 LE N= yyABS

SEGMENT 1

0000 :L KB 2 Manual initialization of

0001 :T FY 246 the pages

0002 :

0003 :L KY 1,100 The assignment list is entered

0005 :T FW 248 in DB 100 from data word 16

0006 :L KF+16 onwards

00 08 :T F W 250

0009 :

000A :L KB 246 SF OB:

000B :JU OB 200 "Init iali ze"

000C :

000D :AN F 252.5 Block end if there is no

000E :BEC initialization conflict

000F :

0010 : The error handling routine

0011 : is inserted here if an

0012 : i nitializatio n clonflict

0013 : o ccurs (e.g. stop , output

0014 : message on printer, or ...)

00xx :BE

Continued on the next page

Applications

CPU 948 Programming Guide

C79000-G8576-C848-04 10 - 79

Application example continued:

4. Program calls for the function blocks in FB 1 of the CPUs:

The user program on each CPU is extended by the RECV-DAT and SEND-DAT call.

Function block FB 1 shown below is for CPU 1. For the other CPUs, the input

parameter CPUN (CPU number) must be modified.

FB 1 LAN=yy

SEGMENT 1 0000

NAME:EM-SE

0000

0000 :C DB100 Link list DB 100

0 00 1 : JU FB 10 1 Receive the input

0002 : d ata blocks

0003 NAME :RECV-DAT

0004 CPUN : KF+1

0 00 5 ER WA : FY0

0006 :JC =ERWA Abort if error/warning

0007 :

0008 :

0009 : Here, the cyclic user program that

000A : reads data from the input data

000B : blocks and enters data in the

000C : output data blocks is inserted.

000D :

000E :

000F :

0010 :C DB 100 Link list DB 100

0011 :JU FB100 Sen d the output

0012 : d ata blocks

0012 NAME :SEND-DAT

0013 CPUN : KF+1

0014 ERWA : FY0

0015 :JC =ERWA Abort if error/warning

0016 :BEU

0017 :

0018 ERWA : Run an error handling routine

0019 : following an error/warning (here,

0 01 A : the erro r handling routine is

001B : inserted, e.g. stop, output error

001C : message on printer or screen, or ..)

00xx :BE

Applications

CPU 948 Programming Guide

10 - 80 C79000-G8576-C848-04

Contents of Chapter 11

11.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 4

11 .2 PG Funct ion s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 5

11 . 2.1 Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 6

11.2.2 Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 7

11 . 2.3 Pr ogram Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 8

1 1 .3 Seri al Link PG - PL C via 1st or 2nd Seria l Inte rfac e. . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 - 16

11. 4 Parallel Operation of Tw o Se rial PG In t erfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 - 17

11.4.1 Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 - 19

11.4.2 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 19

11.4.3 Sequence in Certain Operating Situations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 21

11.5 PG Funct ions via the S5 Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 2 7

11.5.1 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 27

11 .5 .2 How the PG Functions Work via the S5 Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 29

11.5.3 Installation and Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 31

11 .5 .4 Condi tion Codes Indic ating Problem s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 35

PG Interfaces and Functions 11

CPU 948 Progra mming Gu ide

C79000-G8576-C848-04 11 - 1

Contents

CPU 948 Prog ramming Gu id e

11 - 2 C79000-G8576-C848-04

11PG Interfaces and Func tions

Thi s c hapt e r explai ns how to con ne ct your PG to the CPU 948 and the

fu ncti ons pro vid ed by the PG soft war e with whic h you ca n test yo ur

STEP 5 program.

If you onl y use the sta nd ar d PG int er fa ce (1st seria l PG interfa c e) you

do not ne ed to rea d Se cti ons 11. 4 and 11 .5 . The se sec tions t el l you

abou t furthe r interf ac e s with whic h yo u ca n conn ect a PG to your

CPU. The se se cti ons also c ont a in point s to note if yo u use PG

fu ncti ons on bo th inte rf ace s.

CPU 948 Programming Guide

C79000-G8576-C848-04 11 - 3

11.1 Overview

You ca n lo ad and te st you r use r progra m usi ng the online func t ion s of

the STE P 5 soft war e.

To use these func t ion s, the CPU must be con ne cte d to the PG. The

fo llowin g inte rfa c es are av aila ble for this li nk:

•• link via the serial sta nda rd i nte rface "PG - PLC",

•• link via the 2nd serial interfa c e of the CPU 948,

•• link via the S5 bus wi th SINEC H1.

The PG func tions c a n ope rate simul ta ne ou sly on the two se ri al

interf ac es, howe ver, via the SINEC H1 link, th e PG functio ns can only

be used alternately with those on the seri al interfa c es

PG funct io ns prov ide the foll owin g support fo r insta lling and te sti ng

yo ur ST EP 5 program:

Function Section

Info

Size of the intern al RAM an d free

user memory "Memo ry c onfi gur at io n"

List of loaded blocks "Output DIR"

Displa y conten ts of me mory

words/bytes an d I/O byte s "Outp ut address"

Memory management

Dele te th e who le me m ory "Overall re set"

Cre ate more mem ory spac e "Com pre ss me m ory

Manage blocks "Transfer/delete b locks"

Program test

Sta rt/st op CP U "St art/ stop "

Test the operat ion sequence in a

block "Status block"

Test single prog ra m steps "Prog ra m test "

Displa y signa l stat e of proce ss

variables "St at u s va riable s "

Out put signa l s in the st op mode "Force "

Display/change process variables "Force variables"

Tabl e 11-1 F unc tion s for insta lla tion and t est ing

Overview

CPU 948 Programming Guide

11 - 4 C79000-G8576-C848-04

11.2 PG Functions

Note

The term s use d in this se cti on for the PG func tions m a y in some

ca ses di ffe r from the term s in your PG soft war e. Ple a se ref er to

yo ur ST EP 5 m a nua l.

Calling and using funct ions

How to cal l and use the indiv idu al PG functions i s desc ri be d in the

ma nua l for your PG.

Checkpoint

The PG func tions a re pe rfor med at defi ne d checkpoints in the CPU.

In the CPU 948 the re are fou r dif fere nt che c kpoi nt s. Each of these

che ckpoints has c erta in test fu nc tions a ssign ed to it.

Checkpoint "Stop"

You can acc ess PG func ti ons tha t are permi ssib le onl y in the STO P

mode a t che ck poi nt "st op" (e . g. "start", "ove ral l re se t", "co mp re s s

memory" in the stop mode).

The "stop" chec kpoint is lo ca t ed im medi ately before OB 39 i s ca ll e d

(the block for cyc lic proc essi ng in the soft STOP mode ).

Checkpoint "Cycle"

PG fun ctio ns tha t y ou wa nt to exec ut e duri ng cyc li c program

pr ocessi ng a re cal led a t check poi nt "c ycle " (e. g. "com pr ess me mo ry"

in the RUN m ode , "stop", "sta t us"). The "c ycle " che ck poi nt is loc a ted

i mm ediat ely before the upd atin g of th e proc ess i mage of the inpu ts

(PI I). At this poi nt , the syste m progr am has not upda ted t he PII ye t.

Checkpoint "Test"

PG funct io ns that you wa nt to execut e as soon as th e next bre a kpoi nt

is rea che d are ca ll ed at ch eckp oin t "test " (in the progr am test ), see

Se c ti on 11. 2. 3) .

Checkpoint "General Functions"

Thi s che c kpo int exist s both in th e STOP an d the RUN mode. Online

PG fun ct io ns that ca n be ex ecuted in all operati ng modes of the

pr ogra mm ab le co ntr olle r are ca lled at che c kpo int "gene ra l functio ns".

The se func ti ons inc lud e "t ra nsfe r bloc k", "del ete blo ck", "st atu s

va ri a ble s". In th e STO P mo de , this c he c kpoi nt is located i mm e di at ely

before OB 39 is ca lled (the bl ock for c ycli c processing in the soft

STOP mo de ). Durin g cyclic pro gram proce ssing , the che ckpo int is

located after upda t ing the proce ss im age of the input s a nd bef ore

calling OB 1.

PG Functions

CPU 948 Programming Guide

C79000-G8576-C848-04 11 - 5

11.2.1

Info

Memory con figurati on

The CPU 948 is ava i labl e with two me m ory ver sion s and you c an

check the memory capacity using the PG function "memory

conf igu ra ti on". With thi s function, th e foll owin g inf orm a tion a bout

the CPU user me mory i s tra nsfe rr ed to the PG (from PG softwa re

versi on V6. 0 upwar ds wit h "Del ta di ske tte" for the CPU 948 ):

•• me mory c apac ity (640 Kbyt e s/16 64 Kbyte s)

•• longe st f re e bloc k of use r me mo ry

•• sum of a ll free bloc ks of user m e mory.

The PG software V6. 3 with "De lta diske tte " for the CPU 948 disp lays

the me mory c onf igurati on exa ct ly .

Wit h olde r PG softwa re versi ons (e .g. V3.0 or MT1 .0) the memor y

conf igurati on is as for t he CPU 9 46/ 947 (r ef er t o Fig . 11-1). The tot al

me mo ry confi gur atio n of the CPU 948 mu st then be ca lcul ate d from

the total of the submodule values.

PLC info SIMATIC S5 / OES0C

M e m o r y configuration S 5 1 5 5 U

Module Submod Type Start address End address Length

Longest free block of RAM

Sum of all free blocks of RAM

RAM

00000

10000

30000

Submod. empty / not plugged in

0FFFF

2FFFF

4FFFF

64 KW

1) corresponds to the memory configuration of the CPU 948-1: 320 Kw = 640 Kbytes

128 KW

: 314800 Words

: 315664 Words

F1 F2 F3 F4 F5 F6

OUTP ADDR MEM CONF SYSPAR BSTACK ISTACK RETURN

F7 F8

Fig. 11-1 PG display of the memory configuration

PG Functions

CPU 948 Programming Guide

11 - 6 C79000-G8576-C848-04

Output DIR

If you wa nt to displa y a list of all the progra mme d bloc ks on th e PG

wi th the CPU 9 48, OB 0 is displa ye d inste a d of the syste m progr am

blocks.

The funct ion is perm itte d in t he ope ra ting mode s RUN, SOFT ST OP,

HARD STOP an d can also be ca lled within the "progr am test "

function.

Output address

Wit h the "outpu t addre ss" fun ct ion, you can displ a y the cont en ts of

me mo ry and I/O add re sses in he xade cim al forma t. You ca n acc ess al l

addr esse s (RAM, S5 bus, are as with no mod ules a ssign ed). In the

proc ess i mage are a no ADF is trigge re d, in the I/O area the re is no

QVZ.

In the area s a ddre sse d a s byte s (fl a gs, process i mag e) t he hig h byt e is

represente d as ’FF’.

11.2.2

Installation

Overall reset

With the function "delete all blocks" you can carry out an overall reset

of the CPU from the PG. The over all rese t is carried out

unconditionally (refer to Section 4.2).

Compress memory

Thi s f unc ti on shi ft s al l vali d bl oc ks in t he user me m ory t o the

begi nni ng of the user mem ory . Unused are a s that resu lt ed from

del et in g or c orre c ting blocks a re el im in at ed. Thi s func t ion shift s

com plete bloc ks t o the be gi nni ng of t he m em ory a re a . Id eal ly, one

lar ge fre e area resu lt s from many sma ll unuse d are as. You ca n load

bloc ks in to the resu lting l arge spa ce.

You ca n cal l this fu nc ti on in the RUN an d soft STOP m ode s. In the

RUN mode , DBs and DXs that are longe r than 512 data words are not

shift ed . In the STOP m ode, all blocks are shifted.

The blocks are shifted via a buffer so that no data is lost if there is a

power failu re . If thi s buffe r is insuf fic ien t for inter medi a te storag e of a

bloc k, co mpressing con tinues at the ne xt unuse d m em ory area .

Conse que nt ly, some unuse d areas c an sti ll remain aft e r comp ressing .