(> DALLAS SEMICONDUCTOR DS1210 Nonvolatile Controller Chip FEATU RES Converts CMOS RAMs into nonvolatile memories =" Unconditionally write protects when Vcc is out of tolerance = Automatically switches to battery when power-fail occurs = Space saving 8-pin DIP = Consumes less than 100 nA of battery current = Tests battery condition on power up = Provides for redundant batteries = Optional 5% or 10% power-fail detection = Low forward voltage drop on the Vcc switch = Optional 16-pin SOIC surface mount package = Optional industrial temperature range of -40C to +85C DESCRIPTION PIN ASSIGNMENT YW vcco[}1 8 ]vcci vBaTiL]2 7] veat2 ToLL]3 6_Llcteo enpL] 4 5LIce DS1210 8-pin DIP (300-mil) See Mech. Drawings Section YQ Ne OC4}1 16 (1) Nc veco OL] |2 15 1] vcci Nc O4/3 14 FT] NC VBAT1 TL1|4 13 [J VBAT2 Nc OO1}5 12 OI Nc TOL QL||6 11 CEO Ne O0|7 10 (I) Nc GND T1]|8 9 0 CE DS1210S 16-pin SOIC (300-mil) See Mech. Drawings Section PIN DESCRIPTION Veco - RAM Supply VRATI -+ Battery 1 TOL - Power Supply Tolerance GND - Ground CE - Chip Enable Input CEO - Chip Enable Output Vepar. -+ Battery 2 Vect -+ Supply NC - No Connect The DS1210 Nonvolatile Controller Chip is a CMOS circuit which solves the application problem of converting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-of-tolerance condition. When such a condition is detected, chip enable is inhibited to accomplish write protection and the battery is switched on to supply the RAM with uninterrupted power. Special circuitry uses a low- leakage CMOS process which affords precise voltage detection at extremely low battery consumption. The 8-pin DIP package keeps PC board real estate requirements to a minimum. By combining the DS1210 Nonvolatile Controller Chip with a CMOS memory and batteries, nonvolatile RAM operation can be achieved. 111899DS1210 OPERATION The DS1210 nonvolatile controller performs five circuit functions required to battery back up a RAM. First, a switch is provided to direct power from the battery or the incoming supply (Vcc1) depending on which is greater. This switch has a voltage drop of less than 0.3V. The second function which the nonvolatile controller provides is power-fail detection. The DS1210 constantly monitors the incoming supply. When the supply goes out of tolerance a precision comparator detects power-fail and inhibits chip enable (CEO ). The third function of write protection is accomplished by holding the CEO output signal to within 0.2 volts of the Vcc; or battery supply. If CE input is low at the time power-fail detection occurs, the CEO output is kept in its present state until CE is returned high. The delay of write protection until the current memory cycle is completed prevents the corruption of data. Power-fail detection occurs in the range of 4.75 volts to 4.5 volts with the tolerance Pin 3 grounded. If Pin 3 in connected to Voco, then power-fail detection occurs in the range of 4.5 volts to 4.25 volts. During nominal supply conditions CEO will follow CE with a maximum propagation delay of 20ns. The fourth function the DS1210 performs is a battery status warning so that potential data loss is avoided. Each time that the circuit is powered up the battery voltage is checked with a precision comparator. If the battery voltage is less than 2.0 volts, the second memory cycle is inhibited. Battery status can, therefore, be determined by performing a read cycle after power-up to any location in memory, verifying that memory location content. A subsequent write cycle can then be executed to the same memory location altering the data. If the next read cycle fails to verify the written data, then the batteries are less than 2.0V and data is in danger of being corrupted. The fifth function of the nonvolatile controller provides for battery redundancy. In many applications, data integrity is paramount. In these applications it is often desirable to use two batteries to ensure reliability. The DS1210 controller provides an internal isolation switch which allows the connection of two batteries. During battery backup operation the battery with the highest voltage is selected for use. If one battery should fail, the other will take over the load. The switch to a redundant battery is transparent to circuit operation and to the user. A battery status warning will occur when the battery in use falls below 2.0 volts. A grounded Vgar pin will not activate a battery-fail warning. In applications where battery redundancy is not required, a single battery should be connected to the BAT1 pin. The BAT2 battery pin must be grounded. The nonvolatile controller contains circuitry to turn off the battery backup. This is to maintain the battery(s) at its highest capacity until the equipment is powered up and valid data is written to the SRAM. While in the freshness seal mode the CEO and Veco will be forced to Voy. When the batteries are first attached to one or both of the Vgar pins, Veco will not provide battery back-up until Vcci exceeds Veccrp, as set by the To, pin, and then falls below Vgar. Figure 1 shows a typical application incorporating the DS1210 in a microprocessor-based system. Section A shows the connections necessary to write protect the RAM when Vcc is less than 4.75 volts and to back up the supply with batteries. Section B shows the use of the DS1210 to halt the processor when Vcc is less than 4.75 volts and to delay its restart on power-up to prevent spurious writes. 2 of 6SECTION A - BATTERY BACKUP Figure 1 Veco 081210 Voc Vv}, 2 7 FROM DECODER DS1210 BATTERY BACKUP CURRENT DRAIN EXAMPLE CONSUMPTION DS1210 Igar 100 nA RAM Teco2 10 uA Total Drain 10.1 pA SECTION B - PROCESSOR RESET +5V Voc; PROCE RESET PUSH _ BUTTON RESET 3 of 6DS1210 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * -0.3V to +7.0V OC to 70C -55C to +125C 260C for 10 seconds This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0C to 70C) PARAMETER SYMBOL MIN TYP MAX UNITS | NOTES Pin 3 = GND Supply Voltage Vect 4.75 5.0 5.5 Vv 1 Pin 3 = Vcco Supply Voltage Vect 4.5 5.0 5.5 Vv 1 Logic 1 Input Vin 2.2 Voct0.3 Vv 1 Logic 0 Input Vin -0.3 +0.8 Vv 1 Battery Input VRATI> 2.0 4.0 Vv 1,2 Vpat2 (0C to 70C; Veci = 4.75 to 5.5V PIN 3 = GND) DC ELECTRICAL CHARACTERISTICS (Voci = 4.5 to 5.5V, PIN 3 = Veco) PARAMETER SYMBOL MIN TYP MAX UNITS | NOTES Supply Current Tect 5 mA 3 Supply Voltage Veco Vec-0.2 Vv 1 Supply Current Teco 80 mA 4 Input Leakage I -1.0 +1.0 uA Output Leakage lo -1.0 +1.0 WA CEO Output @ 2.4V Tou -1.0 mA 5 CEO Output @ 0.4V To. 4.0 mA 5 Vcc Trip Point (TOL=GND) Veccte 4.50 4.62 4.74 Vv 1 Vec Trip Point (TOL=Vecco) Vecte 4.25 4.37 4.49 Vv 1 (0C to 70%; Vecr =< Vat) CEO Output VonL Vpat-0.2 Vv 7 Vgati OF VgatT2 Battery Current bar 100 nA 2,3 Battery Backup Current @ Veco = Vear 0.3V Keco2 50 HA 6,7 4 of 6DS1210 CAPACITANCE (Ta = 25) PARAMETER SYMBOL MIN TYP MAX UNITS | NOTES Input Capacitance Ci 5 pF Output Capacitance Cour 7 pF (0C to 70C; Voc, = 4.75V to 5.5V, PIN 3 = GND) AC ELECTRICAL CHARACTERISTICS (Voc) = 4.75V to 5.5V, PIN 3 = GND) PARAMETER SYMBOL MIN TYP MAX UNITS | NOTES CE Propagation Delay tep 5 10 20 ns 5 CE High to Power-Fail ter 0 ns (0C to 70; Veci = 4.75V, PIN 3 = GND; Veci < 4.5, PIN 3 = Veco) Recovery at Power Up trac 2 80 125 ms Vec Slew Rate Power-Down tr 300 us Vec Slew Rate Power-Down trB 10 us Vcc Slew Rate Power-Down tr 0 Us CE Pulse Width ter 15 [Us 8 NOTES: 1. All voltages are referenced to ground. 2. Only one battery input is required. Unused battery inputs must be grounded. 3. Measured with Vcco and CEO open. 4. Icco1is the maximum average load which the DS1210 can supply to the memories. 5. Measured with a load as shown in Figure 2. 6. Iccoz2 is the maximum average load current which the DS1210 can supply to the memories in the battery backup mode. 7. tcg max. must be met to ensure data integrity on power loss. 8. CEO can only sustain leakage current in the battery backup mode. 5 of 6DS1210 TIMING DIAGRAM: POWER-UP te 4.75V 4.5V 4.25V Veci S ta TIMING DIAGRAM: POWER-DOWN te CEO Vec OUTPUT LOAD Figure 2 +5 VOLTS PIN 6 GEO 1.1K 6 of 6