MT18HTS25672RHY-53E - Micron - Datasheet.Directory

Products and specifications discussed herein are subject to change by Micron without notice.

2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Features

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DDR2 SDRAM SORDIMM

MT18HTS25672RH – 2GB

MT18HTS51272RH – 4GB

For component data sheets, refer to Micron’s Web site: www.micron.com

Features

• 200-pin, small-outline registered, dual in-line

memory module (SORDIMM)

• Fast data transfer rates: PC2-6400, PC2-5300, PC2-

4200, or PC2-3200

• 2GB (256 Meg x 72), 4GB (512 Meg x 72)

• S upports ECC error detection and correction

•V

DD = +1.8V

•V

DDSPD = +1.7V to +3.6V

• JEDEC-standar d 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS, DQS#) option

•4n-bit prefetch architecture

• Dual rank, using TwinDie™ devices

• Multipl e internal device banks for concurrent

operation

• Programmable CAS# latency (CL)

• Posted CAS additive latency (AL)

• WRITE latency = READ latency - 1 tCK

• Programmable burst lengths (BL): 4 or 8

• Adjustable data-output drive strength

• 64ms, 8192-cycle refresh

• On-die termination (ODT)

• Serial presence-detect (SPD) with EEPROM

• PLL to reduce system clock line loading

• Gold edge contacts

•I

2C temperature sensor

Figure 1: 200-Pin SORDIMM (MO-274 R/C B)

Notes: 1. Contact Micron for industrial temperature

module offerings.

2. CL = CAS (READ) latency; registered mode

will add one clock cycle to CL.

Options Marking

• Operating temperature1

–Commercial (0°C ≤ TA ≤ +70°C) None

–Industrial (–40°C ≤ TA ≤ +85°C) I

•Package

–200-pin DIMM (lead-free) Y

• Frequency/CAS latency2

–2.5ns @ CL = 5 (DDR2-800) -80E

–3.0ns @ CL = 5 (DDR2-667) -667

–3.75ns @ CL = 4 (DDR2-533) -53E

–5.0ns @ CL = 3 (DDR2-400) -40E

PCB height: 30mm (1.18in)

Table 1: Key Timing Parameters

Speed

Grade Industry Nomenclature

Data Rate (MT/s) tRCD

(ns) tRP

(ns) tRC

(ns)CL = 5 CL = 4 CL = 3

-80E PC2-6400 800 533 – 12.5 12.5 55

-667 PC2-5300 667 533 400 15 15 55

-53E PC2-4200 – 533 400 15 15 55

-40E PC2-3200 – – 400 15 15 55

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Features

Notes: 1. Data sheets for the base devices can be found on Micron ’s Web si te.

2. All part numbers end with a two-place code (not shown), designating compo nent and PCB

revisions. Consult factory for current revision codes. Example: MT18HTS51272RHY-667A1.

Table 2: Addressing

Parameter 2GB 4GB

Refresh count 8K 8K

Row address 16K A[13:0] 32K A[14:0]

Device bank address 8 BA[2:0] 8 BA[2:0]

Device configuration 2Gb TwinDie (256 Meg x 8) 4Gb TwinDie (512 Meg x 8)

Column address 1K A[9:0] 1K A[9:0]

Module rank address 2 S#[1:0] 2 S#[1:0]

Table 3: Part Numbers and Timing Parameters – 2GB Modules

Base device: MT47H256 M8THN,1 2Gb TwinDie DDR2 SDRAM

Part Number2Module

Density Configuration Module

Bandwidth Memory

Clock/Data Rate Clock Cycles

(CL-tRCD-tRP)

MT18HTS25672RH(I)Y-80E__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5

MT18HTS25672RH(I)Y-667__ 2GB 256 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5

MT18HTS25672RH(I)Y-53E__ 2GB 256 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4

MT18HTS25672RH(I)Y-40E__ 2GB 256 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3

Table 4: Part Numbers and Timing Parameters – 4GB Modules

Base device: MT47H512 M8THM,1 4Gb TwinDie DDR2 SDRAM

Part Number2Module

Density Configuration Module

Bandwidth Memory

Clock/Data Rate Clock Cycles

(CL-tRCD-tRP)

MT18HTS51272RH(I)Y-667__ 4GB 512 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5

MT18HTS51272RH(I)Y-53E__ 4GB 512 Meg x 72 4.3 GB/s 3 .7 5ns/533 MT/s 4-4-4

MT18HTS51272RH(I)Y-40E__ 4GB 512 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Pin Assignments and Descriptions

Table 5: Pin Assignments

200-Pin SORDIMM Front 200-Pin SORDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

REF 51 DQ18 101 VDD 151 VSS 2V

SS 52 VSS 102 A6 152 VSS

3 DQ0 53 DQ19 103 A5 153 DQS5# 4 DQ4 54 DQ28 104 A4 154 DM5

SS 55 VSS 105 A3 155 DQS5 6 DQ5 56 DQ29 106 VDD 156 VSS

7 DQ1 57 DQ24 107 A2 157 VSS 8V

SS 58 VSS 108 A1 158 DQ46

9 DQS0# 59 DQ25 109 VDD 159 DQ42 10 DM0 60 DM3 110 A0 160 DQ47

11 DQS0 61 VSS 111 A10 161 DQ43 12 VSS 62 VSS 112 BA1 162 VSS

13 VSS 63 DQS3# 113 BA0 163 VSS 14 DQ6 64 DQ30 114 VDD 164 DQ52

15 DQ2 65 DQS3 115 RAS# 165 DQ48 16 DQ7 66 DQ31 116 WE# 166 DQ53

17 DQ3 67 VSS 117 VDD 167 DQ49 18 VSS 68 VSS 118 S0# 168 VSS

19 VSS 69 DQ26 119 CAS# 169 VSS 20 DQ12 70 CB4 120 ODT0 170 DM6

21 DQ8 71 DQ27 121 S1# 171 DQS6# 22 DQ13 72 CB5 122 A13 172 VSS

23 DQ9 73 VSS 123 VDD 173 DQS6 24 VSS 74 VSS 124 VDD 174 DQ54

25 VSS 75 CB0 125 ODT1 175 VSS 26 DM1 76 DM8 126 CK0 176 DQ55

27 DQS1# 77 CB1 127 NC 177 DQ50 28 VSS 78 VSS 128 CK0# 178 VSS

29 DQS1 79 VSS 129 DQ32 179 DQ51 30 DQ14 80 CB6 130 VSS 180 DQ60

31 VSS 81 DQS8# 131 VSS 181 VSS 32 DQ15 82 CB7 132 DQ36 182 DQ61

33 DQ10 83 DQS8 133 DQ33 183 DQ56 34 VSS 84 VSS 134 DQ37 184 VSS

35 DQ11 85 VSS 135 DQS4# 185 DQ57 36 DQ20 86 CB2 136 VSS 186 DM7

37 VSS 87 CKE0 137 DQS4 187 VSS 38 DQ21 88 CB3 138 DM4 188 DQ62

39 DQ16 89 CKE1 139 VSS 189 DQS7# 40 VSS 90 VSS 140 VSS 190 VSS

41 DQ17 91 EVENT# 141 DQ34 191 DQS7 42 RESET# 92 BA2 142 DQ38 192 DQ63

43 VSS 93 VDD 143 DQ35 193 DQ58 44 DM2 94 A14 144 DQ39 194 SDA

45 DQS2# 95 A12 145 VSS 195 VSS 46 VSS 96 A11 146 VSS 196 SCL

47 DQS2 97 A9 147 DQ40 197 DQ59 48 DQ22 98 VDD 148 DQ44 198 SA1

49 VSS 99 A7 149 DQ41 199 VDDSPD 50 DQ23 100 A8 150 DQ45 200 SA0

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Pin Assignments and Descriptions

Table 6: Pin Descriptions

Symbol Type Description

A[14:0] Input Address inputs: Provide the row address for ACTIVE commands, and the column address

and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A10 sampled during a PRE CHARGE command

determines whether the PRECHARGE applies to one devi ce bank (A10 LOW, device bank

selected by BA[2:0]) or all device banks (A10 HIGH). The address inputs also provide the op-

code during a LOAD MODE command. A[13:0] address the 2GB module; A[14:0] address the

4GB module.

BA[2:0] Input Bank address inputs: BA[2:0] define the device bank to which an ACTIVE, READ, WRITE, or

PRECHARGE command is being applied. BA[2:0] define which mode register (MR, EMR1,

EMR2, and EMR3) is loaded during the LOAD MODE command.

CK0, CK0# Input Clock: CK and CK# are differential clock inputs. All control, command, and address input

signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.

CKE[1:0] Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DDR2 SDRAM.

DM[8:0] Input Input data mask: DM i s an input ma sk signal f or write data. Input data is masked when DM

is sampled HIGH, along with the input data, during a write access. DM is sampled on both

edges of DQS. Although the DM pins are input-only, DM loading is designed to match th at

of the DQ and DQS pins.

ODT[1:0] Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR2 SDRAM. When enabled in normal operation,

ODT is applied only to the following pins: DQ, DQS, DQS# , DM, and CB. The ODT in put will

be ignore d if disabled via the LOAD MODE command.

RAS#, CAS#,

WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being

entered.

RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal

can be used during power-up to ensure that CKE is LOW and DQ are High-Z.

S#[1:0] Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command

decoder.

SA[1:0] Input Serial address inputs: These pins are used to configure the SPD EEPROM address range on

the I2C bu s.

SCL Input Serial clock for SPD EEPROM: SCL is used to synchronize communication to and from the

SPD EEPROM.

CB[7:0] I/O Check bits.

DQ[63:0] I/O Data input/output: Bidirectional data bus.

DQS[8:0],

DQS#[8:0] I/O Data strobe: DQS# is used only when differential data strobe mode is enabled via the LOAD

MODE comma nd. Output wit h read data. Edge-aligned with read data. Input with write

data. Center-aligned with write data.

SDA I/O Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of

the SPD EEPROM on the module on the I2C bus.

EVENT# Output

(open-

drain)

Temperature event: The EVENT# pin is asserted by the temperature sensor when criti ca l

temperature thresholds have been exceeded.

VDD Supply Power supply: 1.8V ±0.1V.

VDDSPD Supply SPD EEPROM power supply: +1.7V to +3.6V.

VREF Supply Reference voltage: VDD/2.

VSS Supply Ground.

NC – No connect: These pins are not connected on the module.

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Functional Block Diagram

Figure 2: Functional Block Diagram

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1b

DM CS# DQS DQS#

U1t

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

U8b

U8t

DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS#

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

U14b

DM CS# DQS DQS#

U14t

DM CS# DQS DQS#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

U2b

DM CS# DQS DQS#

U2t

DM CS# DQS DQS#

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

U13b

DM CS# DQS DQS#

U13t

DM CS# DQS DQS#

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

U11b

U11t

DM CS# DQS DQS# DM CS# DQS DQS#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

U9b

U6t

DM CS# DQS DQS# DM CS# DQS DQS#

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

U10b

U10t

DM CS# DQS DQS# DM CS# DQS DQS#

DQS0#

DQS0

DM0

RS0#

RS1#

DQS1#

DQS1

DM1

DQS2#

DQS2

DM2

DQS3#

DQS3

DM3

DQS4#

DQS4

DM4

DQS5#

DQS5

DM5

DQS6#

DQS6

DM6

DQS7#

DQS7

DM7

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

U12b

DM CS# DQS DQS#

U12t

DM CS# DQS DQS#

DQS8#

DQS8

DM8

VREF

VSS

DDR2 SDRAM

VDD

VDDSPD SPD EEPROM, Temperature Sensor

DDR2 SDRAM

PLL

CK0

CK0#

U6 DDR2 SDRAM x 2

DDR2 SDRAM x 2

Rank 0 = U1b, U2b, U[14b–8b]

Rank 1 = U1t, U2t, U[14t–8t]

SPD EEPROM

A1 A2

SA0

EVENT#

SA1

SDA

SCL

Temp Sensor

A1 A2

SA0 SA1

EVT

S0#

S1#

BA[2:0]

A[14/13:0]

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

RESET#

RS0#: Rank 0

RS1#: Rank 1

RBA[2:0]: DDR2 SDRAM

RA[14/13:0]: DDR2 SDRAM

RRAS#: DDR2 SDRAM

RCAS#: DDR2 SDRAM

RWE#: DDR2 SDRAM

RCKE0: Rank 0

RCKE1: Rank 1

RODT0: Rank 0

RODT1: Rank 1

U7 VSS VSS

VSS

RESET#

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

General Description

The MT18HTS25672RH and MT18HTS51272RH DDR2 SDRAM modules are high-speed,

CMOS dynamic random access 2GB and 4GB memory modules organized in a x72 con-

figuration. These modules use 2Gb TwinDie and 4Gb TwinDie DDR2 SDRAM devices

with eight internal banks.

DDR2 SDRAM modules use double data ra te architecture to achieve high-speed opera-

tion. The double data rate archi t ecture is essentially a 4n-prefetch architecture with an

interface designed to transfer two data words per clock cycle at the I/O pins. A single

read or write access for the DDR2 SDRAM module effectively consis ts of a single

4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corre-

sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS, DQS#) i s transmitted externally, along with data, for

use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM

device during READs and by the memory controller during WRITEs. DQS is edge-

aligned with data for READs and center-aligned with data for WRITEs.

DDR2 SDRAM modul es operate from a differential clock (CK and CK#); the crossing of

CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-

mands are registered at every positive edge of CK . Input data is registered on both edges

of DQS, and output data is referenced to both edges of DQS, as well as to both edges of

CK.

These DDR2 SDRAM modules operate in r egister ed mode , wher e the command/ addr ess

input signals are latched in the registers on the risi ng clock edge and sent to the DDR2

SDRAM devices on the following rising clock edge (data access is delayed by one clock

cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock

signals (CK, CK#) to the DDR2 SDRAM devices. The register (s) and PLL reduce clock,

control, command, and addr ess sig nals loadi ng by isolating DRAM from the system con-

troller. PLL clock timing is defined by JEDEC specifications and ensured by use of the

JEDEC clock reference board. Registered mode will add one clock cycle to CL.

Temperature Sensor

An onboard temper atur e sensor provides the ability to monitor the module temperatur e

along with monitoring alarms. Programmable registers can be used to specify tempera-

ture events and critical boundaries. An EVENT# pin is used to signal when different con-

ditions occur based on how the registers are defined.

Serial Presence-Detect EEPROM Operation

DDR2 SDRAM modules incorporate ser i al presence -d etect. The SPD data is stored in a

256-b yte EEPROM. The first 128 b ytes ar e programmed b y Micron to identify the module

type and various SDRAM organizations and timing parameters . The remaining 128 b ytes

of storage are av ailable for use by the customer. System RE AD/WRITE operations

between the master (system logic) and the slave EEPROM device occur via a standard

I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[1:0],

which provide four unique DIMM/EEPROM addresses. Write protect (WP) is connected

to Vss, permanently disabling hardware write protect.

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Electrical Specifications

S tresses greater than those listed in Table 7 may cause permanent damage to the d evice.

This is a stress rating only, and functional operation of the device at these or any other

conditions above those indicated in each device’s data sheet is not implied. Exposure to

absolute maximum ra ting conditions for extended periods may adversely affect reliabil-

ity.

Notes: 1. Refresh rate is required to double when 85°C < TC ≤ 95°C.

2. For fur th e r informatio n, r ef er to technical note TN-00-08: “Thermal Applications,” avail-

able on Micron’s W eb site.

Table 7: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD VDD supply voltage relative to VSS –0.5 +2.3 V

VIN, VOUT Voltage on any pin relative to VSS –0.5 +2.3 V

IIInput leakage current; Any input 0V ≤ VIN ≤ VDD;

VREF input 0V ≤ VIN ≤ 0.95V (All other pins not under

test = 0V)

Address inputs,

RAS#, CAS#, WE# S#,

CKE, ODT, BA

–5 +5 µA

CK0, CK0# –250 +250

DM –10 +10

IOZ Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ and

ODT are disabled DQ, DQS, DQS# –10 +10 µA

IVREF VREF leakage current; VREF = valid VREF level –36 +36 µA

TAModule ambient operating temperature Commercial 0+70°C

Industrial –40 +85 °C

TC1DDR2 SDRAM component case operating

temperature2Commercial 0+85°C

Industrial –40 +95 °C

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Electrical Specifications

DRAM Operating Conditions

Re commended AC operating conditions are given in the DDR2 component data sheets.

Component specifications are available on Micron’s Web site. Module speed grades cor-

relate with component speed grades, as shown in Table 8.

Design Considerations

Simulations

Micron memor y mod u le s are designed to optimize signal integrity through carefully

designed terminations, controlled board impedances, routing topologies, trace length

matching, and decoupling. However, good signal integrity starts at the system level.

Micron encourages designers to si mulate the signal character i stics of the system’s mem-

ory bus to ensure adequate signal integrity of the entir e memory system.

Power

Operating v oltages ar e specified at the DRAM, not at the edge connector of the module.

Designers must account for any system voltage drops at anticipated power levels to

ensure the required supply voltag e is maintained.

Table 8: Module and Component Speed Grades

DDR2 components may exce ed the listed module sp eed grades

Module Speed Grade Component Speed Grade

-80E -25E

-667 -3

-53E -37E

-40E -5E

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Electrical Specifications

IDD Specifications

Table 9: DDR2 IDD Specifications and Conditions – 2GB

Values are for the MT47H256M8THN DDR2 SDRAM only and are computed from values specified in the

2Gb TwinDie (256 Meg x 8) component data sheet

Parameter/Condition Combined

Symbol -80E -667 -53E -40E Units

Operating one bank active-precharge current: tCK = tCK (IDD),

tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH

between valid commands; Address bus inputs are switching; Data

bus inputs are switching

ICDD0 TBD 873 738 738 mA

Operating one bank active-read-precharge current:

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC

(IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is

HIGH between valid commands; Address bus inputs are switching;

Data pattern is same as IDD4W

ICDD1 TBD 1008 963 918 mA

Precharge power-down current: All device banks idle; tCK = tCK

(IDD); CKE is LOW; Other control and address bus inputs are stable;

Data bus inputs are floating

ICDD2P TBD 126 126 126 mA

Precharge quiet standby current: All device banks idle;

tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Oth e r co ntrol an d address

bus inputs are stable; Data bus inputs are floating

ICDD2Q TBD 603 612 621 mA

Precharge standby current: All device banks idle; tCK = tCK (IDD);

CKE is HIGH, S# is HIGH; Other control and address bus inputs are

switching; Data bus inputs are switching

ICDD2N TBD 468 468 423 mA

Active power-down current: All device banks

open; tCK = tCK (IDD); CKE is LOW; Other control and

address bus inputs are stable; Data bus inputs are

floating

Fast PDN

exit MR[12]

= 0

ICDD3P TBD 270 270 270 mA

Slow PDN

exit MR[12]

= 1

TBD 90 90 90 mA

Active standby current: All device banks open; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH

between valid commands; Other control and address bus inputs are

switching; Data bus inputs are switching

ICDD3N TBD 603 513 468 mA

Operating burst write current: All devic e banks open;

Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK

(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH

between valid commands; Address bus inputs are switching; Data

bus inputs are switching

ICDD4W TBD 1278 1188 1008 mA

Operating burst read current: All device banks open;

Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH,

S# is HIGH between valid commands; Address bus inputs are

switching; Data bus inputs are switching

ICDD4R TBD 1323 1233 1053 mA

Burst refresh curr ent: tCK = tCK (IDD); REFRESH c ommand at every

tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid

commands; Other control and address bus inputs are switching;

Data bus inputs are switching

ICDD5 TBD 2043 1998 1953 mA

Self re fresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control

and address bus inputs are floating; Data bus inputs are floating ICDD6 TBD 126 126 126 mA

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Electrical Specifications

Operating bank interleave read current: All device banks

interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD)

- 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD),

tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are stable during deselects; Data

bus inputs are switching

ICDD7 TBD 2628 2538 2448 mA

Table 10: DDR2 IDD Specifications and Conditions – 4GB

Values are for the MT47H512M8THM DDR2 SDRAM only and are computed from values specified in the

4Gb TwinDie (512 Meg x 8) component data sheet

Parameter/Condition Combined

Symbol -667 -53E -40E Units

Operating one bank active-precharge current: tCK = tCK (IDD),

tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are switching; Data bus inputs are switching

ICDD0 1017 927 927 mA

Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4,

CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),

tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address

bus inputs are switching; Data pattern is same as IDD4W

ICDD1 1422 1062 1062 mA

Precha rge power-down curre nt: All device banks id le; tCK = tCK (IDD); CKE

is LOW; Other control and address bus inputs are stable; Data bus inputs are

floating

ICDD2P 144 144 144 mA

Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);

CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;

Data bus inputs are floating

ICDD2Q 567 576 585 mA

Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is

HIGH, S# is HIGH; Other control and ad dress bus inputs are switching; Data

bus inputs are switching

ICDD2N 657 567 522 mA

Active power-down current: All device banks open;

tCK = tCK (IDD); CKE is LOW; Other control and address bus

inputs are stable; Data bus inputs are floating

Fast PDN exit

MR[12] = 0 ICDD3P 360 315 270 mA

Slow PDN exit

MR[12] = 1 90 90 90 mA

Active standby current: All device banks open; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid

commands; Other control and address bus inputs are switching; Data bus

inputs are switching

ICDD3N 612 522 477 mA

Operating burst write current: All device banks open; Continuous burst

writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),

tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switching

ICDD4W 1422 1242 1197 mA

Operating burst read current: All device banks open; Continuous burst

reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are switching; Data bus inputs are switching

ICDD4R 1647 1656 1665 mA

Table 9: DDR2 IDD Specifications and Conditions – 2GB (continued)

Values are for the MT47H256M8THN DDR2 SDRAM only and are computed from values specified in the

2Gb TwinDie (256 Meg x 8) component data sheet

Parameter/Condition Combined

Symbol -80E -667 -53E -40E Units

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Electrical Specifications

Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC

(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other

control and address bus inputs are switching; Data bus inputs are switching

ICDD5 2637 2457 2367 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and

address bus inputs are floating; Data bus inputs are floating ICDD6 144 144 144 mA

Operating bank interleave read current: All device banks interleaving

reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD);

tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is

HIGH, S# is HIGH between valid commands; Address bus inputs are stable

during deselects; Data bus inputs are switching

ICDD7 3177 2772 2772 mA

Table 10: DDR2 IDD Specifications and Conditions – 4GB (continued)

Values are for the MT47H512M8THM DDR2 SDRAM only and are computed from values specified in the

4Gb TwinDie (512 Meg x 8) component data sheet

Parameter/Condition Combined

Symbol -667 -53E -40E Units

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Table 11: Register Specifications

SSTU32872 devices or equivalent

Parameter Symbol Pins Condition Min Max Units

DC high-level

input voltage VIH(DC) Address,

control,

command

SSTL_18 VREF(DC) + 125 – mV

DC low-level

input voltage VIL(DC) Address,

control,

command

SSTL_18 – VREF(DC) - 125 mV

AC high-level

input voltage VIH(AC) Address,

control,

command

SSTL_18 VREF(DC) + 250 – mV

AC low-level

input voltage VIL(AC) Address,

control,

command

SSTL_18 – VREF(DC) - 250 mV

Output high voltage VOH Parity output LVCMOS 1.2 – V

Output low voltage VOL Parity output LVCMOS – 0.5 V

Input current IIAll pins VI = VDDQ or VSSQ –5 5 µA

Static standby IDD All pins RESET# = VSSQ (IO = 0) – 2 00 µA

Static operating IDD All pins RESET# = VSSQ;

VI = VIH(AC) or VIL(DC)

IO = 0

–80mA

Dynamic operating

(clock tree) IDDD n/a RESET# = V DD, VI = VIH(AC) or

VIL(AC), IO = 0; CK and CK#

switching 50% duty cycle

–Varies by

manufacturer µA

Dynamic operating

(per each input) IDDD n/a RESET# = VDD, VI = VIH(AC) or

VIL(AC), IO = 0; CK and CK#

switching 50% duty cyc le;

One data input switching at

tCK/2, 50% duty cycle

–Varies by

manufacturer µA

Input capacitance

(per device, per pin) CIAll inputs

except RESET# VI = VREF ±350mV;

VDDQ = 1.8V 2.5 3.5 pF

Input capacitance

(per device, per pin) CIRESET# VI = VDDQ or VSSQ –Varies by

manufacturer pF

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Notes: 1. PLL timing and switching specifications are critical for proper operation of the DDR2

DIMM. This is a subset of parameters for the specific PLL used. Detailed PLL information is

available in JEDEC Standard JESD82.

Table 12: PLL Specifications

CUA845 device or equivalent JESD82-21

Parameter Symbol Pins Condition Min Max Units

DC high-level input

voltage VIH OE, OS, CK, CK# LVCMOS 0.65 × VDD –V

DC low-level input voltage VIL OE, OS, CK, CK# LVCMOS – 0.35 × VDD V

Input voltage (limits) VIN –0.3 VDD + 0.3 V

Input differential-pair

cross voltage VIX Differential input (VDD/2) - 0.15 (VDD/2) + 0.15 V

Input differential voltage VID(DC) Differential input 0.3 VDD + 0.4 V

Input differential voltage VID(AC) Differential input 0.6 VDD + 0.4 V

Input current IIOE, OS, FBIN, FBIN# VI = VDD or VSS –10 +10 µA

CK, CK# VI = VDD or VSS –250 250 µA

Output disabled current IODL OE = L, VODL = 100mV 100 – µA

Static supply current IDDLD C

L = 0pf – +500 µA

Dynamic supply IDD n/a CK and CK# = 410 MHz

all output are open

(not connected to a PCB)

–+300mA

Input capacitance CIN Each input VI = VDD or VSS 23pF

Table 13: PLL Clock Driver Timing Requirements and Switching Characteristics

Parameter Symbol Min Max Units

Stabilization time tL–15µs

Input clock slew rate slr(i) 1.0 4 V/ns

SSC modulation frequency 30 33 kHz

SSC clock input frequ ency deviation 0.0 –0.50 %

PLL loop bandwi dth (–3dB from unity gain) 2.0 – MHz

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

The temperature sensor continuousl y monitors the modul e’s temperature and can be

read back at any time over the I2C bus shar ed with the serial pr esence-detect (SPD)

EEPROM.

EVENT# Pin

The temperature sensor also adds the E VENT# pin (open-drain). Not used by the SPD

EEPR OM, EVENT# is a temperature sensor output used to flag critical events that can be

set up in the sensor’s configuration register.

EVENT# has thre e defined modes of operati o n: interrupt mode, compare mode , and

critical temperature mode. The open-drain output of EVENT# under the three separate

operating modes is shown in Figure 3 on page 15. Event thresholds are programmed in

the 0x01 register using a hysteresis. The alarm window provides a comparison window,

with upper and lower limits set in the alarm upper boundary register and the alarm

lower boundary register, respe ctively. When the alarm window is enabled, EVENT# trig-

gers whenever the temper ature is outside the MIN or MAX values set by the user.

The interrupt mode enables software to reset EVENT# after a critical temperature

threshold has been detected. Threshold points ar e set in the configuration r egister b y the

user. This mode triggers the critical temper atur e limit and both the MIN and MAX points

of the temperature alarm window.

Table 14: Temperature Sensor Operating Conditions

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD +3.0 +3.6 V

Supply current: V DD = 3.3V IDD –+2.0mA

Input high volt ag e: Logic 1; SCL, SDA VIH +1.45 VDDSPD + 1 V

Input low voltage: Logic 0; SCL, SDA VIL –+0.55V

Output low voltage: IOUT = 2.1mA VOL –+0.4V

Input current IIN –5.0 +5.0 µA

Temperature sensing range – –40 +125 °C

Temperature sensor accuracy (class B) ––1.0+1.0°C

Table 15: Temperature Sensor Serial Interface Timing

Parameter/Condition Symbol Min Max Units

Time bus must be free before a new transition can start tBUF 4.7 – µs

SDA fall time tF20300ns

SDA rise time tR – 1000 ns

Data hold time tHD:DAT 200 900 ns

Start condition hold time tH:STA 4.0 – µs

Clock HIGH period tHIGH 4.0 50 µs

Clock LOW period tLOW 4.7 – µs

SCL clock frequency fSCL 10 100 kHz

Data setup time tSU:DAT 250 – ns

Start condition setup time tSU:STA 4.7 – µs

Stop condition setup time tSU:STO 4.0 – µs

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

The compar e mode is similar to the interrupt mode, except EVENT # cannot be reset by

the user and returns to the logic HIGH state only when the temp erature falls below the

programmed thresholds.

Critical temperature mode triggers EVENT# only when the temperature exceeds the pro-

grammed critical trip point. When the critical trip point is reached, the temperature sen-

sor goes into comparator mode, and the critical EVENT# cannot be cleared through

software.

SM Bus Slave Subaddress Decoding

The temperature sensor’s physical address differs from the SPD EEPROM’s physical

address: binary 0011 for A0, A1, A2, and RW#, where A0, A1, and A2 are the three slave

subaddress pins and the R W# bit is the READ/WRITE flag.

If the slave base address is fixed for the temperature sensor/SPD EEPROM, then pins

A[2:0] set the subaddress bits of the slave address, enabling the devices to be located

anywhere within the eight slave address locations. For example, they could be set from

30h to 3Eh.

Figure 3: EVENT# Pin Functionality

Time

Critical

Alarm window

(MAX)

Alarm window

(MIN)

EVENT#

interrupt mode

EVENT#

comparator mode

EVENT#

critical temperature

only mode

Clears event

Hysteresis affects

these trip points

Temperature

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

Pointer Register

The pointer r eg ister selec ts which of the 16-bit registers is being accessed in subsequent

READ and WRITE operations. This register is a write-only register.

Capability Register

The capability register indicates the features and functionality supported b y the temper-

ature sensor. This register is a read-only register.

Table 16: Temperature Sensor Registers

Name Address Power-On Default

Pointer register Not applicable Undefined

Capability register 0x00 0x0001

Configuration register 0x01 0x0000

Alarm temperature upper boundary register 0x02 0x0000

Alarm temperature lower boundary register 0x03 0x0000

Critical temperature register 0x04 0x0000

Temperature register 0x05 Undefined

Table 17: Pointer Register Bits 0–7

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0000Register

select Register

select

Table 18: Pointer Register Bits 0–2 Descriptions

Bit 2 Bit 1 Bit 0 Register

000

Capability register

001

Configuration register

010

Alarm temperature upper boundary register

011

Alarm temperat ure lower boundary register

100

Critical temperature register

101

Temper a ture register

Table 19: Capability Register Bits

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

RFU RFU RFU RFU RFU RFU RFU RFU

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RFU RFU RFU TRES1 TRES0 Wider range Precision Has alarm and

critical

temperature

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

Configuration Register

Table 20: Capability Register Bit Descriptions

Bit Description

0Basic capability

1: Has alarm and critical trip point capabilities

1Accuracy

0: ±2°C over the active range and ±3°C over the monitor range

1: ±1°C over the active range and ±2°C over the monitor range

2Wider range

0: Temperatures lower than 0°C are clamped to a binary value of 0

1: Temperatures below 0°C can be read

4:3 Temperature resolution

00: 0.5°C LSB

01: 0.25°C LSB

10: 0.125°C LSB

11: 0.0625°C LSB

15:5 0: Must be set to zero

Table 21: Configuration Register (Address: 0x01

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

RFU RFU RFU RFU RFU Hysteresis Shutdown

mode

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Critical lock

bit Alarm lock bit Clear event Event output

status Event output

control Critical event

only Event polarity Event mode

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

Table 22: Configuration Register Bit Descriptions

Bit Description Notes

0Event mode

0: Comparator mode

1: Interrupt mode

Event mode cannot be changed if either of the lock

bits is set.

1EVENT# polarity

0: Active LOW

1: Active HIGH

Event # polarity cannot be changed if either of the

lock bits is set.

2Critical event only

0: EVENT# trips on alarm or critical temperature event

1: EVENT# trips only if critical temperature is re ached

3Event output control

0: Event output disabled

1: Event output enabled

4Event status

0: EVENT# has not been asserted by this device

1: EVENT# is being asserted due to an alarm window or

critical temperature cond ition

This is a read-only field in the register. The event

causing the event can be determined from the read

temperature register.

5Clear event

0: No effect

1: Clears the event when the temperature sensor is in the

interrupt mode

6Alarm window lock bit

0: Alarm trips are not locked and can be changed

1: Alarm trips are locked and cannot be changed

7Critical trip lock bit

0: Critical trip is not locked and can be changed

1: Critical trip is locked and cannot be changed

8Shutdown mode

0: Enabled

1: Shutdown

The shutdown mode is a power-saving mode that

disables the temperature sensor.

10:9 Hysteresi s enable

00: Disable

01: Enable at 1.5°C

10: Enable at 3°C

11: Enable at 6°C

When enabled, a hysteresis is applied to temperature

movement around the trip points (see Figure 4 on

page 19). As an example, if the hysteresis register is

enabled to a delta of 6°C, t he preset trip points will

toggle when the temperature reaches the

programmed value. These values will reset when the

temperature drops below the trip points minus the

set hysteresis level. In this case, this would be critical

temperature minus 6°C.

The hysteresis is applied to both the above alarm

window and the below alarm window bits found in

the read-only temperature register (see Table 23 on

page 19). EVENT# is also affected by this register.

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

Figure 4: Hysteresis Applied to Temperature Around Trip Points

Notes: 1. TH is the value set in the alarm temperat ure upper boundary trip register.

2. TL is the value set in the alarm tempera ture lower boundary trip register.

3. Hyst is the value set in the hysteresis bits of the configuration regis ter.

Table 23: Hysteresis Applied to Alarm Window Bits in the Temperature Register

Condition

Below Alarm Window Bit Above Alarm Window Bit

Temperature

Gradient Critical Temperature Temperature

Gradient Critical Temperature

Sets Falling TL - Hyst Rising TH

Clears Rising TLFalling TH - Hyst

TH - Hyst

TL - Hyst

Below window bit

Above window bit

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

Temperature Format

The temperature trip point registers and temper ature readout register use a

2’s complement format to enable negative numbers. The least significant bit (LSB) is

equal to 0.0625°C or 0.25°C depending on which register is referenced. As an example,

assuming an LSB of 0.0625°C:

• A value of 0x018C equals 24.75°C

• A value of 0x06C0 equals 108°C

• A value of 0x1E74 equals –24.75°C

Temperature Trip Point Registers

The upper and lower temperature boundary registe r s are used to set the maximum and

minimum values of the alarm window. LSB for these registers is 0.25°C. All RFU bits in

the register will always report 0s.

Critical Temperature Register

The critical temperature register is used to set the maximum temperature above the

alarm window. The LSB for this register is 0.25°C. All RFU bits in the register will always

report 0s.

Table 24: Alarm Temperature Upper Boundary Register (Address: 0x02)

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000MSB LSB RFU RFU

Alarm window upper boundary temperature

Table 25: Alarm Temperature Lower Boundary Register (Address: 0x03)

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000MSB LSB RFU RFU

Alarm window lower boundary temperature

Table 26: Critical Temperature Register (Address: 0x04)

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000MSB LSB RFU RFU

Critical temperature trip point

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

Temperature Register

The temperature r egister is a read -only register that provides the current temperature

detected by the temperature sensor. The LSB for this register is 0.0625°C with a resolu-

tion of 0.0625°C. The most significant bit (MSB) is 128°C in the readout section of this

The upper three bits of the register are used to monitor the trip points that are set in the

previous t hre e re gisters.

Table 27: Temperature Register (Address: 0x05)

Bit

15 14 13 12 11 10 9876543210

Above

critical

trip

Above

alarm

window

Below

alarm

window

MSB LSB

Temperature

Table 28: Temperature Register Bit Descriptions

BIT Description

13 Below alarm window

0: Temperature is equal to or above the lower boundary

1: Temperature is below alarm window

14 Above alarm window

0: Temperature is equal to or below the upper boun dary

1: Temperature is above alarm window

15 Above critical trip point

0: Temperature is below critical trip point

1: Temperature is above critical trip point

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Serial Pr esence-Detect EEPROM

Serial Presence-Detect EEPROM

Notes: 1. For a restart condition or following a WRITE cycle.

2. This parameter is sampled.

3. To avoid spurious start and stop conditi ons, a minimum delay is placed between SCL = 1

and the falling or rising edge of SDA.

4. This specif ication may conflict with SMBus timing specifications.

Serial Presence-Detect Data

For the latest serial presence-detect data, refer to Micron’s SPD page:

www.micron.com/SPD.

Table 29: SPD EEPROM DC Operating Conditions

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD 1.7 3.6 V

Input leakage current: VIN = GND to VDD ILI ±2 µA

Output leakage current: VOUT = GND to VDD ILO 0.05 ±2 µA

Supply current:: VDDSPD = 1.7V, fC = 100kHz

(rise/fall time < 30ns) IDD –1mA

Standby Supply current: VIN = VSSSPD or VDDSPD,

VDDSPD = 1.7V IDD1 –0.5µA

Standby Supply current: VIN = VSSSPD or VDDSPD,

VDDSPD = 3.6V IDD1 –1µA

Input low voltage: (SCL, SDA, WC#) VIL –0.45 VDDSPD × 0.3 V

Input high voltage: Logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 1 V

SA0 high voltage: VHV - VDDSPD ≥ 4.8V VHV 710V

Output low voltage: IOL = 0.7m A , VDDSPD = 1.7V VOL –0.2V

Output low voltage: IOL = 2.1mA, 2.2V ≤ VDDSPD ≤ 3.6V VOL –0.4V

Table 30: SPD EEPROM AC Operating Conditions

Parameter/Condition Symbol

VDDSPD < 2.2V VDDSPD ≥ 2.2V

Units NotesMin Max Min Max

Clock frequenc y fSCL 10 100 10 400 kHz

Clock pulse widt h hig h time tHIGH 4 – 0.6 – µs

Clock pulse width low time tLOW 4.7 – 1.3 – µs

SDA rise time tR–1–0.3µs2

SDA fall time tF 0.02 0.3 0.02 0.3 µs 2

Data-in setup time tSU:DAT 0.25 – 0.1 – µs

Data-in hold time tHD:DI 0 – 0 – µs

Data-out hold time tHD:DAT 0.2 0.9 0.2 0.9 ns 4

Data out access time from SCL low tAA:DAT 0.2 3.5 0.2 0.9 µs 3

Start condition setup time tSU:STA 4.7 – 0.6 – µs 1

Start condition hold time tHD:STA 4 – 0.6 – µs

Stop condition setup time tSU:STO 4 – 0.6 – µs

Time between Stop Condition an d next

Start Condition

tBUF 4.7 – 1.3 – µs

WRITE time tW–10– 5ms4

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although

considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Module Dimensions

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Module Dimensions

Figure 5: 200-Pin DDR2 SORDIMM

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only.

3.8 (0.150)

MAX

Pin 1

67.75 (2.667)

67.45 (2.656)

20.0 (0.787)

TYP

1.8 (0.071)

(2X)

0.6 (0.024)

TYP

0.45 (0.018)

TYP

2.0 (0.079) R

(2X)

Pin 199

Pin 200 Pin 2

Front view

2.0 (0.079)

TYP

6.0 (0.236)

TYP

63.60 (2.504)

TYP

3.50 (0.138) TYP

Back view

1.1 (0.043)

0.9 (0.035)

47.4 (1.87)

TYP 11.4 (0.45)

TYP

4.2 (0.165)

TYP

0.5(0.0197) R

16.26 (0.64)

TYP

U1 U2 U5

U8 U9

U10 U11 U12 U13 U14

1.0 (0.039)

TYP

10.0 (0.394)

TYP

1.0 (0.039) R

(2X)

30.15 (1.187)

29.85 (1.175)