LTC2234
1
2234fa
FEATURES
DESCRIPTIO
U
TYPICAL APPLICATIO
U
■
Sample Rate: 135Msps
■
61dB SNR up to 200MHz Input
■
75dB SFDR up to 400MHz Input
■
775MHz Full Power Bandwidth S/H
■
Single 3.3V Supply
■
Low Power Dissipation: 630mW
■
CMOS Outputs
■
Selectable Input Ranges: ±0.5V or ±1V
■
No Missing Codes
■
Optional Clock Duty Cycle Stabilizer
■
Shutdown and Nap Modes
■
Data Ready Output Clock
■
Pin Compatible Family
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
■
48-Pin 7mm × 7mm QFN Package
■
Wireless and Wired Broadband Communication
■
Cable Head-End Systems
■
Power Amplifier Linearization
■
Communications Test Equipment
10-Bit, 135Msps ADC
The LTC
®
2234 is a 135Msps, sampling 10-bit A/D con-
verter designed for digitizing high frequency, wide dy-
namic range signals. The LTC2234 is perfect for demand-
ing communications applications with AC performance
that includes 60.5dB SNR and 75dB spurious free dy-
namic range for signals up to 400MHz. Ultralow jitter of
0.15ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ)
and ±0.8LSB INL, ±0.6LSB DNL over temperature. The
transition noise is a low 0.12LSB
RMS
.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC
+
and ENC
–
inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
–
+
INPUT
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
10-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
FLEXIBLE
REFERENCE
D9
•
•
•
D0
0.5V TO 3.6V
OV
DD
OGND
ENCODE
INPUT
REFH
REFL
ANALOG
INPUT
2234 TA01
3.3V
V
DD
APPLICATIO S
U
SFDR vs Input Frequency
SFDR (dBFS)
INPUT FREQUENCY (MHz)
0600500400
2234 TA01b
100 200 300
4th OR HIGHER
2nd OR 3rd
90
85
80
75
70
65
60
55
50
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
LTC2234
2
2234fa
CO VERTER CHARACTERISTICS
U
Supply Voltage (V
DD
) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (V
DD
+ 0.3V)
Digital Input Voltage .................... –0.3V to (V
DD
+ 0.3V)
Digital Output Voltage ............... –0.3V to (OV
DD
+ 0.3V)
Power Dissipation............................................ 1500mW
Operating Temperature Range
LTC2234C ............................................... 0°C to 70°C
LTC2234I.............................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
ORDER PART
NUMBER
UK PART*
MARKING
T
JMAX
= 125°C, θ
JA
= 29°C/W
LTC2234UK
LTC2234UK
LTC2234CUK
LTC2234IUK
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
OVDD = VDD (Notes 1, 2)
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) ●10 Bits
Integral Linearity Error Differential Analog Input (Note 5) ●–0.8 ±0.2 0.8 LSB
Differential Linearity Error Differential Analog Input ●–0.6 ±0.1 0.6 LSB
Integral Linearity Error Single-Ended Analog Input (Note 5) ±0.5 LSB
Differential Linearity Error Single-Ended Analog Input ±0.1 LSB
Offset Error (Note 6) ●–37 ±537 mV
Gain Error External Reference ●–2.5 ±0.5 2.5 %FS
Offset Drift ±10 µV/C
Full-Scale Drift Internal Reference ±30 ppm/C
External Reference ±15 ppm/C
Transition Noise SENSE = 1V 0.12 LSB
RMS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
TOP VIEW
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
EXPOSED PAD IS GND (PIN 49),
MUST BE SOLDERED TO PCB
A
IN+
1
A
IN–
2
REFHA 3
REFHA 4
REFLB
5
REFLB
6
REFHB 7
REFHB 8
REFLA 9
REFLA 10
V
DD
11
V
DD
12
36 D7
35 D6
34 D5
33 OV
DD
32 OGND
31 D4
30 D3
29 D2
28 OV
DD
27 OGND
26 D1
25 D0
49
48 GND
47 V
DD
46 V
DD
45 GND
44 V
CM
43 SENSE
42 MODE
41 OF
40 D9
39 D8
38 OGND
37 OV
DD
GND 13
V
DD
14
GND 15
ENC
+
16
ENC
–
17
SHDN
18
OE
19
CLOCKOUT
20
NC 21
OGND 22
OV
DD
23
NC 24
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
LTC2234
3
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Analog Input Range (A
IN+
– A
IN–
) 3.1V < V
DD
< 3.5V ●±0.5 to ±1V
V
IN, CM
Analog Input Common Mode (A
IN+
+ A
IN–
)/2 Differential Input ●1 1.6 1.9 V
Single Ended Input (Note 7) ●0.5 1.6 2.1 V
I
IN
Analog Input Leakage Current 0 < A
IN+
, A
IN–
< V
DD
●–1 1 µA
I
SENSE
SENSE Input Leakage 0V < SENSE < 1V ●–1 1 µA
I
MODE
MODE Pin Pull-Down Current to GND 10 µA
t
AP
Sample and Hold Acquisition Delay Time 0 ns
t
JITTER
Sample and Hold Acquisition Delay Time Jitter 0.15 ps
RMS
CMRR Analog Input Common Mode Rejection Ratio 80 dB
Full Power Bandwidth Figure 8 Test Circuit 775 MHz
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 30MHz Input (1V Range) 59.5 dB
30MHz Input (2V Range) ●60.4 61.2 dB
70MHz Input (1V Range) 59.5 dB
70MHz Input (2V Range) 61.1 dB
140MHz Input (1V Range) 59.4 dB
140MHz Input (2V Range) 61.0 dB
250MHz Input (1V Range) 59.0 dB
250MHz Input (2V Range) 60.6 dB
SFDR Spurious Free Dynamic Range 30MHz Input (1V Range) 80 dB
30MHz Input (2V Range) ●69 78 dB
70MHz Input (1V Range) 80 dB
70MHz Input (2V Range) 78 dB
140MHz Input (1V Range) 78 dB
140MHz Input (2V Range) 78 dB
250MHz Input (1V Range) 78 dB
250MHz Input (2V Range) 78 dB
SFDR Spurious Free Dynamic Range 30MHz Input (1V Range) 86 dB
4th Harmonic or Higher 30MHz Input (2V Range) 86 dB
70MHz Input (1V Range) 86 dB
70MHz Input (2V Range) 86 dB
140MHz Input (1V Range) 86 dB
140MHz Input (2V Range) 86 dB
250MHz Input (1V Range) 85 dB
250MHz Input (2V Range) 85 dB
S/(N+D) Signal-to-Noise Plus 30MHz Input (1V Range) 59.5 dB
Distortion Ratio 30MHz Input (2V Range) ●60.2 61.2 dB
70MHz Input (1V Range) 59.5 dB
70MHz Input (2V Range) 61.1 dB
IMD Intermodulation Distortion f
IN1
= 138MHz, f
IN2
= 140MHz 81 dBc
A ALOG I PUT
UU
DY A IC ACCURACY
U
W
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
LTC2234
4
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DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
I TER AL REFERE CE CHARACTERISTICS
UU U
(Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CM
Output Voltage I
OUT
= 0 1.570 1.600 1.630 V
V
CM
Output Tempco ±25 ppm/°C
V
CM
Line Regulation 3.1V < V
DD
< 3.5V 3 mV/V
V
CM
Output Resistance –1mA < I
OUT
< 1mA 4 Ω
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC
+
, ENC
–
)
V
ID
Differential Input Voltage ●0.2 V
V
ICM
Common Mode Input Voltage Internally Set 1.6 V
Externally Set (Note 7) ●1.1 1.6 2.5 V
R
IN
Input Resistance 6kΩ
C
IN
Input Capacitance (Note 7) 3 pF
LOGIC INPUTS (OE, SHDN)
V
IH
High Level Input Voltage V
DD
= 3.3V ●2V
V
IL
Low Level Input Voltage V
DD
= 3.3V ●0.8 V
I
IN
Input Current V
IN
= 0V to V
DD
●–10 10 µA
C
IN
Input Capacitance (Note 7) 3 pF
LOGIC OUTPUTS
OV
DD
= 3.3V
C
OZ
Hi-Z Output Capacitance OE = High (Note 7) 3 pF
I
SOURCE
Output Source Current V
OUT
= 0V 50 mA
I
SINK
Output Sink Current V
OUT
= 3.3V 50 mA
V
OH
High Level Output Voltage I
O
= –10µA 3.295 V
I
O
= –200µA●3.1 3.29 V
V
OL
Low Level Output Voltage I
O
= 10µA 0.005 V
I
O
= 1.6mA ●0.09 0.4 V
OV
DD
= 2.5V
V
OH
High Level Output Voltage I
O
= –200µA 2.49 V
V
OL
Low Level Output Voltage I
O
= 1.6mA 0.09 V
OV
DD
= 1.8V
V
OH
High Level Output Voltage I
O
= –200µA 1.79 V
V
OL
Low Level Output Voltage I
O
= 1.6mA 0.09 V
LTC2234
5
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Analog Supply Voltage (Note 7) ●3.1 3.3 3.5 V
OV
DD
Output Supply Voltage (Note 7) ●0.5 3.3 3.6 V
I
VDD
Analog Supply Current ●191 206 mA
P
DISS
Power Dissipation ●630 680 mW
P
SHDN
Shutdown Power SHDN = High, OE = High, No CLK 2 mW
P
NAP
Nap Mode Power SHDN = High, OE = Low, No CLK 35 mW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
S
Sampling Frequency ●1 135 MHz
t
L
ENC Low Time Duty Cycle Stabilizer Off ●3.5 3.7 500 ns
Duty Cycle Stabilizer On ●2 3.7 500 ns
t
H
ENC High Time Duty Cycle Stabilizer Off ●3.5 3.7 500 ns
Duty Cycle Stabilizer On ●2 3.7 500 ns
t
AP
Sample-and-Hold Aperture Delay 0 ns
t
OE
Output Enable Delay (Note 7) ●510 ns
t
D
ENC to DATA Delay (Note 7) ●1.3 2.1 3.5 ns
t
C
ENC to CLOCKOUT Delay (Note 7) ●1.3 2.1 3.5 ns
DATA to CLOCKOUT Skew (t
C
- t
D
) (Note 7) ●–0.6 0 0.6 ns
Pipeline Latency 5 Cycles
TI I G CHARACTERISTICS
UW
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
POWER REQUIRE E TS
WU
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V
DD
, they will
be clamped by internal diodes. This product can handle input currents of
greater than 100mA below GND or above V
DD
without latchup.
Note 4: V
DD
= 3.3V, OV
DD
= 1.8V, f
SAMPLE
= 135MHz, differential
ENC
+
/ENC
–
= 2V
P-P
sine wave, input range = 2V
P-P
with differential drive,
unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve. The
deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when the
output code flickers between 00 0000 0000 and 11 1111 1111 in 2’s
complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: V
DD
= 3.3V, OV
DD
= 1.8V, f
SAMPLE
= 135MHz, differential
ENC
+
/ENC
–
= 2V
P-P
sine wave, input range = 1V
P-P
with differential drive,
output C
LOAD
= 5pF.
LTC2234
6
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TYPICAL PERFOR A CE CHARACTERISTICS
UW
OUTPUT CODE
0
ERROR (LSB)
1024
2234 G01
256 512 768
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
OUTPUT CODE
0
ERROR (LSB)
1024
2234 G02
256 512 768
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
CODE
513
140000
120000
100000
80000
60000
40000
20000
0
2234 G03
514 515
COUNT
131064
53
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
65
64
63
62
61
60
59
58
57
56
55 100 200 300 400
2234 G04
500 600
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
65
64
63
62
61
60
59
58
57
56
55 100 200 300 400
2234 G05
500 600
INPUT FREQUENCY (MHz)
0100 200 300 400
2234 G06
500 600
SFDR (dBFS)
90
85
80
75
70
65
60
55
50
INPUT FREQUENCY (MHz)
0100 200 300 400
2234 G07
500 600
SFDR (dBFS)
90
85
80
75
70
65
60
55
50
INPUT FREQUENCY (MHz)
0100 200 300 400
2234 G08
500 600
SFDR (dBFS)
90
85
80
75
70
65
60
55
50
INPUT FREQUENCY (MHz)
0100 200 300 400
2234 G09
500 600
SFDR (dBFS)
90
85
80
75
70
65
60
55
50
LTC2234: INL, 2V Range LTC2234: DNL, 2V Range
LTC2234: Shorted Input Noise
Histogram
LTC2234: SFDR (HD2 and HD3) vs
Input Frequency, –1dB, 1V Range
LTC2234: SFDR (HD4+) vs Input
Frequency, –1dB, 2V Range
LTC2234: SFDR (HD4+) vs Input
Frequency, –1dB, 1V Range
LTC2234: SNR vs Input
Frequency, –1dB, 2V Range
LTC2234: SNR vs Input
Frequency, –1dB, 1V Range
LTC2234: SFDR (HD2 and HD3) vs
Input Frequency, –1dB, 2V Range
LTC2234
7
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SAMPLE RATE (Msps)
0
I
VDD
(mA)
80
220
210
200
190
180
170
160
150
2234 G12
40 160 180120
20 100
60 140
SAMPLE RATE (Msps)
0
SFDR AND SNR (dBFS)
80
85
80
75
70
65
60
55
50
2234 G10
4020 60 100 140 160120
SFDR
SNR
SAMPLE RATE (Msps)
0
SFDR AND SNR (dBFS)
80
85
80
75
70
65
60
55
50
2234 G11
4020 60 100 140 160120
SFDR
SNR
2V RANGE
1V RANGE
INPUT LEVEL (dBFS)
0
SFDR (dBc AND dBFS)
100
90
80
70
60
50
40
30
20
10
0–40
2234 G14
–10
–20
–30
–50
dBFS
dBc
SAMPLE RATE (Msps)
0
I
OVDD
(mA)
40 80 100 180
2234 G13
20 60 120 140 160
20
10
0
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC2234: SFDR and SNR
vs Sample Rate, 2V Range,
fIN = 30MHz, –1dB
LTC2234: SFDR and SNR
vs Sample Rate, 1V Range,
fIN = 30MHz, –1dB
LTC2234: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
LTC2234: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB,
OVDD = 1.8V
LTC2234: SFDR vs Input Level,
f
IN
= 70MHz, 2V Range
LTC2234
8
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2234 G18
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
AMPLITUDE (dB)
2234 G19
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
AMPLITUDE (dB)
2234 G20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
AMPLITUDE (dB)
2234 G23
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
AMPLITUDE (dB)
2234 G22
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
AMPLITUDE (dB)
2234 G21
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
AMPLITUDE (dB)
2234 G15
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
AMPLITUDE (dB)
2234 G16
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
AMPLITUDE (dB)
2234 G17
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
AMPLITUDE (dB)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC2234: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range
LTC2234: 8192 Point FFT,
fIN = 30MHz, –1dB, 1V Range
LTC2234: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range
LTC2234: 8192 Point FFT,
fIN = 70MHz, –1dB, 1V Range
LTC2234: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range
LTC2234: 8192 Point FFT,
fIN = 140MHz, –1dB, 1V Range
LTC2234: 8192 Point FFT,
fIN = 250MHz, –1dB, 2V Range
LTC2234: 8192 Point FFT,
fIN = 250MHz, –1dB, 1V Range
LTC2234: 8192 Point FFT,
fIN = 500MHz, –6dB, 1V Range
LTC2234
9
2234fa
UU
U
PI FU CTIO S
A
IN
+ (Pin 1): Positive Differential Analog Input.
A
IN
– (Pin 2): Negative Differential Analog Input.
REFHA (Pins 3, 4): ADC High Reference. Bypass to Pins
5, 6 with 0.1µF ceramic chip capacitor, to Pins 9, 10 with
a 2.2µF ceramic capacitor and to ground with a 1µF
ceramic capacitor.
REFLB (Pins 5, 6): ADC Low Reference. Bypass to Pins 5,
6 with 0.1µF ceramic chip capacitor. Do not connect to
Pins 9, 10.
REFHB (Pins 7, 8): ADC High Reference. Bypass to Pins
9, 10 with 0.1µF ceramic chip capacitor. Do not connect to
Pins 3, 4.
REFLA (Pins 9, 10): ADC Low Reference. Bypass to Pins
7, 8 with 0.1µF ceramic chip capacitor, to Pins 3, 4 with a
2.2µF ceramic capacitor and to ground with a 1µF ceramic
capacitor.
V
DD
(Pins 11, 12, 14, 46, 47): 3.3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors. Adjacent pins
can share a bypass capacitor.
GND (Pins 13, 15, 45, 48): ADC Power Ground.
ENC+ (Pin 16): Encode Input. The input is sampled on the
positive edge.
ENC– (Pin 17): Encode Complement Input. The input is
sampled on the negative edge. Bypass to ground with
0.1µF ceramic for single-ended ENCODE signal.
SHDN (Pin 18): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to V
DD
results in normal operation with the
outputs at high impedance. Connecting SHDN to V
DD
and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to V
DD
and OE to V
DD
results in sleep mode with the outputs at high impedance.
OE (Pin 19): Output Enable Pin. Refer to SHDN pin
function.
CLOCKOUT (Pin 20): Data Valid Output. Latch data on the
falling edge of CLOCKOUT.
NC (Pins 21, 24): Do not connect these pins.
D0 – D9 (Pins 25, 26, 29, 30, 31, 34, 35, 36, 39, 40):
Digital Outputs. D9 is the MSB.
OGND (Pins 22, 27, 32, 38): Output Driver Ground.
OV
DD
(Pins 23, 28, 33, 37): Positive Supply for the
Output Drivers. Bypass to ground with 0.1µF ceramic chip
capacitors.
OF (Pin 41): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 42): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3 V
DD
selects offset
binary output format and turns the clock duty cycle stabi-
lizer on. Connecting MODE to 2/3 V
DD
selects 2’s comple-
ment output format and turns the clock duty cycle stabi-
lizer on. Connecting MODE to V
DD
selects 2’s complement
output format and turns the clock duty cycle stabilizer off.
SENSE (Pin 43): Reference Programming Pin. Connecting
SENSE to V
CM
selects the internal reference and a ±0.5V
input range. V
DD
selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±V
SENSE
. ±1V is the largest valid input range.
V
CM
(Pin 44): 1.6V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
Exposed Pad (Pin 49): ADC Power Ground. The exposed
pad on the bottom of the package needs to be soldered to
ground.
LTC2234
10
2234fa
FUNCTIONAL BLOCK DIAGRA
UU
W
Figure 1. Functional Block Diagram
DIFF
REF
AMP
REF
BUF
2.2µF
1µF
0.1µF 0.1µF
1µF
INTERNAL CLOCK SIGNALSREFH REFL
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
RANGE
SELECT
1.6V
REFERENCE
ENC
+
REFHAREFLB REFLA REFHB
ENC
–
SHIFT REGISTER
AND CORRECTION
M0DE
OGND
OV
DD
2234 F01
INPUT
S/H
SENSE
V
CM
A
IN–
A
IN+
2.2µF
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
SHDN
OF
D9
D0
CL0CKOUT
•
•
•
OE
LTC2234
11
2234fa
Timing Diagram
TI I G DIAGRA S
WUW
tAP
N + 1
N + 2 N + 4
N + 3
N
ANALOG
INPUT
tH
tOE tOE
tD
tC
tL
N – 5 N – 4 N – 3 N – 2 N – 1
ENC–
ENC+
CLOCKOUT
D0-D9, OF
2234 TD01
OE
DATA OF, D0-D9, CLOCKOUT
LTC2234
12
2234fa
APPLICATIO S I FOR ATIO
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DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log (√(V2
2
+ V3
2
+ V4
2
+ . . . Vn
2
)/V1)
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Full Power Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re-
duced by 3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC
+
equals the ENC
–
voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNR
JITTER
= –20log (2π • f
IN
• t
JITTER
)
LTC2234
13
2234fa
CONVERTER OPERATION
As shown in Figure 1, the LTC2234 is a CMOS pipelined
multistep converter. The converter has five pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later (see the Timing Diagram section).
For optimal AC performance the analog inputs should be
driven differentially. For cost sensitive applications, the
analog inputs can be driven single-ended with slightly
worse harmonic distortion. The encode input is differen-
tial for improved common mode noise immunity. The
LTC2234 has two phases of operation, determined by the
state of the differential ENC
+
/ENC
–
input pins. For brevity,
the text will refer to ENC
+
greater than ENC
–
as ENC high
and ENC
+
less than ENC
–
as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is re-
peated for the third and fourth stages, resulting in a fourth
stage residue that is sent to the fifth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2234
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (C
SAMPLE
) through
CSAMPLE
1.6pF
VDD
VDD
LTC2234
AIN+
2234
F02
CSAMPLE
1.6pF
VDD
AIN–
ENC–
ENC+
1.6V
6k
1.6V
6k
CPARASITIC
1pF
CPARASITIC
1pF
15Ω
15Ω
Figure 2. Equivalent Input Circuit
APPLICATIO S I FOR ATIO
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LTC2234
14
2234fa
NMOS transistors. The capacitors shown attached to each
input (C
PARASITIC
) are the summation of all other capaci-
tance associated with each input.
During the sample phase when ENC is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to, and track the differential input voltage.
When ENC transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when ENC is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As ENC transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, A
IN+
should be driven with the input signal and A
IN–
should be
connected to 1.6V or V
CM
.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.6V. The V
CM
output pin (Pin
44) may be used to provide the common mode bias level.
V
CM
can be tied directly to the center tap of a transformer
to set the DC input level or as a reference level to an op amp
differential driver circuit. The V
CM
pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2234 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can influence SFDR. At the falling edge of ENC, the sample-
and-hold circuit will connect the 1.6pF sampling capacitor
to the input pin and start the sampling period. The sam-
pling period ends when ENC rises, holding the sampled
input on the sampling capacitor. Ideally the input circuitry
should be fast enough to fully charge the sampling capaci-
tor during the sampling period 1/(2F
ENCODE
); however,
this is not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2234 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with V
CM
, setting the ADC input
25Ω
25Ω25Ω
25Ω
0.1µF
A
IN+
A
IN–
12pF
2.2µF
V
CM
LTC2234
ANALOG
INPUT
0.1µFT1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2234 F03
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
APPLICATIO S I FOR ATIO
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LTC2234
15
2234fa
APPLICATIO S I FOR ATIO
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signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen by
the ADC does not exceed 100Ω for each ADC input. A
disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
Figure 5 shows a single-ended input circuit. The imped-
ance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input. For input frequen-
cies higher than 100MHz, the capacitor may need to be
decreased to prevent excessive signal loss.
For input frequencies above 100MHz the input circuits of
Figure 6, 7 and 8 are recommended. The balun trans-
former gives better high frequency response than a flux
coupled center tapped transformer. The coupling capaci-
tors allow the analog inputs to be DC biased at 1.6V. In
Figure 8 the series inductors are impedance matching
elements that maximize the ADC bandwidth.
Reference Operation
Figure 9 shows the LTC2234 reference circuitry consisting
of a 1.6V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage refer-
ence can be configured for two pin selectable input ranges
of 2V (±1V differential) or 1V (±0.5V differential). Tying the
SENSE pin to V
DD
selects the 2V range; tying the SENSE
pin to V
CM
selects the 1V range.
The 1.6V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.6V reference output, V
CM
. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
Figure 4. Differential Drive with an Amplifier Figure 5. Single-Ended Drive
25Ω
25ΩAIN+
AIN–
12pF
2.2µF
3pF
3pF
VCM
LTC2234
2234 F04
––
++
CM
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
AMPLIFIER = LTC6600-20,
"LT1993", ETC.
25Ω
0.1µF
ANALOG
INPUT
VCM
AIN
+
AIN
–
1k
12pF
2234 F05
2.2µF
1k
25Ω
0.1µF
LTC2234
LTC2234
16
2234fa
The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has four pins: two each of REFHA
and REFHB for the high reference and two each of REFLA
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 250MHz and 500MHz
and REFLB for the low reference. The multiple output pins
are needed to reduce package inductance. Bypass capaci-
tors must be connected as shown in Figure 9.
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
25Ω
25Ω
0.1µF
A
IN+
A
IN–
2pF
2.2µF
V
CM
LTC2234
ANALOG
INPUT
0.1µF
0.1µF
T1
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
2234 F08
4.7nH
4.7nH
APPLICATIO S I FOR ATIO
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Figure 6. Recommended Front End Circuit for
Input Frequencies Between 100MHz and 250MHz
25Ω
25Ω12Ω
12Ω
0.1µF
A
IN+
A
IN–
8pF
2.2µF
V
CM
LTC2234
ANALOG
INPUT
0.1µF
0.1µF
T1
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2234 F06
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 500MHz
25Ω
25Ω
0.1µF
A
IN+
A
IN–
2.2µF
V
CM
LTC2234
ANALOG
INPUT
0.1µF
0.1µF
T1
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2234 F07
VCM
REFHA
REFLB
SENSE
TIE TO VDD FOR 2V RANGE;
TIE TO VCM FOR 1V RANGE;
RANGE = 2 • VSENSE FOR
0.5V < VSENSE < 1V
1.6V
REFLA
REFHB
2.2µF
2.2µF
INTERNAL ADC
HIGH REFERENCE
BUFFER
0.1µF
2234 F09
LTC2234
4Ω
DIFF AMP
1µF
1µF0.1µF
INTERNAL ADC
LOW REFERENCE
1.6V BANDGAP
REFERENCE
1V 0.5V
RANGE
DETECT
AND
CONTROL
Figure 9. Equivalent Reference Circuit
VCM
SENSE
1.6V
0.8V
2.2µF
12k
1µF
12k
2234 F10
LTC2234
Figure 10. 1.6V Range ADC
LTC2234
17
2234fa
APPLICATIO S I FOR ATIO
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V
DD
V
DD
LTC2234
2234 F11
V
DD
ENC–
ENC
+
1.6V BIAS
1.6V BIAS
1:4
0.1µF
CLOCK
INPUT
50Ω
6k
6k
TO INTERNAL
ADC CIRCUITS
Figure 11. Transformer Driven ENC+/ENC–
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise perfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 1.7dB. See the Typical Performance Charac-
teristics section.
Driving the Encode Inputs
The noise performance of the LTC2234 can depend on the
encode signal quality as much as on the analog input. The
ENC
+
/ENC
–
inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a
1.6V bias. The bias resistors set the DC operating point for
transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at both
inputs as common mode noise. The encode inputs have a
common mode range of 1.1V to 2.5V. Each input may be
driven from ground to V
DD
for single-ended drive.
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2234 is 135Msps.
For the ADC to operate properly, the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have
at least 3.5ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise
50% duty cycle is easy with differential sinusoidal drive
using a transformer or using symmetric differential logic
such as PECL or LVDS.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the ENC
+
pin to sample the analog
input. The falling edge of ENC
+
is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 30% to 70% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require one
hundred clock cycles for the PLL to lock onto the input
clock. To use the clock duty cycle stabilizer, the MODE pin
should be connected to 1/3V
DD
or 2/3V
DD
using external
resistors.
The lower limit of the LTC2234 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC2234 is 1Msps.
LTC2234
18
2234fa
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overflow bit.
APPLICATIO S I FOR ATIO
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LTC2234
2234 F13
OV
DD
V
DD
V
DD
0.1µF
43ΩTYPICAL
DATA
OUTPUT
OGND
OV
DD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Figure 13. Digital Output Buffer
Digital Output Buffers
Figure 13 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
DD
and OGND, which
are isolated from the ADC power and ground. The addi-
tional N-channel transistor in the output driver allows
operation down to voltages as low as 0.5V. The internal
resistor in series with the output makes the output appear
as 50Ω to external circuitry and may eliminate the need for
external damping resistors.
2234 F12a
ENC
–
1.6V
V
THRESHOLD
= 1.6V ENC
+
0.1µF
LTC2234
2234 F12b
ENC
–
ENC
+
130Ω
3.3V
3.3V
130Ω
D0
Q0
Q0
MC100LVELT22
LTC2234
83Ω83Ω
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 12b. ENC Drive Using a CMOS to PECL Translator
Table 2. MODE Pin Function
Clock Duty
MODE Pin Output Format Cycle Stablizer
0 Offset Binary Off
1/3V
DD
Offset Binary On
2/3V
DD
2’s Complement On
V
DD
2’s Complement Off
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2234 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. For full speed
operation the capacitive load should be kept under 5pF.
Lower OV
DD
voltages will also help reduce interference
from the digital outputs and improve the SNR.
Data Format
The LTC2234 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. Connecting MODE to GND or
1/3V
DD
selects offset binary output format. Connecting
MODE to 2/3V
DD
or V
DD
selects 2’s complement output
format. An external resistor divider can be used to set the
1/3V
DD
or 2/3V
DD
logic values. Table 2 shows the logic
states for the MODE pin.
Table 1. Output Codes vs Input Voltage
A
IN+
– A
IN–
D9 – D0 D9 – D0
(2V Range) OF (Offset Binary) (2’s Complement)
>+1.000000V 1 11 1111 1111 01 1111 1111
+0.998047V 0 11 1111 1111 01 1111 1111
+0.996094V 0 11 1111 1110 01 1111 1110
+0.001953V 0 10 0000 0001 00 0000 0001
0.000000V 0 10 0000 0000 00 0000 0000
–0.001953V 0 01 1111 1111 11 1111 1111
–0.003906V 0 01 1111 1110 11 1111 1110
–0.998047V 0 00 0000 0001 10 0000 0001
–1.000000V 0 00 0000 0000 10 0000 0000
<–1.000000V 1 00 0000 0000 10 0000 0000
LTC2234
19
2234fa
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Overflow Bit
The converter is either overranged or underranged when
OF outputs a logic high.
Output Clock
The ADC has a delayed version of the ENC
+
input available
as a digital output, CLOCKOUT. The CLOCKOUT pin can be
used to synchronize the converter data to the digital sys-
tem. This is necessary when using a sinusoidal encode. Data
will be updated just after CLOCKOUT rises and can be
latched on the falling edge of CLOCKOUT.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
DD
, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply then OV
DD
should be tied to that same 1.8V supply.
OV
DD
can be powered with any voltage up to 3.6V. OGND
can be powered with any voltage from GND up to 1V and
must be less than OV
DD
. The logic outputs will swing be-
tween OGND and OV
DD
.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF and
CLOCKOUT. The data access and bus relinquish times are
too slow to allow the outputs to be enabled and disabled
during full speed operation. The output Hi-Z state is intended
for use during long periods of inactivity.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to V
DD
and OE to V
DD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to V
DD
and OE
to GND results in nap mode, which typically dissipates
35mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap mode all digital outputs are disabled and enter the
Hi-Z state.
GROUNDING AND BYPASSING
The LTC2234 requires a printed circuit board with a clean
unbroken ground plane. A multilayer board with an inter-
nal ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital signal alongside an
analog signal or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the V
DD
, OV
DD
, V
CM
, REFHA, REFHB, REFLA and REFLB pins
as shown in the block diagram on the front page of this data
sheet. Bypass capacitors must be located as close to the
pins as possible. Of particular importance are the capaci-
tors between REFHA and REFLB and between REFHB and
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recommended. The 2.2µF capacitor between REFHA and
REFLA can be somewhat further away. The traces connect-
ing the pins and bypass capacitors must be kept short and
should be made as wide as possible.
The LTC2234 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
HEAT TRANSFER
Most of the heat generated by the LTC2234 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad should
be soldered to a large grounded pad on the PC board. It is
critical that all ground pins are connected to a ground plane
of sufficient area.
LTC2234
20
2234fa
APPLICATIO S I FOR ATIO
WUUU
Clock Sources for Undersampling
Undersampling raises the bar on the clock source and the
higher the input frequency, the greater the sensitivity to
clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a 3V canned oscillator from vendors such as Saronix or
Vectron can be placed close to the ADC and simply
connected directly to the ADC. If there is any distance to
the ADC, some source termination to reduce ringing that
may occur even over a fraction of an inch is advisable. You
must not allow the clock to overshoot the supplies or
performance will suffer. Do not filter the clock signal with
a narrow band filter unless you have a sinusoidal clock
source, as the rise and fall time artifacts present in typical
digital clock signals will be translated into phase noise.
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a filter
close to the ADC may be beneficial. This filter should be
close to the ADC to both reduce roundtrip reflection times,
as well as reduce the susceptibility of the traces between
the filter and the ADC. If you are sensitive to close-in phase
noise, the power supply for oscillators and any buffers
must be very stable, or propagation delay variation with
supply will translate into phase noise. Even though these
clock sources may be regarded as digital devices, do not
operate them on a digital supply. If your clock is also used
to drive digital devices such as an FPGA, you should locate
the oscillator, and any clock fan-out devices close to the
ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination
at the source to prevent high frequency noise from the
FPGA disturbing the substrate of the clock fan-out device.
If you use an FPGA as a programmable divider, you must
re-time the signal using the original oscillator, and the re-
timing flip-flop as well as the oscillator should be close to
the ADC, and powered with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated
in the waveguides that exist between the layers of multi-
layer PCBs. The differential pairs must be close together,
and distanced from other signals. The differential pair
should be guarded on both sides with copper distanced at
least 3x the distance between the traces, and grounded
with vias no more than 1/4 inch apart.
LTC2234
21
2234fa
GND
GND
GND
VCC
2LE
1LE
2OE
1OE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
GND
VCC
GND
GND
VCC
GND
GND
VCC
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
AIN+
AIN–
REFHA
REFHA
GND
GND
REFLB
REFLB
REFHB
REFHB
REFLA
REFLA
VDD
VDD
VDD
VDD
VDD
ENC+
ENC–
SHDN
OEL
VCM
SENSE
MODE
CLOCKOUT
NC
NC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
OF
OVDD
OVDD
OVDD
OVDD
OGND
OGND
OGND
OGND
GND
GND
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
34
45
39
42
25
48
24
1
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
28
31
21
15
18
10
4
7
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
RN1D 33Ω
RN1C 33Ω
RN1B 33Ω
RN1A 33Ω
RN2D 33Ω
RN2C 33Ω
RN2B 33Ω
RN2A 33Ω
RN3D 33Ω
RN3C 33Ω
RN3B 33Ω
RN3A 33Ω
A0
A1
A2
A3
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
R10
10k
R9
10k
R8
10k
C17
0.1µF
C16
0.1µF
C33
0.1µF
VCC
VCC
NC7SV86P5X
4
4
51
2
1
2
3
5
3
VCC
JP1
R3
33Ω
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
1
2
3
4
13
15
5
6
7
8
9
10
46
47
11
12
14
16
17
18
19
44
43
42
20
21
24
25
26
29
30
31
34
35
36
39
40
41
37
33
28
23
38
32
27
22
48
45
C13
0.1µF
C12
0.1µF
C10
0.1µF
C11
33pF
C15
2.2µF
C7
2.2µF
C6
0.1µF
C9
0.1µF
C5
1µF
C8
1µF
VCC
C21
0.1µF
C20
0.1µF
C19
0.1µF
C18
0.1µF
C24
0.1µF
C22
0.1µF
VDD
VDD
VDD
VCM
EXT
REF
VDD
VCM
EXT
REF
R12
1k
R13
1k
R14
1k
2/3VDD
1/3VDD
GND
JP4
MODE
JP3
SENSE
CLK
CLK
VDD
VDD
SHDN
JP2
VCC
C4
0.1µF
C1
0.1µF
C3
0.1µF
R5
50Ω
R2
24.9Ω
R4
24.9Ω
R6*
R1*
C2*
VCM
ANALOG
INPUT
T1*
J1
R19
OPT
R17
105k
C32
0.1µF
C25
4.7µF
C31
0.1µF
C30
0.1µF
C29
0.1µF
VCC
OUT
ADJ
GND
BYP
IN
GND
GND
SHDN
R18
100k
1
2
3
4
8
7
6
5
C26
0.1µF
C23
0.1µF
R15
100Ω
R16
100Ω
ENCODE
INPUT
CLK
CLK
T2
ETC1-1T
J3
VDD
VDD
3.3V
PWR
GND
GND
C27
10µF
6.3V
C28
0.01µF
VCC
VDD
GND
49
PI74VCX16373A
24LC025
3201S-40G1
NC7SV86P5X
C34
1µF
2234 AI01
U1 LTC2234*
CLOCKOUT CLOCKOUT
U3
U2
U6 LT1763
U4
U5
APPLICATIO S I FOR ATIO
WUUU
Evaluation Circuit Schematic of the LTC2234
Assembly Type U1 R1, R6 C2 T1
DC751A-I LTC2224IUK 24.9Ω12pF ETC1-1T
DC751A-J LTC2234IUK 24.9Ω12pF ETC1-1T
DC751A-K LTC2224IUK 12.4Ω8.2pF ETC1-1-13
DC751A-L LTC2234IUK 12.4Ω8.2pF ETC1-1-13
*Version Type
LTC2234
22
2234fa
APPLICATIO S I FOR ATIO
WUUU
Silkscreen Top
Layer 1 Component Side Layer 2 GND Plane
Layer 3 Power Plane Layer 4 Bottom Side
LTC2234
23
2234fa
PACKAGE DESCRIPTIO
U
7.00 ± 0.10
(4 SIDES)
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1
CHAMFER
0.40 ± 0.10
4847
1
2
BOTTOM VIEW—EXPOSED PAD
5.15 ± 0.10
(4-SIDES)
0.75 ± 0.05 R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UK48) QFN 1103
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
5.15 ±0.05
(4 SIDES) 6.10 ±0.05 7.50 ±0.05
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220
VARIATION (WKKD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT
INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT
EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON
THE TOP AND BOTTOM OF PACKAGE
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-1704)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2234
24
2234fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
LT 0106 REV A • PRINTED IN USA
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