1/39July 2003
M29F800DT
M29F800DB
8 Mbit (1Mb x8 or 512Kb x16, Boot Block)
5V S uppl y Fl ash Memory
FEATURES SUM M ARY
SUPPLY VOLTAG E
–V
CC = 5V ±10% for Program, Erase and Read
ACCESS TIME: 55, 70, 90ns
PRO GRAMMIN G TIME
10µs per Byte/Word typical
19 MEMORY BLOCKS
1 Boot Block (Top or Bottom Locat ion)
2 Parameter and 16 Main Blocks
PROGRAM/ERASE CON TROLLER
Embedded Byt e/Word Program algorithms
ERASE SUSPEND and RESUM E MOD ES
Read and Program another Block during
Erase Su spend
UNLOCK BYPASS PROGRAM COMM AND
Fas ter Production/Batc h Prog ramm ing
TEMPORARY BLOCK UNPROTECTION
MODE
COMMON FLASH INTERFACE
64 bit Security Code
LOW POWER CONSUM PTION
Standby and Autom atic Standby
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIG NATURE
Manufacturer Code: 0020h
Top Device Code M29 F800D T: 22ECh
Bottom Device Code M2 9F800 DB: 2258h
Figure 1. Packages
TSOP48 (N)
12 x 20mm
SO44 (M)
M29F800DT, M29F80 0DB
2/39
TABLE OF CONT ENTS
SUMMARY DESCRIPT ION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic D iagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Si gnal Nam es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TSOP Connec tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SIGNA L DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Address In puts (A0-A18 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
D ata Inputs/Ou tputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
D ata Inputs/Ou tputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
D ata Input/Output or Address Input (DQ15A-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip En able (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Out put Enabl e (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
W rite Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
R eady/Busy Out put (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Byte/W ord Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
V
CC Supply Volt age. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
BUS OPERAT IONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Autom at ic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Special Bu s Ope ratio ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ele ctronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Bus Operations, BYTE = V IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
R ead/Res et Comm and.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Auto Se lect Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Unlock Bypass C ommand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unlock Bypass R eset Com mand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
C hip Erase Comm and. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Erase S uspend Com ma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3/39
M29F800DT, M29F800DB
R ead CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Protect and Ch ip Unprotect Commands.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Commands, 16-bit mode, BYT E = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Commands, 8-bit mode, B YTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Program , Erase Times and Program, Erase Enduranc e Cycles . . . . . . . . . . . . . . . . . . . . 15
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Toggl e Bit (DQ6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Alternative Toggle Bit (DQ2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Status Reg ister Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Data To ggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9
Table 9. Operating and AC Measurement Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. AC Measureme nt I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. AC Measurement Load Circui t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0
Figure 11. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1
Figure 12. Write A C Wav eforms, W rite Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Writ e AC Waveforms, Chip En able Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. Write AC Characteristics, Ch ip Ena ble Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Reset/Block T emporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. Reset/Block T emporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. SO44 - 44 lead Plastic Sm all Outline, 525 mils body width, Package Outlin e . . . . . . . . 25
Table 16. SO44 – 44 lead Plastic Small Outline , 525 mils body width, Package Mechani ca l Data 25
Figure 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 26
Table 17. TSOP48 – 48 lead Plast ic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18. Ordering Information Schem e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19. Top Boot Block Ad dresses, M29 F800DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 20. Bottom Boot Block Addresses, M29F800DB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
M29F800DT, M29F80 0DB
4/39
APPENDIX B. COMMON FLASH INTERFACE (CF I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21. Query Structure Ove rview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 22. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 23. CFI Q uery System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 24. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 25. Pri mary Al gorithm -Spe cific Extende d Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 25. Pri mary Al gorithm -Spe cific Extende d Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
APPENDIX C. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
In-System Techn ique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 27. Programmer Techni que Bu s Operations , BYTE = V IH or VIL . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. Progra mmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 18. Programmer Equ ipment Chip Un protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 19. In-System Equ ipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 20. In-System Equ ipment Chip Unprote ct Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 28. Document Revision Hi story. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5/39
M29F800DT, M29F800DB
SUMMARY DESCRIPTION
The M29F800D is a 8 Mbit (1Mb x8 or 512Kb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single low voltage (5V) supply. On
power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or
EPROM.
The memory is divided into blocks that can be
erased independently so it is pos sible to preserv e
valid data while old dat a is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. P rogram and Eras e com m ands are wri t-
ten to the Com mand Interface of t he memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of al l of the special operations that are
required to update the memory contents.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Figures 5 and 6, Block Addresses.
The first or la st 64 Kbytes h ave been divide d into
four additional blocks. The 16 Kbyte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 Kbyte Parameter
Blocks can be us ed for parameter st orage and the
remaining 32K is a small Main Block where the ap-
plication may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic .
The memory is offered in SO44 a nd TSOP4 8 (12
x 20mm ) pac kages. T he memory is supplied with
all the bits erased (set to ’1’).
Figure 2. Logic Diagram Tabl e 1. Signal Names
AI06148B
19
A0-A18
W
DQ0-DQ14
VCC
M29F800DT
M29F800DB
E
VSS
15
G
RP
DQ15A–1
RB
BYTE
A0-A18 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
EChip Enable
GOutput Enable
WWrite Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
(not available on SO44 package)
BYTE Byte/Word Organization Select
VCC Supply Voltage
VSS Ground
NC Not Connected Internally
M29F800DT, M29F80 0DB
6/39
Figu re 3. SO C onnecti on s Figu re 4. TSOP C onnec tion s
G
DQ0
DQ8
A3
A0
E
VSS
A2
A1
A13
VSS
A14
A15
DQ7
A12
A16
BYTE
DQ15A–1
DQ5DQ2
DQ3 VCC
DQ11 DQ4
DQ14
A9
W
RB
A4
RP
A7
AI06150
M29F800DT
M29F800DB
8
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
2322
20
19
18
17DQ1
DQ9
A6
A5
DQ6
DQ13
44
39
38
37
36
35
34
33
A11
A10
DQ10 21 DQ12
40
43
1
42
41
A17 A8
A18
DQ3
DQ9
DQ2
A6 DQ0
W
A3
RB
DQ6
A8
A9 DQ13
A17
A10 DQ14
A2
DQ12
DQ10
DQ15A–1
VCC
DQ4
DQ5
A7
DQ7
NC
NC
AI06149
M29F800DT
M29F800DB
12
1
13
24 25
36
37
48
DQ8
NC
NC
A1
A18
A4
A5
DQ1
DQ11
G
A12
A13
A16
A11
BYTE
A15
A14 VSS
E
A0
RP
VSS
7/39
M29F800DT, M29F800DB
Figure 5. Block Add resse s (x8)
Note: Also see A ppendix A, T ables 19 and 20 for a f ul l l is t i ng of the Bl ock Add resses .
AI06152
16 KByte
FFFFFh
FC000h
64 KByte
1FFFFh
10000h
64 KByte
0FFFFh
00000h
M29F800DT
Top Boot Block Addresses (x8)
32 KByte
F7FFFh
F0000h
64 KByte
E0000h
EFFFFh
Total of 15
64 KByte Blocks
16 KByte
FFFFFh
F0000h 64 KByte
64 KByte
03FFFh
00000h
M29F800DB
Bottom Boot Block Addresses (x8)
32 KByte
EFFFFh
1FFFFh 64 KByte
E0000h
10000h
Total of 15
64 KByte Blocks
0FFFFh
08000h
8 KByte
8 KByte
FBFFFh
FA000h
F9FFFh
F8000h
8 KByte
8 KByte
07FFFh
06000h
05FFFh
04000h
M29F800DT, M29F80 0DB
8/39
Figure 6. Block Addresses (x16)
Note: Also see A ppendix A, T ables 19 and 20 for a f ul l l is t i ng of the Bl ock Add resses .
AI06153
8 KWord
7FFFFh
7E000h
32 KWord
0FFFFh
08000h
32 KWord
07FFFh
00000h
M29F800DT
Top Boot Block Addresses (x16)
16 KWord
7BFFFh
78000h
32 KWord
70000h
77FFFh
Total of 15
32 KWord Blocks
8 KWord
7FFFFh
78000h 32 KWord
32 KWord
01FFFh
00000h
M29F800DB
Bottom Boot Block Addresses (x16)
16 KWord
77FFFh
0FFFFh 32 KWord
70000h
08000h
Total of 15
32 KWord Blocks
07FFFh
04000h
4 KWord
4 KWord
7DFFFh
7D000h
7CFFFh
7C000h
4 KWord
4 KWord
03FFFh
03000h
02FFFh
02000h
9/39
M29F800DT, M29F800DB
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diag ram, and T able 1, Sign al
Names, for a brief overview of the s ignals connect -
ed to this device.
Address Inputs (A0-A18). The Address Inputs
select the cell s in the memory arra y to access dur-
ing Bus Read operations. During Bus Writ e opera-
tions they control the commands sent to the
Comman d Interface of the internal stat e ma chine.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Output s (DQ8-DQ14). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operati on when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bit s. When reading t he Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low wil l select t he LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the t ext consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to inc lude this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memor y, allowing Bus Read and Bus Wr ite op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
ma nd Inte r face.
Reset/Block Temporary Unprotect ( RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardwar e Reset to the memory or
to temporarily u nprotect al l Block s that have been
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, V IH, the memory will be read y for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Ready/ Busy
Output section, Table 15 and Figure 14, Reset/
Temporary Unprot ect AC Characte ristics for more
details.
Holding RP at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V OL. Read y/Busy is high-im-
pedance during Read mode, Auto Select mode
and Erase Suspend m ode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes h igh-impeda nc e. See Tabl e 15 and Figure
14, Reset/Temporary Unprotect AC Characteris-
tics.
The use of an open-drain out put allows the Ready/
Busy pins from several memor ies to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch bet ween t he 8-bit and 16-bit Bus m odes of
the memory. When Byte/Word Organization Se-
lect is Low, VIL, the memory is in 8-bit mode, when
it is High , V IH, the memo ry is in 16-bi t mode .
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is dis abled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevent s Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being alt ered will be invalid.
A 0.1µF capacitor should be connected between
the V CC Supply Voltage pin and the VSS Ground
pin to decoupl e the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operat ions, ICC3.
VSS Ground. The VSS Ground is the reference for
all voltage measureme nts.
M29F800DT, M29F80 0DB
10/39
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Wri te, Out-
put Disable, Standby and Automatic Standby. See
Tables 2 and 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chi p Enable
or Write Enable are ignored by the memory and do
not affec t bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desi red address on the Address
Inputs, appl ying a Low s ig nal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Input s/Ou tputs will outp ut the
value, see Figure 11, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desire d address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Dat a Input s/Outpu ts a re latched by the Com -
mand Interface on the rising edge of Chip Enab le
or Write Enable, whichever occurs first. Output En-
able must remai n High, VIH, during the whole Bus
Write operat ion. See Figures 12 and 13, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing require-
ments.
Outp ut Disable . The Data Inputs/Outputs are in
the high impeda nce state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For t he Standby current
level see Table 11, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations un-
til t he operat ion com pletes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operati ons. Additional bus opera-
tions can be performed to read t he Electron ic Sig-
nature and also to apply and remove Block
Protection. These bus operations are intended for
use by programming eq uipm ent a nd are not usu-
ally used in applications. They require VID to be
applied to some pins.
Electronic Sign atur e. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These co des can be re ad by app lying the si gnals
listed in Tables 2 and 3, Bus Operations.
Block Protection and Blocks Unprotection.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. Bloc k Protec t and Chi p Unprot ect operat ions
are desc ri bed i n Appendix C.
Table 2. Bus Operations, BYTE = VIL
No te: X = VIL or VIH.
Operation E G W Address Inputs
DQ15A–1, A0-A18 Data Inputs/Outputs
DQ14-DQ8 DQ7-DQ0
Bus Read VIL VIL VIH Cell Address Hi-Z Data Output
Bus Write VIL VIH VIL Command Address Hi-Z Data Input
Output Disable X VIH VIH X Hi-Z Hi-Z
Standby VIH X X X Hi-Z Hi-Z
Read Manufacturer
Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH Hi-Z 20h
Read Device Code VIL VIL VIH A0 = V IH, A1 = VIL, A9 = V ID,
Others VIL or VIH Hi-Z ECh (M29F800DT)
58h (M29F800DB)
11/39
M29F800DT, M29F800DB
Table 3. Bus Operations, BYTE = VIH
No te: X = VIL or VIH.
COMMAND INTERFACE
All Bus Write operations t o the memory are in ter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a vali d sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes de-
pending on whether the mem ory is in 16-bit or 8-
bit mode. See e ither Table 4, or 5, depending on
the configuration that is being used, for a summary
of the c om m ands.
Read/Reset Comm and. The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless other-
wise s tated. It also resets t he errors in the S tatus
Register. Either one or three Bus Write operations
can be used to is sue the Read/Reset command.
The Read/Reset Command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. Once the program or eras e o peration
has started the Read/Res et comm and is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select com-
mand i s us ed to read the Man ufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until a Read/Reset
command is issued. Read CFI Query and Read/
Reset commands are accepted in Auto Select
mode, all other commands are ignored .
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A 0 = VIL and A1 = VIL. The other address bits
may be set to either VIL or VIH. T he Ma nufa cturer
Code for STMicroelectronics is 0020h.
The Device Code can b e read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to eithe r VIL or VIH.
Th e Bloc k Protecti on Status of each block can b e
read using a Bus Read operation with A0 = VIL,
A1 = VIH, and A 12-A1 8 s p ecifyi ng th e addr ess of
th e block. The oth er address bits may be set to ei-
ther VIL or VIH. If th e addr ess ed bloc k is p rot ecte d
then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
Progra m Command . The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data in the internal
state machine and starts the Program/Erase Con-
troller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the me mory will ig-
nore all co mmands. I t is not poss ible t o issue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
Operation E G W Address Inputs
A0-A18 Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Bus Read VIL VIL VIH Cell Address Data Output
Bus Write VIL VIH VIL Command Address Data Input
Output Disable X VIH VIH X Hi-Z
Standby VIH X X X Hi-Z
Read Manufacturer
Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH 0020h
Read Device Code VIL VIL VIH A0 = V IH, A1 = VIL, A9 = V ID,
Others VIL or VIH 22ECh (M29F800DT)
2258h (M29F800DB)
M29F800DT, M29F80 0DB
12/39
memory will continue to output the Status Regis-
ter. A Read/Reset command must be i ssued to re-
set the error condition and return to Read mode.
Note that t he Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Comman d. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program c ommand to program the memo-
ry. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unlock Bypass comm and.
Once the Unlock Bypass command has been is-
sued the memory will only accept the Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory can be read as i f in
Read mode.
Unlock Bypass Prog ram Comm an d. The Un-
lock Bypass Program command can be used to
program one address in memory at a time. The
command requires two Bus Write ope ra tions, the
final write operation latches the address and data
in the internal state machine and starts the Pro-
gram/Erase Controller.
The Program operation using the Unlock Bypass
Program c ommand behaves identically to the Pro-
gram operation using the Program command. A
protected block cannot be program m ed; the oper-
ation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, w hich l eaves the de vice in Unlo ck By-
pass Mode. See the Program command for details
on the behavior.
Unlock Bypass Reset Comman d. The Unlock
Bypass Re se t comm and can be used t o return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset
command does not exit from Unlock Bypass
Mode.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks a re p rote cted the Chi p Era se o perat i on ap-
pears to start but will terminate within about 100µs,
leaving the data unchange d. No error condit ion is
given when protected blocks are ignored.
During the erase operation the memory wi ll ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has com pleted t he
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be i ssued to re-
set the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Wr ite operation using the addres s of the
additional block. The Bl ock Erase operation st arts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer r estarts when an additional block is select ed.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are pro tected
the Block Erase operation appears to s tart but will
terminate within about 100µs, l eaving the data un-
changed. No error condition is given when protect-
ed blocks are ignored.
During the Blo ck Erase ope ra tion the me mory will
ignore all commands except the Erase Suspend
co mmand. Typical b lock e ra se tim es are given in
Table 6. All Bus Read operations during the Block
Erase op eration will ou t pu t the Status R eg i st er o n
the Data Inputs/Outputs. See the section on the
Status Regist er for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be i ssued to re-
set the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selec ted blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Comm and. The Erase Suspend
Comman d m ay be used to temporari ly sus pend a
Block Erase operation and return the memory to
13/39
M29F800DT, M29F800DB
Read mode. The command requires one Bus
Write operation.
The Prog ram/Eras e Controlle r will sus pend within
the Erase Suspend Latency Time (refer t o Table 6
for va lue) of the Erase Suspend Command being
issued. Once the Program/Erase Controller has
stopped the memory will be set t o Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is susp ended i mmedi ately and wi ll start im-
mediately when the Erase Resume Command is
issued. It is not possible to select any further
blocks to erase after the Erase Resume.
During Erase Suspend it is p ossi ble to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protec ted block o r in the suspen ded
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error condi tion is gi ven. Read-
ing from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be i ssued to return the device to Read Array
mode before the Resume command will be ac-
cepted.
Erase Resum e Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
Read CFI Query Comman d. The Read CFI
Query Command is used to read data from the
Common Flash Interface (CFI) Memory Area. This
command is valid when the device is ready to read
the array data or when the device is in autoselect-
ed mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is-
sued subsequen t Bus Read ope rations re ad from
the Common Flash Interface Memory Area. The
Read/Reset command must be issued to return
the device to Re ad Array mode. See Appendix B,
Tables 21, 22, 23, 24, 25 and for details on the in-
formation contained in the Common Flash Inter-
face (CFI) memory area.
Block Protect and
Chip Unprotect Commands.
Each block can be separately protected against
accidental Progra m or E rase. The whol e c hip can
be unprotect ed to allow the data inside the blo cks
to be changed.
Block Protect and Chip Unprotect operations are
described in Appendix C.
M29F800DT, M29F80 0DB
14/39
Table 4. Commands, 16- bit mode, BYTE = VIH
Note: X Don’t Care, PA Program Address, PD Program Da ta, BA An y addre ss in the Block.
All values in the tabl e are in he xadeci m al .
Th e Com ma nd In terf ace o nl y us es A –1, A0-A 10 a nd DQ 0-DQ7 t o ver ify t he com man ds; A1 1-A 18, DQ 8-DQ1 4 a nd DQ 15 ar e Don’ t
Care. DQ15A–1 i s A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset 1X F0
3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program 2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Read CFI Query 1 55 98
15/39
M29F800DT, M29F800DB
Table 5. Commands, 8-bi t mode, BYTE = VIL
Note: X Don’t Care, PA Program Address, PD Program Da ta, BA An y addre ss in the Block.
All values in the tabl e are in he xadeci m al .
Th e Com ma nd In terf ace o nl y us es A –1, A0-A 10 a nd DQ 0-DQ7 t o ver ify t he com man ds; A1 1-A 18, DQ 8-DQ1 4 a nd DQ 15 ar e Don’ t
Care. DQ15A–1 i s A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Table 6. Program , Erase Times and Progra m , Erase Endu ran ce Cycles
No te : 1. Typ i cal values mea sured at room tempera tu re and no minal v ol tages.
2. Sampled, but not 100% tested.
3. Max imum valu e measu red at worst case conditions for both tem pera ture and V CC aft er 100 ,0 0 progr am / erase cy cl es.
4. Max imum valu e measu red at worst case conditions for both tem pera ture and V CC.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset 1X F0
3 AAA AA 555 55 X F0
Auto Select 3 AAA AA 555 55 AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass
Program 2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Read CFI Query 1 AA 98
Parameter Min Typ (1, 2) Max(2) Unit
Chip Erase 12 60(3) s
Block Erase (64 Kbytes) 0.8 6(4) s
Erase Suspend Latency Time 30 µs
Program (Byte or Word) 10 200(3) µs
Chip Program (Byte by Byte) 12 60(3) s
Chip Program (Word by Word) 6 30(3) s
Program/Erase Cycles (per Block) 100,000 cycles
Data Retention 20 years
M29F800DT, M29F80 0DB
16/39
STATUS REGIST ER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus-
pend when an address within a block being erased
is acce ssed .
The bits in the Status Register are s um marized in
Table 7, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read oper ations from t he ad-
dress just programmed output DQ7, not its com-
plement.
During Erase ope rations the Data Po lling Bit out-
puts ’0’, the complement of the erased state of
DQ7. Aft er s uc cessful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change f rom a ’0’ to a ’1’ when the Program/Erase
Controller has suspe nded the Erase operation.
Figure 7, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A V alid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit c an be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes f rom ’0 ’ to ’ 1’ to ’ 0’, et c., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
If any attempt is ma de to erase a protected bl ock,
the o peration is aborted, no error i s sig nalled and
DQ6 toggles for approximately 100µs. If any at-
tempt is made to program a protected block or a
suspended b lock, the operatio n is aborted, no er-
ror is signalled and DQ6 toggles for approxi mately
1µs.
Figure 8 , Data Toggle Flowchart, g ives an exam-
ple of how to use the Data Toggle Bit .
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Erro r Bit is set to ’1’ wh en a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Rea d/Re se t comm and must be iss ued
before other command s a re issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that t he Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dres s w ill s how the bit is s ti ll ‘0’. On e of the E r as e
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the E rase Ti mer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional block s to be eras ed
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes fro m ’0’ to ’1’ to ’0’, etc., with
successive Bus Re ad operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will ou tput
the memory cell data as i f in Read mode.
After an Erase operation that c auses t he Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or bl ocks have caused t he er-
ror. The Altern ative Toggle Bit changes from ’0’ t o
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
17/39
M29F800DT, M29F800DB
Table 7. Status Register Bits
No te : Unspecified da ta bits should be i gnore d.
Figu re 7. Da ta Po lli ng Fl owch a rt Fi gure 8. Dat a Toggle Fl owchart
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Any Address DQ7 Toggle 0 ––0
Program During Erase
Suspend Any Address DQ7 Toggle 0 0
Program Error Any Address DQ7 Toggle 1 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0
Block Erase before
timeout Erasing Block 0 Toggle 0 0 Toggle 0
Non-Erasing Block 0 Toggle 0 0 No Toggle 0
Block Erase Erasing Block 0 Toggle 0 1 Toggle 0
Non-Erasing Block 0 Toggle 0 1 No Toggle 0
Erase Suspend Erasing Block 1 No Toggle 0 Toggle 1
Non-Erasing Block Data read as normal 1
Erase Error Good Block Address 0 Toggle 1 1 No Toggle 0
Faulty Block Address 0 Toggle 1 1 Toggle 0
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
at VALID ADDRESS
FAIL PASS
AI03598
DQ7
=
DATA YES
NO
YES
NO
DQ5
= 1
DQ7
=
DATA YES
NO
READ DQ6
START
READ DQ6
TWICE
FAIL PASS
AI01370C
DQ6
=
TOGGLE NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
=
TOGGLE
READ
DQ5 & DQ6
M29F800DT, M29F80 0DB
18/39
MAX I MUM R A TI N G
Stressing the device ab ove t he rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above t hose indicat -
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute Maximum Ratings
Note: 1. Minim um voltage may under shoot t o –2V during transitio n and for less than 20ns duri ng trans i tions.
2. Max imum voltage may overshoot to V CC +2V duri ng trans i tion an d fo r l ess tha n 20ns duri ng transitions.
Symbol Parameter Min Max Unit
TBIAS Temperature Under Bias –50 125 °C
TSTG Storage Temperature –65 150 °C
VIO Input or Output Voltage (1,2) –0.6 VCC +0.6 V
VCC Supply Voltage –0.6 6 V
VID Identification Voltage –0.6 13.5 V
19/39
M29F800DT, M29F800DB
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, a nd the DC and AC characteris-
tics of the device. The parameters in the D C and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 9, Operating and
AC Measurement Conditions. Designers should
check t hat the operating cond itions in their circuit
match the operating conditions when relying on
the quot ed parameters.
Table 9. Operating and AC Measurem en t Conditions
Figure 9. AC Measurement I/O Wavefo rm Figure 10. AC Measure ment Lo ad Circuit
Table 10. Device Capacitance
No te : Sam pled o n l y, not 100% test ed.
Parameter
M29F800D
Unit55 70/ 90
Min Max Min Max
VCC Supply Voltage 4.5 5.5 4.5 5.5 V
Ambient Operating Temperature (range 1) 0 70 0 70 °C
Ambient Operating Temperature (range 3) –40 125 –40 125 °C
Ambient Operating Temperature (range 6) –40 85 –40 85 °C
Load Capacitance (CL)30 100 pF
Input Rise and Fall Times 10 10 ns
Input Pulse Voltages 0 to 3 0.45 to 2.4 V
Input and Output Timing Ref. Voltages 1.5 0.8 and 2.0 V
AI05276
3V
High Speed (55ns)
0V
1.5V
2.4V
Standard (70, 90ns)
0.45V
2.0V
0.8V
AI05277
1.3V
OUT
CL
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
VCC
0.1µF
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 6pF
C
OUT Output Capacitance VOUT = 0V 12 pF
M29F800DT, M29F80 0DB
20/39
Table 11. DC Characteristics
Not e: 1. Sampled only, not 100% tested.
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V VIN VCC ±1 µA
ILO Output Leakage Current 0V VOUT VCC ±1 µA
ICC1 Supply Current (Read) E = VIL, G = VIH,
f = 6MHz 20 mA
ICC2 Supply Current (Standby) TTL E = VIH 2mA
I
CC3 Supply Current (Standby) CMOS E = VCC ±0.2V,
RP = VCC ±0.2V 150 µA
ICC4 (1) Supply Current (Program/Erase) Program/Erase
Controller active 20 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 2V
CC + 0.5 V
VOL Output Low Voltage IOL = 5.8mA 0.45 V
VOH Output High Voltage TTL CMOS IOH = –2.5mA 2.4 V
VID Identification Voltage 11.5 12.5 V
IID Identification Current A9 = VID 100 µA
VLKO Program/Erase Lockout Supply
Voltage 3.2 4.2 V
21/39
M29F800DT, M29F800DB
Figure 11. Read Mode AC Waveforms
Table 12. Read AC Characteristi cs
Not e: 1. Sampled only, not 100% tested.
Symbol Alt Parameter Test Condition M29F800D Unit
55 70/ 90
tAVAV tRC Address Valid to Next Address Valid E = VIL,
G = VIL Min 55 70 ns
tAVQV tACC Address Valid to Output Valid E = VIL,
G = VIL Max 55 70 ns
tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns
tELQV tCE Chip Enable Low to Output Valid G = VIL Max 55 70 ns
tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns
tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 30 ns
tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 18 20 ns
tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 18 20 ns
tEHQX
tGHQX
tAXQX tOH Chip Enable, Output Enable or Address
Transition to Output Transition Min 0 0 ns
tELBL
tELBH tELFL
tELFH Chip Enable to BYTE Low or High Max 5 5 ns
tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 30 ns
tBHQV tFHQV BYTE High to Output Valid Max 30 40 ns
AI06154
tAVAV
tAVQV tAXQX
tELQX tEHQZ
tGLQV
tGLQX tGHQX
VALID
A0-A18/
A–1
G
DQ0-DQ7/
DQ8-DQ15
E
tELQV tEHQX
tGHQZ
VALID
tBHQV
tELBL/tELBH tBLQZ
BYTE
M29F800DT, M29F80 0DB
22/39
Figure 12. Write AC Waveforms, Wr ite Enable Controlled
Table 13. Write AC Characteristics, Write Enable Controlle d
Not e: 1. Sampled only, not 100% tested.
Symbol Alt Parameter M29F800D Unit
55 70/ 90
tAVAV tWC Address Valid to Next Address Valid Min 55 70 ns
tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns
tWLWH tWP Write Enable Low to Write Enable High Min 45 45 ns
tDVWH tDS Input Valid to Write Enable High Min 45 45 ns
tWHDX tDH Write Enable High to Input Transition Min 0 0 ns
tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns
tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 ns
tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns
tWLAX tAH Write Enable Low to Address Transition Min 45 45 ns
tGHWL Output Enable High to Write Enable Low Min 0 0 ns
tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns
tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns
tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs
AI06155
E
G
W
A0-A18/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
VCC
tVCHEL
tWHEH
tWHWL
tELWL
tAVWL
tWHGL
tWLAX
tWHDX
tAVAV
tDVWH
tWLWHtGHWL
RB
tWHRL
23/39
M29F800DT, M29F800DB
Figure 13. Write AC Wavefo rms, Chip Enable Controlled
Table 14. Wri te AC Characteristics, Chip Enable Controlled
Not e: 1. Sampled only, not 100% tested.
Symbol Alt Parameter M29F800D Unit
55 70/ 90
tAVAV tWC Address Valid to Next Address Valid Min 55 70 ns
tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns
tELEH tCP Chip Enable Low to Chip Enable High Min 45 45 ns
tDVEH tDS Input Valid to Chip Enable High Min 45 45 ns
tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns
tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns
tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 20 ns
tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns
tELAX tAH Chip Enable Low to Address Transition Min 45 45 ns
tGHEL Output Enable High Chip Enable Low Min 0 0 ns
tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns
tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns
tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs
AI06156
E
G
W
A0-A18/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
VCC
tVCHWL
tEHWH
tEHEL
tWLEL
tAVEL
tEHGL
tELAX
tEHDX
tAVAV
tDVEH
tELEHtGHEL
RB
tEHRL
M29F800DT, M29F80 0DB
24/39
Figure 14. Reset/Block Tem porary Unp rotec t AC Wavefo rms
Table 15. Reset/Block Temporary Unprotect AC Characteri stics
Not e: 1. Sampled only, not 100% tested.
Symbol Alt Parameter M29F800D Unit
55 70/ 90
tPHWL (1)
tPHEL
tPHGL (1) tRH RP High to Write Enable Low, Chip Enable Low,
Output Enable Low Min 50 50 ns
tRHWL (1)
tRHEL (1)
tRHGL (1) tRB RB High to Write Enable Low, Chip Enable Low,
Output Enable Low Min 0 0 ns
tPLPX tRP RP Pulse Width Min 500 500 ns
tPLYH (1) tREADY RP Low to Read Mode Max 10 10 µs
tPHPHH (1 ) tVIDR RP Rise Time to VID Min 500 500 ns
AI06870
RB
W,
RP tPLPX
tPHWL, tPHEL, tPHGL
tPLYH
tPHPHH
E, G
tRHWL, tRHEL, tRHGL
25/39
M29F800DT, M29F800DB
PACKAGE MECHANICAL
Figure 15. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outl ine
Not e: Drawing is not to scale.
Table 16. SO44 – 44 lead Plastic Smal l Outline, 525 mil s body width, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 2.80 0.1102
A1 0.10 0.0039
A2 2.30 2.20 2.40 0.0906 0.0866 0.0945
b 0.40 0.35 0.50 0.0157 0.0138 0.0197
C 0.15 0.10 0.20 0.0059 0.0039 0.0079
CP 0.08 0.0030
D 28.20 28.00 28.40 1.1102 1.1024 1.1181
E 13.30 13.20 13.50 0.5236 0.5197 0.5315
EH 16.00 15.75 16.25 0.6299 0.6201 0.6398
e1.27 0.0500
L 0.80 0.0315
a8 8
N44 44
SO-d
E
N
D
C
LA1 α
EH
A
1
eCP
b
A2
M29F800DT, M29F80 0DB
26/39
Figure 16. TSOP48 – 48 lead Plastic Thin Small Ou tline, 12 x 20mm, Package Outline
Not e: Drawing is not to scale.
Table 17. TS OP 48 – 48 lead Plastic Thin Sma ll Outline, 12 x 20mm, Package Me chan ical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.100 0.050 0.150 0.0039 0.0020 0.0059
A2 1.000 0.950 1.050 0.0394 0.0374 0.0413
B 0.220 0.170 0.270 0.0087 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.080 0.0031
D1 12.000 11.900 12.100 0.4724 0.4685 0.4764
E 20.000 19.800 20.200 0.7874 0.7795 0.7953
E1 18.400 18.300 18.500 0.7244 0.7205 0.7283
e 0.500 0.0197
L 0.600 0.500 0.700 0.0236 0.0197 0.0276
L1 0.800 0.0315
α305305
TSOP-G
B
e
DIE
C
LA1 α
E1
E
A
A2
1
24
48
25
D1
L1
CP
27/39
M29F800DT, M29F800DB
PAR T NUMBERING
Table 18. Ordering Information Scheme
Devices are shipped from the fac tory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Example: M29F800DB 55 N 6 T
Device Type
M29
Operating Voltage
F = VCC = 5V ± 10%
Device Function
800D = 8 Mbit (x8/x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
55 = 55 ns
70 = 70 ns
90 = 90 ns
Package
M = SO44
N = TSOP48: 12 x 20 mm
Temperature Range
1 = 0 to 70 °C
3 = –40 to 125°C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing
M29F800DT, M29F80 0DB
28/39
APPENDIX A. BLOCK ADDRESS TABLE
Table 19. Top Boot Block Addresse s,
M29F800DT Tabl e 20. Bottom Boot Block Addresses,
M29F800DB
#Size
(Kbytes) Add ress R ange
(x8) Address Range
(x16)
18 16 FC000h-FFFFFh 7E000h-7FFFFh
17 8 FA000h-FBFFFh 7D000h-7DFFFh
16 8 F8000h-F9FFFh 7C000h-7CFFFh
15 32 F0000h-F7FFFh 78000h-7BFFFh
14 64 E0000h-EFFFFh 70000h-77FFFh
13 64 D0000h-DFFFFh 68000h-6FFFFh
12 64 C0000h-CFFFFh 60000h-67FFFh
11 64 B0000h-BFFFFh 58000h-5FFFFh
10 64 A0000h-AFFFFh 50000h-57FFFh
9 64 90000h-9FFFFh 48000h-4FFFFh
8 64 80000h-8FFFFh 40000h-47FFFh
7 64 70000h-7FFFFh 38000h-3FFFFh
6 64 60000h-6FFFFh 30000h-37FFFh
5 64 50000h-5FFFFh 28000h-2FFFFh
4 64 40000h-4FFFFh 20000h-27FFFh
3 64 30000h-3FFFFh 18000h-1FFFFh
2 64 20000h-2FFFFh 10000h-17FFFh
1 64 10000h-1FFFFh 08000h-0FFFFh
0 64 00000h-0FFFFh 00000h-07FFFh
#Size
(Kbytes) Address Rang e
(x8) Address Range
(x16)
18 64 F0000h-FFFFFh 78000h-7FFFFh
17 64 E0000h-EFFFFh 70000h-77FFFh
16 64 D0000h-DFFFFh 68000h-6FFFFh
15 64 C0000h-CFFFFh 60000h-67FFFh
14 64 B0000h-BFFFFh 58000h-5FFFFh
13 64 A0000h-AFFFFh 50000h-57FFFh
12 64 90000h-9FFFFh 48000h-4FFFFh
11 64 80000h-8FFFFh 40000h-47FFFh
10 64 70000h-7FFFFh 38000h-3FFFFh
9 64 60000h-6FFFFh 30000h-37FFFh
8 64 50000h-5FFFFh 28000h-2FFFFh
7 64 40000h-4FFFFh 20000h-27FFFh
6 64 30000h-3FFFFh 18000h-1FFFFh
5 64 20000h-2FFFFh 10000h-17FFFh
4 64 10000h-1FFFFh 08000h-0FFFFh
3 32 08000h-0FFFFh 04000h-07FFFh
2 8 06000h-07FFFh 03000h-03FFFh
1 8 04000h-05FFFh 02000h-02FFFh
0 16 00000h-03FFFh 00000h-01FFFh
29/39
M29F800DT, M29F800DB
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system sof tware t o query the device to det ermine
various electrical and timing parameters, density
information and functions supported by t he mem-
ory. The system can interface easily with the de-
vice, enabling the s oftware to upgrad e itse lf when
necessary.
When the CFI Query Command is issued the de-
vice enters CFI Query mode and the data structure
is read from the memory. Tables 21, 22, 23, 24, 25
and 26 show the addresses used to retrieve the
data.
The CFI data structure also contains a security
area where a 64 bit unique security number is writ-
ten (see Table 26, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impos sible to change t he secu ri ty num-
ber after it ha s bee n written by ST. Issue a Read
command to return to Read mode.
Table 21. Query Structure Overview
Note: Query data are always presented on the lowest order data outputs.
Table 22. CFI Query Identification String
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
Address Sub-section Name Description
x16 x8
10h 20h CFI Query Identification String Command set ID and algorithm data offset
1Bh 36h System Interface Information Device timing & voltage information
27h 4Eh Device Geometry Definition Flash device layout
40h 80h Primary Algorithm-specific Extended
Query table Additional information specific to the Primary
Algorithm (optional)
61h C2h Security Code Area 64 bit unique device number
Address Data Description Value
x16 x8
10h 20h 0051h "Q"
11h 22h 0052h Query Unique ASCII String "QRY" "R"
12h 24h 0059h "Y"
13h 26h 0002h Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algori thm AMD
Compatible
14h 28h 0000h
15h 2Ah 0040h Address for Primary Algorithm extended Query table (see Table 24) P = 40h
16h 2Ch 0000h
17h 2Eh 0000h Alternate Vendor Command Set and Control Interface ID Code second
vendor - specified algorithm supported NA
18h 30h 0000h
19h 32h 0000h Address for Alternate Algorithm extended Query table NA
1Ah 34h 0000h
M29F800DT, M29F80 0DB
30/39
Table 23. CFI Query System In terface Information
No te : 1. Not su pported in the CF I
Address Data Description Value
x16 x8
1Bh 36h 0045h VCC Logic Supply Minimum Program/Erase voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV 4.5V
1Ch 38h 0055h VCC Logic Supply Maximum Program/Erase voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV 5.5V
1Dh 3Ah 0000h VPP [Programming] Supply Minimum Program/Erase voltage NA
1Eh 3Ch 0000h VPP [Programming] Supply Maximum Program/Erase voltage NA
1Fh 3Eh 0004h Typical timeout per single byte/word program = 2n µs 16µs
20h 40h 0000h Typical timeout for minimum size write buffer program = 2n µs NA
21h 42h 000Ah Typical timeout per individual block erase = 2n ms 1s
22h 44h 0000h Typical timeout for full chip erase = 2n ms see note (1)
23h 46h 0004h Maximum timeout for byte/word program = 2n times typical 256µs
24h 48h 0000h Maximum timeout for write buffer program = 2n times typical NA
25h 4Ah 0003h Maximum timeout per individual block erase = 2n times typical 8s
26h 4Ch 0000h Maximum timeout for chip erase = 2n times typical see note (1)
31/39
M29F800DT, M29F800DB
Table 24. Device Geometry Definition
Address Data Description Value
x16 x8
27h 4Eh 0014h Device Size = 2n in number of bytes 1 MByte
28h
29h 50h
52h 0002h
0000h Flash Device Interface Code description x8, x16
Async.
2Ah
2Bh 54h
56h 0000h
0000h Maximum number of bytes in multi-byte program or page = 2n NA
2Ch 58h 0004h Number of Erase Block Regions within the device.
It specifies the number of regions within the device containing
contiguous Erase Blocks of the same size. 4
2Dh
2Eh 5Ah
5Ch 0000h
0000h Region 1 Information
Number of identical size erase block = 0000h+1 1
2Fh
30h 5Eh
60h 0040h
0000h Region 1 Information
Block size in Region 1 = 0040h * 256 byte 16 Kbyte
31h
32h 62h
64h 0001h
0000h Region 2 Information
Number of identical size erase block = 0001h+1 2
33h
34h 66h
68h 0020h
0000h Region 2 Information
Block size in Region 2 = 0020h * 256 byte 8 Kbyte
35h
36h 6Ah
6Ch 0000h
0000h Region 3 Information
Number of identical size erase block = 0000h+1 1
37h
38h 6Eh
70h 0080h
0000h Region 3 Information
Block size in Region 3 = 0080h * 256 byte 32 Kbyte
39h
3Ah 72h
74h 000Eh
0000h Region 4 Information
Number of identical-size erase block = 000Eh+1 15
3Bh
3Ch 76h
78h 0000h
0001h Region 4 Information
Block size in Region 4 = 0100h * 256 byte 64 Kbyte
M29F800DT, M29F80 0DB
32/39
Table 25. Primary Algorithm- Speci fic Extended Qu ery Ta ble
Table 26. Security Code Area
Address Data Description Value
x16 x8
40h 80h 0050h
Primary Algorithm extended Query table unique ASCII string “PRI”
"P"
41h 82h 0052h "R"
42h 84h 0049h "I"
43h 86h 0031h Major version number, ASCII "1"
44h 88h 0030h Minor version number, ASCII "0"
45h 8Ah 0000h Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)
Yes
46h 8Ch 0002h Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write 2
47h 8Eh 0001h Block Protection
00 = not supported, x = number of sectors in per group 1
48h 90h 0001h Temporary Block Unprotect
00 = not supported, 01 = supported Yes
49h 92h 0004h Block Protect /Unprotect
04 = M29W400B 4
4Ah 94h 0000h Simultaneous Operations, 00 = not supported No
4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No
4Ch 98h 0000h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No
Address Data Description
x16 x8
61h C3h, C2h XXXX
64 bit: unique device number
62h C5h, C4h XXXX
63h C7h, C6h XXXX
64h C9h, C8h XXXX
33/39
M29F800DT, M29F800DB
APPENDIX C. BLOCK PRO TECTION
Block protection can be used to prevent any oper-
ation from modifying the dat a stored in the Flash.
Each Block can be protected individually. Once
protected, Program and Erase operations on the
block fail to change the data.
There are three techniques that can be used to
control Block Protection, these are the Program-
mer technique, the In- System technique and Tem-
porary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unpro-
tection pi n, RP; this is described in the S ign al De-
scriptions section.
Unlike the Command Interface of the Program/
Erase Cont roller, the techniques for protecting and
unprotecting blocks change between different
Flash memory suppliers. For example, the tech-
niques for AMD parts will not work on STMicro-
electronics parts. Care should be taken when
changing drivers for one part t o work on another.
Programm er Technique
The Programmer technique uses high (VID) volt-
age levels on some of the bus pins. These cannot
be achieved using a standar d microproces sor bus,
therefore the technique is recommended only for
use in Programmi ng Equipment.
To protect a block follow the flowchart in Figure 17,
Programmer Equipment Block Protect Flowchart.
To unprotect the whole chip it is necessary to pro-
tect all of the blocks firs t, then all blocks can be un-
protected at the same time. To unprotect the chip
follow Figure 18, Programmer Equipment Chip
Unprotect Flowchart. Table 27, Programmer
Technique Bus Operations, gives a summary of
each operation.
The timing on these flowcharts is critical. Care
should be taken t o ensure that, where a pau se is
specified, it is followed as closely as possible. Do
not abort the procedure be fore reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP . This can be achieved without violating the
maximum ratings of the components on the micro-
processor bus, therefore this techniqu e is suitable
for use after the Flash has been fitted to the sys-
tem.
To protect a block follow the flowchart in Figure 19,
In-System Block Protect Flowchart. To unprotect
the whole c hip it is necessary to protect all of the
blocks f irst, then all the blocks can be unprotected
at the same time. To unprotect the chip foll ow Fig-
ure 20, I n-System Chi p Unprot ect Flowchart.
The timing on these flowcharts is critical. Care
should be taken t o ensure that, where a pau se is
specified, it is followed as closely as possible. Do
not allow the m icroprocessor t o service interrupts
that will upset the timing and do not abort the pro-
cedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.
Table 27. Program mer Tech niqu e Bus Op erati ons, BYTE = VIH or VIL
Operation E G W Address Inputs
A0-A18 Data Input s/Out puts
DQ15 A–1, DQ14 -DQ0
Block Protect VIL VID VIL Pulse A9 = VID, A12-A18 Block Address
Others = X X
Chip Unprotect VID VID VIL Pulse A9 = VID, A12 = VIH, A15 = VIH
Others = X X
Block Protection
Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIL, A9=V
ID,
A12-A18 Block Address
Others = X
Pass = XX01h
Retry = XX00h
Block Unprotection
Verify VIL VIL VIH A0 = VIL, A1 = VIH, A 6 = VIH, A9 = VID,
A12-A18 Block Address
Others = X
Retry = XX01h
Pass = XX00h
M29F800DT, M29F80 0DB
34/39
Figure 17. Programmer Equi pment Block Protect Flowchart
ADDRESS = BLOCK ADDRESS
AI03469
G, A9 = VID,
E = VIL
n = 0
Wait 4µs
Wait 100µs
W = VIL
W = VIH
E, G = VIH,
A0, A6 = VIL,
A1 = VIH
A9 = VIH
E, G = VIH
++n
= 25
START
FAIL
PASS
YES
NO
DATA
=
01hYES
NO
W = VIH
E = VIL
Wait 4µs
G = VIL
Wait 60ns
Read DATA
Verify Protect Set-upEnd
A9 = VIH
E, G = VIH
35/39
M29F800DT, M29F800DB
Fi gure 18. Pr ogra m m er Equipme nt Chi p U nprot ect Flowchar t
PROTECT ALL BLOCKS
AI03470
A6, A12, A15 = VIH(1)
E, G, A9 = VID
DATA
W = VIH
E, G = VIH
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1, A6 = VIH
Wait 10ms
=
00h
INCREMENT
CURRENT BLOCK
n = 0
CURRENT BLOCK = 0
Wait 4µs
W = VIL
++n
= 1000
START
YES
YESNO
NO LAST
BLOCK
YES
NO
E = VIL
Wait 4µs
G = VIL
Wait 60ns
Read DATA
FAIL PASS
Verify Unprotect Set-upEnd
A9 = VIH
E, G = VIH A9 = VIH
E, G = VIH
M29F800DT, M29F80 0DB
36/39
Figure 19. In-System Equipment Block Protect Flowchart
AI03471
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
n = 0
Wait 100µs
WRITE 40h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
RP = VIH ++n
= 25
START
FAIL
PASS
YES
NO
DATA
=
01hYES
NO
RP = VIH
Wait 4µs
Verify Protect Set-upEnd
READ DATA
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
RP = VID
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
37/39
M29F800DT, M29F800DB
Figure 20. In-System Equipment Chip Unprotect Flowchart
AI03472
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
n = 0
CURRENT BLOCK = 0
Wait 10ms
WRITE 40h
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
RP = VIH
++n
= 1000
START
FAIL PASS
YES
NO
DATA
=
00h
YESNO
RP = VIH
Wait 4µs
READ DATA
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
RP = VID
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
PROTECT ALL BLOCKS
INCREMENT
CURRENT BLOCK
LAST
BLOCK
YES
NO
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Verify Unprotect Set-upEnd
M29F800DT, M29F80 0DB
38/39
RE VISION HISTORY
Table 28. D ocum ent Revision History
Date Version Revision Details
13-Dec-2001 -01 First Issue
21-Jan-2002 -02 VIH(max) value corrected
01-Mar-2002 -03 Description of Ready/Busy signal clarified (and Figure 14 modified)
Clarified allowable commands during block erase
Clarified the mode the device returns to in the CFI Read Query command section
17-Feb-2003 4.0
Revision numbering modified: a minor revision will be indicated by incrementing the digit
after the dot, and a major revision, by incrementing the digit before the dot (revision
version 03 equals 3.0).
Erase Suspend Latency Time (typical) and Data Retention parameters added to Table 6,
Program, Erase Times and Program, Erase Endurance Cycles, and notes added to the
table. Logic Diagram and Data Toggle Flowchart corrected.
Lead-free package options E and F added to Table 18, Ordering Information Scheme.
Document promoted to full datasheet.
08-Jul-2003 4.1 TSOP48 package information updated (see Figure 16 and Table 17). Cross-references
updated on page 29, COMMON FLASH INTERF A CE (CFI) Appendix. Temperature range
3 added.
39/39
M29F800DT, M29F800DB
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