Power
PGND
ACFET
HIDRV
LODRV
HSRP
HSRN
FB
VCC
CHG
BAT
DSG
SRP
SRN
Adapter
Pack–
ACP
PH
REGN
BST
VC4
VC3
VC2
VC1
TS1
TS2
TS3
TS4
PBI
VSS
SMBD
SMBC
GPIO0
GPIO1
AFEFUSE
FUSE
SMBD
SMBC
GPIO0
GPIO1
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq40z60
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bq40z60 Programmable Battery Management Unit
1
1 Features
1• Fully Integrated 2-Series to 4-Series Cell Li-Ion or
Li-Polymer Battery Management Unit
• Input Voltage Range on Pack+: 2.5 V to 25 V
• Battery Charger Efficiency > 92%
• Battery Charger Operation Range: 4 V to 25 V
• Battery Charger, 1-MHz Synchronous Buck
Controller for External NFETs
– Soft Start to Limit In-Rush Current
– Current Limit Protection for External Switches
– Programmable Charging
– Supports JEITA/Enhanced Charging Modes
• Fuel Gauging
– High Resolution 16-Bit Integrator for Coulomb
Counter
– ADC, 16-Bit for Precision V, I, and T
Measurements with 16-Channel Multiplexer
– Support for Simultaneous CC and ADC
Sampling (Power Conversion)
– Supports Two-Wire SMBus v2.0 Interface with
Accelerated 400-kHz Programming Option
– SHA-1 Hash Message Authentication Code
(HMAC) Responder for Increased Battery Pack
Security
– Split Key (2 × 64) Stored in Secure Memory
– Supports Field Updates
• AFE Protection
– Programmable Current Protection
– Overcurrent in Discharge
– Short-Circuit Current in Charge
– Short-Circuit Current in Discharge
• N-FET High-Side Protection FET Drive
• Support for Four LEDs
• Thermistor inputs for NTC
• Compact 32-Pin QFN Package (RHB)
2 Applications
• Notebooks, Ultrabooks, Netbooks, Tablets,
UMPCs
• Medical and Test Equipment
• Portable Instrumentation
3 Description
The Texas Instruments bq40z60 device is a
Programmable Battery Management Unit that
integrates battery charging control output, gas
gauging, and protection for completely autonomous
operation of 2-series to 4-series cell Li-Ion and Li-
Polymer battery packs. The architecture enables
internal communication between the fuel gauging
processor and battery charger controller to optimize
the charging profile based on the external load
conditions and power path source management
during load transients and adaptor current limitations
in the system. The charging current efficiency is
scalable for power transfer based on the external
components, such as the NFETs, inductor, and
sensing resistor.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
bq40z60 VQFN (32) 5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Description (continued)......................................... 3
6 Pin Configuration and Functions......................... 3
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Supply Voltage.......................................................... 6
7.6 Supply Current.......................................................... 7
7.7 Power Supply Control ............................................... 7
7.8 Low-Voltage General Purpose I/O (TSx).................. 7
7.9 High-Voltage General Purpose I/O (GPIO0, GPIO1) 8
7.10 AFE Power-On Reset ............................................. 8
7.11 Internal 1.8-V LDO................................................. 8
7.12 Current Wake Comparator...................................... 9
7.13 Coulomb Counter.................................................... 9
7.14 CC Digital Filter....................................................... 9
7.15 ADC......................................................................... 9
7.16 ADC Digital Filter .................................................. 10
7.17 ADC Multiplexer.................................................... 10
7.18 Cell Balancing Support ......................................... 10
7.19 Cell Detach Detection ........................................... 10
7.20 Internal Temperature Sensor................................ 11
7.21 NTC Thermistor Measurement Support (ADCx)... 11
7.22 High-Frequency Oscillator..................................... 11
7.23 Low-Frequency Oscillator ..................................... 11
7.24 Voltage Reference 1 ............................................. 11
7.25 Voltage Reference 2 ............................................. 12
7.26 Instruction Flash.................................................... 12
7.27 Data Flash............................................................. 12
7.28 Current Protection Thresholds.............................. 12
7.29 N-CH FET Drive (CHG, DSG)............................... 13
7.30 FUSE Drive (AFEFUSE)....................................... 14
7.31 Battery Charger Voltage Regulation (VFB)........... 14
7.32 Battery Charger Current Sense (HSRP, HSRN)... 14
7.33 Battery Charger Precharge Current Sense (HSRP,
HSRN)...................................................................... 15
7.34 AC Adapter Fault Detect (HSRN, VCC)................ 15
7.35 Battery Charger Overcurrent Detection (V)HSRP,
(V)HSRN..................................................................... 15
7.36 Battery Charger Undercurrent Detection (V)HSRP,
(V)HSRN..................................................................... 15
7.37 System Operation Detection (V)HSRN.................... 15
7.38 Battery Overvoltage Comparator (VFB)................ 15
7.39 Regulator (REGN)................................................. 16
7.40 PWM High-Side Driver (HiDRV) ........................... 16
7.41 PWM Low-Side Driver (LoDRV)............................ 16
7.42 PWM Information .................................................. 16
7.43 Charger Power-Up Sequence............................... 16
7.44 Thermal Shutdown Comparator............................ 16
7.45 SMBus High Voltage I/O....................................... 17
7.46 SMBus................................................................... 17
7.47 SMBus XL............................................................. 17
7.48 Timing Requirements............................................ 18
7.49 Typical Characteristics ......................................... 18
8 Detailed Description............................................ 19
8.1 Overview................................................................. 19
8.2 Functional Block Diagram....................................... 20
8.3 Feature Description................................................. 21
9 Application and Implementation ........................ 29
9.1 Application Information .......................................... 29
9.2 Typical Applications ................................................ 30
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 34
11.1 Layout Guidelines ................................................. 34
11.2 Layout Example ................................................... 36
12 Device and Documentation Support................. 37
12.1 Related Documentation......................................... 37
12.2 Community Resources.......................................... 37
12.3 Trademarks........................................................... 37
12.4 Electrostatic Discharge Caution............................ 37
12.5 Glossary................................................................ 37
13 Mechanical, Packaging, and Orderable
Information........................................................... 37
4 Revision History
Changes from Revision C (July 2015) to Revision D Page
• Changed Simplified Schematic............................................................................................................................................... 1
• Changed Pin Configuration and Functions............................................................................................................................. 3
• Changed Absolute Maximum Ratings ................................................................................................................................... 5
• Changed Recommended Operating Conditions .................................................................................................................... 6
• Changed High-Voltage General Purpose I/O (GPIO0, GPIO1) ............................................................................................. 8
• Changed Detailed Description Overview ............................................................................................................................. 19
• Changed Functional Block Diagram .................................................................................................................................... 20
• Changed Internal Power Source Selection........................................................................................................................... 22
• Changed Power Path Overview .......................................................................................................................................... 25
32 CHG9VSS
1BAT 24 PGND
31 PACKACP10TS1
2PBI 23 REGN
30 DSG11TS2
3VC4 22 VCC
29 ACFET12TS3
4VC3 21 AFEFUSE
28 BTST13TS4
5VC2 20 HSRP
27 HIDRV14GPIO0
6VC1 19 HSRN
26 PH15GPIO1
7SRN 18 VFB
25 LODRV16SMBD
8SRP 17 SMBC
Not to scale
Thermal
Pad
3
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Revision History (continued)
(1) P = Power Connection, O = Digital Output, IA = Analog Input, I = Digital Input, I/OD = Digital Input/Output
• Changed Typical Application Schematic ............................................................................................................................. 30
5 Description (continued)
The device provides an array of battery and system safety functions, including overcurrent in discharge, short
circuit in charge, and short circuit in discharge protection for the battery, as well as FET protection for the N-CH
FETs, internal AFE watchdog, and cell disconnection detection. Through firmware, the device can provide a
larger array of protection features including overvoltage, undervoltage, overtemperature, and more.
6 Pin Configuration and Functions
QFN Package (RHB)
32 Pins
Pin Functions
PIN DESCRIPTION
NAME NUMBER I/O(1)
BAT 1 P Battery input pin. Primary power supply
PBI 2 P Power supply backup input pin
VC4 3 IA Sense voltage input pin for the most positive cell, balance current input for the most positive cell,
and battery stack measurement input
VC3 4 IA Sense voltage input pin for the third most positive cell, balance current input for the third most
positive cell, and return balance current for the most positive cell
VC2 5 IA Sense voltage input pin for the second most positive cell, balance current input for the second
most positive cell, and return balance current for the most positive cell
VC1 6 IA Sense voltage input pin for the least positive cell, balance current input for the least positive cell,
and return balance current for the second most positive cell
SRN 7 IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small
voltage between SRP and SRN, where SRP is the top of the sense resistor.
SRP 8 IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small
voltage between SRP and SRN, where SRP is the top of the sense resistor.
VSS 9 P Device ground
TS1 10 IA Thermistor input for temperature sensor channel 1
TS2 11 IA Thermistor input for temperature sensor channel 2
TS3 12 IA Thermistor input for temperature sensor channel 3
TS4 13 IA Thermistor input for temperature sensor channel 4
GPIO0 14 I/O Multi-function I/O (open drain). For more information, see IO Configuration in the bq40z60
Technical Reference Manual (SLUUA04).
4
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Pin Functions (continued)
PIN DESCRIPTION
NAME NUMBER I/O(1)
GPIO1 15 I/O Multi-function I/O (open drain). See IO Configuration in the bq40z60 Technical Reference Manual
(SLUUA04).
SMBD 16 I/OD SMBus data pin
SMBC 17 I/OD SMBus clock pin
VFB 18 IA Feedback sense input for charger control loop
HSRN 19 IA High sense resistor negative node input
HSRP 20 IA High sense resistor positive node input
AFEFUSE 21 O Fuse drive output pin
VCC 22 P Power supply input
REGN 23 O Charger FET gate drive regulator
PGND 24 P Power ground
LODRV 25 O Low side charging FET gate control output
PH 26 I/O Charger phase signal input
HIDRV 27 O High side charging FET gate control output
BTST 28 IA High side bootstrap capacitor input
ACFET 29 O AC FET gate control output
DSG 30 O N-CH FET drive output pin
ACP 31 IA Adapter input pin
CHG 32 O N-CH FET drive output pin
5
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(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
7 Specifications
7.1 Absolute Maximum Ratings
Over-operating free-air temperature range (unless otherwise noted)(1)
MIN TYP MAX UNIT
Supply voltage
range, VSupply
BAT, VCC, PBI –0.3 30 V
REGN –0.3 7 V
Input voltage range,
VIN
ACP, SMBC, SMBD, GPIO0, GPIO1 –0.3 30 V
TS1, TS2, TS3, TS4 –0.3 VREG + 0.3 V
SRP, SRN –0.3 0.3 V
HSRP, HSRN –0.3 30 V
PH –0.3 32 V
VFB –0.3 16 V
VC4 VC3 – 0.3 VC3 + 8.5 V,
or VSS + 30 V
VC3 VC2 – 0.3 VC2 + 8.5 V,
or VSS + 30 V
VC2 VC1 – 0.3 VC1 + 8.5 V,
or VSS + 30 V
VC1 VSS – 0.3 VSS + 8.5 V,
or VSS + 30 V
Output voltage
range, VO
CHG, DSG –0.3 32 V
HIDRV, BTST, ACFET –0.3 36 V
LODRV –0.3 7 V
AFEFUSE –0.3 30 V
Maximum VSS current, ISS 50 mA
Functional Temperature, TFUNC –40 110 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings VALUE UNIT
V(ESD) Rating HBM(1) ±2000 V
CDM(2) ±500 V
7.3 Recommended Operating Conditions
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted) MIN NOM MAX UNIT
VSupply Supply voltage BAT, VCC, PBI 2.2 26 V
ACFET, BTST 0 35 V
REGN 0 6.5 V
VSHUTDOWN– Shutdown voltage VACP < VSHUTDOWN– 1.8 2.0 2.2 V
VSHUTDOWN+ Start-up voltage VACP > VSHUTDOWN– + VHYS 2.05 2.25 2.45 V
VHYS Shutdown voltage
hysteresis VSHUTDOWN+ – VSHUTDOWN– 250 mV
6
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Recommended Operating Conditions (continued)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted) MIN NOM MAX UNIT
VIN Input voltage range
ACP, SMBC, SMBD, GPIO0, GPIO1 26
V
TSx VREG
SRP, SRN –0 .2 0.2
HSRP, HSRN –0 .5 0.5
PH –2 VACP
VFB 0 14
VC4 VVC3 VVC3 + 5
VC3 VVC2 VVC2 + 5
VC2 VVC1 VVC1 + 5
VC1 VVSS VVSS + 5
VOOutput voltage
range
CHG, DSG, AFEFUSE 26 V
HIDRV 35 V
LODRV 0 6.5 V
CPBI External PBI
capacitor 2.2 µF
TOPR Operating
temperature –40 85 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.4 Thermal Information
THERMAL METRIC(1) bq40z60
UNITRHB (VQFN)
32 PINS
RθJA, High K Junction-to-ambient thermal resistance 36 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 31.5 °C/W
RθJB Junction-to-board thermal resistance 8 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 7.9 °C/W
RθJCbot Junction-to-case(bottom) thermal resistance 2.2 °C/W
7.5 Supply Voltage
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC Device Operating Range Operation with charger enabled 4.0 25 V
Operation with charger disabled 2.5 25
VCC-UV Undervoltage lock out VCC falling 2.2 2.45 V
7
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(1) VCC ≤20 V when CHG = ON and DSG = ON
7.6 Supply Current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INORMAL NORMAL mode(1)
CPU = ACTIVE, HFO = ON, ADC_FILTER = ON,
CC_FILTER = ON, LFO = ON, REG18 = ON, CHG
= ON, DSG = ON, ADC = ON, CC = ON, Charger
Enabled, No Communication 1250 1850
µA
CPU = HALT, HFO = ON, ADC_FILTER = ON,
CC_FILTER = ON, LFO = ON, REG18 = ON, CHG
= ON, DSG = ON, ADC = ON, CC = ON, Charger
Disabled, No Communication 310 445
ISLEEP SLEEP mode(1)
CPU = HALT, HFO = ON, ADC_FILTER = OFF,
CC_FILTER = OFF, LFO = ON, REG18 = ON, CHG
= ON, DSG = ON, ADC = OFF, CC = OFF, Charger
Disabled, No Communication 122 183
µA
CPU = HALT, HFO = OFF, ADC_FILTER = OFF,
CC_FILTER = OFF, LFO = ON, REG18 = ON, CHG
= ON, DSG = ON, ADC = OFF, CC = OFF, Charger
Disabled, No Communication 92 138
CPU = HALT, HFO = ON, ADC_FILTER = OFF,
CC_FILTER = OFF, LFO = ON, REG18 = ON, CHG
= OFF, DSG = OFF, ADC = OFF, CC = OFF,
Charger Disabled, No Communication 82 128
CPU = HALT, HFO = OFF, ADC_FILTER = OFF,
CC_FILTER = OFF, LFO = ON, REG18 = ON, CHG
= OFF, DSG = OFF, ADC = OFF, CC = OFF,
Charger Disabled, No Communication 52 83
ISHUTDOWN SHUTDOWN mode CPU = HALT, HFO = OFF, ADC_FILTER = OFF,
CC_FILTER = OFF, LFO = OFF, REG18 = OFF,
CHG = OFF, DSG = OFF, ADC = OFF, CC = OFF,
Charger Disabled, No Communication 0.5 2 µA
7.7 Power Supply Control
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSWITCHOVER– BAT to VCC
switchover voltage VBAT < VSWITCHOVER– 2.0 2.1 2.2 V
VSWITCHOVER+ VCC to BAT
switchover voltage VBAT > VSWITCHOVER– + VHYS 3.0 3.1 3.2 V
VHYS Switchover voltage
hysteresis VSWITCHOVER+ – VSWITCHOVER– 1000 mV
ILKG Input leakage
current
BAT pin, BAT = 0 V, VCC = 25 V 1
µA
VCC pin, BAT = 25 V, VCC = 0 V 1
BAT and VCC pins, BAT = 0 V, VCC = 0 V, PBI =
25 V 1
RPD Internal pulldown
resistance ACP 30 40 50 kΩ
7.8 Low-Voltage General Purpose I/O (TSx)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input 0.65 × VREG V
VIL Low-level input 0.35 × VREG V
VOH Output voltage high IOH = –1.0 mA 0.75 × VREG V
IOH = –10 µA
VOL Output voltage low IOL = 1.0 mA 0.2 × VREG V
8
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Low-Voltage General Purpose I/O (TSx) (continued)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CIN Input capacitance 5 pF
ILKG Input leakage current 1 µA
7.9 High-Voltage General Purpose I/O (GPIO0, GPIO1)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input 1.3 V
VIL Low-level input 0.55 V
VOH Output voltage
high VBAT > 5.5 V, IOH = –0 µA 3.5 V
VBAT > 5.5 V, IOH = –10 µA 1.8
VOL Output voltage
low IOL = 1.5 mA 0.4 V
CIN Input
capacitance 5 pF
ILKG Input leakage
current 1 µA
ROOutput reverse
resistance Between GPIO0/1 and PBI 5 kΩ
7.10 AFE Power-On Reset
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREGIT– Negative-going
voltage input VREG 1.51 1.55 1.59 V
VHYS Power-on reset
hysteresis VREGIT+ – VREGIT– 70 100 130 mV
tRST Power-on reset time 200 300 400 µs
7.11 Internal 1.8-V LDO
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREG Regulator voltage 1.6 1.8 2.0 V
ΔVO(TEMP) Regulator output
over temperature ΔVREG/ΔTA, IREG = 10 mA ±0.25%
ΔVO(LINE) Line regulation ΔVREG/ΔVBAT, VBAT = 10 mA –0 .6% 0.5%
ΔVO(LOAD) Load regulation ΔVREG/ΔIREG, IREG = 0 mA to 10 mA –1.5% 1.5%
IREG Regulator output
current limit VREG = 0.9 × VREG(NOM), VIN > 2.2 V 20 mA
ISC Regulator short-
circuit current limit VREG = 0 × VREG(NOM) 25 40 50 mA
PSRRREG Power supply
rejection ratio ΔVBAT/ΔVREG, IREG = 10 mA ,VIN > 2.5 V, f = 10 Hz 40 dB
VSLEW Slew rate
enhancement
voltage threshold 1.58 1.65 V
9
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7.12 Current Wake Comparator
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VWAKE Wake voltage
threshold
VWAKE = VSRP – VSRN ±0.3 ±0.625 ±0.9
mV
VWAKE = VSRP – VSRN ±0.6 ±1.25 ±1.8
VWAKE = VSRP – VSRN ±1.2 ±2.5 ±3.6
VWAKE = VSRP – VSRN ±2.4 ±5.0 ±7.2
VWAKE(DRIFT) Temperature drift
of VWAKE accuracy 0.5% °C
tWAKE Time from
application of
current to wake 0.25 0.5 ms
tWAKE(SU) Wake comparator
startup time 500 1000 µs
(1) Coulomb counter electrical specifications are assured when battery charging function is disabled.
(2) 1 LSB = VREF1/(10 × 2N) = 1.215/(10 × 215) = 3.71 µV
(3) Full-scale reference
7.13 Coulomb Counter(1)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range –0.1 0.1 V
Full scale range –VREF1/10 VREF1/10 V
Integral nonlinearity(2) 16-bit, Best fit over input voltage range ±5.2 ±22.3 LSB
Offset error 16-bit, Post-calibration ±5 ±10 µV
Offset error drift 15-bit + sign, Post-calibration 0.2 0.3 µV/°C
Gain error 15-bit + sign, Over input voltage range ±0.2% ±0.8% FSR(3)
Gain error drift 15-bit + sign, Over input voltage range 150 PPM/°C
Effective input resistance 2.5 MΩ
7.14 CC Digital Filter
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Conversion time Single conversion 250 ms
Effective resolution Single conversion 15 Bits
(1) ADC electrical specifications are assured when battery charging function is disabled.
(2) 1 LSB = VREF1/(2N) = 1.225/(215) = 37.4 µV (when ADCTL[SPEED1, SPEED0] = 0, 0)
(3) For VC1–VSS, VC2–VC1, VC3–VC2, VC3–VSS, ACP–VSS, and VREF1/2, the offset error is multiplied by (1/ADC multiplexer scaling
factor (K)).
7.15 ADC(1)
Over-operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range Internal reference (VREF1) –0.2 1 V
External reference (VREG) –0.2 0.8 × VREG
Full scale range VFS = VREF1 or VREG –VFS VFS V
Integral nonlinearity(2) 16-bit, Best fit, –0.1 V to 0.8 × VREF1 ±6.6 LSB
16-bit, Best fit, –0.2 V to –0.1 V ±13.1
Offset error(3) 16-bit, Post-calibration, VFS = VREF1 ±67 ±157 µV
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ADC(1) (continued)
Over-operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Offset error drift 16-bit, Post-calibration, VFS = VREF1 0.6 3 µV/°C
Gain error 16-bit, –0.1 V to 0.8 × VFS ±0.2% ±0.8% FSR
Gain error drift 16-bit, –0.1 V to 0.8 × VFS 150 PPM/°C
Effective input resistance 8 MΩ
7.16 ADC Digital Filter
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Conversion time
ADCTL[SPEED1, SPEED0] = 0, 0 31.25
ms
ADCTL[SPEED1, SPEED0] = 0, 1 15.63
ADCTL[SPEED1, SPEED0] = 1, 0 7.81
ADCTL[SPEED1, SPEED0] = 1, 1 1.95
Resolution No missing codes, ADCTL[SPEED1, SPEED0] = 0, 0 16 Bits
Effective resolution
With sign, ADCTL[SPEED1, SPEED0] = 0, 0 14 15
Bits
With sign, ADCTL[SPEED1, SPEED0] = 0, 1 13 14
With sign, ADCTL[SPEED1, SPEED0] = 1, 0 11 12
With sign, ADCTL[SPEED1, SPEED0] = 1, 1 9 10
7.17 ADC Multiplexer
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
K Scaling factor
VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3 0.1980 0.2000 0.2020
—
VC4–VSS, ACP–VSS 0.049 0.050 0.051
VREF2 0.490 0.500 0.510
HSRN–VSS 0.049 0.050 0.051
VIN Input voltage range VC4–VSS, ACP–VSS –0.2 20 VTSx –0.2 0.8 × VREF1
TSx –0.2 0.8 × VREG
ILKG Input leakage current VC1, VC2, VC3, VC4, cell balancing off, cell
detach detection off, ADC multiplexer off 1 µA
7.18 Cell Balancing Support
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RCB Internal cell balance
resistance RDS(ON) for internal FET switch at 2 V < VDS < 4 V 200 Ω
7.19 Cell Detach Detection
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICD Internal cell detach
check current VCx > VSS + 0.8 V 30 50 70 µA
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7.20 Internal Temperature Sensor
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VTEMP Internal temperature
sensor voltage drift VTEMPP –1.9 –2.0 –2.1 mV/°C
VTEMPP – VTEMPN, assured by design 0.177 0.178 0.179
7.21 NTC Thermistor Measurement Support (ADCx)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RNTC(PU) Internal pullup
resistance 14.4 18 21.6 kΩ
RNTC(DRIFT) Resistance drift over
temperature –360 –280 –200 PPM/°C
7.22 High-Frequency Oscillator
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fHFO Operating frequency 16.78 MHz
fHFO(ERR) Frequency error TA= –20°C to 70°C, includes frequency drift –2.5% ±0.25% 2.5%
TA= –40°C to 85°C, includes frequency drift –3.5% ±0.25% 3.5%
tHFO(SU) Start-up time
TA= –20°C to 85°C, CLKCTL[HFRAMP] = 1, oscillator
frequency within +/–3% of nominal 4 ms
CLKCTL[HFRAMP] = 0, oscillator frequency within +/–3%
of nominal 100 µs
7.23 Low-Frequency Oscillator
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fLFO Operating frequency 262.144 kHz
fLFO(ERR) Frequency error TA= –20°C to 70°C, includes frequency drift –1.5% ±0.25% 1.5%
TA= –40°C to 85°C, includes frequency drift –2.5 ±0.25 2.5
fLFO(FAIL) Failure detection
frequency 30 80 100 kHz
7.24 Voltage Reference 1
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF1 Internal reference
voltage TA= 25°C, after trim 1.21 1.215 1.22 V
VREF1(DRIFT) Internal reference
voltage drift TA= 0°C to 60°C, after trim ±50 PPM/°C
TA= –40°C to 85°C, after trim ±80
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7.25 Voltage Reference 2
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF2 Internal reference
voltage TA= 25°C, after trim 1.22 1.225 1.23 V
VREF2(DRIFT) Internal reference
voltage drift TA= 0°C to 60°C, after trim ±50 PPM/°C
TA= –40°C to 85°C, after trim ±80
7.26 Instruction Flash
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Data retention 10 Years
Flash programming
write cycles 1000 Cycles
tPROGWORD Word programming
time TA= –40°C to 85°C 40 µs
tMASSERASE Mass-erase time TA= –40°C to 85°C 40 ms
tPAGEERASE Page-erase time TA= –40°C to 85°C 40 ms
IFLASHREAD Flash-read current TA= –40°C to 85°C 2 mA
IFLASHWRITE Flash-write current TA= –40°C to 85°C 5 mA
IFLASHERASE Flash-erase current TA= –40°C to 85°C 15 mA
7.27 Data Flash
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Data retention 10 Years
Flash programming
write cycles 20000 Cycles
tPROGWORD Word programming
time TA= –40°C to 85°C 40 µs
tMASSERASE Mass-erase time TA= –40°C to 85°C 40 ms
tPAGEERASE Page-erase time TA= –40°C to 85°C 40 ms
IFLASHREAD Flash-read current TA= –40°C to 85°C 1 mA
IFLASHWRITE Flash-write current TA= –40°C to 85°C 5 mA
IFLASHERASE Flash-erase current TA= –40°C to 85°C 15 mA
7.28 Current Protection Thresholds
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOCD OCD detection
threshold voltage
range
VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 –16.6 –100 mV
VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 –8.3 –50
ΔVOCD OCD detection
threshold voltage
program step
VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 –5.56 mV
VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 –2.78
VSCC SCC detection
threshold voltage
range
VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 44.4 200 mV
VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 22.2 100
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Current Protection Thresholds (continued)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ΔVSCC SCC detection
threshold voltage
program step
VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 22.2 mV
VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 11.1
VSCD1 SCD1 detection
threshold voltage
range
VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 –44.4 –200 mV
VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 –22.2 –100
ΔVSCD1 SCD1 detection
threshold voltage
program step
VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 –22.2 mV
VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 –11.1
VSCD2 SCD2 detection
threshold voltage
range
VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 –44.4 –200 mV
VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 –22.2 –100
ΔVSCD2 SCD2 detection
threshold voltage
program step
VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 –22.2 mV
VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 –11.1
VOFFSET OCD, SCC, and
SCDx offset error Post-trim –2.5 2.5 mV
VSCALE OCD, SCC, and
SCDx scale error No trim –10% 10%
Post-trim –5% 5%
7.29 N-CH FET Drive (CHG, DSG)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output voltage ratio
RatioDSG = (VDSG – VBAT)/VBAT, 2.2 V < VBAT <
4.07 V, 10 MΩbetween HSRN and DSG 2.133 2.333 2.533
—
RatioCHG = (VCHG – VBAT)/VBAT, 2.2 V < VBAT <
4.07 V, 10 MΩbetween BAT and CHG 2.133 2.333 2.533
RatioACFET = (VACFET – VBAT)/VBAT, 2.2 V < VBAT
< 4.07 V, 10 MΩbetween ACP and ACFET 2.133 2.333 2.533
V(FETON)
Output voltage, CHG and
DSG on
VDSG(ON) = VDSG – VBAT, VBAT ≥4.07 V, 10 MΩ
between VHSRN and DSG, VBAT = 18 V 9.0 9.5 10
V
VCHG(ON) = VCHG – VBAT, VBAT ≥4.07 V, 10 MΩ
between BAT and CHG, VBAT = 18 V 9.0 9.5 10
ACFET VACFET(ON) = VACFET – VBAT, VBAT ≥4.07 V, 10
MΩbetween ACP and ACFET, VBAT = 18 V 9.0 9.5 10
V(FETOFF)
Output voltage, CHG and
DSG off
VDSG(OFF) = VDSG – VACP, 10 MΩbetween HSRN
and DSG –0.4 0.4
V
VCHG(OFF) = VCHG – VBAT, 10 MΩbetween BAT
and CHG –0.4 0.4
ACFET VACFET(OFF) = VACFET – VACP, VBAT ≥4.07 V, 10
MΩbetween ACP and ACFET, VBAT = 18 V –0.4 0.4
tRRise time
VDSG from 0% to 35% VDSG(ON)(TYP), VACP ≥2.2 V,
CL= 4.7 nF between DSG and VHSRN, 5.1 kΩ
between DSG and CL, 10 MΩbetween VHSRN and
DSG 200 500
µs
VCHG from 0% to 35% VCHG(ON)(TYP), VACP ≥2.2
V, CL= 4.7 nF between CHG and BAT, 5.1 kΩ
between CHG and CL, 10 MΩbetween BAT and
CHG 200 500
VACFET from 0% to 35% VACFET(ON)(TYP), VACP ≥
2.2 V, CL= 4.7 nF between ACFET and ACP, 5.1
kΩbetween CHG and CL, 10 MΩbetween ACP
and ACFET 200 500
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N-CH FET Drive (CHG, DSG) (continued)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tFFall time
VDSG from VDSG(ON)(TYP) to 1 V, VACP ≥2.2 V, CL
= 4.7 nF between DSG and ACP, 5.1 kΩbetween
DSG and CL, 10 MΩbetween ACP and DSG 40 300
µs
VCHG from VCHG(ON)(TYP) to 1 V, VACP ≥2.2 V, CL
= 4.7 nF between CHG and BAT, 5.1 kΩbetween
CHG and CL, 10 MΩbetween BAT and CHG 40 200
VACFET from VACFET(ON)(TYP) to 1 V, VACP ≥2.2 V,
CL= 4.7 nF between ACFET and ACP, 5.1 kΩ
between CHG and CL, 10 MΩbetween ACP and
ACFET 40 200
7.30 FUSE Drive (AFEFUSE)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH Output voltage high VBAT ≥8 V, CL= 1 nF, IAFEFUSE = 0 µA 6 7 8.65 V
VBAT < 8 V, CL= 1 nF, IAFEFUSE = 0 µA VBAT – 0.1 VBAT
VIH High-level input 1.5 2.0 2.5 V
IAFEFUSE(PU) Internal pullup current VBAT ≥8 V, VAFEFUSE = VSS 150 330 nA
RAFEFUSE Output impedance 2 2.6 3.2 kΩ
CIN Input capacitance 5 pF
tDELAY Fuse trip detection delay 128 256 µs
tRISE Fuse output rise time VBAT ≥8 V, CL= 1 nF, VOH = 0 V to 5 V 5 20 µs
7.31 Battery Charger Voltage Regulation (VFB)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VFB Regulation range Based on internal DAC reference setting 0.61 1.22 V
VFBACC Voltage feedback
accuracy VFB = 1.22 V –2% 2%
VFB(STEPS) Programmable regulation
steps 2.5 mV
RVFB Total feedback resistor
divider range 500 700 kΩ
7.32 Battery Charger Current Sense (HSRP, HSRN)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN(Normal
range) Differential Input range DAC range for current measurement 2 100 mV
VACC Measurement accuracy VHSRP – VHSRN = 50 mV, RSense= 10 mΩ–5% 5%
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7.33 Battery Charger Precharge Current Sense (HSRP, HSRN)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN(Normal
range) Differential Input range DAC range for current measurement 2 20 mV
VACC Measurement accuracy VHSRP – VHSRN = 2 mV, RSense= 10 mΩ
(VHSRN > 2.3 V) –70% 70%
7.34 AC Adapter Fault Detect (HSRN, VCC)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VHSRN – VCC AC adapter input fault
detect Battery > AC adapter input (Falling) 150 225 300 mV
VHys Recovery hysteresis AC adapter input > Battery (Rising) 50 100 150 mV
7.35 Battery Charger Overcurrent Detection (V)HSRP, (V)HSRN
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOC(max) Charger overcurrent
threshold Charging current as a percentage of max sense
voltage range 180 200 mV
IOC(min) Charger overcurrent
threshold Minimum charging overcurrent detected 45 55 mV
7.36 Battery Charger Undercurrent Detection (V)HSRP, (V)HSRN
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IUC(Detect) Detect under current for
negative inductor current VHSRP – VHSRN < 0 mV, for negative inductor
current, VHSRP > 2.3 V 1 5 16 mV
IUC(Non-synch) Minimum sense voltage to
enter non-synchronous
mode 1.7 mV
7.37 System Operation Detection (V)HSRN
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VHSRN Input voltage for operation VHSRN Falling 2.05 2.15 2.25 V
VHys Recovery hysteresis VHSRN Rising 100 150 200 mV
7.38 Battery Overvoltage Comparator (VFB)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOV(max) Battery over-voltage
detection VFB > Set value (Rising) 106%
VOV(Recovery) Battery over-voltage
recovery VFB < VOV (Falling) 103%
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7.39 Regulator (REGN)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VLODRV Gate drive for low side
charger FET VCC > 10 V, ILoad = 0 to 60 mA 5.7 6.0 6.3 V
ISC Short circuit current limit VLODRV = 0 V 60 mA
VREGN Power good indicator VREGN Rising 3.6 3.68 3.75 V
VHys Hysteresis VREGN Falling 240 260 280 mV
7.40 PWM High-Side Driver (HiDRV)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RON Driver turn ON resistance VBTST – VPH ≥5.5 V 6.0 8.6 Ω
ROFF Driver turn OFF resistance VFB < VOV (Falling) 2.5 3.3 Ω
VBOOTSTRAP Bootstrap refresh
comparator VCC = 4 V to 6 V 2.6 2.9 V
VCC > 6 V 3.9 4.1 V
7.41 PWM Low-Side Driver (LoDRV)
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RON Driver turn ON resistance VREGN – VPGND ≥5.5 V 5.2 7.6 Ω
ROFF Driver turn OFF
resistance VFB < VOV (Falling) 1.9 2.4 Ω
7.42 PWM Information
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tDEADTIME Deadtime between FET
driver output switching 30 ns
Duty cycle 99.5%
fSW PWM switching frequency 0.8 1.0 1.1 MHz
7.43 Charger Power-Up Sequence
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tDELAY Power-up sequence 8 ms
tSS(STEPS) Soft start steps 8
tSS(STEP TIME) Soft start time 2 ms
7.44 Thermal Shutdown Comparator
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TSHUTDOWN 135 145 C
THys 12 C
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7.45 SMBus High Voltage I/O
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input voltage high SMBC, SMBD, VREG = 1.8 V 1.3 V
VIL Input voltage low SMBC, SMBD, VREG = 1.8 V 0.8 V
VOL Output low voltage SMBC, SMBD, VREG = 1.8 V, IOL = 1.5 mA 0.4 V
CIN Input capacitance 5 pF
ILKG Input leakage current 1 µA
RPD pulldown resistance 0.7 1.0 1.3 MΩ
7.46 SMBus
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSMB SMBus operating
frequency SLAVE mode, SMBC 50% duty cycle 10 100 kHz
fMAS SMBus master clock
frequency MASTER mode, no clock low slave extend 51.2 kHz
tBUF Bus free time between
start and stop 4.7 µs
tHD(START) Hold time after
(repeated) start 4.0 µs
tSU(START) Repeated start setup
time 4.7 µs
tSU(STOP) Stop setup time 4.0 µs
tHD(DATA) Data hold time 300 ns
tSU(DATA) Data setup time 250 ns
tTIMEOUT Error signal detect time 25 35 ms
tLOW Clock low period 4.7 µs
tHIGH Clock high period 4.0 50 µs
tRClock rise time 10% to 90% 1000 ns
tFClock fall time 90% to 10% 300 ns
tLOW(SEXT) Cumulative clock low
slave extend time 25 ms
tLOW(MEXT) Cumulative clock low
master extend time 10 ms
7.47 SMBus XL
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSMBXL SMBus XL operating frequency SLAVE mode 40 400 kHz
tBUF Bus free time between start and
stop 4.7 µs
tHD(START) Hold time after (repeated) start 4.0 µs
tSU(START) Repeated start setup time 4.7 µs
tSU(STOP) Stop setup time 4.0 µs
tTIMEOUT Error signal detect time 5 20 ms
tLOW Clock low period 20 µs
tHIGH Clock high period 20 µs
950000
960000
970000
980000
990000
1000000
1010000
1020000
1030000
1040000
1050000
-40 10 60
Frequency (Hz)
Temperature (ƒC)
Typical Charger Switching Frequency
C001
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7.48 Timing Requirements
Typical values stated where TA= 25°C and VCC = 10.8 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted) MIN TYP MAX UNIT
CURRENT PROTECTION TIMING
tOCD OCD detection delay
time 1 31 ms
ΔtOCD OCD detection delay
time program step 2 ms
tSCC SCC detection delay
time 0 915 µs
ΔtSCC SCC detection delay
time program step 61 µs
tSCD1 SCD1 detection delay
time PROTECTION_CONTROL[SCDDx2] = 0 0 915 µs
PROTECTION_CONTROL[SCDDx2] = 1 0 1850
ΔtSCD1 SCD1 detection delay
time program step PROTECTION_CONTROL[SCDDx2] = 0 61 µs
PROTECTION_CONTROL[SCDDx2] = 1 121
tSCD2 SCD2 detection delay
time PROTECTION_CONTROL[SCDDx2] = 0 0 458 µs
PROTECTION_CONTROL[SCDDx2] = 1 0 915
ΔtSCD2 SCD2 detection delay
time program step PROTECTION_CONTROL[SCDDx2] = 0 30.5 µs
PROTECTION_CONTROL[SCDDx2] = 1 61
tDETECT Current fault detect
time VSRP – VSRN = VT– 3 mV for OCD, SCD1, and SC2,
VSRP – VSRN = VT+ 3 mV for SCC 160 µs
tACC Current fault delay time
accuracy Max delay setting –10% 10%
7.49 Typical Characteristics
Figure 1. Charger Switching Frequency Across Temperature
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8 Detailed Description
8.1 Overview
The bq40z60 is a fully integrated battery manager that employs flash-based firmware and integrated hardware
protection to provide a complete solution for 2-series to 4-series cell battery stack architectures. The bq40z60
interfaces with a host system via an SBS v1.1-compliant SMBus interface, and processes instructions and data
using a state-of-the-art, ultra-low-power TI bqBMP CPU. High-performance, integrated analog peripherals enable
support for a sense resistor down to 5 mΩ, battery charge control, and simultaneous current/voltage data
conversion for instant power calculations.
The bq40z60 controls the cell charging profile based on user-programmed data flash parameters for charging
current and voltage based on temperature and cell voltage. The gas gauge provides the cell voltage and
charging information to the battery charging through an internal communication bus. The charger function is
controlled based on cell voltage measurements both on individual cell and total series stack readings.
The analog front end provides this voltage-based information to the charging circuit to set the profiles pre-
programmed in the data flash settings, which are useful for zero voltage and PRECHARGE mode operation. The
following sections detail all of the major component blocks in the bq40z60 device.
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8.2 Functional Block Diagram
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8.3 Feature Description
The bq40z60 consists of an integrated analog front end, charge controller, and fuel gauge. The following sections
provide an overview of the device features. For additional details, refer to the bq40z60 Technical Reference
Manual (SLUUA04).
8.3.1 Safety Features
The bq40z60 provides support for primary safety, including:
• Cell Over/Undervoltage Protection
• Charge and Discharge Overcurrent
• Short Circuit Protection
• Charge and Discharge Overtemperature
The secondary safety features of the bq40z60 can be used to indicate more serious faults via the FUSE pin. This
pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or discharging. The
secondary safety features provide protection against:
• Safety Over/Undervoltage Permanent Failure
• Safety Overtemperature Permanent Failure
• Safety FET Overtemperature Permanent Failure
• Qmax Imbalance Permanent Failure
• Impedance Imbalance Permanent Failure
• Capacity Degradation Permanent Failure
• Cell Balancing Permanent Failure
• Fuse Failure Permanent Failure
• Voltage Imbalance at Rest Permanent Failure
• Voltage Imbalance Active Permanent Failure
• Charge/Discharge FET Permanent Failure
• Second Level Protector Permanent Failure
• Instruction Flash Checksum Permanent Failure
• Open Cell Connection Permanent Failure
• Data Flash Permanent Failure
• Open Thermistor Permanent Failure
8.3.2 Analog Front End (AFE) Details
The analog front end (AFE) consists of circuits responsible for managing internal power and interfacing to outside
components for measuring current, voltage, and temperature. The bq40z60 AFE includes an active-high interrupt
output connected internally to the fuel gauge to notify it of important changes in some of the AFE registers.
The bq40z60 manages its supply voltage dynamically according to operating conditions. When VBAT >
VSWITCHOVER– + VHYS, the AFE connects an internal switch to BAT and uses this pin to supply power to its internal
1.8-V LDO, which subsequently powers all device logic and flash operations. Once BAT decreases to VBAT <
VSWITCHOVER–, the AFE disconnects its internal switch from BAT and connects another switch to VCC, allowing
sourcing of power from a charger (if present). An external capacitor connected to PBI provides a momentary
supply voltage to help guard against system brownouts due to transient short-circuit or overload events that pull
VBAT below VSWITCHOVER–.
normal operation
(untrimmed)
normal operation
(trimmed)
1.8-V Regulator
LFO
tOSU
tRST
AFE RESET
VIT+ VIT–
AGG writes trim values to
AFE
Pack–
AC
FET
ACFET VCCACP
BAT
Power Regulator
–
+
VSWITCHOVER–
SRP
SRN
ACP
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Feature Description (continued)
Figure 2. Internal Power Source Selection
In the event of a power-cycle, the bq40z60 AFE will hold its internal RESET output pin high for tRST duration to
allow its internal 1.8-V LDO and LFO to stabilize before running the analog gas gauge (AGG). The AFE enters
power-on reset when the voltage at VREG falls below VREGIT–, and exits reset when VREG rises above VREGIT– +
VHYS for tRST time. After tRST, the bq40z60 AGG writes its trim values to the AFE.
Figure 3. Power-On Reset Operation
The bq40z60 AFE includes a low frequency oscillator (LFO) running at 262.144 kHz. The AFE monitors the LFO
frequency and indicates a failure via LATCH_STATUS[LFO] if the output frequency is much lower than normal.
The bq40z60 AFE provides two internal voltage references: VREF1, used by the ADC and CC, and VREF2 used by
the LDO, LFO, current wake comparator, and over- and short-current protection circuitry.
8.3.2.1 Wake Up Comparator
The internal wake comparator can be used to wake the bq40z60 from a HALT state if a configurable threshold is
detected across SRP and SRN.
Pack–
BAT
SRP
SRN
VC4
VC3
VC2
VC1
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Feature Description (continued)
8.3.2.2 Cell Balancing Support
The integrated cell balancing FETs included in the bq40z60 device allow the AFE to bypass cell current around a
given cell or numerous cells to effectively balance the entire battery stack. External series resistors placed
between the cell connections and the VCx input pins set the balancing current magnitude. The cell balancing
circuitry can be enabled or disabled via the CELL_BAL_DET[CB3, CB2, CB1] control register. Series input
resistors between 100 Ωand 1 kΩare recommended for effective cell balancing.
Figure 4. Cell Balancing Configuration
8.3.2.3 FET Drive
The bq40z60 controls two external N-CH MOSFETs in a back-to-back configuration for battery protection. The
charge (CHG) and discharge (DSG) FETs are automatically disabled if a safety fault is detected and can also be
manually turned off using AFE_CONTROL[CHGEN, DSGEN] = 0, 0. When the gate drive is disabled, an internal
circuit discharges CHG to BAT and DSG to HSRN.
The AC FET (N-CH MOSFET) controls power input from the AC adaptor to the battery charging system by
monitoring the voltage at the VCC pin, and turning ON the ACFET if the voltage exceeds the VHSRN voltage. The
following register command sets the AC FET gate drive output control, AFE_STATUS register (0x01) ACFET
(Pin 2): Setting this pin to 1 allows the AC FET gate drive to be on if other conditions are satisfied.
8.3.2.4 Fuse Drive
The bq40z60 AFE has the ability to blow an external fuse in the event of a permanent failure. The fuse drive
itself is supplied from the BAT input pin and its state can be monitored using the AFE_STATUS[FUSE_RAW]
register. If AFE_STATUS[FUSE_RAW} = 1 for tDELAY duration, then LATCH_STATUS[FUSE] is set to 1, and after
an additional 500 ms, the CHG and DSG FET drive outputs will be disabled if LATCH_STATUS[FUSE] has not
been cleared by then. If the AFEFUSE output is not used, it should be connected to VSS. When AFEFUSE is in
the low state, it uses an internal weak pullup to enable detection of disconnection between the AFEFUSE pin and
the fuse drive circuitry.
CHGR
0mA
IPRECHG /
ITERM
ICHG
VPRECHG
IBAT
VSYS VBAT
Constant
Current Termination
Pre
Charge
Current Loop Voltage Loop
VSYS = VBAT + IBAT · (RBAT+RSNS)
Termination Detect
Constant
Voltage
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Feature Description (continued)
8.3.3 Charge Controller Details
The charge controller, under control from the fuel gauge's processor, provides autonomous control over the
charging of the battery pack. The controller uses a 1-MHz buck architecture using external FETs driven by
internal gate drivers. The charge voltage and current can be adjusted via data flash values to account for the
temperature and voltage of the battery cells, allowing for a JEITA type charge profile. The voltage and current
may also be directly written to the charge controller from an external host, allowing for a user-defined charging
profile. The charger runs in Narrow Voltage DC, that is, the output voltage of the charger will only exceed the
battery voltage by a small amount; by contrast, a charger that does not run in Narrow Voltage DC mode will
output the adapter voltage to the system.
The charger is designed to enable the system to continue to run while the battery is charged. If the system
requires more current than the charger is able to provide, the battery supplements the current to the system. The
charger can support an external precharge FET, allowing the VSYS to remain above a minimum voltage needed
for the system to operate.
The charger supports precharge, constant current/constant voltage, and termination, as shown below. The
voltage and current thresholds for precharge and termination are controlled by data flash values. Refer to the
bq40z60 Technical Reference Manual (SLUUA04) for more information.
Figure 5. Normal Charge Profile
Power
GND
AC
FET
ACFET HIDRV LODRV HSRP HSRN FB
VCC
CHG
DSG
FET
CHG
FET
ACP
BAT
Charger PWM
Control
Charger
Current Sense DSG
Protection
FET
Control
Zero Volt
Charge Enable
SRPSRN
Adapter
RCHG R1R2
Pack–
IADAPTER
Path IBAT
Path
RSNS
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Feature Description (continued)
The charger maintains a cycle-by-cycle current limit by sensing across a resistor in series with the inductor
(shown in Figure 6 as RCHG). In precharge and constant voltage, the DC current is regulated by sensing the
current across the sense resistor at the bottom on of the cell stack. When the charger is enabled, the initial
current is set for either the Precharge or Constant Current/Constant Voltage (CC/CV) value, based on the
minimum cell voltage. Once the charger enters CONSTANT CURRENT mode, the temperature and maximum
cell voltage-adjusted–charging current is set, and the voltage output of the charger is automatically regulated to
maintain the current across RCHG. Once the temperature-adjusted voltage is reached by the charger output, the
current starts to taper.
Throughout the charge cycle, the current available from the charger is limited by the ChargingCurrent() value.
The system draws more current, however, with the battery supplementing the difference. Once battery charging
is terminated, the charger is capable of supplying all of the current defined by the Advanced Charge
Algorithm:Maximum Current Register value. Refer to the bq40z60 Technical Reference Manual (SLUUA04) for
more information.
Figure 6 shows the system power path with the adaptor current and battery current overlaid. Further information
is available in Application and Implementation.
Figure 6. Power Path Overview
8.3.3.1 Precharge Modes
The charge controller is designed to allow for both internal precharge control and external precharge control. The
device can operate in precharge with external FETs and a current limiting resistor. Refer to the bq40z60
Technical Reference Manual (SLUUA04) for more information.
8.3.3.2 Zero-Volt Charge Support
This mode of operation is similar to PRECHARGE mode switched charging, but with the charge FET operation in
the saturation region. The NVDC out is connected to the CHG gate drive output internally to allow for precharge
current from the charger through the CHG FET. This current is limited based on the value of the external Rsense
(10-mΩresistor the lowest precharge current = 200 mA). This will increase the power dissipation of the charge
FET and will require thermal heat management and protection to ensure correct operation.
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Feature Description (continued)
8.3.3.3 Charge Termination
Once the highest cell voltage reaches the value specified in the data flash, the charger output voltage will no
longer increase and the current will start to taper. Once the highest cell voltage is within the Charge Term
Voltage window and the measured current is below Charge Term Taper Current for 40 s or more, the charger
will terminate by disabling the CHG FET and setting the appropriate flags. Refer to the bq40z60 Technical
Reference Manual (SLUUA04) for more information.
The system can still provide load current from the battery pack if the adaptor current cannot support the system
load. The diode of the CHG FET starts to conduct as the system voltage decreases to a point where the pack
voltage is greater than the system regulation voltage – Vdiode. If the average discharge current is high, the system
can turn ON the CHG FET for improved efficiency and minimized line losses during the discharge phase.
8.3.4 Fuel Gauge and Control Details
The bq40z60 uses the Impedance Track™ algorithm to measure and calculate the available capacity in battery
cells. The bq40z60 accumulates a measure of charge and discharge currents and compensates the charge
current measurement for the temperature and state-of-charge of the battery. The bq40z60 estimates self-
discharge of the battery and also adjusts the self-discharge estimation based on temperature. The device also
has TURBO BOOST mode support, which enables the bq40z60 to provide the necessary data for the MCU to
determine what level of peak power consumption can be applied without causing a system reset or a transient
battery voltage level spike to trigger termination flags. See the bq40z60 Technical Reference Manual (SLUUA04)
for further details.
8.3.4.1 Battery Trip Point (BTP)
Required for WIN8 OS, the Battery Trip Point (BTP) feature indicates when the RSOC of a battery pack has
depleted to a certain value set in a DF register. This feature allows a host to program two capacity-based
thresholds that govern triggering a BTP interrupt on the BTP_INT pin, and setting or clearing the
OperationStatus[BTP_INT] on the basis of RemainingCapacity().
An internal weak pullup is applied when the BTP feature is active. Depending on the system design, an external
pullup may be required to put on the BTP_INT pin. See High-Voltage General Purpose I/O (GPIO0, GPIO1) for
details.
8.3.4.2 Lifetime Data Logging Features
The bq40z60 offers lifetime data logging for several critical battery parameters. The following parameters are
updated every 10 hours if a difference is detected between values in RAM and data flash:
• Maximum and Minimum Cell Voltages
• Maximum Delta Cell Voltage
• Maximum Charge Current
• Maximum Discharge Current
• Maximum Average Discharge Current
• Maximum Average Discharge Power
• Maximum and Minimum Cell Temperature
• Maximum Delta Cell Temperature
• Maximum and Minimum Internal Sensor Temperature
• Maximum FET Temperature
• Number of Safety Events Occurrences and the Last Cycle of the Occurrence
• Number of Valid Charge Termination and the Last Cycle of the Valid Charge Termination
• Number of Qmax and Ra Updates and the Last Cycle of the Qmax and Ra Updates
• Number of Shutdown Events
• Cell Balancing Time for Each Cell
(This data is updated every 2 hours if a difference is detected.)
• Total FW Runtime and Time Spent in Each Temperature Range
(This data is updated every 2 hours if a difference is detected.)
!"#$%&$
!"#
!"#$
%&'(
)*+
',-./,0
$!%
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Feature Description (continued)
8.3.5 Authentication
The bq40z60 supports authentication by the host using SHA-1. More information about the algorithm can be
found in the bq40z60 Technical Reference Manual (SLUUA04).
8.3.6 LED Display
The bq40z60 can drive a 4-segment LED display for remaining capacity indication and/or a permanent fail (PF)
error code indication.
8.3.7 Internal Temperature Sensor
An internal temperature sensor is available on the bq40z60 to reduce the cost, power, and size of the external
components necessary to measure temperature. It is available for connection to the ADC using the multiplexer,
and is ideal for determining pack temperature during storage and IC temperature during normal operation.
8.3.8 External Temperature Sensor Support
Each of the TSx input pins can be enabled with an 18-kΩ(Typ.) linearization pullup resistor to support using a 10
kΩ(25°C) NTC external thermistor, such as the Semitec 103AT–2. One or more thermistors can be connected
between VSS and the individual RCx pin. The analog measurement is then taken via the ADC through its input
multiplexer. If a different thermistor type is required, then changes to the external support components may be
required.
Figure 7. Thermistor Pin Configuration
8.3.9 High Frequency Oscillator
The bq40z60 includes a high frequency oscillator (HFO) running at 16.78 MHz. It is synthesized from the LFO
output and scaled down to 8.388 MHz with 50% duty cycle. There is no need for external oscillator components.
8.3.10 Communications
The bq40z60 uses SMBus v1.1 with MASTER mode and packet error checking (PEC) options per the SBS
specification.
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Feature Description (continued)
8.3.10.1 SMBus On and Off State
The bq40z60 detects an SMBus off state when SMBC and SMBD are low for two or more seconds. Clearing this
state requires that either SMBC or SMBD transition high. The communication bus will resume activity within
1 ms.
8.3.10.2 SBS Commands
The ManufacturerAccess() Command List shows the supported Manufacturer Access and SBS commands. See
the bq40z60 Technical Reference Manual (SLUUA04) for further details.
Table 1. ManufacturerAccess() Command List
FUNCTION MANUFACTURER
ACCESS
COMMAND
SBS
COMMAND ACCESS FORMAT DATA READ ON
0x44 OR 0x23 AVAILABLE IN
SEALED MODE
DeviceType 0x0001 R Block Yes Yes
FirmwareVersion 0x0002 R Block Yes Yes
HardwareVersion 0x0003 R Block Yes Yes
IFChecksum 0x0004 R Block Yes Yes
StaticDFSignature 0x0005 R Block Yes Yes
ChemID 0x0006 R Block Yes Yes
StaticChemDFSignature 0x0008 R Block Yes Yes
AllDFSignature 0x0009 R Block Yes Yes
ShutdownMode 0x0010 W — — Yes
SleepMode 0x0011 W — — —
AutoCCOfset 0x0013 W — — —
FuseToggle 0x001D W — — —
PrechargeFET 0x001E W — — —
ChargeFET 0x001F W — — —
DischargeFET 0x0020 W — — —
Gauging 0x0021 W — — —
FETControl 0x0022 W — — —
LifetimeDataCollection 0x0023 W — — —
PermanentFailure 0x0024 W — — —
BlackBoxRecorder 0x0025 W — — —
Fuse 0x0026 W — — —
LifetimeDataReset 0x0028 W — — —
PermanentFailureData
Reset 0x0029 W — — —
LifetimeDataFlush 0x002E W — — —
LifetimeDataSpeedUp
Mode 0x002F W — — —
BlackBoxRecorderReset 0x002A W — — —
CalibrationMode 0x002D W — — —
SealDevice 0x0030 W — — —
SecurityKeys 0x0035 R/W Block Yes —
AuthenticationKey 0x0037 R/W Block — —
DeviceReset 0x0041 W — — —
SafetyAlert 0x0050 0x50 R Block Yes Yes
SafetyStatus 0x0051 0x51 R Block Yes Yes
PFAlert 0x0052 0x52 R Block Yes Yes
PFStatus 0x0053 0x53 R Block Yes Yes
OperationStatus 0x0054 0x54 R Block Yes Yes
ChargingStatus 0x0055 0x55 R Block Yes Yes
GaugingStatus 0x0056 0x56 R Block Yes Yes
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Feature Description (continued)
Table 1. ManufacturerAccess() Command List (continued)
FUNCTION MANUFACTURER
ACCESS
COMMAND
SBS
COMMAND ACCESS FORMAT DATA READ ON
0x44 OR 0x23 AVAILABLE IN
SEALED MODE
ManufacturingStatus 0x0057 0x57 R Block Yes Yes
AFERegister 0x0058 0x58 R Block Yes Yes
LifetimeDataBlock1 0x0060 0x60 R Block Yes Yes
LifetimeDataBlock2 0x0061 0x61 R Block Yes Yes
LifetimeDataBlock3 0x0062 0x62 R Block Yes Yes
ManufacturerInfo 0x0070 0x70 R Block Yes Yes
DAStatus1 0x0071 0x71 R Block Yes Yes
DAStatus2 0x0072 0x72 R Block Yes Yes
GaugeStatus1 0x0073 0x73 R Block Yes Yes
GaugeStatus2 0x0074 0x74 R Block Yes Yes
GaugeStatus3 0x0075 0x75 R Block Yes Yes
StateofHealth 0x0077 R Block Yes Yes
CHGR_EN 0x00C0 W — — No
CVRD_ARM 0x00C1 W — — Yes
ACFETEST 0x00C2 W — — No
CHGONTEST 0x00C3 W — — No
ROMMode 0x0F00 W — — —
ExitCalibrationOutput 0xF080 R/W Block Yes —
OutputCCandADCfor
Calibration 0xF081 R/W Block Yes —
OutputShortedCCand
ADCforCalibration 0xF082 R/W Block Yes —
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The bq40z60 is a monolithic charger and gas gauge solution for multi-cell battery packs. By integrating these
devices, software control can be handed off from the host microcontroller to the gas gauge controller, providing
for potential energy savings that correlate to runtime.
0.1µF
C3
0.1µF
C6
0.1µF
C8
0.1µF
C9
0.1µF
C11
GND
GND
GND 0.1µF
C4
GND
1.0k
R12
1.0k
R13
1.0k
R16
1.0k
R19
100
R4
5.1k
R5
0.1µF
C10
0.1µF
C1
0.1µF
C2
GND GND
5.1k
R11
5.1k
R10
10Meg
R2
10Meg
R3
5
4
1
2
3
J3
0.1µF
C21
0.1µF
C22
0.1µF
C23
GND
10
R25
0.005
R43
0.1µF
C26
2.2µF
C20
1µF
C24
GND
GND
PGND
GND GND GND
100
R30
100
R32
100
R35
100
R37
100
R33
100
R42
100
R36
100
R41
5.6V
D2
5.6V
D5
1.0k
R34
TP2
PGND 4
1
2
3
J6
100
R40
100
R39
5.6V
D4
10k
R14
10Meg
R8
5.1k
R15
0.01
R20
2.2µF
C5
2.0
R7
100k
R6
0.1µF
C17
0.1µF
C16
5.1k
R22
0.1µF
C25
30V
D3
1.5µF
C27
22pF
C15
GND
PGND
1
23
Q4
PGND
GND
GND
GND
PGND PGND
Alert /BTP
PGND
PGND
GND
12
34
56
J4
2-Cell
3-Cell
4-Cell
332k
R21
26.1k
R26
9.53k
R27
20.5k
R28
78.7k
R29
Vfb = 0.66 to 1.22V
VDD
1
V4
2
V3
3
V2
4V1 5
VSS 6
CD 7
OUT 8
PAD
U1 BQ294700DSG
VAC
SYSPRES
SMBD
SMBC
Green
D9
Green
D8
Green
D7
Green
D6
50V
1
2 3
Q13
BSS138
50V
1
2 3
Q11
BSS138
50V
1
2 3
Q12
BSS138
50V
1
2 3
Q10
BSS138
1.0k
R50
1.0k
R51
1.0k
R52
1.0k
R53
GND
GND
1µF
C32
1µF
C33
1µF
C34
1µF
C31
20
R1
1.00Meg
R9
OUTPUT 1
SENSE 2
SHUTDOWN
3GND 4
ERROR 5
VTAP
6FEEDBACK
7
INPUT
8
U3
LP2951-33DRG4
4P
GND GND
3.3V
1µF
C28
100pF
C30
332k
R54
3.3V 3.3V 3.3V 3.3V
VCC
4
1
3
2
S1
GND
LED Display
330k
R49
330k
R45
330k
R46
330k
R47
1
LED regulator is not required for single cell applications
2
Replace D1 with a 10 ohm resistor for single cell applications
1
2
Place filter components as close to the bq40z60 as possible.
3
3
30V
D1
1µF
C18
GND
50V
1
2 3
Q7
BSS138
4
7,8
1,2,3
5,6,
Q2
4
7,8 1,2,3
5,6,
Q3
4
7,8
1,2,3
5,6,
30V
Q8
CSD17308Q3
4
7,8
1,2,3
5,6,
30V
Q9
CSD17308Q3
499k
R17
4
7,8 1,2,3
5,6,
Q5
3
1
2
-30V
Q1 FDN358P
1
4
3
2
F1
1
2 3
Q6
VSYS
TP3
GND
20k
R18
4
1
3
2
S2
VAC
4P
0
R23
0
R24
PGND
10.0k ohm
t°
RT4
10.0k ohm
t°
RT1
10.0k ohm
t°
RT2
10.0k ohm
t°
RT3
1
2
3
J2
0
R48
4P
TP1
L1
10µF
C7
10µF
C12
10µF
C13
10
R31
2.2µF
C29
0.1µF
C19
0.1µF
C14
5.1k
R55
BAT 1
PBI 2
VC4
3
VC3
4
VC2
5
VC1
6
SRN
7SRP
8
VSS
9
TS1
10
TS2
11
TS3
12
TS4
13
GPIO0
14
GPIO1
15
SMBD 16
SMBC 17
VFB 18
HSRN 19
HSRP 20
AFEFUSE
21
VCC 22
REGN 23
PGND
24
LODRV 25
PH 26
HIDRV 27
BTST 28
ACFET 29
DSG 30
ACP 31
CHG 32
PAD
33
U2
bq40z60RHBT/bq40z60RHBR
10µF
C35
J5
PGND
1
2
J7
PGND
100pF
C36
4
1
2
3
J1
0
R38
0
R44
Copyright © 2017, Texas Instruments Incorporated
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9.2 Typical Applications
Figure 8. Typical Application Schematic
CIN CHG
I = I D (1 D)´ ´ -
IN
RIPPLE
S
V D (1 D)
I = f L
´ ´ -
´
SAT CHG RIPPLE
I I + (1/2) I³
31
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Typical Applications (continued)
NOTE
The feedback resistor to VFB from charging output will have different values based on the
number of series cells configured for charging the pack.
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
Design Parameter Example Value
Input Voltage Range 15–22 V
3-Cell Battery Voltage Range 9 V–12.6 V
4-Cell Battery Voltage Range 12 V–16.8 V
Operating Frequency 1000 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The bq40z60 has a 1000-kHz switching frequency to allow the use of small inductor and capacitor values.
Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
(1)
The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fs) and
inductance (L):
(2)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging
voltage range is from 9 V to 12.6 V for a 3-cell battery pack. For 20-V adaptor voltage, 10-V battery voltage gives
the maximum inductor ripple current. Another example is a 4-cell battery: The battery voltage range is from 12 V
to 16.8 V, and 12-V battery voltage gives the maximum inductor ripple current.
Usually inductor ripple is designed in the range of (20%–40%) maximum charging current as a trade-off between
inductor size and efficiency for a practical design.
The bq40z60 has cycle-by-cycle charge undercurrent protection (UCP) by monitoring the charging-current
sensing resistor to prevent negative inductor current. The typical UCP threshold is 5-mV falling edge
corresponding to 0.5-A falling edge for a 10-mΩcharging-current sensing resistor.
9.2.2.2 Input Capacitor
The input capacitor should have enough ripple-current rating to absorb input switching ripple current. The worst-
case RMS ripple current is half of the charging current when the duty cycle is 0.5. If the converter does not
operate at 50% duty cycle, then the worst-case capacitor RMS current ICIN occurs where the duty cycle is closest
to 50% and can be estimated using the following equation:
(3)
A low-ESR ceramic capacitor such as X7R or X5R is preferred for the input-decoupling capacitor and should be
placed to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. The
voltage rating of the capacitor must be higher than the normal input voltage level. A 25-V or higher-rating
capacitor is preferred for 20-V input voltage. 10-µF to 20-µF capacitance is suggested for typical of 3-A to 4-A
charging current.
2
bottom CHG DS(on)
P = (1 D) I R- ´ ´
REG N plt plt
on off
on off
V V V
I = , I =
R R
-
SW GD GS
1
Q = Q + Q
2
´
SW SW
on off
on off
Q Q
t = , t =
I I
( )
2
top CHG DS(on) IN CHG on off S
1
P = D I R + V I t + t f
2
´ ´ ´ ´ ´ ´
top DS(on) G D bottom D S(on) G
FOM = R Q FOM = R Q´ ´
æ ö
D = -
ç ÷
ç ÷
è ø
2
BAT
o BAT
2
IN
s
V
1
V V
V
8LCf
RIPPLE
COUT RIPPLE
I
I = 0.29 I
2 3
» ´
´
32
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9.2.2.3 Output Capacitor
Output capacitor also should have enough ripple-current rating to absorb the output switching ripple current. The
output capacitor RMS current ICOUT is given:
(4)
The output capacitor voltage ripple can be calculated as follows:
(5)
At a certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC. The bq40z60 has an internal loop compensator. To get good loop stability, the resonant
frequency of the output inductor and output capacitor should be designed between 21 kHz and 27 kHz. The
preferred ceramic capacitor has a 25-V or higher rating, X7R or X5R for a 4-cell application.
9.2.2.4 Power MOSFETs Selection
Two external N-CH MOSFETs are used for a synchronous switching battery charger. The gate drivers are
internally integrated into the IC with 6 V of gate drive voltage. 30-V or higher voltage rating MOSFETs are
preferred for 20-V input voltage, and 40 V or higher-rating MOSFETs are preferred for 20-V to 28-V input
voltage.
Figure-of-merit (FOM) is usually used for selecting the proper MOSFET based on a tradeoff between the
conduction loss and switching loss. For a top-side MOSFET, FOM is defined as the product of the MOSFET on-
resistance, rDS(on), and the gate-to-drain charge, QGD. For a bottom-side MOSFET, FOM is defined as the product
of the MOSFET on-resistance, rDS(on), and the total gate charge, QG.
(6)
The lower the FOM value, the lower the total power loss. Usually a lower rDS(on) has a higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D =
VOUT/VIN), charging current (ICHG), the MOSFET on-resistance tDS(on)), input voltage (VIN), switching frequency
(fS), turn-on time (ton), and turn-off time (toff):
(7)
The first item represents the conduction loss. Usually MOSFET rDS(on) increases by 50% with 100°C junction
temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn-off times are
given by:
(8)
where Qsw is the switching charge, Ion is the turn-on gate-driving current, and Ioff is the turn-off gate driving
current. If the switching charge is not given in the MOSFET data sheet, it can be estimated by gate-to-drain
charge (QGD) and gate-to-source charge (QGS):
(9)
Total gate-driving current can be estimated by the REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total
turn-on gate resistance (Ron), and turn-off gate resistance (Roff) of the gate driver:
(10)
The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous continuous-conduction mode:
(11)
R1
2 Ω
C1
2.2
D1
C2
0.1-1 µF
R2
1 Ω
Adapter
connector VCC pin
(2010)
(1206)
µF
ICLoss_driver IN g_total s
P V Q f= × ×
33
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If the HSRP–HSRN voltage decreases below 5 mV (the charger is also forced into non-synchronous mode when
the average HSRP–HSRN voltage is lower than 1.7 mV), the low-side FET is turned off for the remainder of the
switching cycle to prevent negative inductor current. As a result, all the freewheeling current goes through the
body diode of the bottom-side MOSFET. The maximum charging current in non-synchronous mode can be up to
1.6 A (0.5 A typ) for a 10-mΩcharging-current sensing resistor, considering IC tolerance. Choose the bottom-
side MOSFET with either an internal Schottky or body diode capable of carrying the maximum non-synchronous
mode charging current.
MOSFET gate-driver power loss contributes to the dominant losses on the controller IC when the buck converter
is switching. The combined high side and low side MOSFET gate charge, Qg_total, is proportional to the power
dissipation of the IC, as shown in Equation 12:
(12)
Choosing FETs with a lower Qg_total will reduce power loss.
9.2.2.5 Input Filter Design
During adaptor hot plug-in, the parasitic inductance and input capacitor from the adaptor cable form a second-
order system. The voltage spike at the VCC pin may be beyond the IC maximum voltage rating and damage the
IC. The input filter must be carefully designed and tested to prevent an overvoltage event on the VCC pin.
There are several methods for damping or limiting the overvoltage spike during adaptor hot plug-in. An
electrolytic capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC
maximum pin voltage rating. A high-current-capability TVS Zener diode can also limit the overvoltage level to an
IC safe level. However, these two solutions may not have low cost or small size.
Figure 9 shows a cost-effective and small size solution. The R1 and C1 are composed of a damping RC network
to damp the hot plug-in oscillation. As a result, the overvoltage spike is limited to a safe level. D1 is used for
reverse voltage protection for the VCC pin (it can be the body diode of input ACFET). C2 is a VCC pin-
decoupling capacitor and it should be placed as close as possible to the VCC pin. R2 and C2 form a damping
RC network to further protect the IC from high dv/dt and high-voltage spike. The C2 value should be less than
the C1 value so R1 can be dominant over the ESR of C1 to get enough of a damping effect for hot plug-in. The
R1 and R2 packages must be sized to handle inrush-current power loss according to the resistor manufacturer’s
datasheet. The filter component values always must be verified with the real application, and minor adjustments
may be needed to fit in the real application circuit.
Figure 9. Input Filter
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!'($$%)#
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9.2.3 Application Curves
1 A/div (on both channels)
4 s/div Timescale
Figure 10. Battery Current with Load Steps
10 V/div
400 ns/div Timescale
Figure 11. Charge Controller Phase (Switch) Node
Operation During Constant Current Charging
10 Power Supply Recommendations
The bq40z60 is designed to operate from a well-regulated input voltage supply range between 4.0 V and 25 V;
however, with a multi-cell pack, the input voltage should be a minimum of 1 V above the maximum stack voltage.
If the input supply is more than a few inches from the bq40z60, additional bulk capacitance in the form of a 47-µF
electrolytic capacitor should be used.
11 Layout
11.1 Layout Guidelines
The following information is related to external component selection and guidelines for PCB layout.
11.1.1 PCB Layout
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high-frequency current-path loop (see Figure 12) is important to prevent electrical and
magnetic field radiation and high-frequency resonant problems. The following is a PCB layout priority list for
proper layout. Layout of the PCB according to this specific order is essential.
1. Place the input capacitor as close as possible to the switching MOSFET supply and ground connections and
use the shortest possible copper trace connection. The capacitors should be placed on the same layer as the
FETs instead of using vias to connect the capacitor and the FETs. Additionally, any vias connecting the input
capacitor to the adaptor node should not be placed between the capacitor and the FETs; the capacitor
should have a solid copper path to the FET.
2. The IC should be placed close to the switching MOSFET gate pins to keep the gate-drive signal traces short
for a clean MOSFET drive. The IC can be placed on the other side of the PCB from the switching MOSFETs.
3. Place the inductor input pin as close as possible to the switching MOSFET output pin. Minimize the copper
area of this trace to lower electrical and magnetic field radiation, but make the trace wide enough to carry the
charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance
from this area to any other trace or plane.
4. The charging-current sensing resistor should be placed right next to the inductor output. Route the sense
Current Direction
To SRP – SRN pin or HSRP – HSRN pin
RSNS
Current Sensing Direction
High
Frequency
Current
Path
L1 R1
C3
C1 C2
PGND
SW VBAT
BAT
VIN
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Layout Guidelines (continued)
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
area) and do not route the sense leads through a high-current path (see Figure 13 for Kelvin connection for
best current accuracy). Place the decoupling capacitor on these traces next to the IC.
5. Place the output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Place the sense resistor and filter components, R1, C2, and C3, as close as possible to the IC and directly
adjacent to the decoupling capacitor between HSRN and HSRP.
8. Route the analog ground separately from the power ground and use a single ground connection to tie the
charger power ground to the charger analog ground. Just beneath the IC, use the copper-pour for analog
ground, but avoid power pins to reduce inductive and capacitive noise coupling. Connect analog ground to
GND. Connect analog ground and power ground together using the thermal pad as the single ground
connection point. Or use a 0-Ωresistor to tie analog ground to power ground (thermal pad should tie to
analog ground in this case). A star connection under the thermal pad is highly recommended.
9. It is critical that the exposed thermal pad on the back side of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC connecting to the ground plane on the other
layers.
10. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
11. Size and number of all vias should be enough for a given current path.
Figure 12. High-Frequency Current Path
Figure 13. Sensing Resistor PCB Layout
For the recommended component placement with trace and via locations, see the bq40z60EVM SBS 1.1
Impedance Track™ Technology Enabled Battery Management Solution Evaluation Module User's Guide
(SLUUB71).
For the QFN information, see the Quad Flatpack No-Lead Logic Packages Application Note (SCBA017) and the
QFN/SON PCB Attachment Application Note (SLUA271).
!
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"
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'
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!
!
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$,-
#.!/
#.!,
/#
/#
$,-
/0'1*234(5)21'(21067*2)62#.289:2;3)<2
462=3'72>*);**4?
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#.!/D#.!,21644*1)3647
36
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11.2 Layout Example
Figure 14. Board Layout Example
37
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12 Device and Documentation Support
12.1 Related Documentation
For related documentation, see the bq40z60 Technical Reference Manual (SLUUA04).
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
Impedance Track, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
BQ40Z60RHBR ACTIVE VQFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ40Z60
BQ40Z60RHBT ACTIVE VQFN RHB 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ40Z60
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Dec-2016
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BQ40Z60RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
BQ40Z60RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Dec-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ40Z60RHBR VQFN RHB 32 3000 367.0 367.0 35.0
BQ40Z60RHBT VQFN RHB 32 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Dec-2016
Pack Materials-Page 2
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and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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