4.75VCover 88PH8101 Field Programmable, High Voltage Synchronous Switching Regulator Controller Datasheet Doc. No. MV-S103978-01, Rev. - February 4, 2009 Marvell. Moving Forward Faster Document Classification: Proprietary 88PH8101 Datasheet Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: 2.00 Technical Publication: 0.xx For more information, visit our website at: www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. 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No. MV-S103978-01 Rev. - Page 2 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 88PH8101 Field Programmable, High Voltage Synchronous Switching Regulator Controller PRODUCT OVERVIEW The Marvell(R) 88PH8101 is a simple, easy to use synchronous switching regulator controller. A digital control algorithm provides a fast transient response and requires no external compensation components, minimizing the external component count. A feature unique with Marvell regulators is the ability to set the output voltage with either an external resistor, logic programmability, or serial interface. Features Portable devices place tough design requirements on the power supply. To address these applications, the 88PH8101 operates as a fixed-frequency PWM when the load currents are high and automatically switches over to a pulse-skipping DCM mode at light loads. This characteristic results in high efficiency over a wide range of load currents. Current limit utilizes the RDS(ON) of the upper MOSFET eliminating the need for a current sense resistor. Other key features of the 88PH8101 include soft start, short detection, under/over input voltage detection, diode emulation, forced PWM mode, adaptive dead time, and a power good signal. Operates from a 4.75V to 16V input Output voltage from 0.9V to 5.5V 500kHz switching frequency Stable with low-ESR ceramic output capacitors Up to 95% efficiency Drives N-channel MOSFETs Upper MOSFETs RDS (on) current limiting 2.5mA quiescent current (DCM-mode) Pre-bias Soft Start (DCM-Mode) Serial / Logic Programmability AnyVoltageTM Technology provides 72 output voltage selections to provide up most flexibility Input over voltage protection Output voltage margining capability Lead-free package TSSOP-16L package Applications Point-of-load power supplies 12V PCI Express Bus Figure 1: Typical Application Diagram for High Efficiency Step-Down Regulator VIN 12V C5 NOB U1 1 EN VIN 16 C4 10uF/25 V 2 PSET CSH VSET VSW 15 C3 10uF/25 V 3 R3 0 Ohm 14 88PH8101 R4 470k 4 C6 0.1uF R1 43k ILIM TG 13 Q1 IRF7821 C2 5 SFB VBS GND VCC 12 0.22 uF 6 4.2 uH 11 V OUT 5V/5A L1 C1 4.7uF 7 R2 100K PG Caution! 8 PWM/SDI PG BG PGND 10 Q2 IRF7832 C9 47uF/6.3V C10 47uF/6.3V C 11 47uF/6.3V C12 47uF/6.3V 9 Caution: This is a very high frequency device. Proper PCB layout is required. Section 6.1, PC Board Layout Considerations and Guidelines, on page 45. Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 3 88PH8101 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103978-01 Rev. - Page 4 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Table of Contents Table of Contents Table of Contents ....................................................................................................................................... 5 List of Figures............................................................................................................................................. 7 List of Tables .............................................................................................................................................. 9 1 Signal Description ....................................................................................................................... 11 1.1 Pin Configuration.............................................................................................................................................11 1.2 Pin Descriptions ..............................................................................................................................................11 2 Electrical Specifications ............................................................................................................. 15 2.1 Absolute Maximum Ratings ............................................................................................................................15 2.2 Recommended Operating Conditions .............................................................................................................16 2.3 Electrical Characteristics .................................................................................................................................16 2.4 Switching Step-down Regulator ......................................................................................................................18 3 Functional Description................................................................................................................ 21 3.1 Overview .........................................................................................................................................................21 3.2 Regulation and Start-up ..................................................................................................................................22 3.3 Soft Start .........................................................................................................................................................23 3.4 Output Voltage Setting ....................................................................................................................................23 3.4.1 Logic Programmability ......................................................................................................................23 3.4.2 Serial Programmability......................................................................................................................24 3.5 Output Voltage--AnyVoltageTM Technology ...................................................................................................26 3.6 Thermal Shutdown ..........................................................................................................................................28 3.7 PFM or PWM Mode Selection .........................................................................................................................28 3.8 Under Voltage Lockout (UVLO) ......................................................................................................................28 3.9 Over Voltage Protection (OVP) .......................................................................................................................28 3.10 Power Good (PG)............................................................................................................................................29 3.11 Hiccup Current Limit........................................................................................................................................29 4 Functional Characteristics ......................................................................................................... 31 4.1 Startup Waveforms .........................................................................................................................................31 4.2 Switching Waveforms......................................................................................................................................32 4.3 Load Transient Waveforms .............................................................................................................................34 4.3.1 Step-Down Regulator ......................................................................................................................34 4.4 Output Voltage Transient Waveforms .............................................................................................................36 4.4.1 Step-Down Regulator .......................................................................................................................36 Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 5 88PH8101 Datasheet 5 Typical Characteristics ............................................................................................................... 37 5.1 Efficiency .........................................................................................................................................................37 5.2 IC Case, MOSFET, and Inductor Temperature...............................................................................................37 5.3 Input Voltage ..................................................................................................................................................40 5.3.1 Step-down Regulator ........................................................................................................................41 5.4 Temperature....................................................................................................................................................42 5.4.1 Step-down Regulator ......................................................................................................................43 6 Applications Information ............................................................................................................ 45 6.1 PC Board Layout Considerations and Guidelines ...........................................................................................45 6.1.1 PC Board Layout Example ...............................................................................................................47 6.1.2 Bill of Materials .................................................................................................................................51 7 Mechanical Drawings .................................................................................................................. 53 7.1 Mechanical Drawing ........................................................................................................................................53 7.2 Mechanical Dimensions ..................................................................................................................................54 7.3 Typical Pad Layout Dimensions ......................................................................................................................55 7.3.1 Recommended Solder Pad Layout ...................................................................................................55 8 Part Order Numbering / Package Marking ................................................................................ 57 8.1 Part Order Numbering Scheme.......................................................................................................................57 8.2 Part Ordering Options .....................................................................................................................................57 8.3 Package Marking ............................................................................................................................................58 A Revision History .......................................................................................................................... 59 Doc. No. MV-S103978-01 Rev. - Page 6 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 List of Figures List of Figures Figure 1: 1 Typical Application Diagram for High Efficiency Step-Down Regulator ..............................................3 Signal Description ........................................................................................................................... 11 Figure 2: TSSOP-16 Diagram (Top View) .......................................................................................................11 2 Electrical Specifications ................................................................................................................. 15 3 Functional Description.................................................................................................................... 21 4 5 Figure 3: Block Diagram ..................................................................................................................................21 Figure 4: Output Voltage Window ....................................................................................................................22 Figure 5: Soft Startup (1V, 1.5V, 2.5V, 3.3V, 5V) ............................................................................................23 Figure 6: Serial Programmability......................................................................................................................24 Figure 9: Power Good Operating Waveform....................................................................................................29 Functional Characteristics.............................................................................................................. 31 Figure 10: Startup Using the Enable Pin ...........................................................................................................31 Figure 11: Turn Off Using the Enable Pin ..........................................................................................................31 Figure 12: Soft Start ..........................................................................................................................................31 Figure 13: Hot Plug ............................................................................................................................................31 Figure 14: PWM Mode ......................................................................................................................................32 Figure 15: PWM Mode ......................................................................................................................................32 Figure 16: DCM Mode .......................................................................................................................................32 Figure 17: DCM Mode-zoom..............................................................................................................................32 Figure 18: PWM Output Ripple Figure 19: Fast Load Rise Time ........................................................................................................................34 Figure 20: Slow Load Rise Time ........................................................................................................................34 Figure 21: Fast Load Fall Time .........................................................................................................................34 Voltage .........................................................................................................33 Figure 22: Slow Load Fall Time .........................................................................................................................34 Figure 23: Load Transient Response ................................................................................................................35 Figure 24: Double-Pulsed Load Response ........................................................................................................35 Figure 25: Load Transient Response ................................................................................................................35 Figure 26: Double-Pulsed Load Response ........................................................................................................35 Figure 27: VOUT = 1.0V to 1.2V with ILoad = 0A ...............................................................................................36 Figure 28: VOUT = 1.0V to 1.5V with ILoad = 0A................................................................................................36 Typical Characteristics ................................................................................................................... 37 Figure 29: Efficiency vs. Output Current ............................................................................................................37 Figure 30: Efficiency vs. Output Current in Log Scale .......................................................................................37 Figure 31: Input Current vs. Output Current ......................................................................................................38 Figure 32: IC Case Temperature vs. Output Current .........................................................................................38 Figure 33: Top FET Temperature vs. Output Current ........................................................................................38 Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 7 88PH8101 Datasheet 6 7 8 Figure 34: Bottom FET Temperature vs. Output Current...................................................................................39 Figure 35: Inductor Temperature vs. Output Current .........................................................................................39 Figure 36: Supply Current vs. Input Voltage ......................................................................................................40 Figure 37: Shutdown Supply Current vs. Input Voltage .....................................................................................40 Figure 38: Enable Threshold vs. Input Voltage ..................................................................................................40 Figure 39: Output Voltage vs. Input Voltage ......................................................................................................41 Figure 40: Efficiency vs. Input Voltage...............................................................................................................41 Figure 41: Load Regulation vs. Input Voltage ....................................................................................................41 Figure 42: Frequency vs. Input Voltage .............................................................................................................41 Figure 43: Average Output Current Limit vs. Input Voltage ...............................................................................41 Figure 44: Supply Current vs. Temperature.......................................................................................................42 Figure 45: UVLO Threshold vs. Temperature ....................................................................................................42 Figure 46: OVP Threshold vs. Temperature ......................................................................................................42 Figure 47: Enable Threshold vs. Temperature ..................................................................................................42 Figure 48: Shutdown Supply Current vs. Temperature......................................................................................42 Figure 49: Output Voltage vs. Temperature.......................................................................................................43 Figure 50: Efficiency vs. Temperature ...............................................................................................................43 Figure 51: Load Regulation vs. Temperature ....................................................................................................43 Figure 52: Line Regulation vs. Temperature......................................................................................................43 Figure 53: Frequency vs. Temperature..............................................................................................................43 Figure 54: Average Output Current Limit vs. Temperature ................................................................................43 Applications Information ................................................................................................................ 45 Figure 55: PCB Board Schematic ......................................................................................................................46 Figure 56: Top Silk-Screen, Top Traces, Vias, and Copper (Not to Scale) .......................................................47 Figure 57: GND_Layer2 Vias, and Copper (Not to Scale) .................................................................................48 Figure 58: GND_Layer3 Vias, and Copper (Not to Scale) .................................................................................49 Figure 59: Bottom Silk Screen, Bottom Traces, Vias, and Copper (Not to Scale) .............................................50 Mechanical Drawings ...................................................................................................................... 53 Figure 60: 16-Pin TSSOP Mechanical Drawing .................................................................................................53 Figure 61: TSSOP-16 Land Pattern (mm) .........................................................................................................55 Part Order Numbering / Package Marking..................................................................................... 57 Figure 62: Sample Part Number ........................................................................................................................57 Figure 63: Package Marking and Pin 1 Location ...............................................................................................58 Doc. No. MV-S103978-01 Rev. - Page 8 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 List of Tables List of Tables 1 2 3 Signal Description ............................................................................................................................ 11 Table 1: Pin Types ..........................................................................................................................................11 Table 2: Pin Descriptions ................................................................................................................................12 Electrical Specifications .................................................................................................................. 15 Table 3: Absolute Maximum Ratings ..............................................................................................................15 Table 4: Recommended Operating Conditions...............................................................................................16 Table 5: Electrical Characteristics ..................................................................................................................16 Table 6: Switching Step-down Regulator........................................................................................................18 Functional Description..................................................................................................................... 21 Table 7: Output Voltage Setting......................................................................................................................23 Table 8: Default Value of Data Field ...............................................................................................................24 Table 9: Voltage and Percent Set ...................................................................................................................25 Table 10: VSET and PSET Programming Table for 5% Resistors ...................................................................26 Table 11: Number of Voltage Steps for Each Output .......................................................................................27 4 Functional Characteristics............................................................................................................... 31 5 Typical Characteristics .................................................................................................................... 37 6 Applications Information ................................................................................................................. 45 Table 12: 7 Mechanical Drawings ....................................................................................................................... 53 Table 13: 8 BOM..................................................................................................................................................51 16-Pin TSSOP Dimensions ..............................................................................................................54 Part Order Numbering / Package Marking...................................................................................... 57 Table 14: Part Ordering Options .......................................................................................................................57 Table 15: Revision History ................................................................................................................................59 Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 9 88PH8101 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103978-01 Rev. - Page 10 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Signal Description Pin Configuration 1 Signal Description 1.1 Pin Configuration Figure 2: TSSOP-16 Diagram (Top View) 1.2 EN 1 16 VIN PSET 2 15 CSH VSET 3 14 VSW ILIM 4 13 TG SFB 5 12 VBS GND 6 11 VCC PWM/SDI 7 10 BG PG 8 9 Pin Descriptions Table 1: Pin Types P in Typ e D e f in it io n s I Input Only O Output Only S Supply NC Not Connected GND Ground Copyright (c) 2009 Marvell February 4, 2009, 2.00 PGND Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 11 88PH8101 Datasheet Table 2: Pin Descriptions Pi n # P in N a m e P in Ty pe Pi n F u nc t io n 1 EN I Enable Logic high (> 2.0V) enables the regulator and logic low (< 0.8V) disables the regulator. If the pin is left floating, an internal 10 A current source pulls this pin high to enable the regulator. (see Table 5, Electrical Characteristics, on page 16) Do not float this pin. 2 PSET I Percent Set 1. This is used for selecting the output voltage level when it is connected to GND or VCC in conjunction with VSET connection to GND or VCC. 2. Connect an external resistor to ground to set the output voltage of the step-down switching regulator. See Table 5, Electrical Characteristics, on page 16 for resistor values and Output Voltage Settings section. The total capacitance across this pin and GND should be equal to 25pF or less. Use resistor values with a tolerance of 5% tolerance or better. Do not float this pin. 3 VSET I Voltage Set 1. This is used for selecting the output voltage level, when it is connected to GND or VCC in conjunction with PSET connection GND or VCC. 2. Connect to an external resistor from VSET to GND to set eight nominal output voltages. See Table 11, Number of Voltage Steps for Each Output, on page 27. The total capacitance across this pin and GND should be equal to 25pF or less. Use resistor values with a tolerance of 5% tolerance or better. Do not float this pin. 4 ILIM I Current Limit Setting Point Connect a resistor to GND to set the peak current limit. ILIM = 0.2 * 20 A * REXT/RDSON (Top FET) 5 SFB I Switch Regulator Output Voltage Sense Feedback Senses the output voltage of the switching regulator. Connect to the output capacitor of the switching regulator. 6 GND GND Signal Ground This pin must be connected to PGND and make a star connection to system ground. 7 PWM/ SDI I PWM / Serial Data Input 1. Logic high (> 2.0V) enables PWM mode operation and logic low (< 0.8V) to enable DCM mode operation at light loads. If the pin is left floating, an internal 10A current source pulls this pin low, enabling DCM mode operation. 2. The input data into this pin is used to program the output voltage. See Section 3.4.2, Serial Programmability, on page 24. 3. Do not float this pin. 8 PG O Power Good (active high) This is an open-drain output that indicates the status of the output voltage. The output is pulled to ground when the output voltage is not within the specified tolerance. A 40s falling edge de-glitch delay prevents tripping of the power good comparator due to high frequency noise. Doc. No. MV-S103978-01 Rev. - Page 12 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Signal Description Pin Descriptions Table 2: Pin Descriptions Pi n # P in N a m e P in Ty pe Pi n F u nc t io n 9 PGND GND Power Ground It must be connected to the negative terminals of the input and output capacitors. 10 BG O Gate drive for bottom MOSFET This pin drives the bottom MOSFET gate between 0V and VCC. 11 VCC O Internal 5V Regulator Output Place a ceramic capacitor close to this pin. * For 5V input operation, the internal LDO is one VTH below VIN. The internal LDO is not disabled. The VCC pin is connected to VIN for better efficiency. 12 VBS I Boot-Strap Voltage Node Place a ceramic capacitor as close as possible to the VBS and VSW pins. 13 TG O Gate drive for top MOSFET This pin drives the top MOSFET gate between 0V and VIN + VCC 14 VSW I Switching Node This pin must be connected to the Source of top N-channel MOSFET using a Kelvin connection for more accurate current sensing. 15 CSH I High Side Current Sense Input This pin must be connected to the Drain of top N-channel MOSFET using a Kelvin connection for more accurate current sensing. 16 VIN S Internal LDO Input Power supply for internal LDO for generating VCC (5V). Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 13 88PH8101 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103978-01 Rev. - Page 14 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Electrical Specifications Absolute Maximum Ratings 2 Electrical Specifications 2.1 Absolute Maximum Ratings Table 3: Absolute Maximum Ratings1 NOTE: Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. P a r a m et e r R a ng e U n i ts VVIN to GND -0.3 to 20.0 V PGND to GND -0.3 to 0.3 V -0.3 to (VIN + 3.0) V -0.3 to Minimum (VIN + 0.3, 6.0) V VSW to PGND2 VVCC to GND VEN, VCSH to GND -0.3 to VIN V VVSET, VPSET to GND -0.3 to 6.0 V VSFB, VPG, VPWM/SDI, VILIM to GND -0.3 to 6.0 V VBG to PGND -0.3 to 6.0 V VTG to VSW -0.3 to 6.0 V -0.3 to 6.0 V -40 to 85 C 150 C -65 to 150 C 300 C 2.0 kV VBS to VSW3 Operating Ambient Temperature Range4 Maximum Junction Temperature Storage Temperature Range Lead Temperature (soldering, 10s) 5 ESD Rating Human Body Model 1. Exceeding the absolute maximum rating may damage the device. 2. Capable of -1.0V to (VIN +0.3) for less than 50ns. 3. During normal operation, VBS is periodically boosted to (VIN + VCC). However, do not externally force the VBS pin to more than (VCC + 0.3V). 4. Specifications over the -40C to 85C operating temperature ranges are assured by design, characterization and correlation with statistical process controls. 5. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF. Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 15 88PH8101 Datasheet 2.2 Table 4: Recommended Operating Conditions Recommended Operating Conditions1 S y m b ol Parameter VVIN Input Voltage JA Package Thermal Min Typ 4.75 Resistance2 JC TJMAX Max U n i ts 16 V 86.3 C/W 21.5 C/W Maximum Operating Junction Temperature 125 C 1. This device is not guaranteed to function outside the specified operating range. 2. Test on 4-layer (JESD51-7) and vias (JESD51-5) board. 2.3 Table 5: Electrical Characteristics Electrical Characteristics The following applies unless otherwise noted (refer to schematic shown in Figure 1): VVIN = VEN =12V, VPFM = GND, GND = PGND, VOUT = 5V, L1 = 4.2H, C1 = 4.7F, C2 = 0.22F, C3 = C4 = 10F, C6 = 0.1F, C9 = C10 = C11 = C12 = 47F, TA = 25C. Bold values indicate -40C < TA < 85C. S y m bo l Pa r am e te r VVIN Input Voltage Range IQ Total Quiescent Current (PFM Mode) IQ C o nd i ti on s M in Ty p Max Units 4.75 12 16 V No load, VPWM = 0V 2.5 5.8 mA Total Quiescent Current (PWM Mode) No load, VPWM = 5V 21 40 mA ISHDN Shutdown Supply Current VEN = 0V, VVIN = 12V 45 65 A VUVLO Under Voltage Lockout High Threshold, VVIN increasing 4.44 TBD V VUVLO Under Voltage Lockout Low Threshold, VVIN decreasing VOVP Over Voltage Protection High Threshold, VVIN increasing VOVP Over Voltage Protection Low Threshold, VVIN decreasing TOTS Over Temperature Shutdown TOTS TBD 4.35 17.5 18.5 V 16.7 V TJ increasing (Disable regulators) 150 C Over Temperature Shutdown TJ decreasing (Enable regulators) 100 C VIH EN and PWM Input Voltage Threshold Logic high VIL EN and PWM Input Voltage Threshold Logic low 0.4 V IEN Enable Input Current VEN = 12V 1 A IEN Enable Input Current VEN = 0V -10 A IPWM PWM Input Current VPWM = 5V 1 A IPWM PWM Input Current VPWM = 0V 1 A Doc. No. MV-S103978-01 Rev. - Page 16 16.5 V 2.0 V Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Electrical Specifications Electrical Characteristics 2.3 Table 5: Electrical Characteristics Electrical Characteristics The following applies unless otherwise noted (refer to schematic shown in Figure 1): VVIN = VEN =12V, VPFM = GND, GND = PGND, VOUT = 5V, L1 = 4.2H, C1 = 4.7F, C2 = 0.22F, C3 = C4 = 10F, C6 = 0.1F, C9 = C10 = C11 = C12 = 47F, TA = 25C. Bold values indicate -40C < TA < 85C. S y m bo l Pa r am e te r IILIM ILIM Pin Current TC Current Limit C o nd i ti on s ILIM Temperature Coefficient Copyright (c) 2009 Marvell February 4, 2009, 2.00 M in Ty p Max Units -5 -10 A 2000 ppm Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 17 88PH8101 Datasheet 2.4 Table 6: Switching Step-down Regulator Switching Step-down Regulator The following applies unless otherwise noted (refer to schematic shown in Figure 1): VVIN = VEN =12V, VPFM = GND, GND = PGND, VOUT = 5V, L1 = 4.2H, C1 = C9 = C10 = C11 = C12 = 4.7F, C2 = 0.22F, C3 = C4 = 10F, C6 = 0.1F, TA = 25C. Bold values indicate -40C < TA < 85C. S y m b ol P a r a m e te r C o n di ti on s M in Ty p Max Units VOUT Output Voltage (PFM Mode) RVSET = 11K, PFM Mode, ILOAD = 10mA 1.0 V RVSET = 18K, PFM Mode, ILOAD = 10mA 1.2 V RVSET = 30K, PFM Mode, ILOAD = 10mA 1.5 V RVSET = 51K, PFM Mode, ILOAD = 10mA 1.8 V RVSET = 100K, PFM Mode, ILOAD = 10mA 2.5 V 3.0 V 3.3 V 5.0 V VVSET = 0V, VPSET = 0V, PFM Mode, ILOAD = 10mA RVSET = 160K, PFM Mode, ILOAD = 10mA VVSET = 0V, VPSET = VCC, PFM Mode, ILOAD = 10mA RVSET = 270K, PFM Mode, ILOAD = 10mA VVSET = VCC, VPSET = 0V, PFM Mode, ILOAD = 10mA RVSET = 470K, PFM Mode, ILOAD = 10mA VVSET = VCC, VPSET = VCC, PFM Mode, ILOAD = 10mA Doc. No. MV-S103978-01 Rev. - Page 18 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Electrical Specifications Switching Step-down Regulator S y m b ol P a r a m e te r C o n di ti on s VOUT Output Voltage (PWM Mode) RVSET = 11K, PWM Mode, ILOAD = 100mA TA = 25C M in TA = 25C +3 1.2 +3 1.5 % V -2.5 +2.5 1.8 % V -2.5 RVSET = 100K, PWM Mode, ILOAD = 100mA % V -3 RVSET = 51K, PWM Mode, ILOAD = 100mA Units V -3 RVSET = 30K, PWM Mode, ILOAD = 100mA TA = 25C Max 1.0 RVSET = 18K, PWM Mode, ILOAD = 100mA TA = 25C Ty p +2.5 2.5 % V VVSET = 0V, VPSET = 0V, PWM Mode, ILOAD = 100mA TA = 25C -2 RVSET = 160K, PWM Mode, ILOAD = 100mA +2 3.0 % V VVSET = 0V, VPSET = VCC, PWM Mode, ILOAD = 100mA TA = 25C -2 RVSET = 270K, PWM Mode, ILOAD = 100mA +2 3.3 % V VVSET = VCC, VPSET = 0V, PWM Mode, ILOAD = 100mA TA = 25C -2 RVSET = 470K, PWM Mode, ILOAD = 100mA +2 5.0 % V VVSET = VCC, VPSET = VCC, PWM Mode, ILOAD = 100mA TA = 25C -2 +2 % PSET Percentage Set RPSET = 11K -10.0 % PSET Percentage Set RPSET= 18K -7.5 % PSET Percentage Set RPSET = 30K -5.0 % PSET Percentage Set RPSET = 51K -2.5 % PSET Percentage Set RPSET = 0K 0 % PSET Percentage Set RPSET = 100K 2.5 % PSET Percentage Set RPSET = 160K 5.0 % PSET Percentage Set RPSET = 270K 7.5 % PSET Percentage Set RPSET = 470K 10.0 % Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 19 88PH8101 Datasheet S y m b ol P a r a m e te r C o n di ti on s VLNREG Output Voltage Line Regulation VVIN = 9V to 12V, ILOAD = 2.5A 0.01 % VLDREG Output Voltage Load Regulation VVIN = 12V, ILOAD = 2.5A to 5A 0.1 % fSW Switching Frequency DMAX Maximum Duty Cycle 90 % tDEGLITCH Deglitch 40 s VPGTH Power Good (PG) Threshold Voltage VOUT > 1.35V VOUT x 90% V VPGTH Power Good (PG) Threshold Voltage VOUT < 1.32V VOUT - 130mV V VPGL Maximum PG Output Low Voltage ISINK = 1mA tDELAY PG Delay Time IPG PG Leakage Current VEN = 5.0V 1 tDNV Driver Non Overlap CL = 3300 pF 30 ns tR, tF Driver Rise/Fall Time CL = 3300 pF 15 ns RSOURCE Output Driver Impedance Top Driver 1.5 3 RSINK Output Driver Impedance Top Driver 1.0 2.5 RSOURCE Output Driver Impedance Bottom Driver 1.5 4.2 RSINK Output Driver Impedance Bottom Driver 0.5 2.5 400 Ty p 500 Max 600 0.4 512 Doc. No. MV-S103978-01 Rev. - Page 20 M in Units kHz V s 20 A Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 88PH8101 Datasheet 3 Functional Description Figure 3: Block Diagram C1 C3-C4 VIN 4.75V to 16V VCC 20 EN A 10 A ON OSCILLATOR OFF Level Shift ILIM VIN LDO INTERNAL CIRCUITRY POWER SUPPLY Current Sense CSH + - VBS R1 ANALOGDIGITAL CONVERTER DSP TG PWM CONTROL VSW PWM VOUT BG Serial Data Interface PGND 10 A THERMAL SHUTDOWN DCM BAND-GAP VOLTAGE REFERENCE UNDERVOLTAGE LOCKOUT Vout FAULT SFB RESISTOR NETWORK R2 THIS PAGE INTENTIONALLY LEFT BLANK RESISTOR SENSING CIRCUITRY GND VSET R4 3.1 L1 C9-C12 VCC PWM/SDI C2 PG Power Good PG PSET R3 Overview The 88PH8101 incorporates a new controller architecture that minimizes the number of external passive components, improves efficiency and provides fast transient response. A non-linear control algorithm is able to detect and react to severe load changes in less than 100 ns and requires no external compensation components, reducing design time. Efficiency is improved by having an adaptive dead time control that reduces the on time of the parasitic diode of the low-side MOSFET. Lossless switch current sensing utilizes the RDS (ON) of the high-side MOSFET to eliminate the need for a current sense resistor, improving efficiency. Other features include under and over voltage lockout, over temperature shutdown, power good detection, and cycle-by-cycle current limiting. Additionally, there are 3 simple ways to set the output voltage using external resistors, logic control or a serial interface. External resistors connected to the VSET and PSET pins are measured once before start up. These 2 resistors provide up to 72 output voltage options from 0.9V to 5.5V. These external resistors can be eliminated by tying the VSET and PSET pin high or low, generating 2.5V, 3.0V, 3.3V or 5.0V. Some applications require voltage margining, forcing the output voltage a percentage above and below its nominal value. In this case, the serial interface can be used to change the output 0%, 2.5%, 5.0%, 7.5%, 10% or any one of the 72 voltage options. Doc. No. MV-S103978-01 Rev. - Page 21 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 88PH8101 Datasheet To address portable applications, the 88PH8101 operates as a fixed frequency PWM when the load currents are high and automatically switches over to pulse skipping DCM mode at light loads, reducing no-load supply current from 21 mA to 2.5mA. For DDR applications where the converter must source and sink current, the PWM pin can be tied high, forcing PWM mode under all output current conditions. 3.2 Regulation and Start-up The step-down switching regulator can operate in Pulse Width Modulation Mode (PWM), Discontinuous Current Operating Mode (DCM), or Pulse Frequency Mode (PFM). The mode of operation depends on the level of output current and the output voltage. In steady states, the step-down switching regulator monitors the current flowing through the inductor to determine if the regulator is handling a heavy or light load. For heavy loads, the step-down regulator operates in the PWM mode (B) to minimize the ripple current for optimum efficiency and to minimize the ripple output voltage. The step-down regulator automatically switches over to pulse frequency (PFM) mode (A) at light loads for optimum efficiency in light load applications. In this mode, the average output voltage is slightly higher than the average output voltage when operating in PWM mode. In over current conditions and during start up, the regulator operates in PFM mode (C). Figure 4: Output Voltage Window Typical VOUT A B C D Doc. No. MV-S103978-01 Rev. - Page 22 PFM Mode PWM Mode PFM Mode Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Functional Description Soft Start 3.3 Soft Start Soft start is a highly desirable property in "Hot-Plug" applications. It limits the large inrush currents on the input power supply during start up. The 88PH8101 device controls the rise time of the output voltage, thereby dramatically reducing the inrush current. The rise time is tyically 5ms for VOUT higher than 1.65V and 0.33V/ms for VOUT < 1.65V and it is independent of output capacitance and load current. Figure 5 shows the rise time for various output voltage settings. Figure 5: Soft Startup (1V, 1.5V, 2.5V, 3.3V, 5V) 1V/DIV VOUT 1ms/DIV ILOAD = 1A, COUT = 4x22F 3.4 3.4.1 Output Voltage Setting Logic Programmability The output voltage of the step-down switching regulator can be programmed for the standard output voltages by connecting VSET and PSET pins to GND and/or VCC. This method will eliminate the use of external resistor to set the output voltage. Table 7: Output Voltage Setting V VS E T V P SE T VOUT GND GND 2.5V GND VCC 3.0V VCC GND 3.3V VCC VCC 5.0V Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 23 88PH8101 Datasheet 3.4.2 Serial Programmability The output voltage of the step-down switching regulator can also be programmed by using 18-bit serial data into the SDI pin. Figure 6: Serial Programmability WRITE MODE Stop Start "1" Pulse Chip Select Registor Address "1" "1" "0" "0" pulse Pulse pulse Pulse "0" "0" "1" "0" pulse pulse Pulse pulse The period of a pulse is 1 s +/- 200 ns V HIGH > VIH VLow < VIL DATA FIELD "1" Pulse D7 D6 D5 D4 D3 D2 D1 D0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 "1 " pulse The write operation: V HIGH 1 ) Each write sequence needs 18 pulses to complete . 2 ) During a non- write operation, the input needs to be at VLOW (<0.8V). 3) In between two successive write operations , the SDI input needs to be at VLOW (<0.8V ) for a minimum of 10 s VLOW For "1 " pulse, the high is 0. 75 s +/- 150 ns and the low period is 0. 25 s+/- 50 ns THIS PAGE INTENTIONALLY LEFT BLANK "0 " pulse Low for at least 10 s 1st Write sequence V LOW nd 2 Write sequence VHIGH For "0 " pulse, the high is 0.25 s +/- 50 ns and the low period is 0. 75 s+/- 150 ns The first 4 bits (MSB) of the data field are used to select the output voltage where the second 4 bits (LSB) of the data field are used to trim the output voltage (percent of output voltage). The default value for the data field is as follows: Table 8: Default Value of Data Field D a ta F i e ld D e s c r i p t io n Vo lta g e S e t Bits 7 6 5 4 3 2 1 0 Default value 0 0 1 0 0 1 0 0 Doc. No. MV-S103978-01 Rev. - Page 24 Percent Set Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Functional Description Output Voltage Setting The value for position 7 and 3 of the register will enable use of either logic or serial output voltage programmability. Bit value of "0" for positions 7 and 3 will enable the resistor/logic programmability and the output voltage will be set according to Section 3.4.1 A bit value of "1" will enable the serial programmability. The output voltage and percent set are selected per following table: Table 9: Voltage and Percent Set D a ta Fi e ld VO UT ( V) Bits 7 6 5 4 Value 1 0 0 0 1 0 0 1 0 1 D a ta F i e l d Percent Set 3 2 1 0 1.0 1 0 0 0 -10% 1 1.2 1 0 0 1 -7.5% 1 0 1.5 1 0 1 0 -5.0% 0 1 1 1.8 1 0 1 1 -2.5% 1 1 0 0 2.5 1 1 0 0 +2.5% 1 1 0 1 3.0 1 1 0 1 +5.0% 1 1 1 0 3.3 1 1 1 0 +7.5% 1 1 1 1 5.0 1 1 1 1 +10% All combinations of the Voltage Set and Percentage Set provide flexability in output voltage selection, as shown in Table 9. Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 25 88PH8101 Datasheet 3.5 Output Voltage--AnyVoltageTM Technology The output voltage of the step-down switching regulator is programmed by using Table 10 to select resistor values for VSET and PSET pin. The VSET pin sets the output voltage and the PSET pin trims the set voltage to a percentage value. For example, to program 2.25V output, a 100 k resistor is selected for the VSET pin, and an 11 k resistor is selected for the PSET pin. The 100 k resistor sets the output voltage to 2.5V and the 11 k resistor trims the set voltage by -10%. Using the VSET resistor's value greater than 619 k or less than 7.68 k disables the step-down switching regulator and sets the SW pin to high impedance. If the VSET resistor's value is outside the 5% tolerance, the output can be either higher or lower than the set voltage. Using resistor values greater than 619 k or less than 7.68 k for the PSET pin does not affect the set voltage. When the PSET pin is not used, it must be connected to ground. Like the VSET resistor, the percent value is either higher or lower if the PSET resistor's value is outside the 5% tolerance. Table 10: VSET and PSET Programming Table for 5% Resistors Vol ta g e S e t ( V ) P e r ce n tag e S e t ( % ) -10.00% -7.50% -5.00% -2.50% 0% 2.50% 5.00% 7.50% 10% 11K 18K 30K 51K GND 100K 160K 270K 470K 11K 0.900 0.925 0.950 0.975 1.00 1.025 1.050 1.075 1.100 18K 1.080 1.110 1.140 1.170 1.20 1.230 1.260 1.290 1.320 30K 1.350 1.388 1.425 1.463 1.50 1.538 1.575 1.613 1.650 51K 1.620 1.665 1.710 1.755 1.80 1.845 1.890 1.935 1.980 100K 2.250 2.313 2.375 2.438 2.50 2.563 2.625 2.688 2.750 160K 2.700 2.775 2.850 2.925 3.00 3.075 3.150 3.225 3.300 270K 2.970 3.053 3.135 3.218 3.30 3.383 3.465 3.548 3.630 470K 4.500 4.625 4.750 4.875 5.00 5.125 5.250 5.375 5.500 The VSET and PSET resistors are read once during start-up before the output voltage is turned on. After the output voltage is turned on, the output voltage can change to different values using serial programming interface. Otherwise to configure the output to a different voltage, power has to recycle or the 88PH8101 has to turn OFF and back ON using the enable pin. Figure 7 shows the startup waveforms of the 88PH8101. Once the input voltage (VIN) is above the under voltage lockout (UVLO) upper threshold (UTH), the VSET and PSET pin become active. Current is first sourced out of PSET pin and then the VSET pin, in exponentially increasing steps. After each step there is a blanking time before the VSET voltage is compared to an internal 1.2V reference. If the VSET voltage is below internal reference voltage and the current source proceeds to the next set. Once the VSET voltage is above the internal reference voltage the sequence stops and the output voltage (VOUT) is allowed to turn-on. Figure 7 shows the VSET waveform for VSET = 2.5V and PSET = -5% output in low-voltage mode. The 88PH8101 keeps track of how many steps were required to determine the appropriate output voltage. Table 11 provides the number of steps necessary for each output voltage option. Using a VSET resistor of 100k requires the current source to step 5 times, and a PSET resistor of 30 k requires 7 steps. Doc. No. MV-S103978-01 Rev. - Page 26 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Functional Description Output Voltage--AnyVoltageTM Technology Figure 7: Startup Sequence Figure 8: Soft Startup VIN 5V/DIV VOUT 2V/DIV VVSET 2V/DIV VPSET VVSET 500 mV/DIV VPSET 2V/DIV 500 mV/DIV 200s/DIV 10ms/DIV Table 11: St ep 1 Number of Voltage Steps for Each Output V OUT (V) R VSET ( k) 0 0 St ep 1 P SET (%) R PSET ( k) 0 0 2 5.0 470 2 +10 470 3 3.3 270 3 +7.5 270 4 3.0 160 4 +5.0 160 5 2.5 100 5 +2.5 100 6 1.8 51 6 -2.5 51 7 1.5 30 7 -5.0 30 8 1.2 18 8 -7.5 18 9 1.0 11 9 -10 11 The 88PH8101 provides an innovative technique to set the output voltage. During start-up it reads the value of external resistors, which are located outside the regulator's feedback loop, to program the output voltage. By placing the output voltage programming resistor outside the regulator's feedback loop, its tolerance does not affect the accuracy of the output voltage. While in conventional designs, adjustable regulators use 1% resistors to set the output voltage. However, these resistors are located inside the feedback loop, introducing as much as 2% of initial accuracy error to the output voltage, resulting in an overall initial accuracy of 3%. Whereas, the 88PH8101 initial accuracy is 2% for any of the eight output voltages. The VSET and PSET pins are sensitive to excessive leakage currents and stray capacitance. The output voltage can potentially be programmed to the lower output voltage if there is contamination, which introduces excessive leakage current on the VSET and PSET pin, especially for a RVSET and RPSET of 470k. The parasitic resistance on these nodes must be greater than 3M and the stray capacitance must be less than 25pF; otherwise, a 5.0V output can potential end up at 3.3V in low-voltage mode. Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 27 88PH8101 Datasheet 3.6 Thermal Shutdown When the junction temperature of the 88PH8101 exceeds OTS high threshold, the thermal shutdown circuitry disables the step-down regulator. The step-down switching regulator is enabled when the junction temperature is decreased to OTS low threshold. 3.7 PFM or PWM Mode Selection When PFM pin is connected to high state, the regulator is in the forced PWM mode, where the regulator runs at a constant frequency. The quiescent current of the forced PWM mode increases to 21mA (typical). When PFM pin is connected to a low state, the regulator runs in PFM mode, where the switching frequency decreases when the load current reduces, thus improving the light load efficiency. 3.8 Under Voltage Lockout (UVLO) The Under Voltage Lockout (UVLO) feature insures that both MOSFETs have adequate voltage levels to operate properly. When the input voltage drops below UVLO low threshold, both MOSFETs are off until the input rises above UVLO high threshold. See Section 2.3 for the UVLO low and high threshold voltages. 3.9 Over Voltage Protection (OVP) For Over Voltage Protection (OVP), an over voltage comparator guards against transient overshoots, as well as other serious conditions, that may damage the IC. When the input voltage is above the OVP high threshold voltage, both external high-side N-channel MOSFET are turned off until the input voltage drops below the OVP low threshold voltage. See section 2.3 for the OVP low and high voltages.. VOVP_HTH VOVP-LTH VUVLO-HTH VUVLO-LTH VIN BUCK Output Enable Undefined BUCK Output Disable Doc. No. MV-S103978-01 Rev. - Page 28 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Functional Description Power Good (PG) 3.10 Power Good (PG) The Power Good (PG) pin is an active-high, open-drain output pin. It is low when the output voltage of the step-down regulator is below the threshold. When the output voltage is above the threshold for more than 512s (tDELAY), the power good pin goes high. The threshold voltage is 0.9% * VOUT (typical) for all output voltage settings. A built-in tDEGLITCH (40s typical) delay is incorporated to prevent nuisance tripping. Figure 9: Power Good Operating Waveform VPG_TH < t DEGLITCH 0V VPG RPG_PULLUP x IPG V PGL tDELAY 3.11 tDEGLITCH Hiccup Current Limit The "Hiccup" short-circuit protection is a feature that is not common among other switching regulators. Hiccup mode offers extra protection against over current situations, since it limits the average current to the load, reducing power dissipation and case temperature of the IC. When the current-sense circuit sees an over-current condition together with a low output voltage condition (VOUT < 75% nominal), the 88PH8101 device shuts off for about 2ms and then tries to start up again. If the over-load condition is removed, the devices will start-up normally; otherwise, the IC will see another over-current event and shut off once again, repeating the previous cycle. Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 29 88PH8101 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103978-01 Rev. - Page 30 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Functional Characteristics Startup Waveforms 4 Functional Characteristics Unless otherwise noted, the following typical scope photographs were taken using test circuit shown in figure 1 at TA = 25C. 4.1 Startup Waveforms NOTE: When the input voltage rises above the UVLO's upper threshold, then there is a delay (4ms typ) before the step-down regulator's output voltage powers on. Figure 10: Startup Using the Enable Pin Figure 11: Turn Off Using the Enable Pin VEN VEN 5V/DIV 5V/DIV VOUT 2V/DIV VOUT 2V/DIV 5ms/DIV VIN = 12V 5ms/DIV ILOAD = 10mA VIN = 12V VOUT = 5V ILOAD = 10mA VOUT = 5V Figure 12: Soft Start Figure 13: Hot Plug VIN 5V/DIV VIN 5V/DIV VOUT 5V/DIV VOUT 5V/DIV VPG 5V/DIV VPG 5V/DIV 10ms/DIV VIN = 12V VOUT = 5V ILOAD = No Load 10ms/DIV VIN = 12V VOUT = 5V Copyright (c) 2009 Marvell February 4, 2009, 2.00 ILOAD = No Load Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 31 88PH8101 Datasheet 4.2 Switching Waveforms NOTE: For repeatability of measuring output ripple (VOUT (P-P)) for the BUCK regulator, the standard test procedure limits the scope bandwidth to 20MHz and uses a coax cable with very short leads terminated into 50. The coax leads must be routed away from the switching node as much as possible. . Figure 14: PWM Mode Figure 15: PWM Mode VSW 10V/DIV VSW 10V/DIV IIND 5A/DIV IIND 5A/DIV VOUT 50mV/DIV VOUT 50mV/DIV VIN 50mV/DIV VIN 50mV/DIV 1s/DIV 1s/DIV CIN = 4x22F VIN(P-P) = 57.1mV CIN = 8x22F VIN(P-P) = 47.6mV VIN = 12V IIND(P-P) = 2.1A VIN = 12V IIND(P-P) = 2.06A VOUT = 5V IIND(PK) = 6A VOUT = 5V IIND(PK) = 6.05A ILOAD = 5A Frequency = 500kHz ILOAD = 5A Frequency = 500kHz VOUT(P-P) = 22.7mV (note) VOUT(P-P) = 28.3mV (note) Figure 16: DCM Mode Figure 17: DCM Mode-zoom VSW 10V/DIV VOUT VSW 10V/DIV VOUT 50mV/DIV 50mV/DIV IIND 1A/DIV 1A/DIV IIND 5s/DIV 2s/DIV VIN = 12V ILOAD = 24mA VIN = 12V ILOAD = 24mA VOUT = 5V IIND(PK) = 1.82A VOUT = 5V Ringing Frequency = 1.8MHz VOUT(P-P) = 60.4mV (note) Frequency = 49kHz Doc. No. MV-S103978-01 Rev. - Page 32 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Functional Characteristics Switching Waveforms Figure 18: PWM Output Ripple Voltage VOUT 20mV/DIV 100ms/DIV VIN = 12V ILOAD = 5A VOUT = 5V VOUT(P-P) = 35.3mV (Note) Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 33 88PH8101 Datasheet 4.3 Load Transient Waveforms 4.3.1 Step-Down Regulator Figure 19: Fast Load Rise Time Figure 20: Slow Load Rise Time VSW 10V/DIV VOUT VSW 10V/DIV VOUT 50mV/DIV 50mV/DIV ILOAD ILOAD 2A/DIV IIND 2A/DIV IIND 5s/DIV 5s/DIV VIN = 12V COUT = 4 x 47F VIN = 12V COUT = 4 x 47F VOUT = 5V tRISE = 50A/s VOUT = 5V tRISE = 2.5A/s ILOAD = 2A to 5A ILOAD = 2A to 5A Figure 21: Fast Load Fall Time Figure 22: Slow Load Fall Time VSW 10V/DIV VOUT 50mV/DIV ILOAD VSW 10V/DIV VOUT 50mV/DIV ILOAD 2A/DIV IIND 2A/DIV IIND 5s/DIV 5s/DIV VIN = 12V COUT = 4 x 47F VIN = 12V COUT = 4 x 47F VOUT = 5V tRISE = 230A/s VOUT = 5V tRISE = 2.5A/s ILOAD = 5A to 2A ILOAD = 5A to 2A Doc. No. MV-S103978-01 Rev. - Page 34 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Functional Characteristics Load Transient Waveforms Figure 23: Load Transient Response Figure 24: Double-Pulsed Load Response VOUT 200mV/DIV ILOAD VOUT 200mV/DIV ILOAD 2A/DIV 2A/DIV 20s/DIV 20s/DIV VIN = 12V COUT = 4 x 47F VIN = 12V COUT = 4 x 47F VOUT = 5V tRISE = 50A/s VOUT = 5V tRISE = 50A/s ILOAD = 2A to 5A tFALL = 230A/s ILOAD = 2A to 5A tFALL = 230A/s Figure 25: Load Transient Response VOUT Figure 26: Double-Pulsed Load Response 200mV/DIV ILOAD VOUT 200mV/DIV ILOAD 2A/DIV 2A/DIV 20s/DIV 20s/DIV VIN = 12V COUT = 4 x 47F VIN = 12V COUT = 4 x 47F VOUT = 5V tRISE = 50A/s VOUT = 5V tRISE = 50A/s ILOAD = 1A to 3A tFALL = 230A/s ILOAD = 1A to 3A tFALL = 230A/s Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 35 88PH8101 Datasheet 4.4 Output Voltage Transient Waveforms The following graphs show the effect of changing the step-down regulator's output voltage using the serial interface. Depending on the change in the step-size of the output voltage, the output load, and the output capacitance, the power-on reset pin de-asserts when the changes of the output voltage occur beyond the 25s (typical) delay. 4.4.1 Step-Down Regulator Figure 27: VOUT = 1.0V to 1.2V with ILoad = 0A Figure 28: VOUT = 1.0V to 1.5V with ILoad = 0A VOUT 1V/DIV VPG 1V/DIV VSDI 5V/DIV 1V/DIV VOUT VPG 1V/DIV VSDI 5V/DIV 100s/DIV 100s/DIV VIN = 12V VIN = 12V COUT = (4 x 47F) + 1000F COUT = (4 x 47F) +1000F Doc. No. MV-S103978-01 Rev. - Page 36 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Typical Characteristics Efficiency 5 Typical Characteristics Unless otherwise noted, the following typical scope photographs were taken using test circuit shown in figure 1 at TA = 25C. 5.1 Efficiency Figure 29: Efficiency vs. Output Current Efficiency vs. Output Current Vin = 9.0V Efficiency vs. Output Current Vin = 12.0V 100 100 5.0V 5.0V 80 3.3V 3.0V 60 2.5V 1.8V 40 1.5V Efficiency (%) Efficiency (%) 80 1.2V 20 3.3V 3.0V 60 2.5V 1.8V 40 1.5V 1.2V 20 1.0V 1.0V 0 0 0 1 2 3 4 0 5 1 2 3 4 5 Output Current (A) Output Current (A) Figure 30: Efficiency vs. Output Current in Log Scale Efficiency vs. Output Current Vin = 12.0V Efficiency vs. Output Current Vin = 9.0V 100 100 5.0V 5.0V 80 3.3V 3.0V 60 2.5V 1.8V 40 1.5V 1.2V 20 Efficiency (%) Efficiency (%) 80 3.3V 3.0V 60 2.5V 1.8V 40 1.5V 1.2V 20 1.0V 0 0.01 0.1 1 10 1.0V 0 0.01 1 10 Output Current (A) Output Current (A) 5.2 0.1 IC Case, MOSFET, and Inductor Temperature The following data was taken using a 2.0 square inch PCB 1 oz. copper and L = 4.2H. Actual results depend upon the size of the PCB proximity to other heat emitting components Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 37 88PH8101 Datasheet Figure 31: Input Current vs. Output Current Input Current vs. Output Current Vin = 12V, TA = 25C Input Current vs. Output Current Vin = 9.0V, TA = 25C 5.0 6.0 5.0V 4.0 Input Current (A) Input Current (A) 5.0 3.3V 4.0 3.0V 2.5V 3.0 1.8V 2.0 1.5V 1.2V 1.0 3.3V 3.0V 3.0 2.5V 1.8V 2.0 1.5V 1.2V 1.0 1.0V 1.0V 0.0 0.0 0 1 2 3 4 5 6 7 8 9 0 10 1 2 3 4 5 6 7 8 9 10 Output Current (A) Output Current (A) Figure 32: IC Case Temperature vs. Output Current IC Case Temperature vs. Output Current Vin = 9.0V, TA = 25C IC Case Temperature vs. Output Current Vin = 12V, TA = 25C 90 90 5.0V 80 3.3V 80 Temperature (C) Temperature (C) 100 3.0V 70 2.5V 60 1.8V 50 1.5V 40 1.2V 1.0V 30 3.3V 3.0V 70 2.5V 60 1.8V 1.5V 50 1.2V 40 1.0V 30 20 20 0 1 2 3 4 5 6 7 8 9 0 10 1 2 3 4 5 6 7 8 9 10 Output Current (A) Output Current (A) Figure 33: Top FET Temperature vs. Output Current Top FET Temperature vs. Output Current Vin = 9.0V, TA = 25C Top FET Temperature vs. Output Current Vin = 12V, TA = 25C 100 100 5.0V 90 3.3V 90 3.3V 80 3.0V 80 3.0V 70 2.5V 60 1.8V 1.5V 50 1.2V 40 Temperature (C) Temperature (C) 110 1.0V 1.8V 60 1.5V 50 1.2V 40 1.0V 30 30 20 20 0 1 2 3 4 5 6 7 8 9 10 0 Output Current (A) 1 2 3 4 5 6 7 8 9 10 Output Current (A) Doc. No. MV-S103978-01 Rev. - Page 38 2.5V 70 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Typical Characteristics IC Case, MOSFET, and Inductor Temperature Figure 34: Bottom FET Temperature vs. Output Current Bottom FET Temperature vs. Output Current Vin = 9.0V, TA = 25C Bottom FET Temperature vs. Output Current Vin = 12V, TA = 25C 110 110 5.0V 100 3.3V 100 3.3V 90 3.0V 90 3.0V 80 2.5V 80 2.5V 70 1.8V 70 1.8V 60 1.5V 60 1.5V 50 1.2V 40 1.0V Temperature (C) Temperature (C) 120 1.2V 50 1.0V 40 30 30 20 20 0 1 2 3 4 5 6 7 8 9 0 10 1 2 3 4 5 6 7 8 9 10 Output Current (A) Output Current (A) Figure 35: Inductor Temperature vs. Output Current Inductor Temperature vs. Output Current Vin = 12V, TA = 25C Inductor Temperature vs. Output Current Vin = 9.0V, TA = 25C 90 80 5.0V 70 3.3V 3.0V 60 2.5V 1.8V 50 1.5V 40 1.2V 30 1.0V 20 Temperature (C) Temperature (C) 90 80 3.3V 70 3.0V 2.5V 60 1.8V 1.5V 50 1.2V 40 1.0V 30 20 0 1 2 3 4 5 6 7 8 9 10 0 Output Current (A) 2 3 4 5 6 7 8 9 10 Output Current (A) Copyright (c) 2009 Marvell February 4, 2009, 2.00 1 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 39 88PH8101 Datasheet 5.3 Input Voltage Figure 36: Supply Current vs. Input Voltage Figure 37: Shutdown Supply Current vs. Input Voltage Supply Current vs. Input Voltage PFM Mode Shutdow n Supply Current vs. Input Voltage 30 3.0 Current (A) Current (mA) 25 2.0 1.0 20 15 0.0 10 9.0 10.0 11.0 12.0 13.0 9.0 14.0 Input Voltage (V) 10.0 11.0 12.0 13.0 14.0 Input Voltage (V) ILOAD = No Load VIN = 12V; ILOAD = No Load; VEN = 0V Figure 38: Enable Threshold vs. Input Voltage Enable Threshold vs. Input Voltage 2.5 UTH-Enable Voltage (V) 2.0 LTH-Disable 1.5 1.0 0.5 9 10 11 12 13 14 Input Voltage (V) ILOAD = 10mA Doc. No. MV-S103978-01 Rev. - Page 40 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Typical Characteristics Input Voltage 5.3.1 Step-down Regulator Figure 39: Output Voltage vs. Input Voltage Figure 40: Efficiency vs. Input Voltage Efficiency vs. Input Voltage 100% 5.05 98% Efficiency Output Voltage (V) Output Voltage vs. Input Voltage 5.10 5.00 95% 93% 4.95 90% 4.90 9 10 11 12 13 9 14 10 ILOAD = 2.5A 12 13 14 VOUT = 5V; ILOAD = 5A Figure 41: Load Regulation vs. Input Voltage Figure 42: Frequency vs. Input Voltage Load Regulation vs. Input Voltage Frequency vs. Input Voltage 550 0.20% 0.10% Frequency (kHz) Load Regulation 11 Input Voltage (V) Input Voltage (V) 0.00% -0.10% 525 500 475 -0.20% 9 10 11 12 13 14 450 Input Voltage (V) 9 10 11 12 13 14 Input Voltage (V) VOUT = 5V; ILOAD = 2.5 - 5A VOUT = 5V; ILOAD = 5A Figure 43: Average Output Current Limit vs. Input Voltage Average Output Current Limit vs. Input Voltage Current (A) 9 8 7 6 9 10 11 12 13 14 Input Voltage (V) Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 41 88PH8101 Datasheet 5.4 Temperature Figure 44: Supply Current vs. Temperature Figure 45: UVLO Threshold vs. Temperature Supply Current vs. Temperature PFM Mode 3 UVLO Threshold vs. Temperature 7 UTH LTH Voltage (V) Current (mA) 6 2 1 5 4 3 -40 0 -40 -20 0 20 40 60 80 -20 0 20 40 ILOAD = No Load; VPWM = 0V Figure 47: Enable Threshold vs. Temperature OVP Threshold vs. Temperature Enable Threshold vs. Temperature 19 2.5 OVP HIGH UTH - Enable OVP LOW LTH - Disable 2.0 Voltage (V) 18 Voltage (V) 80 ILOAD = 10mA Figure 46: OVP Threshold vs. Temperature 17 16 15 -40 60 Temperature (C) Temperature (C) 1.5 1.0 -20 0 20 40 60 0.5 -40 80 -20 0 20 40 60 80 Temperature (C) Temperature (C) ILOAD = 10mA ILOAD = 10mA Figure 48: Shutdown Supply Current vs. Temperature Shutdow n Supply Current vs.Temperature 80 Current (uA) 60 40 20 0 -40 -20 0 20 40 60 80 Temperature (C) ILOAD = No Load; VEN = 0V Doc. No. MV-S103978-01 Rev. - Page 42 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Typical Characteristics Temperature 5.4.1 Step-down Regulator Figure 49: Output Voltage vs. Temperature Figure 50: Efficiency vs. Temperature Output Voltage vs. Temperature Efficiency vs. Temperature 100% 5.15 Efficiency Output Voltage (V) 98% 5.10 5.05 95% 93% 5.00 -40 90% -20 0 20 40 Temperature (C) 60 -40 80 -20 0 20 40 60 80 Temperature (C) VIN = 12V; ILOAD = 2.5A VIN = 12V; VOUT = 5V; ILOAD = 5A Figure 51: Load Regulation vs. Temperature Figure 52: Line Regulation vs. Temperature Line Regulation vs. Temperature Load Regulation vs. Temperature 0.20% 0.10% 0.10% Line Regulation Load Regulation 0.20% 0.00% 0.00% -0.10% -0.10% -0.20% -0.20% -40 -20 0 20 40 60 -40 80 -20 0 20 40 60 80 Temperature (C) Temperature (C) VIN = 12V; VOUT = 5V; ILOAD = 2.5A - 5A VIN = 9V - 12V; VOUT = 5V; ILOAD = 5A Figure 53: Frequency vs. Temperature Figure 54: Average Output Current Limit vs. Temperature Frequency vs. Temperature Average Output Current Limit vs. Temperature 550 9 Current (A) Frequency (kHz) 525 500 7 5 475 450 -40 3 -20 0 20 40 60 -40 80 VIN = 12V; ILOAD = 5A 0 20 40 60 80 VIN = 12V Copyright (c) 2009 Marvell February 4, 2009, 2.00 -20 Temperature (C) Temperature (C) Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 43 88PH8101 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103978-01 Rev. - Page 44 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Applications Information PC Board Layout Considerations and Guidelines 6 Applications Information 6.1 PC Board Layout Considerations and Guidelines To avoid noise and abnormal operating behavior, follow these layout recommendations. Warning The PC board layout is very critical in any switching converter. An improper layout can contribute to system instability, excessive Electro-Magnetic Interference (EMI), and high switching loss. Follow these basic guidelines for good PC layout: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Copy the layout on page 47 as much as possible and use the recommend BOM on page 51. Contact the factory if substitutions are made. Review the recommended solder pad layout and notes on page 53. Do not replace the Ceramic input or output capacitors with Tantalum capacitors! Any type of capacitor can be placed in parallel with the input capacitor as long as the Ceramic input capacitor is placed next to the IC. If Tantalum input capacitor is used, it must be rated for switching regulator applications and the operating voltage be derated by 50%. Any type of capacitor can be placed in parallel with the output capacitor. Low-ESR capacitors like the POSCAP from Sanyo can replace the Ceramic output capacitors as long as the capacitor value is the same or greater. Note that the Ceramic capacitors provide the lowest noise and smallest foot print solution. Use planes for the ground, input and outputs power to maintain good voltage filtering and to keep power losses low. If there is not enough space for a power plane for the input supply, then the input supply trace must be at least 3/8 inch wide. If there is not enough space for a power plane for the output supplies, then place the output as close to the load as possible with a trace of at least 3/8 inch wide. Do not lay out the inductor first. The input capacitors, Q1 and Q2 placement are the most critical for proper operation. These components must be placed as close as possible to each other with as short and wide trace as possible. The AC current circulating through these components and loop 1 (LP1) are square wave with rise and fall times of 8ns and slew rates as high as 300A/s (see Figure 11). At these fast slew rates, stray PCB inductance can generate a voltage spike as high as 3V per inch of PCB trace, VIND = L * di/dt. Also, the VIN and PGND traces must be placed on the top layer. This will isolate the fast AC currents from interfering with the analog ground plane. Place the bootstrap capacitor, C2, as close as possible to the VBS and VSW pins. The 88PH8101 has two internal grounds, analog (GND) and power (PGND). The analog ground ties to all the noise sensitive signals (PSET, VSET, and VCC) while the power ground ties to the higher current power paths. Noise on an analog ground can cause problems with the IC's internal control and bias signals. For this reason, separate analog and power ground traces are recommended. The signal ground is connected to the power ground at one point, which is the (-) terminal of the output capacitor. Connect the CSH and VSW pins as close to Q1 drain and source as possible. These pins are the sense terminals of the current limit comparator circuitry. Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 45 88PH8101 Datasheet 14. The VIN pin is sensitive to noise; therefore, connect the VIN pin to the (+) terminal of the input capacitor and distance the PVIN from the CSH connection as far as possible. 15. Connect the (-) terminal of the output capacitor as close to the (-) terminal of the input capacitor. A back-to-back placing of bypass capacitors, as shown in Figure 55, is recommended for best results. 16. Keep the switching node (VSW) away from the SFB pin and all sensitive signal nodes, minimizing capacitive coupling effects. If the SFB trace must cross the VSW node, cross it at a right angle. 17. Try not to route analog or digital lines in close proximity to the power supply especially the VSW node. If this can't be avoided, shield these lines with a power plane placed between the VSW node and the signal lines. Figure 55: PCB Board Schematic VIN 12V C5 NOB U1 1 EN VIN 16 C4 10uF/25 V 2 3 R3 0 Ohm PSET VSET CSH VSW 15 LP1 C3 10uF/25 V 14 88PH8101 R4 470k 4 C6 0.1uF R1 43k ILIM TG SFB VBS 13 Q1 IRF7821 C2 5 12 0.22 uF 4.2uH 6 GND VCC 11 V OUT 5V/5A L1 C1 4.7uF 7 R2 100K PG 8 PWM/SDI PG BG PGND LP2 10 C10 47uF/6.3V C 11 47uF/6.3V C12 47uF/6.3V 9 I Cin I Cout LP1 LP2 Doc. No. MV-S103978-01 Rev. - Page 46 C9 47uF/6.3V Q2 IRF7832 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Applications Information PC Board Layout Considerations and Guidelines 6.1.1 PC Board Layout Example Actual board size = 1450 mil x 1330 mil Total copper layers = 4 All the components are on the top layer Figure 56: Top Silk-Screen, Top Traces, Vias, and Copper (Not to Scale) Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 47 88PH8101 Datasheet Figure 57: GND_Layer2 Vias, and Copper (Not to Scale) Doc. No. MV-S103978-01 Rev. - Page 48 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Applications Information PC Board Layout Considerations and Guidelines Figure 58: GND_Layer3 Vias, and Copper (Not to Scale) Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 49 88PH8101 Datasheet Figure 59: Bottom Silk Screen, Bottom Traces, Vias, and Copper (Not to Scale) Doc. No. MV-S103978-01 Rev. - Page 50 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Applications Information PC Board Layout Considerations and Guidelines 6.1.2 Bill of Materials Table 12: Ite m BOM Qty R ef M a n u fa c tu r e r M an u fa c tu r e r P a r t N o. D e s c r ip t i o n 1 1 U1 Marvell Semiconductor 88PH8101 High Voltage Switching Regulator Controller 2 1 C1 Murata GRM21BR71C475K CAP CER 4.7F 16V 10% X7R 0805 3 1 C2 Murata GRM188R61A224K A01D CAP CER 0.22F 10V 10% X5R 0603 4 1 C3 Murata GRM32DR61E106K A12L CAP CER 10F 25V 10% X5R 1210 5 1 C4 Murata GRM32DR61E106K A12L CAP CER 10F 25V 10% X5R 1210 6 0 C5 -- NOB NOT ON BOARD 7 1 C6 TDK Corporation C1608X7R1E104K CAP CER 0.1F 25V X7R 10% 0603 8 1 C9 TDK Corporation C3216X5R0J476M CAP CER 47F 6.3V X5R 20% 1206 9 1 C10 TDK Corporation C3216X5R0J476M CAP CER 47F 6.3V X5R 20% 1206 10 1 C11 TDK Corporation C3216X5R0J476M CAP CER 47F 6.3V X5R 20% 1206 11 1 C12 TDK Corporation C3216X5R0J476M CAP CER 47F 6.3V X5R 20% 1206 12 1 L1 Sumida CDEP145NP-4R2M C-170 CDEP145 Series, 4.2H, 12.3A @ 20C, 7.4 m, H = 6 mm, L = 14.9 mm, W = 14.9 mm 13 1 Q1 IRF IRF7821TRPBF N-Channel MOSFETs SO-8 30V 13.6A @ 25C 14 1 Q2 IRF IRF7832PBFCT N-Channel MOSFETs SO-8 30V 20A 15 1 R1 Yageo Corporation RC0603JR-0743KL RES 43K 1/10W 5% 0603 SMD 16 1 R2 Panasonic - ECG ERJ-3GEYJ104V RES 100K 1/10W 5% 0603 SMD 17 1 R3 Yageo America RC0603JR-070RL RES 0.0 1/10W 5% 0603 SMD 18 1 R4 Yageo Corporation RC0603JR-07470KL RES 470K 1/10W 5% 0603 SMD Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 51 88PH8101 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103978-01 Rev. - Page 52 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Mechanical Drawings Mechanical Drawing 7 Mechanical Drawings 7.1 Mechanical Drawing Figure 60: 16-Pin TSSOP Mechanical Drawing Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 53 88PH8101 Datasheet 7.2 Mechanical Dimensions Table 13: 16-Pin TSSOP Dimensions S YM B O L S D IM E N S I O N S IN M I L LI M E TE R S MIN NOM D I M EN SI O N S I N IN C H E S MAX M IN NOM MAX A 1.05 1.10 1.20 0.041 0.043 0.047 A1 0.05 0.10 0.15 0.002 0.004 0.006 1.00 1.05 0.039 0.041 0.25 0.28 0.010 0.011 A2 b 0.20 C 0.008 0.127 0.005 D 4.90 5.00 5.10 0.193 0.200 0.200 E 6.20 6.40 6.60 0.244 0.252 0.260 E1 4.30 4.40 4.50 0.170 0.173 0.177 e 0.65 L 0.50 0.60 y 0.026 0.70 0.020 0.024 0.076 0 4 8 0.028 0.003 0 4 8 Notes: 1. 2. 3. CONTROLLING DIMENSION: mm DIMENSION "D" DOES NOT INCLUDE MOLD FLASH, TIE BAR BURRS AND GATE BURRS. MODE FLASH, TIE BAR BURRS AND GATE BURRS SHALL NOT EXCEED 0.006" [0.15mm] PER END DIMENSION "E1" DOES NOT INCLUDE INTERLEAD FLASH INTERLEAD FLASH SHALL NOT EXCEED 0.010" [0.25mm] PER SIDE. REFERENCE DOCUMENT: JEDEC SPEC MO-153 Doc. No. MV-S103978-01 Rev. - Page 54 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Mechanical Drawings Typical Pad Layout Dimensions 7.3 Typical Pad Layout Dimensions 7.3.1 Recommended Solder Pad Layout Figure 61: TSSOP-16 Land Pattern (mm) 6.60 4.50 1 0.65 5.00 1.05 0.45 Notes: 1. 2. 3. 4. 5. TOP VIEW DRAWING NOT TO SCALE CONTROLLING DIMENSION: mm OVERSIZE SOLDER MASK BY 4 MILS OVER PAD SIZE (2 MIL ANNULAR RING) TOLERANCE 0.05mm Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 55 88PH8101 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103978-01 Rev. - Page 56 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 Part Order Numbering / Package Marking Part Order Numbering Scheme 8 Part Order Numbering / Package Marking 8.1 Part Order Numbering Scheme Figure 62 shows the part order numbering scheme. Refer to a Marvell(R) Field Application Engineer (FAE) or sales representative for further information when ordering parts. Figure 62: Sample Part Number 88PH8101 xx - UBB 1 C000 - T 123 Part Number Custom Code (optional ) Custom Code Custom Code Custom Code Temperature Code Package Code Environmental 1 - RoHS 6/6 Package 2 - Green Package 8.2 Part Ordering Options The standard ordering part numbers for the respective solutions are as follows: Table 14: Part Ordering Options P a c k a g e Ty p e P a r t O r de r (b o ok i n g) N um be r 16-pin TSSOP 88PH8101xx-UBB1C000 16-pin TSSOP 88PH8101xx-UBB1C000-T (Tape and Reel) Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 57 88PH8101 Datasheet 8.3 Package Marking Figure 63 shows a sample package marking and pin 1 location. Figure 63: Package Marking and Pin 1 Location MRVL Marvell company abbreviation H101 Abbreviated part number XXXX = 4 character abbreviated part YWWG Pin 1 location Date code and assembly house code Y = last digit of year WW = work week G = assembly house code Note: The above example is not drawn to scale. Location of markings are approximate. Doc. No. MV-S103978-01 Rev. - Page 58 Copyright (c) 2009 Marvell Document Classification: Proprietary February 4, 2009, 2.00 A Revision History Table 15: Revision History D o c u m e n t Ty p e D o c u m e n t R e v i s io n Release Rev. - Updated to new template, Removed all "88PH8201" instances, Removed "Confidential", Updated Typ. Dwg. (Fig. 1), Updated Electrical Chars. Output Voltage Specs., Updated Logic Programmability Voltage Output Specs. (Table 3), Replaced PC Board Schematic, Replaced and added silk screens (Fig. 30 - Fig. 34), Updated Bill of Materials. Copyright (c) 2009 Marvell February 4, 2009, 2.00 Doc. No. MV-S103978-01 Rev. - Document Classification: Proprietary Page 59 Back Cover Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Marvell. Moving Forward Faster