88PH8101XX-UBB1C000-T - Marvell Semiconductor, Inc.

Marvell. Moving Forward Faster

Doc. No. MV-S103978-01, Rev. –

February 4, 2009

Document Classification: Proprietary

4.75VCover

88PH8101

Field Programmable, High Voltage

Synchronous Switching Regulator

Controller

Datasheet

Document Conventions

Note: Provides related information or information of special importance.

Caution: Indicates potential damage to h ardware or software, or loss of data.

Warning: Indicates a risk of personal injury.

Document Status

Doc Status: 2.00 Technical Publication: 0.xx

For more information, visit our website at: www.marvell.com

Disclaimer

No part of th i s docu m en t ma y be reproduced or transm itted i n an y for m or by a ny means, electronic or mechani c a l, in cluding photocopying and recor d in g, for any purpose,

without the express written permissi on of Marvell. Marvell retains the right to make cha ng es to this document at any ti me , w itho ut not ice. Marve ll makes no warran ty of an y

kind, expre ssed or impl ied, wi th regar d to any informa tion con tai ned in thi s docum ent, inclu ding, but not li mited to , the i mplied wa rrantie s of merc hant ability or fitness for any

particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document.

Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use

Marvell products in these types of equipment or applications.

With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees:

1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control

Regulations (" EA R"), to a national of EAR Country Groups D:1 or E:2;

2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are

controlled for national security reasons by the EAR; and,

3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant,

not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons

by the EAR, or is subject to controls under the U.S. Munitions List ("USML").

At all times her eund er, the reci pient o f any such info rmati on ag rees t hat the y sha ll be deem ed to h ave m anuall y sign ed this document in con nection with their receip t of an y

such information.

Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell.

Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, a nd VCT are trad emarks of Marvell. All

other trademarks are the property of their respective owners.

88PH8101

Datasheet

Page 2 Document Classification: Proprietary February 4, 2009, 2.00

88PH8101

Field Programmable, High Voltage Synchronous

Switching Regulator Controller

February 4, 2009, 2.00 Document Classification: Proprietary Page 3

PRODUCT OVERVIEW

The Marvell® 88PH8101 is a simple, easy to use

synchronous switching regulator controller. A digital

control algorithm provides a fast transient response and

requires no external compensation components,

minimizing the external componen t count. A feature

unique with Marvell regulators is the abi lity to set the

output voltage with either an external resistor , logic

programmability, or serial interface.

Portable devices place tough design requirements on the

power supply. To address these applications, the

88PH8101 operates as a fixed-frequency PWM when

the load currents are high and automatically switches

over to a pulse-skipping DCM mode at light loads. This

characteristic results in high efficiency over a wide range

of load currents.

Current limit utilizes the RDS(ON) of the upper MOSFET

eliminating the need for a current sense resistor . Other

key features of the 88PH8101 include soft start, short

detection, under/over input voltage detection, diode

emulation, forced PWM mode, adaptive dead time, and a

power good signal.

Features

Operates from a 4.75V to 16V input

Output voltage from 0.9V to 5.5V

500kHz switching frequency

Stable with low-ESR ceramic output capacitors

Up to 95% efficiency

Drives N-channel MOSFETs

Upper MOSFETs RDS (on) current limiting

2.5mA quiescent current (DCM-mode)

Pre-bias Soft Start (DCM-Mode)

Serial / Logic Programmability

AnyVoltage™ Technology provides 72 output voltage

selections to provide up most flexibility

Input over voltage protection

Output voltage margining capability

Lead-free package

TSSOP-16L package

Applications

Point-of-load power supplies

12V PCI Express Bus

Figure 1: Typical Application Diagram for High Efficiency Step-Down Regulator

Caution! Caution: This is a very high frequency device. Proper PCB layout is required. Section 6.1, PC Board Layout

Considerations and Guidelines, on page 45.

470k

43k

IRF7832

0.22uF

47uF/6.3V

0.1uF

OUT

88PH8101

CSH 15

VIN 16

PSET

PWM/SDI

VSET

ILIM

SFB

TG 13

8PGND 9

BG 10

VCC 11

GND

VBS 12

VSW 14

10uF/25V

100K

10uF/25V

4.7uF

5V/5A

4.2uH

IRF7821

12V

0 Ohm

NOB

C10

47uF/6.3V C11

47uF/6.3V C12

47uF/6.3V

88PH8101

Datasheet

Page 4 Document Classification: Proprietary February 4, 2009, 2.00

THIS PAGE INTENTIONALLY LEFT BLANK

Table of Contents

February 4, 2009, 2.00 Document Classification: Proprietary Page 5

Table of Contents

Table of Contents .......................................................................................................................................5

List of Figures.............................................................................................................................................7

List of Tables ..............................................................................................................................................9

1 Signal Description.......................................................................................................................11

1.1 Pin Configuration.............................................................................................................................................11

1.2 Pin Descriptions..............................................................................................................................................11

2 Electrical Specifications .............................................................................................................15

2.1 Absolute Maximum Ratings ............................................................................................................................15

2.2 Recommended Operating Conditions.............................................................................................................16

2.3 Electrical Characteristics.................................................................................................................................16

2.4 Switching Step-down Regulator.............. ... ...................... ...................... ....................... ... ........ .......................18

3 Functional Description................................................................................................................21

3.1 Overview .........................................................................................................................................................21

3.2 Regulation and Start-up.......................... ...................... ....................... ...................... .....................................22

3.3 Soft Start.........................................................................................................................................................23

3.4 Output Voltage Setting................... .................................................................................................................23

3.4.1 Logic Programmability......................................................................................................................23

3.4.2 Serial Programmability........................................................ .......................................... ....................24

3.5 Output Voltage—AnyVoltage™ Technology...................................................................................................26

3.6 Thermal Shutdown..........................................................................................................................................28

3.7 PFM or PWM Mode Selection...... .. .......................................... .......................................... .............................28

3.8 Under Voltage Lockout (UVLO) ................................. ....................... ...................... ........................................28

3.9 Over Voltage Protection (OVP).......................................................................................................................28

3.10 Power Good (PG)............................................................................................................................................29

3.11 Hiccup Current Limit........................................................................................................................................29

4 Functional Characteristics .........................................................................................................31

4.1 Startup Waveforms .......... ... ... .........................................................................................................................31

4.2 Switching Waveforms..................... ....................... .......................................... ................................................32

4.3 Load Transient Waveforms.............................................................................................................................34

4.3.1 Step-Down Regulator ......................................................................................................................34

4.4 Output Voltage Transient Waveforms.............................................................................................................36

4.4.1 Step-Down Regulator .......................................................................................................................36

88PH8101

Datasheet

Page 6 Document Classification: Proprietary February 4, 2009, 2.00

5 Typical Characteristics ...............................................................................................................37

5.1 Efficiency.........................................................................................................................................................37

5.2 IC Case, MOSFET, and Inductor Temperature................ ... ... ...................... ...................... .............................37

5.3 Input Voltage ..................................................................................................................................................40

5.3.1 Step-down Regulator........................................................................................................................41

5.4 Temperature....................................................................................................................................................42

5.4.1 Step-down Regulator ......................................................................................................................43

6 Applications Information ........ ... .... ... ... ................ ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ......................45

6.1 PC Board Layout Considerati ons and Guidelines...........................................................................................45

6.1.1 PC Board Layout Example ...............................................................................................................47

6.1.2 Bill of Materials .......................................................... .......................................... .............................51

7 Mechanical Drawings..................................................................................................................53

7.1 Mechanical Drawing........................................................................................................................................53

7.2 Mechanical Dimensions ..................................................................................................................................54

7.3 Typical Pad Layout Dimensions......................................................................................................................55

7.3.1 Recommended Solder Pad Layout...................................................................................................55

8 Part Order Numbering / Package Marking ................................................................................57

8.1 Part Order Numbering Scheme.......................................................................................................................57

8.2 Part Ordering Options...... .......................................... .......................................... ...........................................57

8.3 Package Marking ....................................................... .....................................................................................58

A Revision History ..........................................................................................................................59

List of Figures

February 4, 2009, 2.00 Document Classification: Proprietary Page 7

List of Figures

Figure 1: Typical Application Diagram for High Efficiency Step-Down Regulator..............................................3

1 Signal Description ........................................................................................................................... 11

Figure 2: TSSOP-16 Diagram (Top View) .......................................................................................................11

2 Electrical Specifications ................................................................................................................. 15

3 Functional Description.................................................................................................................... 21

Figure 3: Block Diagram ..................................................................................................................................21

Figure 4: Output Voltage Window....................................................................................................................22

Figure 5: Soft Startup (1V, 1.5V, 2.5V, 3.3V, 5V) ............................................................................................23

Figure 6: Serial Programmability......................................................................................................................24

Figure 9: Power Good Operating Waveform....................................................................................................29

4 Functional Characteristics.............................................................................................................. 31

Figure 10: Startup Using the Enable Pin ...........................................................................................................31

Figure 11: Turn Off Using the Enable Pin................... ...................... ... ...................... ........................................31

Figure 12: Soft Start ..........................................................................................................................................31

Figure 13: Hot Plug............................................................................................................................................31

Figure 14: PWM Mode ......................................................................................................................................32

Figure 15: PWM Mode ......................................................................................................................................32

Figure 16: DCM Mode .......................................................................................................................................32

Figure 17: DCM Mode-zoom..............................................................................................................................32

Figure 18: PWM Output Ripple Voltage .........................................................................................................33

Figure 19: Fast Load Rise Time ........................................................................................................................34

Figure 20: Slow Load Rise Time........................................................................................................................34

Figure 21: Fast Load Fall Time .........................................................................................................................34

Figure 22: Slow Load Fall Time.........................................................................................................................34

Figure 23: Load Transient Response ................................................................................................................35

Figure 24: Double-Pulsed Load Response........................................................................................................35

Figure 25: Load Transient Response ................................................................................................................35

Figure 26: Double-Pulsed Load Response........................................................................................................35

Figure 27: VOUT = 1.0V to 1.2V with ILoad = 0A ...............................................................................................36

Figure 28: VOUT = 1.0V to 1.5V with ILoad = 0A ................................................................................................36

5 Typical Characteristics ................................................................................................................... 37

Figure 29: Efficiency vs. Output Current............................................................................................................37

Figure 30: Efficiency vs. Output Current in Log Scale .......................................................................................37

Figure 31: Input Current vs. Output Current ......................................................................................................38

Figure 32: IC Case Temperature vs. Output Current.........................................................................................38

Figure 33: Top FET Temperature vs. Output Current........................................................................................38

88PH8101

Datasheet

Page 8 Document Classification: Proprietary February 4, 2009, 2.00

Figure 34: Bottom FET Temperature vs. Output Current...................................................................................39

Figure 35: Inductor Temperature vs. Output Current.........................................................................................39

Figure 36: Supply Current vs. Input Voltage............... .. ....................... ... ...................... ... ..................................40

Figure 37: Shutdown Supply Current vs. Input Voltage.....................................................................................40

Figure 38: Enable Threshold vs. Input Voltage..................................................................................................40

Figure 39: Output Voltage vs. Input Voltage......................................................................................................41

Figure 40: Efficiency vs. Input Voltage...............................................................................................................41

Figure 41: Load Regu lation vs. Input Voltage....................................................................................................41

Figure 42: Frequency vs. Input Voltage.............................................................................................................41

Figure 43: Average Output Current Limit vs. Input Voltage ...............................................................................41

Figure 44: Supply Current vs. Temperature............................................ .. ....................... ... ...............................42

Figure 45: UVLO Threshold vs. Temperature....................................................................................................42

Figure 46: OVP Threshold vs. Temperature......................................................................................................42

Figure 47: Enable Threshold vs. Temperature ..................................................................................................42

Figure 48: Shutdown Supply Current vs. Temperature......................................................................................42

Figure 49: Output Voltage vs. Temperature.......................................................................................................43

Figure 50: Efficiency vs. Temperature...............................................................................................................43

Figure 51: Load Regulation vs. Temperature ....................................................................................................43

Figure 52: Line Regulation vs. Temperature......................................................................................................43

Figure 53: Frequency vs. Tempera ture..............................................................................................................43

Figure 54: Average Output Current Limit vs. Temperature................................................................................43

6 Applications Information .................................... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ................ ............ 45

Figure 55: PCB Board Schematic......................................................................................................................46

Figure 56: Top Silk-Screen, Top Traces, Vias, and Copper (Not to Scale) .......................................................47

Figure 57: GND_La yer2 Vias, and Copper (Not to Scale).................................................................................48

Figure 58: GND_La yer3 Vias, and Copper (Not to Scale).................................................................................49

Figure 59: Bottom Silk Screen, Bottom Traces, Vias, and Copper (Not to Scale).............................................50

7 Mechanical Drawings ...................................................................................................................... 53

Figure 60: 16-Pin TSSOP Mechanical Dr awing.................................................................................................53

Figure 61: TSSOP-16 Land Pattern (mm) .........................................................................................................55

8 Part Order Numbering / Package Marking..................................................................................... 57

Figure 62: Sample Part Number........................................................................................................................57

Figure 63: Package Marking and Pin 1 Location ...............................................................................................58

List of Tables

February 4, 2009, 2.00 Document Classification: Proprietary Page 9

List of Tables

1 Signal Description ............................................................................................................................11

Table 1: Pin Types..........................................................................................................................................11

Table 2: Pin Descriptions................................................................................................................................12

2 Electrical Specifications ..................................................................................................................15

Table 3: Absolute Maximum Ratings..............................................................................................................15

Table 4: Recommended Operating Conditions...............................................................................................16

Table 5: Electrical Characteristics ..................................................................................................................16

Table 6: Switching Step-down Regulator ........................................................................................................18

3 Functional Description.....................................................................................................................21

Table 7: Output Voltage Setting......................................................................................................................23

Table 8: Default Value of Data Field...............................................................................................................24

Table 9: Voltage and Percent Set...................................................................................................................25

Table 10: VSET and PSET Programming Table for 5% Resistors...................................................................26

Table 11: Number of Voltage Steps for Each Output .......................................................................................27

4 Functional Characteristics...............................................................................................................31

5 Typical Characteristics ....................................................................................................................37

6 Applications Information .................................... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ................ .............45

Table 12: BOM ..................................................................................................................................................51

7 Mechanical Drawings .......................................................................................................................53

Table 13: 16-Pin TSSOP Dimensions ..............................................................................................................54

8 Part Order Numbering / Package Marking......................................................................................57

Table 14: Part Ordering Options.......................................................................................................................57

Table 15: Revision History................................................................................................................................59

88PH8101

Datasheet

Page 10 Document Classification: Proprietary February 4, 2009, 2.00

THIS PAGE INTENTIONALLY LEFT BLANK

Signal Description

Pin Configuration

February 4, 2009, 2.00 Document Classification: Proprietary Page 11

1Signal Description

1.1 Pin Configuration

Figure 2: TSSOP-16 Diagram (Top View)

1.2 Pin Descriptions

Table 1: Pin Types

15 CSH

14 VSW

16 VIN

12 VBS

11 VCC

13 TG

9PGND

10 BG

PSET

VSET

SFB

GND

ILIM

PWM/SDI

Pin Type Definitions

I Input Only

O Output Only

S Supply

NC Not Connected

GND Ground

88PH8101

Datasheet

Page 12 Document Classification: Proprietary February 4, 2009, 2.00

Table 2: Pin Descriptions

Pin # Pin Name Pin Type Pin Function

1 EN I Enable

Logic high (> 2.0V) enables the regulator and logic low (< 0.8V) disables

the regulator. If the pin is left fl oating, an internal 10 μA current source pulls

this pin high to enable the regulator. (see Table 5, Electrical

Characteristics, on p age 16)

Do not float this pin.

2 PSET I Percent Set

1. This is used for selecting the output voltage leve l when it is connected

to GND or VCC in conjunction with VSET connection to GND or VCC.

2. Connect an external resistor to ground to set the output voltage of the

step-down switching regulator. See Table 5, Electrical Characteristics,

on page 16 for resistor values and Output Voltage Settings section.

The total capacitance across this pin and GND should be equal to 25pF o r

less. Use resistor values with a tolerance of 5% tolerance or better.

Do not float this pin.

3 VSET I Voltage Set

1. This is used f or select in g t he o utp ut vo ltage level, when i t i s conn ected

to GND or VCC in conjunction with PSET connection GND or VCC.

2. Connect to an external resistor f rom VSET to GND to set eight nominal

output voltages. See Table 11, Number of Voltage Steps for Each

Output, on page 27.

The total capacitance across this pin and GND should be equal to 25pF o r

less. Use resistor va lues wi t h a to lera nce of 5% t ole ra nce or be tter. Do not

float this pin.

4 ILIM I Current Limit Setting Point

Connect a resistor to GND to set the peak current limit.

ILIM = 0.2 * 20 µA * REXT/RDSON (Top FET)

5 SFB I Switch Regulator Output Voltage Sense Feedback

Senses the output volt age of the switching regul ator. Connect to the output

capacitor of the switching regulator.

6 GND GND Signal Ground

This pin must be connected to PGND and make a star connection to

system ground.

7PWM/

SDI I PWM / Serial Data Input

1. Logic high (> 2.0V) enables PWM mode operation and logic low (<

0.8V) to enable DCM mode operation at light loads. If the pin is lef t

floating, an internal 10μA current source pulls this pin low, enabling

DCM mode operation.

2. The input data into this pin is used to program the output voltage. See

Section 3.4.2, Serial Programmability, on page 24.

3. Do not float this pin.

8 PG O Power Good (active high)

This is an open-drain output that indicates the status of the output voltage.

The output is pulled to ground when the output volt age is not within the

specified tole rance. A 40μs fa lling edge de -glitch delay prevent s tripp ing of

the power good comparat or due to high frequency noise.

Signal Description

Pin Descriptions

February 4, 2009, 2.00 Document Classification: Proprietary Page 13

9 PGND GND Power Ground

It must be connected to the negative terminals of the input and output

capacitors.

10 BG O Gate drive for bottom MOSFET

This pin drives the bottom MOSFET gate between 0V and VCC.

11 VCC O Internal 5V Regulator Output

Place a ceramic cap acitor close to this pin.

• For 5V input operation, th e internal LDO is one VTH below VIN. The

internal LDO is not disabled. The VCC pin is connected to VIN for

better efficiency.

12 VBS I Boot-Strap Voltage Node

Place a ceramic capacitor as close as possible to the VBS and VSW pins.

13 TG O Gate drive for top MOSFET

This pin drives the top MOSFET gate between 0V and VIN + VCC

14 VSW I Switching Node

This pin must be con nected to the So urce of top N-channel MOSFET us ing

a Kelvin connection for more accurate current sensing.

15 CSH I Hig h Side Current Sense Input

This pin must be connected to the Drain of top N-channe l MOSFET using a

Kelvin connection for more accurate current sensing.

16 VIN S Internal LDO Input

Power supply for internal LDO for gene rating VCC (5V).

Table 2: Pin Descriptions

Pin # Pin Name Pin Type Pin Function

88PH8101

Datasheet

Page 14 Document Classification: Proprietary February 4, 2009, 2.00

THIS PAGE INTENTIONALLY LEFT BLANK

Electri ca l Specific at io ns

Absolute Maximum Ratings

February 4, 2009, 2.00 Document Classification: Proprietary Page 15

2Electrical Specifications

2.1 Absolute Maximum Ratings

Table 3: Ab solu t e Ma ximu m Rat ings 1

NOTE: Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure . Functionality

at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device

reliability.

1. Exceeding the absolute maximum rating may damage the device.

Parameter Range Units

VVIN to GND -0.3 to 20.0 V

PGND to GND -0.3 to 0.3 V

VSW to PGND2

2. Capable of -1.0V to (VIN +0.3) for less than 50ns.

-0.3 to (VIN + 3.0 ) V

VVCC to GND -0.3 to Minimum (VIN + 0.3, 6.0) V

VEN, VCSH to GND -0.3 to VIN V

VVSET, VPSET to GND -0.3 to 6.0 V

VSFB, VPG, VPWM/SDI, VILIM to GND -0.3 to 6.0 V

VBG to PGND -0.3 to 6.0 V

VTG to VSW -0.3 to 6.0 V

VBS to VSW3

3. During normal operation, VBS is periodically boosted to (VIN + VCC). However, do not externally force the VBS pin to

more than (VCC + 0.3V).

-0.3 to 6.0 V

Operating Ambient Temperature Range4

4. Specifications over the -40°C to 85°C operating temperature ranges are assured by design, characterization and

correlation with statistical process controls.

-40 to 85 °C

Maximum Junction Temperature 150 °C

Storage Temperature Range -65 to 150 °C

Lead Temperature (soldering, 10s) 300 °C

ESD Rating5 Human Body Model

5. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.

2.0 kV

88PH8101

Datasheet

Page 16 Document Classification: Proprietary February 4, 2009, 2.00

2.2 Recommended Operating Conditions

Table 4: Recommended Operating Conditions1

Symbol Parameter Min Typ Max Units

VVIN Input Voltage 4.75 16 V

θJA Package Thermal Resistance286.3 °C/W

θJC 21.5 °C/W

TJMAX Maximum Operating Junction Temperature 125 °C

1. This device is not guaranteed to function outside the specified operating range.

2. Test on 4-layer (JESD51-7) and vias (JESD51-5) board.

2.3 Electrical Characteristics

Table 5: Electrical Characteristics

The following applies unless otherwise noted (refer to schematic shown in Figure 1): VVIN = VEN =12V, VPFM = GND,

GND = PGND, VOUT = 5V, L1 = 4.2μH, C1 = 4.7μF, C2 = 0.22μF, C3 = C4 = 10μF, C6 = 0.1μF, C9 = C10 = C11 = C12

= 47μF, TA = 25°C. Bold values indicate –40°C < TA < 85°C.

Symbol Parameter Conditions Min Typ Max Units

VVIN Input Voltage Range 4.75 12 16 V

IQTotal Quiescent Cu rrent

(PFM Mode) No load, VPWM = 0V 2.5 5.8 mA

IQTotal Quiescent Cu rrent

(PWM Mode) No load, VPWM = 5V 21 40 mA

ISHDN Shutdown Supply

Current VEN = 0V, VVIN = 12V 45 65 μA

VUVLO Under Voltage Lockout High Threshold, VVIN

increasing 4.44 TBD V

VUVLO Under Voltage Lockout Low Threshold, VVIN

decreasing TBD 4.35 V

VOVP Over Volt age Protection High Threshold, VVIN

increasing 17.5 18.5 V

VOVP Over Voltage Protection Low Threshold, VVIN

decreasing 16.5 16.7 V

TOTS Over Temperature

Shutdown TJ increasing

(Disable regulat ors) 150 °C

TOTS Over Temperature Shut-

down TJ decreasing

(Enable regulators) 100 °C

VIH EN and PWM Input

Voltage Threshold Logic high 2.0 V

VIL EN and PWM Input

Voltage Threshold Logic low 0.4 V

IEN Enable Input Current VEN = 12V 1μA

IEN Enable Input Current VEN = 0V -10 μA

IPWM PWM Input Current VPWM = 5V 1μA

IPWM PWM Input Current VPWM = 0V 1μA

Electri ca l Specific at io ns

Electrical Characteristics

February 4, 2009, 2.00 Document Classification: Proprietary Page 17

IILIM ILIM Pin Current -5 -10 μA

TC Current Limit ILIM Temperature

Coefficient 2000 ppm

2.3 Electrical Characteristics

Table 5: Electrical Characteristics

The following applies unless otherwise noted (refer to schematic shown in Figure 1): VVIN = VEN =12V, VPFM = GND,

GND = PGND, VOUT = 5V, L1 = 4.2μH, C1 = 4.7μF, C2 = 0.22μF, C3 = C4 = 10μF, C6 = 0.1μF, C9 = C10 = C11 = C12

= 47μF, TA = 25°C. Bold values indicate –40°C < TA < 85°C.

Symbol Parameter Conditions Min Typ Max Units

88PH8101

Datasheet

Page 18 Document Classification: Proprietary February 4, 2009, 2.00

2.4 Switching Step-down Regulator

Table 6: Switching S tep-down Regulator

The following applies unless otherwise noted (refer to schematic shown in Figure 1): VVIN = VEN

=12V, VPFM = GND, GND = PGND, VOUT = 5V, L1 = 4.2μH, C1 = C9 = C10 = C11 = C12 = 4.7μF, C2

= 0.22μF, C3 = C4 = 10μF, C6 = 0.1μF, TA = 25°C. Bold valu es indicate –40°C < TA < 85°C.

Symbol Parameter Conditions Min Typ Max Units

VOUT Output Voltage

(PFM Mode) RVSET = 11K, PFM Mode,

ILOAD = 10mA 1.0 V

RVSET = 18K, PFM Mode,

ILOAD = 10mA 1.2 V

RVSET = 30K, PFM Mode,

ILOAD = 10mA 1.5 V

RVSET = 51K, PFM Mode,

ILOAD = 10mA 1.8 V

RVSET = 100K, PFM Mode,

ILOAD = 10mA 2.5 V

VVSET = 0V, VPSET = 0V, PFM

Mode, ILOAD = 10mA

RVSET = 160K, PFM Mode,

ILOAD = 10mA 3.0 V

VVSET = 0V, VPSET = VCC,

PFM Mode, ILOAD = 10mA

RVSET = 270K, PFM Mode,

ILOAD = 10mA 3.3 V

VVSET = VCC, VPSET = 0V,

PFM Mode, ILOAD = 10mA

RVSET = 470K, PFM Mode,

ILOAD = 10mA 5.0 V

VVSET = VCC, VPSET = VCC,

PFM Mode, ILOAD = 10mA

Electri ca l Specific at io ns

Switching Step-down Regulator

February 4, 2009, 2.00 Document Classification: Proprietary Page 19

VOUT Output Voltage

(PWM Mode) RVSET = 11K, PWM Mode,

ILOAD = 100mA 1.0 V

TA = 25°C -3 +3 %

RVSET = 18K, PWM Mode,

ILOAD = 100mA 1.2 V

TA = 25°C -3 +3 %

RVSET = 30K, PWM Mode,

ILOAD = 100mA 1.5 V

TA = 25°C -2.5 +2.5 %

RVSET = 51K, PWM Mode,

ILOAD = 100mA 1.8 V

TA = 25°C -2.5 +2.5 %

RVSET = 100K, PWM Mode,

ILOAD = 100mA 2.5 V

VVSET = 0V, VPSET = 0V, PWM

Mode, ILOAD = 100mA

TA = 25°C -2 +2 %

RVSET = 160K, PWM Mode,

ILOAD = 100mA 3.0 V

VVSET = 0V, VPSET = VCC,

PWM Mode, ILOAD = 100mA

TA = 25°C -2 +2 %

RVSET = 270K, PWM Mode,

ILOAD = 100mA 3.3 V

VVSET = VCC, VPSET = 0V,

PWM Mode, ILOAD = 100mA

TA = 25°C -2 +2 %

RVSET = 470K, PWM Mode,

ILOAD = 100mA 5.0 V

VVSET = VCC, VPSET = VCC,

PWM Mode, ILOAD = 100mA

TA = 25°C -2 +2 %

PSET Percentage Set RPSET = 11K -10.0 %

PSET Percentage Set RPSET= 18 K -7.5 %

PSET Percentage Set RPSET = 30K -5.0 %

PSET Percentage Set RPSET = 51K -2.5 %

PSET Percentage Set RPSET = 0K 0 %

PSET Percentage Set RPSET = 100K 2.5 %

PSET Percentage Set RPSET = 160K 5.0 %

PSET Percentage Set RPSET = 270K 7.5 %

PSET Percentage Set RPSET = 470K 10.0 %

Symbol Parameter Conditions Min Typ Max Units

88PH8101

Datasheet

Page 20 Document Classification: Proprietary February 4, 2009, 2.00

VLNREG Output Voltage Line

Regulation VVIN = 9V to 12V,

ILOAD = 2.5A 0.01 %

VLDREG Output Voltage Load

Regulation VVIN = 12V,

ILOAD = 2.5A to 5A 0.1 %

fSW Switching Frequency 400 500 600 kHz

DMAX Maximum Duty Cycle 90 %

tDEGLITCH Deglitch 40 µs

VPGTH Power Good (PG)

Threshold Voltage VOUT > 1.35V VOUT ×

90% V

VPGTH Power Good (PG)

Threshold Voltage VOUT < 1.32V VOUT –

130mV V

VPGL Maximum PG Output

Low Volt age ISINK = 1mA 0.4 V

tDELAY PG Delay Time 512 µs

IPG PG Leakage Current VEN = 5.0V 1 20 µA

tDNV Driver Non Overlap CL = 3300 pF 30 ns

tR, tFDriver Rise/Fall Time CL = 3300 pF 15 ns

RSOURCE Output Driver

Impedance

Top Driver

1.5 3 Ω

RSINK Output Driver

Impedance

Top Driver

1.0 2.5 Ω

RSOURCE Output Driver

Impedance

Bottom Driver

1.5 4.2 Ω

RSINK Output Driver

Impedance

Bottom Driver

0.5 2.5 Ω

Symbol Parameter Conditions Min Typ Max Units

88PH8101

Datasheet

Page 21 Document Classification: Proprietary February 4, 2009, 2.00

THIS PAGE INTENTIONALLY LEFT BLANK

3Functional Description

Figure 3: Block Diagram

3.1 Overview

The 88PH8101 incorporates a new controller architecture that minimizes the number of external

passive components, improves efficiency and provides fast transient response. A non-linear control

algorithm is able to detect and react to severe load changes in le ss than 100 ns and requires no

external compensation components, reducing desig n time. Efficiency is improved by having an

adaptive dead time control that reduces the on time of the parasitic diode of the low-side MOSFET.

Lossless switch current sensing utilizes the RDS (ON) of the high-side MOSFET to eliminate the

need for a current sense resistor, improving efficiency. Other features include under and over

voltage lockout, over temperature shutdown, power good detection, and cycle-by-cycle current

limiting.

Additionally, there are 3 simple ways to set the output voltage using external resistors, logic control

or a serial interface. External resistors connected to the VSET and PSET pins are measured once

before start up. These 2 resistors provide up to 72 output voltage options from 0.9V to 5.5V. These

external resistors can be eliminated by tying the VSET and PSET pin high or low, generating 2.5V,

3.0V, 3.3V or 5.0V.

Some applications require voltage margining, forcin g the output voltage a percentage above and

below its nominal value. In this case, the serial interface can be used to change the output ±0%,

±2.5%, ±5.0%, ±7.5%, ±10% or any one of the 72 voltage options.

OSCILLATOR

RESISTOR

SENSIN G

CIRCUITRY

DSP PWM

CONTROL

ANALOG-

DIGITAL

CONVERTER

VSW

SFB

PSET

VSET

C9-C12

R3R4

CSH

PGND

RESISTOR

NETWORK

Serial Data Interface

PWM/SDI

Vout

Power

Good

VBS

4.75 V t o 16V

FAULT

BAND-GAP

VOLTAGE

REFERENCE

OFF

GND

THERMAL

SHUTDOWN

UNDER-

VOLTAGE

LOCKOUT

OUT

VCC

INTERNAL CIRCUITRY

POWER SU PPLY

VIN

VCC

C3-C4

A10

DCM

PWM

Current

Sense

LDO

ILIM

Level

Shift

88PH8101

Datasheet

Page 22 Document Classification: Proprietary February 4, 2009, 2.00

To address portable applications, the 88PH8101 operates as a fixed frequency PWM when the load

currents are high and automatically switches over to pulse skippi ng DCM mode at light loads,

reducing no-load supply current from 21 mA to 2.5mA. F or DDR applications where the converter

must source and sink current, the PWM pin can be tied high, forcing PWM mode under all output

current conditions.

3.2 Regulation and Start-up

The step-down switching regulator can operate in Pulse Width Modulation Mode (PWM), Discontinu-

ous Current Operating Mode (DCM), or Pulse Frequency Mode (PFM). The mode of operation

depends on the level of output current and the output voltage.

In steady states, the step-down switching regulator monitors the current flowing through the inductor

to determine if the regulator is handling a heavy or light load. For heavy loads, the step-d own

regulator operates in the PWM mode (B) to minimize the ripple current for optimum efficiency and to

minimize the ripple output voltage. The step-down regulator automatically switches over to pulse

frequency (PFM) mode (A) at light loads for optimum efficiency in light load applications. In this

mode, the average output voltage is slightly higher than the average output voltage when operating

in PWM mode. In over current conditions and during start up, the regulator operates in PFM mode

(C).

Figure 4: Output Voltage Window

Typical V

OUT

PF M Mod e

PWM Mode

PFM Mode

Functional Description

Soft Start

February 4, 2009, 2.00 Document Classification: Proprietary Page 23

3.3 Soft Start

Soft start is a highly desirable property in “Hot-Plug” applications. It limits the large inrush currents

on the input power supply during start up. The 88PH8101 device controls the rise time of the output

voltage, thereby dramatically reducing the inru sh current. The rise time is tyically 5ms for VOUT

higher than 1.65V and 0.33V/ms for VOUT < 1.65V and it is independent of output capacitance and

load current. Figure 5 shows the rise time for various output voltage settings.

3.4 Output Voltage Setting

3.4.1 Logic Programmability

The output voltage of the step-down switching regulator can be programmed for the standard output

voltages by connecting VSET and PSET pins to GND and/or VCC. This method will eliminate the

use of external resistor to set the output voltage.

VOUT

Figure 5: Soft Startup (1V, 1.5V,

2.5V, 3.3V, 5V)

1V/DIV

1ms/DIV

ILOAD = 1A, COUT = 4x22μF

Table 7: Output Voltage Setting

VVSET VPSET VOUT

GND GND 2.5V

GND VCC 3.0V

VCC GND 3.3V

VCC VCC 5.0V

88PH8101

Datasheet

Page 24 Document Classification: Proprietary February 4, 2009, 2.00

THIS PAGE INTENTIONALLY LEFT BLANK

3.4.2 Serial Programmability

The output voltage of the step-down switching regulator can also be programmed by using 18-bit

serial data into the SDI pin.

Figure 6: Serial Programmability

The first 4 bits (MSB) of the data field are used to select the output voltage where the second 4 bits

(LSB) of the data field are used to trim the output voltage (percent of output voltage). The default

value for the data field is as follows:

BIT

"1"

Pulse "0"

pulse "0"

pulse

"1"

Pulse

"1"

Pulse

"1"

Pulse "1"

Pulse

DATA FIELD

D7 D6 D5 D4 D3 D2 D1 D0

The period of a pul se is 1 μs +/- 200 ns

HIGH

> V

Low

< V

HIGH

LOW

For " 1" pul se, the hi gh i s 0. 75 μs +/- 150 ns

and the low period is 0. 25 μs+/ - 50 ns

For "0" puls e, the high is 0.25 μs +/- 50 ns

and the low period is 0. 75 μs+/- 150 ns

LOW

HIGH

Th e wr i te op er ati o n:

1 ) Ea ch write se quence needs 18 pulses to c ompl e te.

2 ) During a non-writ e operation, t he i npu t need s to be at V

LOW

(<0.8V).

3 ) I n betw een two s ucc essive write operations, the SDI input needs to

be at V

LOW

(<0.8V) for a minimum of 10 μs

Write

sequence 2

Write

sequence

Low fo r at l east

10 μs

WR I TE MODE

"1" p ul se

"0" pulse

BIT

7BIT

6BIT

5BIT

4BIT

3BIT

1BIT

Registor

Address

Chip

Select

Start Stop

Table 8: Default Value of Data Fi el d

Data Field

Description Voltage Set Percent Set

Bits 76543210

Default value 00100100

Functional Description

Output Voltage Setting

February 4, 2009, 2.00 Document Classification: Proprietary Page 25

The value for position 7 and 3 of the register will enable use of either logic or serial output voltage

programmability. Bit value of “0” for positions 7 and 3 will enable the resistor/logic programmability

and the output voltage will be set according to Section 3.4.1 A bit value of “1” will enable the serial

programmability. The output voltage and percent set are selected per following table:

All combinations of the Voltage Set and Percentage Set provide flexability in output voltage

selection, as shown in Table 9.

Table 9: Voltage and Percent Set

Data Field VOUT (V) Data Field Percent Set

Bits 7654 3 210

Value 1000 1.0 1 000 -10%

1 0 0 1 1.2 1 0 0 1 -7.5%

1 0 1 0 1.5 1 0 1 0 -5.0%

1 0 1 1 1.8 1 0 1 1 -2.5%

1 1 0 0 2.5 1 1 0 0 +2.5%

1 1 0 1 3.0 1 1 0 1 +5.0%

1 1 1 0 3.3 1 1 1 0 +7.5%

1 1 1 1 5.0 1 1 1 1 +10%

88PH8101

Datasheet

Page 26 Document Classification: Proprietary February 4, 2009, 2.00

3.5 Output Voltage—AnyVoltage™ Technology

The output voltage of the step-down switching regulator is programmed by using Table 10 to select

resistor values for VSET and PSET pin. The VSET pin sets the output voltage and the PSET pin

trims the set voltage to a percentage value. For example, to program 2.25V output, a 100 kΩ resistor

is selected for the VSET pin, and an 11 kΩ resistor is selected for the PSET pin. The 100 kΩ resistor

sets the output voltage to 2.5V and the 11 kΩ resistor trims the set voltage by -10%.

Using the VSET resistor’s value greater than 619 kΩ or less than 7.68 kΩ disables the step-down

switching regulator and sets the SW pin to high impedance. If the VSET resistor’s value is outside

the 5% tolerance, the output can be either hig her or lower than the set voltage.

Using resistor values greater than 61 9 kΩ or less than 7.68 kΩ for the PSET pin does not affect the

set voltage. When the PSET pin is not used, it must be connected to ground. Like the VSET resistor,

the percent value is either higher or lower if the PSET resistor’s value is outside the 5% tolerance.

The VSET and PSET resistors are read once during start-up before the output voltage is turned on.

After the output voltage is turned on, the output voltage can change to different values using serial

programming interface. Otherwise to configure the output to a different voltage, power has to recycle

or the 88PH8101 has to turn OFF and back ON using the enable pin.

Figure 7 shows the startup waveforms of the 88PH8101. Once the input voltage (VIN) is above the

under voltage lockout (UVLO) upper threshold (UTH), the VSET and PSET pin become active. Cur-

rent is first sourced out of PSET pin and then the VSET pin, in exponentially increasing steps. After

each step there is a blanking time before the VSET voltage is compared to an internal 1.2V refer-

ence. If the VSET voltage is below internal reference voltage and the current source proceeds to the

next set. Once the VSET voltage is above the internal reference voltage the sequence stops and the

output voltage (VOUT) is allowed to turn-on. Figure 7 shows the VSET waveform for VSET = 2.5V

and PSET = –5% output in low-voltage mode. The 88PH8101 keeps track of how many steps were

required to determine the appropriate output voltage. Table 11 provides the number of steps neces-

sary for each output voltage option. Using a VSET resistor of 100kΩ requires the current source to

step 5 times, and a PSET resistor of 30 kΩ requires 7 steps.

Table 10: VSET and PSET Programming Table for 5% Resistors

Percentage Set (%)

-10.00% -7.50% -5.00% -2.50% 0% 2.50% 5.00% 7.50% 10%

11K 18K 30K 51K GND 100K 160K 270K 470K

Voltage Set (V)

11K 0.900 0.925 0.950 0.975 1.00 1.025 1.050 1.075 1.100

18K 1.080 1.110 1.140 1.170 1.20 1.230 1.260 1.290 1.320

30K 1.350 1.388 1.425 1.463 1.50 1.538 1.575 1.613 1.650

51K 1.620 1.665 1.710 1.755 1.80 1.845 1.890 1.935 1.980

100K 2.250 2.313 2.375 2.438 2.50 2.563 2.625 2.688 2.750

160K 2.700 2.775 2.850 2.925 3.00 3.075 3.150 3.225 3.300

270K 2.970 3.053 3.135 3.218 3.30 3.383 3.465 3.548 3.630

470K 4.500 4.625 4.750 4.875 5.00 5.125 5.250 5.375 5.500

Functional Description

Output Voltage—AnyVoltage™ Technology

February 4, 2009, 2.00 Document Classification: Proprietary Page 27

The 88PH8101 provides an innovative techni que to set the output voltage. During start-up it reads

the value of external resistors, which are located outside the regulator’s feedback loop, to program

the output voltage. By placing the output voltage programmi ng resistor outside the regulator’s

feedback loop, its tolerance does not affect the accuracy of the output voltage. While in conventional

designs, adjustable regulators use 1% resistors to set the output voltage. However, these resistors

are located inside the feedback loop, introducing as much as 2% of initial accuracy error to the

output voltage, resulting in an overall initial accuracy of 3%. Whereas, the 88PH8101 initial accuracy

is 2% for any of the eight output voltages.

The VSET and PSET pins are sensitive to excessive leakage currents and stray capacitance. The

output voltage can potentially be programmed to the lower output voltage if ther e is contamination,

which introduces excessive leakage current on the VSET and PSET pin, especially for a RVSET and

RPSET of 470kΩ. The parasitic resistance on these nodes must be greater th an 3MΩ and the stray

capacitance must be less than 25pF; otherwise, a 5.0V output can po tential end up at 3.3V in

low-voltage mode.

VIN

VOUT

VVSET

VPSET

Figure 7: Startup Sequence

5V/DIV

2V/DIV

VVSET

VPSET

Figure 8: Soft Startup

500 mV/DIV

10ms/DIV 200µs/DIV

Table 11: Number of Voltage Steps for Each Output

Step VOUT (V) RVSET (kΩ)Step PSET (%) RPSET (kΩ)

100 100

25.0 470 2+10 470

33.3 270 3+7.5 270

43.0 160 4+5.0 160

52.5 100 5+2.5 100

61.8 51 6-2.5 51

71.5 30 7-5.0 30

81.2 18 8-7.5 18

91.0 11 9-10 11

88PH8101

Datasheet

Page 28 Document Classification: Proprietary February 4, 2009, 2.00

3.6 Thermal Shutdown

When the junction temperature of the 88PH8101 exceeds OTS high threshold, the th ermal

shutdown circuitry disables the step-down regulator. The step-down switching regulator is enabled

when the junction temperature is decreased to OTS low threshold.

3.7 PFM or PWM Mode Selection

When PFM pin is connected to high state, the regulator is in the forced PWM mode , where the

regulator runs at a constant frequency. The quiescent current of t he f orced PWM mode increases to

21mA (typical). When PFM pin is connected to a low state, the regulator runs in PFM mode, where

the switching frequency decreases when the load current reduces, thus improving the light load

efficiency.

3.8 Under Voltage Lockout (UVLO)

The Under Voltage Lockout (UVLO) feature insures that both MOSFETs have adequate voltage

levels to operate properly. When the input voltage drops below UVLO low threshold, both MOSFETs

are off until the input rises above UVLO high threshold. See Section 2.3 for the UVLO low and high

threshold voltages.

3.9 Over Voltage Protection (OVP)

For Over Voltage Protection (OVP), an over voltage comparator guards against transient

overshoots, as well as other serious conditions, that may damage the IC. When the input voltage is

above the OVP high threshold voltage, both external high-side N-channel MOSFET are turned off

until the input voltage drops below the OVP low threshold voltage. See section 2.3 for the OVP low

and high voltages..

VOVP_HTH

VUVLO-HTH

VUVLO-LTH

VOVP-LTH

Undefined

BUCK Output

Disable

BUCK Output

Enable

VIN

Functional Description

Power Good (PG)

February 4, 2009, 2.00 Document Classification: Proprietary Page 29

3.10 Power Good (PG)

The Power Good (PG) pin is an active-high, open-drain output pin. It is low when the output voltage

of the step-down regulator is below the threshold. When the output voltage is above the threshold for

more than 512µs (tDELAY), the power good pin goes high. The threshold voltage is 0.9% * VOUT

(typical) for all output voltage settings. A built-in tDEGLITCH (40µs typical) delay is incorporated to

prevent nuisance tripping.

Figure 9: Power Good Operating Waveform

3.11 Hiccup Current Limit

The “Hiccup“ short-circuit protection is a featur e that is not common among other switching

regulators. Hiccup mode offers extra protection against over current situations, since it limits the

average current to the load, reducing power dissipation and case temperature of the IC. When the

current-sense circuit sees an over-current condition together with a low output voltage condition

(VOUT < 75% nominal), the 88PH8101 device shuts off for about 2ms and then tries to start up

again. If the over-load condition is removed, the devices will start-up normally; otherwise, the IC will

see another over-current event and shut off once again, repeating the previous cycle.

DELAY

DEGLITCH

< t

DEGLITCH

RPG_PULLUP × IPG

VPGL

PG_TH

88PH8101

Datasheet

Page 30 Document Classification: Proprietary February 4, 2009, 2.00

THIS PAGE INTENTIONALLY LEFT BLANK

Functional Characteristics

S tar tup Waveform s

February 4, 2009, 2.00 Document Classification: Proprietary Page 31

4Functional Characteristics

Unless otherwise noted, the following typical scope photographs were taken using test circuit shown

in figure 1 at TA = 25°C.

4.1 Startup Waveforms

NOTE: When the input voltage rises above the UVLO’s upper threshold, then there is a delay (4ms typ)

before the step-down regulator ’s output voltage powers on.

VEN

VOUT

Figure 10: Startup Using the Enable

5V/DIV

2V/DIV

VEN

VOUT

Figure 11: Turn Off Using the

Enable Pin

5V/DIV

2V/DIV

5ms/DIV 5ms/DIV

VIN = 12V ILOAD = 10mA VIN = 12V ILOAD = 10mA

VOUT = 5V VOUT = 5V

VIN

VOUT

VPG

Figure 12: Soft Start

5V/DIV

VIN

VOUT

VPG

Figure 13: Hot Plug

5V/DIV

10ms/DIV 10ms/DIV

VIN = 12V ILOAD = No Load VIN = 12V ILOAD = No Load

VOUT = 5V VOUT = 5V

88PH8101

Datasheet

Page 32 Document Classification: Proprietary February 4, 2009, 2.00

4.2 Switching Waveforms

NOTE: For repeatabili ty of measuring output ripple (VOUT (P-P)) for th e BUCK regulator, the standard test

procedure limit s the scope bandwidth to 20MHz and uses a coax cable with very short leads

terminated into 50Ω. The coax leads must be routed away from the switching node as much as

possible.

VSW

IIND

VOUT

VIN

Figure 14: PWM Mode

10V/DIV

5A/DIV

50mV/DIV

VSW

IIND

VOUT

VIN

Figure 15: PWM Mode

10V/DIV

5A/DIV

50mV/DIV

1μs/DIV 1μs/DIV

CIN = 4x22μFVIN(P-P) = 57.1mV CIN = 8x22μFVIN(P-P) = 47.6mV

VIN = 12V IIND(P-P) = 2. 1A VIN = 12V IIND(P-P) = 2.06A

VOUT = 5V IIND(PK) = 6A VOUT = 5V IIND(PK) = 6.05A

ILOAD = 5A Frequency = 500kHz ILOAD = 5A Frequency = 500kHz

VOUT(P-P) = 22.7mV (note) VOUT(P-P) = 28.3mV (note)

VSW

VOUT

IIND

Figure 16: DCM Mode

10V/DIV

50mV/DIV

1A/DIV

VSW

VOUT

IIND

Figure 17: DCM Mode-zoom

10V/DIV

50mV/DIV

1A/DIV

5μs/DIV 2μs/DIV

VIN = 12V ILOAD = 24mA VIN = 12V ILOAD = 24mA

VOUT = 5V IIND(PK) = 1.82A VOUT = 5V Ringing Frequency = 1.8MHz

VOUT(P-P) = 60.4mV (note) Frequency = 49kHz

Functional Characteristics

Switching Waveforms

February 4, 2009, 2.00 Document Classification: Proprietary Page 33

VOUT

Figure 18: PWM Output Ripple

Voltage

20mV/DIV

100ms/DIV

VIN = 12V ILOAD = 5A

VOUT = 5V VOUT(P-P) = 35.3mV (Note)

88PH8101

Datasheet

Page 34 Document Classification: Proprietary February 4, 2009, 2.00

4.3 Load Transient Waveforms

4.3.1 Step-Down Regulator

VSW

VOUT

ILOAD

IIND

Figure 19: Fast Load Rise Time

10V/DIV

50mV/DIV

2A/DIV

VSW

VOUT

ILOAD

IIND

Figure 20: Slow Load Rise Time

10V/DIV

50mV/DIV

2A/DIV

5μs/DIV 5μs/DIV

VIN = 12V COUT = 4 x 47μFVIN = 12V COUT = 4 x 47μF

VOUT = 5V tRISE = 50A/μsV

OUT = 5V tRISE = 2.5A/μs

ILOAD = 2A to 5A ILOAD = 2A to 5A

VSW

VOUT

ILOAD

IIND

Figure 21: Fast Load Fall Time

10V/DIV

50mV/DIV

2A/DIV

VSW

VOUT

ILOAD

IIND

Figure 22: Slow Load Fall Time

10V/DIV

50mV/DIV

2A/DIV

5μs/DIV 5μs/DIV

VIN = 12V COUT = 4 x 47μFVIN = 12V COUT = 4 x 47μF

VOUT = 5V tRISE = 230A/μsV

OUT = 5V tRISE = 2.5A/μs

ILOAD = 5A to 2A ILOAD = 5A to 2A

Functional Characteristics

Load Transient Waveforms

February 4, 2009, 2.00 Document Classification: Proprietary Page 35

VOUT

ILOAD

Figure 23: Load T ransient Response

200mV/DIV

2A/DIV

VOUT

ILOAD

Figure 24: Double-Pulsed Load

Response

200mV/DIV

2A/DIV

20μs/DIV 20μs/DIV

VIN = 12V COUT = 4 x 47μFVIN = 12V COUT = 4 x 47μF

VOUT = 5V tRISE = 50A/μsV

OUT = 5V tRISE = 50A/μs

ILOAD = 2A to 5A tFALL = 230A/μsI

LOAD = 2A to 5A tFALL = 230A/μs

VOUT

ILOAD

Figure 25: Load T ransient Response

200mV/DIV

2A/DIV

VOUT

ILOAD

Figure 26: Double-Pulsed Load

Response

200mV/DIV

2A/DIV

20μs/DIV 20μs/DIV

VIN = 12V COUT = 4 x 47μFVIN = 12V COUT = 4 x 47μF

VOUT = 5V tRISE = 50A/μsV

OUT = 5V tRISE = 50A/μs

ILOAD = 1A to 3A tFALL = 230A/μs I

LOAD = 1A to 3A tFALL = 230A/μs

88PH8101

Datasheet

Page 36 Document Classification: Proprietary February 4, 2009, 2.00

4.4 Output Voltage Transient Waveforms

The following graphs show the effect of changing the step-down regulator’s output voltage using the

serial interface. Depending on the change in the step-size of the output voltage, the output load, and

the output capacitance, the power-on reset pin de-asserts when the changes of the output voltage

occur beyond the 25μs (typical) delay.

4.4.1 Step-Down Regulator

VOUT

VPG

VSDI

Figure 27: VOUT = 1.0V to 1.2V with

ILoad = 0A

1V/DIV

5V/DIV

VOUT

VPG

VSDI

Figure 28: VOUT = 1.0V to 1.5V with

ILoad = 0A

1V/DIV

5V/DIV

100μs/DIV 100μs/DIV

VIN = 12V VIN = 12V

COUT = (4 x 47μF) + 1000μFC

OUT = (4 x 47μF) +1000μF

Typical Ch ara ct erist ics

Efficiency

February 4, 2009, 2.00 Document Classification: Proprietary Page 37

5Typical Characteristics

Unless otherwise noted, the following typical scope photographs were taken using test circuit shown

in figure 1 at TA = 25°C.

5.1 Efficiency

Figure 29: Efficiency vs. Output Current

Figure 30: Efficiency vs. Output Current in Log Scale

5.2 IC Case, MOSFET, and Inductor Temperature

The following data was taken using a 2.0 square inch PCB 1 oz. copper and L = 4.2μH. Actual

results depend upon the size of the PCB proximity to other heat emitting components

Efficiency vs. Output Current

Vin = 12.0V

100

012345

Output Current (A)

Effici ency (%)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Efficiency vs. Output Current

Vin = 9.0V

100

012345

Output Current (A)

Effici ency (%)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Effi ciency vs. Output Current

Vin = 12.0 V

100

0.01 0.1 1 10

Ou tp u t Current (A)

E fficien cy (%)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Efficiency vs. Output Current

Vin = 9.0V

100

0.01 0.1 1 10

Output Current (A)

Effi ciency (%)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

88PH8101

Datasheet

Page 38 Document Classification: Proprietary February 4, 2009, 2.00

Figure 31: Input Current vs. Output Current

Figure 32: IC Case Temperatur e vs. Output Current

Figure 33: Top FET Temperature vs. Output Current

Input Curr ent vs. Out put Curr ent

Vin = 12V, TA = 25°C

0.0

1.0

2.0

3.0

4.0

5.0

6.0

012345678910

Output Curre nt (A)

In put Cu r r en t (A)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Input Current vs. Output Current

Vin = 9.0V, TA = 25°C

0.0

1.0

2.0

3.0

4.0

5.0

012345678910

Output Curre nt (A)

Input Current (A)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

IC Case Tem per a t ur e vs. O utput Current

Vin = 12V, TA = 2 5°C

100

012345678910

Outp u t Cu r r ent (A)

Tem p er atu re (°C)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

IC Case Temperature vs. Output Current

Vin = 9 . 0 V, TA = 25°C

012345678910

Output Curre nt (A)

Tem p eratu r e (°C)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Top FET Temperatur e vs. Out put Curr ent

Vin = 12V, TA = 25°C

100

110

012345678910

Output Current (A)

Tem per atur e (°C)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Top FET Tem per ature v s. O u t put Curr e nt

Vin = 9.0V, TA = 25°C

100

012345678910

Output Current (A)

Temperatu r e (°C)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Typical Ch ara ct erist ics

IC Case, MOSFET, and Inductor Temperature

February 4, 2009, 2.00 Document Classification: Proprietary Page 39

Figure 34: Bottom FET Temperature vs. Output Current

Figure 35: Inductor Temperature vs. Output Current

Bottom FET Temperat ure vs. O ut put Curr ent

Vin = 1 2V, TA = 25° C

100

110

120

012345678910

Out put Cur rent (A )

Tem p eratu re (°C)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Bott o m FET Tem p er atur e v s. Outp ut Cur r e nt

Vin = 9. 0V, TA = 25 ° C

100

110

012345678910

Output Current (A)

Tem p er atu r e (°C)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Inductor Temperat ur e vs. Output Current

Vin = 12V, TA = 2 5°C

012345678910

Outp ut Cur r en t ( A)

Tem p eratur e (°C)

5.0V

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

Induct or Tem pera t ure vs. Output Curre nt

Vin = 9. 0V, TA = 2 5° C

012345678910

Outp u t Cu r r ent (A)

Tem p eratu re (°C)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

88PH8101

Datasheet

Page 40 Document Classification: Proprietary February 4, 2009, 2.00

5.3 Input Voltage

Figure 36: Supply Current vs . Input

Voltage Figure 37: Shutdown Supply

Current vs. Input Voltage

ILOAD = No Load VIN = 12V; ILOAD = No Load; VEN = 0V

Figure 38: Enable Threshold vs.

Input Voltage

ILOAD = 10mA

Supply Current vs. Input Voltage

PFM Mode

0.0

1.0

2.0

3.0

9.0 10.0 11.0 12.0 13.0 14.0

Input Voltage (V)

Cu rrent (mA)

Shutdow n Supply Current vs. Input Voltage

9.0 10.0 11.0 12.0 13.0 14.0

Input Voltage (V)

Current (μA)

Enable Threshold vs. Input Voltage

0.5

1.0

1.5

2.0

2.5

9 1011121314

Input Voltage (V)

Voltage (V)

UTH-Enable

LTH-Disable

Typical Ch ara ct erist ics

Input Voltage

February 4, 2009, 2.00 Document Classification: Proprietary Page 41

5.3.1 Step-down Regulator

Figure 39: Output Voltage vs. Input

Voltage Figure 40: Efficiency vs. Input

Voltage

ILOAD = 2.5A VOUT = 5V; ILOAD = 5A

Figure 41: Load Regulation vs.

Input Voltage Figure 42: Frequency vs. Input

Voltage

VOUT = 5V; ILOAD = 2. 5 - 5A VOUT = 5V; ILOAD = 5A

Figure 43: Average Output Current

Limit vs. Input Voltage

Output Voltage vs. Input Voltage

4.90

4.95

5.00

5.05

5.10

91011121314

Input Voltage (V)

Output Voltage (V)

Efficiency vs. I n pu t Voltage

90%

93%

95%

98%

100%

9 1011121314

Input Voltage (V)

Efficiency

Load Regulation vs. Input Voltage

-0.20%

-0.10%

0.00%

0.10%

0.20%

9 1011121314

Input Voltage (V)

Load Regulation

Frequency vs. I np ut Voltage

450

475

500

525

550

9 1011121314

Input V oltage (V)

Frequenc y (kHz

)

Average Output Current Limit vs. Input Voltage

9 1011121314

Input Voltage (V)

Curr ent (A)

88PH8101

Datasheet

Page 42 Document Classification: Proprietary February 4, 2009, 2.00

5.4 Temperature

Figure 44: Supply Current vs.

Temperature Figure 45: UVLO Threshold vs.

Temperature

ILOAD = No Load; VPWM = 0V ILOAD = 10mA

Figure 46: OVP Threshold vs.

Temperature Figure 47: Enable Threshold vs.

Temperature

ILOAD = 10mA ILOAD = 10mA

Figure 48: Shutdown Supply

Current vs. Temperature

ILOAD = No Load; VEN = 0V

Supply Current vs. T emperature

PFM Mode

-40-200 20406080

T emperature ( ° C)

Current (mA)

UVLO Threshold vs. Tem perature

-40 -20 0 20 40 60 80

Temperature (°C)

Voltage (V)

UTH

LTH

OVP Threshold vs. Temperature

-40 -20 0 20 40 60 80

Temperature (°C)

Voltage (V)

OVP HI GH

OVP LOW

Enabl e Threshold vs. Temperature

0.5

1.0

1.5

2.0

2.5

-40 -20 0 20 40 60 80

Temperature (°C)

Vol tage (V)

UTH - Enable

LTH - Disable

Shutdow n Supply Current vs.Temperature

-40-200 20406080

T emperature (°C)

Curre nt (uA)

Typical Ch ara ct erist ics

Temperature

February 4, 2009, 2.00 Document Classification: Proprietary Page 43

5.4.1 Step-down Regulator

Figure 49: Output Voltage vs.

Temperature Figure 50: Efficiency vs.

Temperature

VIN = 12V; ILOAD = 2.5A VIN = 12V; VOUT = 5V; ILOAD = 5A

Figure 51: Load Regulation vs.

Temperature Figure 52: Line Regulation vs.

Temperature

VIN = 12V; VOUT = 5V; ILOAD = 2.5A - 5A VIN = 9V - 12V; VOUT = 5V; ILOAD = 5A

Figure 53: Frequency vs.

Temperature Figure 54: Average Output Current

Limit vs. Temperature

VIN = 12V; ILOAD = 5A VIN = 12V

Output Voltage vs. Temperature

5.00

5.05

5.10

5.15

-40-200 20406080

Temperature (°C)

Output Voltage (V)

Efficiency vs. Temperature

90%

93%

95%

98%

100%

-40-200 20406080

Temperature (°C)

Efficiency

Load Regulation vs. Temperature

-0.20%

-0.10%

0.00%

0.10%

0.20%

-40-200 20406080

Temperature (°C)

Load Regulation

Line Regulation vs. Temperature

-0.20%

-0.10%

0.00%

0.10%

0.20%

-40-200 20406080

Temperature (°C)

Line Regulation

Fr equency vs. Temperatur e

450

475

500

525

550

-40-200 20406080

Temperature (°C)

Frequency (kHz

)

Average Output Current Limit vs. Temperature

-40-200 20406080

Temperature (°C)

Current (A)

88PH8101

Datasheet

Page 44 Document Classification: Proprietary February 4, 2009, 2.00

THIS PAGE INTENTIONALLY LEFT BLANK

Applications Information

PC Board Layout Considerations and Guid el ines

February 4, 2009, 2.00 Document Classification: Proprietary Page 45

6Applications Information

6.1 PC Board Layout Considerations and Guidelines

The PC board layout is very critical in any switching converter. An improper layout can contribute to

system instability, excessive Electro-Magnetic Interference (EMI), and high switching loss. Follow

these basic guidelines for good PC layout:

1. Copy the layout on page 47 as much as possible and use the recommend BOM on page 51.

Contact the factory if substitutions are made.

2. Review the recommended solder pad layout and notes on page 53.

3. Do not replace the Ceramic input or output capacitors with Tantalum capacitors!

4. Any type of capacitor can be placed in parallel with the input capacitor as long as the Ceramic

input capacitor is placed next to the IC. If Tantalum input capacitor is used, it must be rated for

switching regulator applications and t he operating voltage be derated by 50%.

5. Any type of capacitor can be placed in parallel with the output capacitor.

6. Low-ESR capacitors like the POSCAP from Sanyo can replace the Ceramic output capacitors

as long as the capacitor value is the same or greater. Note that the Ceramic capacitors provide

the lowest noise and smallest foot print solution.

7. Use planes for the ground, input and outputs power to maintain good voltage filtering and to

keep power losses low.

8. If there is not enough space for a power plane for the input supply, then th e input supply trace

must be at least 3/8 inch wide.

9. If there is not enough space for a power plane for the output supplie s, th en place the output as

close to the load as possible with a trace of at least 3/8 inch wide.

10. Do not lay out the inductor first. The input capacitors, Q1 and Q2 placement are the most

critical for prop er ope ration . These components must be placed as close as possible to each

other with as short and wide trace as possible. The AC current circu lating through these

components and loop 1 (LP1) are square wave with rise and fall times of 8ns and slew rates as

high as 300A/µs (see Figure 11). At these fast slew rates, stray PCB inductance can generate a

voltage spike as high as 3V per inch of PCB trace, VIND = L * di/dt. Also, the VIN and PGND

traces must be placed on the top layer . This will isolate the fast AC currents from interfering with

the analog ground plane.

11. Place the bootstrap capacitor, C2, as close as possible to the VBS and VSW pins.

12. The 88PH8101 has two internal grounds, analog (GND) and power (PGND). The analog ground

ties to all the noise sensitive signals (PSET, VSET, and VCC) while the power ground ties to the

higher current power paths. Noise on an analo g ground can cause problems with the IC’s

internal control and bias signals. For this reason, separate analog and power ground traces are

recommended. The signal ground is connected to the power ground at one point, which is th e

(-) terminal of the output capacitor.

13. Connect the CSH and VSW pins as close to Q1 drain and source as possib le. The se pins are

the sense terminals of the current limit comparator circuitry.

Warning

To avoid noise and abnormal operating behavior, follow these layout recommendations.

88PH8101

Datasheet

Page 46 Document Classification: Proprietary February 4, 2009, 2.00

14. The VIN pin is sensitive to noise; therefore, connect the VIN pin to the (+) terminal of the input

capacitor and distance the PVIN from the CSH connection as far as possible.

15. Connect the (-) terminal of the output capacitor as close to the (-) terminal of the input capacitor .

A back-to-back placing of bypass capacitors, as shown in Figure 55, is recommended for best

results.

16. Keep the switching node (VSW) away from the SFB pin and all sensitive signal nodes,

minimizing capacitive coupling effects. If the SFB trace must cross the VSW node, cross it at a

right angle.

17. Try not to route analog or digital lines in close proximity to the power supply especially the VSW

node. If this can’t be avoi ded, shield these lines with a power pla ne placed between the VSW

node and the signal lines.

Figure 55: PCB Board Schematic

LP1

LP2

I Cin

LP1

I Cout

LP2

470k

43k

IRF7832

0.22uF

47uF/6.3V

0.1uF

OUT

88PH8101

CSH 15

VIN 16

PSET

PWM/SDI

VSET

ILIM

SFB

TG 13

8PGND 9

BG 10

VCC 11

GND

VBS 12

VSW 14

10uF/25V

100K

10uF/25V

4.7uF

5V/5A

4.2uH

IRF7821

12V

0 Ohm

NOB

C10

47uF/6.3V C11

47uF/6.3V C12

47uF/6.3V

Applications Information

PC Board Layout Considerations and Guid el ines

February 4, 2009, 2.00 Document Classification: Proprietary Page 47

6.1.1 PC Board Layout Example

Actual board size = 1450 mil x 1330 mil

Total copper layers = 4

All the components are on the top layer

Figure 56: Top Silk-Screen, Top Traces, Vias, and Copper (Not to Scale)

88PH8101

Datasheet

Page 48 Document Classification: Proprietary February 4, 2009, 2.00

Figure 57: GND_Layer2 Vias, and Copper (Not to Scale)

Applications Information

PC Board Layout Considerations and Guid el ines

February 4, 2009, 2.00 Document Classification: Proprietary Page 49

Figure 58: GND_Layer3 Vias, and Copper (Not to Scale)

88PH8101

Datasheet

Page 50 Document Classification: Proprietary February 4, 2009, 2.00

Figure 59: Bottom Silk Screen, Bottom Traces, Vias, and Copper (Not to Scale)

Applications Information

PC Board Layout Considerations and Guid el ines

February 4, 2009, 2.00 Document Classification: Proprietary Page 51

6.1.2 Bill of Materials

Table 12: B OM

Item Qty Ref Manufacturer Manufacturer

Part No. Description

1 1 U1 Marvell

Semiconductor 88PH8101 High Voltage Switching Regulator Controller

2 1 C1 Murata GRM21BR71C475K CAP CER 4.7μF 16V 10% X7R 0805

3 1 C2 Murata GRM188R61A224K

A01D CAP CER 0.22μF 10V 10% X5R 0603

4 1 C3 Murata GRM32DR61E106K

A12L CAP CER 10μF 25V 10% X5R 1210

5 1 C4 Murata GRM32DR61E106K

A12L CAP CER 10μF 25V 10% X5R 1210

6 0 C5 -- NOB NOT ON BOARD

7 1 C6 TDK Corporation C1608X7R1E104K CAP CER 0.1μF 25V X7R 10% 0603

8 1 C9 TDK Corporation C3216X5R0J476M CAP CER 47μF 6.3V X5R 20% 1206

9 1 C10 TDK Corporation C3216X5R0J476M CAP CER 47μF 6.3V X5R 20% 1206

10 1 C11 TDK Corporation C3216X5R0J476M CAP CER 47μF 6.3V X5R 20% 1206

11 1 C12 TDK Corporation C3216X5R0J476M CAP CER 47μF 6.3V X5R 20% 1206

12 1 L1 Sumida CDEP145NP-4R2M

C-170 CDEP145 Series, 4.2μH, 12.3A @

20°C, 7.4 mΩ, H = 6 mm, L = 14.9 mm, W = 14.9

13 1 Q1 IRF IRF7821TRPBF N-Channel MOSFETs SO-8 30V 13.6A @ 25°C

14 1 Q2 IRF IRF7832PBFCT N-Channel MOSFETs SO-8 30V 20A

15 1 R1 Yageo

Corporation RC0603JR-0743KL RES 43KΩ 1/10W 5% 0603 SMD

16 1 R2 Panasonic - ECG ERJ-3GEYJ104V RES 10 0KΩ 1/10 W 5% 0603 SMD

17 1 R3 Yageo America RC0603JR-070RL RES 0.0Ω 1/10W 5% 0603 SMD

18 1 R4 Yageo

Corporation RC0603JR-07470KL RES 470KΩ 1/10W 5% 0603 SMD

88PH8101

Datasheet

Page 52 Document Classification: Proprietary February 4, 2009, 2.00

THIS PAGE INTENTIONALLY LEFT BLANK

Mechanical Drawings

Mechanical Drawing

February 4, 2009, 2.00 Document Classification: Proprietary Page 53

7Mechanical Drawings

7.1 Mechanical Drawing

Figure 60: 16-Pin TSSOP Mechanical Drawing

88PH8101

Datasheet

Page 54 Document Classification: Proprietary February 4, 2009, 2.00

7.2 Mechanical Dimensions

Table 13: 16-Pin TSSOP Dimensions

SYMBOLS DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES

MIN NOM MAX MIN NOM MAX

A 1.05 1.10 1.20 0.041 0.043 0.047

A1 0.05 0.10 0.15 0.002 0.004 0.006

A2 1.00 1.05 0.039 0.041

b 0.20 0.25 0.28 0.008 0.010 0.011

C 0.127 0.005

D 4.90 5.00 5.10 0.193 0.200 0.200

E 6.20 6.40 6.60 0.244 0.252 0.260

E1 4.30 4.40 4.50 0.170 0.173 0.177

e 0.65 0.026

L 0.50 0.60 0.70 0.020 0.024 0.028

y 0.076 0.003

α0°4°8°0°4°8°

Notes:

1. CONTROLLING DIMENSION: mm

2. DIMENSION “D” DOES NOT INCLUDE MOLD FLASH, TIE BAR BURRS AND GATE BURRS.

MODE FLASH, TIE BAR BURRS AND GATE BURRS SHALL NOT EXCEED 0.006” [0.15mm] PER

END DIMENSION “E1” DOES NOT INCLUDE INTERLEAD FLASH INTERLEAD FLASH SHALL

NOT EXCEED 0.010” [0.25mm] PER SIDE.

3. REFERENCE DOCUMENT: JEDEC SPEC MO-153

Mechanical Drawings

Typical Pad Layout Dimensions

February 4, 2009, 2.00 Document Classification: Proprietary Page 55

7.3 Typical Pad Layout Dimensions

7.3.1 Recommended Solder Pad Layout

Figure 61: TSSOP-16 Land Pattern (mm)

6.60

1.05 0.45

4.50

0.65

5.00

Notes:

1. TOP VIEW

2. DRAWING NOT TO SCALE

3. CONTROLLING DIMENSION: mm

4. OVERSIZE SOLDER MASK BY 4 MILS OVER PAD SIZE (2 MIL ANNULAR RING)

5. TOLERANCE ±0.05mm

88PH8101

Datasheet

Page 56 Document Classification: Proprietary February 4, 2009, 2.00

THIS PAGE INTENTIONALLY LEFT BLANK

Part Order Numbering / Package Marking

Part Order Numbering Scheme

February 4, 2009, 2.00 Document Classification: Proprietary Page 57

8Part Order Numbering / Package Marking

8.1 Part Order Numbering Scheme

Figure 62 shows the part order numbering scheme. Refer to a Marvell® Field Application Engineer

(FAE) or sales representative for further information when ordering parts.

Figure 62: Sample Part Number

8.2 Part Ordering Options

The standard ordering part numbers for the respective solutions are as follows:

Part Number

Custom Code Custom Code

Custom Code

Temperature Code

–1xx UBB C000 T123

88PH8101 –

Package Code Environmental

(optional )

1 – RoHS 6/6 Package

2 – Green Package

Custom Code

Table 14: Part Ordering Options

Package Type Part Order (booking) Number

16-pin TSSOP 88PH8101xx-UBB1C000

16-pin TSSOP 88PH8101xx-UBB1C000-T (Tape and Reel)

88PH8101

Datasheet

Page 58 Document Classification: Proprietary February 4, 2009, 2.00

8.3 Package Marking

Figure 63 shows a sample package marking and pin 1 location.

Figure 63: Package Marking and Pin 1 Location

MRVL

H101

YWWG

Marvell company abbreviation

Abbreviated part number

XXXX = 4 character abbreviated part

Date code and assembly house code

Y = last digit of year

WW = work week

G = assembly house code

Pin 1 location

Note: The above example is not drawn to scal e. Location of markings are approximate.

February 4, 2009, 2.00 Document Classification: Proprietary Page 59

ARevision History

Table 15: Revisio n History

Document Type Document Revision

Release Rev. –

Updated to new template, Removed all “88PH8201” instances, Removed “Confidential”, Updated Typ. Dwg. (Fig. 1),

Updated Electrical Chars. Output Voltage Specs., Updated Logic Programmability Voltage Output Specs. (Table 3),

Replaced PC Board Schematic, Replaced and added silk screens (Fig. 30 - Fig. 34), Updated Bill of Materials.

Marvell. Moving Forward Faster

Marvell Semiconductor, Inc.

5488 Marvell Lane

Santa Clara, CA 95054, USA

Tel: 1.408.222.2500

Fax: 1.408.752.9028

www.marvell.com

Back Cover