SL74HC75
System Logic
Semiconductor
SLS
Dual 2-Bit Transparent Latch
High-Performance Silicon-Gate CMOS
The SL74HC75 is identical in pinout to the LS/ALS75. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two independent 2-bit transparent latches
and can be used as temporary storage for binary information between
processing units and input/output or indicator units. Each latch stores
the input data while Latch Enable is at a logic low. The outputs follow
the data inputs when Latch Enable is at a logic high.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC75N Plastic
SL74HC75D SOIC
TA = -55° to 125° C for all packages
FUNCTION TABLE
Inputs Outputs
D Latch
Enable Q Q
L H L H
H H H L
X L Q0 Q0
X = Don’t Care
Q0 = latched data
LOGIC DIAGRAM
PIN 5=VCC
PIN 12 = GND
PIN ASSIGNMENT
SL74HC75
System Logic
Semiconductor
SLS
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC).
Unused outputs must be left open.
SL74HC75
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
≤85
°C ≤125
°C Unit
VIH Minimum High-Level
Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT≤ 20 µA 2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL Maximum Low -Level
Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT ≤ 20 µA 2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH Minimum High-Level
Output Voltage VIN=VIH or VIL
IOUT ≤ 20 µA 2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL Maximum Low-Level
Output Voltage VIN= VIL or VIH
IOUT ≤ 20 µA 2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN= VIL or VIH
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN Maximum Input
Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA 6.0 4.0 40 80 µA
SL74HC75
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC Guaranteed Limit
Symbol Parameter V 25 °C to
-55°C ≤85°C ≤125°C Unit
tPLH, tPHL Maximum Propagation Delay, D to Q (Figures 1
and 5) 2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tPLH, tPHL Maximum Propagation Delay , D to Q
(Figures 1 and 5) 2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
tPLH, tPHL Maximum Propagation Delay ,Latch Enable to Q
(Figures 2 and 5) 2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
tPLH, tPHL Maximum Propagation Delay ,Latch Enable to Q
(Figures 2 and 5) 2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 3 and 5) 2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN Maximum Input Capacitance - 10 10 10 pF
Power Dissipation Capacitance (Per Latch) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
35 pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC Guaranteed Limit
Symbol Parameter V 25 °C to
-55°C ≤85°C ≤125°C Unit
tSU Minimum Setup Time,
Input D to Latch Enable
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
th Minimum Hold Time,Latch
Enable to D (Figure 4) 2.0
4.5
6.0
25
5
5
30
6
6
40
8
7
ns
tw Minimum Pulse Width, Latch
Enable Input
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, tf Maximum Input Rise and Fall
Times (Figure 1) 2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
SL74HC75
System Logic
Semiconductor
SLS
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Switching Waveforms
Figure 5. Test Circuit
EXPANDED LOGIC DIAGRAM
