DATA SHEET MOS INTEGRATED CIRCUIT PD78F9306, 78F9316 8-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The PD78F9306 and 78F9316 belong to the PD789306, 789316 Subseries (for LCD drivers) in the 78K/0S Series. The PD78F9306 has flash memory in place of the internal ROM of the PD789304 and 789306, and the PD78F9316 has flash memory in place of the internal ROM of the PD789314 and 789316. Because flash memory allows the program to be written and erased electrically with the device mounted on the board, this product is ideal for the evaluation stages of system development, small-scale production, and rapid development of new products. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. PD789306, 789316 Subseries User's Manual: U14800E 78K/0S Series User's Manual Instructions: U11047E FEATURES * Pin compatible with mask ROM version (except VPP pin) * Flash memory: 16 KB * Main system clock Ceramic/crystal oscillation: PD78F9306 RC oscillation: * I/O ports: 23 * Serial interface: 2 channels PD78F9316 Switchable between 3-wire serial I/O mode and UART mode: 1 channel 3-wire serial I/O mode: * 1 channel LCD controller/driver Segment signals: 24, common signals: 4 * Timer: 5 channels * Power supply voltage: VDD = 1.8 to 5.5 V APPLICATIONS Remote control devices, healthcare equipment, etc. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14564EJ1V0DS00 (1st edition) Date Published March 2001 N CP(K) Printed in Japan The mark shows major revised points. (c) 2001 1999 1996, PD78F9306, 78F9316 ORDERING INFORMATION Part Number Package PD78F9306GC-AB8 64-pin plastic QFP (14 x 14) PD78F9306GK-9ET 64-pin plastic TQFP (12 x 12) PD78F9316GC-AB8 64-pin plastic QFP (14 x 14) PD78F9316GK-9ET 64-pin plastic TQFP (12 x 12) 2 Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 78K/0S SERIES LINEUP The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y Subseries products support SMB. Small-scale package, general-purpose applications 44-pin 42-/44-pin 30-pin 28-pin PD789074 with added subsystem clock PD789014 with enhanced timer and increased ROM, RAM capacity PD789026 with enhanced timer PD789046 PD789026 PD789074 PD789014 On-chip UART and capable of low voltage (1.8 V) operation Small-scale package, general-purpose applications and A/D converter 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A PD789177Y PD789167Y PD789167 with enhanced A/D converter PD789104A with enhanced timer PD789146 with enhanced A/D converter PD789104A with added EEPROMTM PD789124A with enhanced A/D converter RC oscillation version of the PD789104A PD789104A with enhanced A/D converter PD789026 with added A/D converter and multiplier Inverter control 44-pin PD789842 On-chip inverter controller and UART VFD drive 78K/0S Series 52-pin PD789871 Total display outputs: 25 LCD drive 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin PD789488 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 A/D converter and on-chip voltage booster type LCD (28 x 4) PD789407A with enhanced A/D converter A/D converter and resistance division type LCD (28 x 4) PD789446 with enhanced A/D converter A/D converter and on-chip voltage booster type LCD (15 x 4) PD789426 with enhanced A/D converter A/D converter and on-chip voltage booster type LCD (5 x 4) RC oscillation version of the PD789306 On-chip voltage booster type LCD (24 x 4) Dot LCD drive 144-pin 88-pin PD789835 PD789830 Segment/common outputs: 96 Segments: 40, commons: 16 ASSP 80-pin 52-pin PD789477 PD789467 52-pin PD789327 PD789803 PD789800 PD789840 PD789861 PD789860 64-pin 44-pin 44-pin 20-pin 20-pin PD789488 with added remote control receiver and resistance division type LCD For remote controller, with A/D converter and on-chip voltage booster type LCD For remote controller, with SIO and resistance division type LCD For PC keyboard, on-chip USB HUB function For PC keyboard, on-chip USB function For keypad, on-chip POC RC oscillation version of the PD789860 For keyless entry, on-chip POC and key return circuit Data Sheet U14564EJ1V0DS 3 PD78F9306, 78F9316 The major functional differences among the subseries are listed below. Function VDD ROM Capacity 8-Bit 16-Bit Watch WDT 8-Bit 10-Bit A/D A/D Serial Interface Subseries Name Small-scale package, generalpurpose applications PD789046 16 K PD789026 4 K to 16 K PD789074 2 K to 8 K PD789014 2 K to 4 K 2 ch - Small-scale package, generalpurpose applications and A/D converter PD789177 16 K to 24 K 3 ch 1 ch 1 ch 1 ch 1 ch 1 ch - - - 1 ch (UART: 1 ch) I/O MIN. Value Remarks 34 1.8 V - 24 22 - - 8 ch 8 ch - - 4 ch 4 ch - - 4 ch 4 ch - RC-oscillation version PD789114A - 4 ch - PD789104A 4 ch - 1 ch PD789167 PD789156 8 K to 16 K - 1 ch PD789146 PD789134A 2 K to 8 K PD789124A 1 ch (UART: 1 ch) 31 20 On-chip EEPROM Inverter control PD789842 8 K to 16 K 3 ch Note 1 ch 1 ch 8 ch - 1 ch (UART: 1 ch) 30 4.0 V - VFD drive PD789871 4 K to 8 K 3 ch - 1 ch 1 ch - - 1 ch 33 2.7 V - LCD drive PD789488 32 K 3 ch 1 ch 1 ch 1 ch - 8 ch 2 ch (UART: 1 ch) 45 1.8 V - PD789417A 12 K to 24 K 7 ch 1 ch (UART: 1 ch) 43 PD789407A 7 ch - - 6 ch 6 ch - PD789436 - 6 ch PD789426 6 ch - PD789456 PD789446 PD789316 12 K to 16 K 2 ch 8 K to 16 K - 30 40 2 ch (UART: 1 ch) 23 PD789306 Dot LCD drive ASSP - PD789835 24 K to 60 K 6 ch - PD789830 24 K 1 ch 1 ch PD789477 24 K 3 ch 1 ch PD789467 4 K to 24 K 2 ch - 1 ch 1 ch 3 ch 1 ch 1 ch 8 ch 8 K to 16 K PD789800 8K PD789840 - 4 ch 4K - PD789860 28 1.8 V - 30 2.7 V - 2 ch (UART: 1 ch) - 45 1.8 V On-chip LCD 18 1 ch 21 2 ch (USB: 1 ch) 41 3.6 V 1 ch 29 2.8 V - - 31 4.0 V 14 1.8 V RC-oscillation version, on-chip EEPROM On-chip EEPROM Note 10-bit timer: 1 channel 4 1 ch (UART: 1 ch) 1 ch - PD789803 - - PD789327 PD789861 RC-oscillation version Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 OVERVIEW OF FUNCTIONS PD78F9306 Item Internal memory Flash memory 16 KB High-speed RAM 512 bytes LCD display RAM 24 bytes Main system clock (oscillation frequency) Ceramic/crystal oscillation (1.0 to 5.0 MHz) Subsystem clock (oscillation frequency) Crystal oscillation (32.768 kHz) Minimum instruction execution time 0.4 s/1.6 s (@ 5.0 MHz operation with main system clock) PD78F9316 RC oscillation (2.0 to 4.0 MHz) 0.5 s/2.0 s (@ 4.0 MHz operation with main system clock) 122 s (@ 32.768 kHz operation with subsystem clock) General-purpose registers 8 bits x 8 registers Instruction set * 16-bit operation * Bit manipulation (set, reset, test) I/O ports Total: * CMOS I/O: * N-ch open drain: 23 19 4 Timers * * * * 1 channel 2 channels 1 channel 1 channel Serial interface * Switchable between 3-wire serial I/O mode and UART mode: 1 channel * 3-wire serial I/O mode: 1 channel LCD controller/driver * Segment signal outputs: 24 (Max.) * Common signal outputs: 4 (Max.) Vectored interrupt Maskable sources Non-maskable Internal: 9, External: 5 Power supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = -40 to +85C Package * 64-pin plastic QFP (14 x 14) * 64-pin plastic TQFP (12 x 12) 16-bit timer: 8-bit timer/event counter: Watch timer: Watchdog timer: Internal: 1 Data Sheet U14564EJ1V0DS 5 PD78F9306, 78F9316 CONTENTS 1. PIN CONFIGURATION (Top View)....................................................................................................................... 7 2. BLOCK DIAGRAM ................................................................................................................................................ 9 3. PIN FUNCTIONS ................................................................................................................................................. 10 3.1 Port Pins ...................................................................................................................................................... 10 3.2 Non-Port Pins .............................................................................................................................................. 11 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................................... 12 4. MEMORY SPACE................................................................................................................................................ 14 5. FLASH MEMORY PROGRAMMING ................................................................................................................... 15 5.1 Selecting Communication Mode................................................................................................................ 15 5.2 Function of Flash Memory Programming ................................................................................................. 16 5.3 Connecting Flashpro III .............................................................................................................................. 16 5.4 Example of Settings for Flashpro III (PG-FP3).......................................................................................... 18 6. OVERVIEW OF INSTRUCTION SET .................................................................................................................. 19 6.1 Conventions ................................................................................................................................................ 19 6.2 List of Operations ....................................................................................................................................... 21 7. ELECTRICAL SPECIFICATIONS ....................................................................................................................... 26 8. CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES)............................ 42 9. PACKAGE DRAWINGS ...................................................................................................................................... 44 10. RECOMMENDED SOLDERING CONDITIONS................................................................................................... 46 APPENDIX A. DIFFERENCES BETWEEN PD78F9306, 78F9316 AND MASK ROM VERSIONS ................ 47 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................................. 48 APPENDIX C. RELATED DOCUMENTS................................................................................................................. 50 6 Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 1. PIN CONFIGURATION (Top View) 64-pin plastic QFP (14 x 14) 64-pin plastic TQFP (12 x 12) PD78F9306GK-9ET PD78F9316GC-AB8 PD78F9316GK-9ET P20/SCK10 P21/SO10 P22/SI10 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO20 P30/INTP0/CPT20 P31/INTP1/TO30/TMI40 P32/INTP2/TO40 P33/INTP3 P10 P11 P12 P13 S23 PD78F9306GC-AB8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 CAPH CAPL VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 S5 S6 P50 P51 P52 P53 VPP XT1 XT2 VDD VSS X1 (CL1) X2 (CL2) RESET P00/KR0 P01/KR1 P02/KR2 P03/KR3 Caution Connect the VPP pin directly to the VSS pin in normal operation mode. Remark Pin names enclosed in parentheses apply when using the PD78F9316. Data Sheet U14564EJ1V0DS 7 PD78F9306, 78F9316 ASCK20: Asynchronous serial input S0 to S23: Segment output CAPH, CAPL: LCD power supply capacitance control SCK10, SCK20: Serial clock CL1, CL2: RC oscillator SI10, SI20: Serial input COM0 to COM3: Common output SO10, SO20: Serial output CPT20: Capture trigger input TMI40: Timer input INTP0 to INTP3: External interrupt input TO20, TO30, TO40: Timer output KR0 to KR3: Key return TxD20: Transmit data Port 0 VDD: P10 to P13: Port 1 VLC0 P20 to P26: Port 2 VPP: Programming power supply P30 to P33: Port 3 VSS: Ground P50 to P53: Port 5 X1, X2: Crystal/ceramic oscillator RESET: Reset XT1, XT2: Crystal oscillator RxD20: Receive data P00 to P03: 8 Power supply to Data Sheet U14564EJ1V0DS VLC2: LCD power supply PD78F9306, 78F9316 2. BLOCK DIAGRAM TO30/TMI40/P31 TO40/P32 TMI40/TO30/P31 TO20/P26 CPT20/P30 8-bit timer 30 8-bit timer/event counter 40 Cascaded 16-bit timer/event counter 16-bit timer 20 Watch timer 78K/0S CPU core Flash memory Port 0 P00 to P03 Port 1 P10 to P13 Port 2 P20 to P26 Port 3 P30 to P33 Port 5 P50 to P53 Watchdog timer SCK10/P20 SO10/P21 SI10/P22 Serial interface 10 SCK20/ASCK20/P23 SO20/TxD20/P24 SI20/RxD20/P25 Serial interface 20 RAM RAM space for LCD data System control RESET X1 (CL1) X2 (CL2) XT1 XT2 INTP0/P30 INTP1/P31 Interrupt control INTP2/P32 S0 to S23 COM0 to COM3 VLC0 to VLC2 CAPH CAPL INTP3/P33 KR0/P00 to KR3/P03 LCD controller driver VDD Remark VSS VPP Pin names enclosed in parentheses apply when using the PD78F9316. Data Sheet U14564EJ1V0DS 9 PD78F9306, 78F9316 3. PIN FUNCTIONS 3.1 Port Pins Pin Name I/O Function After Reset P00 to P03 I/O Port 0. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified in port units by pull-up resistor option register 0 (PU0) or key return mode register 00 (KRM00). Input P10 to P13 I/O Port 1. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified in port units by pull-up resistor option register 0 (PU0). Input P20 I/O Port 2. 7-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified in bit units by pull-up resistor option register B2 (PUB2). Input P21 P22 P23 P24 Alternate Function KR0 to KR3 - SCK10 SO10 SI10 SCK20/ASCK20 SO20/TxD20 P25 SI20/RxD20 P26 TO20 P30 I/O P31 P32 P33 P50 to P53 10 I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified in bit units by pull-up resistor option register B3 (PUB3). Input Port 5. 4-bit I/O port. Input/output can be specified in 1-bit units. Input Data Sheet U14564EJ1V0DS INTP0/CPT20 INTP1/TO30/TMI40 INTP2/TO40 INTP3 - PD78F9306, 78F9316 3.2 Non-Port Pins Pin Name I/O Input INTP0 INTP1 Function External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified After Reset Input Alternate Function P30/CPT20 P31/TO30/TMI40 INTP2 P32/TO40 INTP3 P33 KR0 to KR3 Input Key return signal detection Input P00 to P03 SCK10 Input/ output Serial clock input/output for serial interface 10 (SIO10) Input P20 Input Serial data input for serial interface 10 (SIO10) SCK20 SI10 SI20 Serial clock input/output for serial interface 20 (SIO20) P23/ASCK20 Input P22 Serial data input for serial interface 20 (SIO20) SO10 Output SO20 Serial data output for serial interface 10 (SIO10) P25/RxD20 P21 Input Serial data output for serial interface 20 (SIO20) P24/TxD20 ASCK20 Input Serial clock input for asynchronous serial interface Input P23/SCK20 RxD20 Input Serial data input for asynchronous serial interface Input P25/SI20 TxD20 Output Serial data output for asynchronous serial interface Input P24/SO20 TO20 Output 16-bit timer 20 (TM20) output Input P26 CPT20 Input Capture edge input Input P30/INTP0 TO30 Output 8-bit timer 30 (TM30) output Input P31/INTP1/TMI40 TO40 Output 8-bit timer 40 (TM40) output Input P32/INTP2 TMI40 Input External count clock input to 8-bit timer 40 (TM40) Input P31/INTP1/TO30 S0 to S23 Output Segment signal output for LCD controller/driver Low-level output - COM0 to COM3 Output Common signal output for LCD controller/driver Low-level output - VLC0 to VLC2 - LCD drive voltage - - CAPH - Connection pin for LCD driver's capacitor - - CAPL - - - - - - - - - - - - - - - Note 1 X1 Input Note 1 X2 Connecting crystal resonator for main system clock oscillation - Note 2 CL1 Input Note 2 CL2 - XT1 Input XT2 Connections to resistor (R) and capacitor (C) for main system clock oscillation Connecting crystal resonator for subsystem clock oscillation - RESET Input System reset input Input - VDD - Positive power supply - - VSS - Ground potential - - VPP - Flash memory programming mode setting. High-voltage application for program write/verify. In normal operation mode, connect directly to VSS. - - Notes 1. PD78F9306 only 2. PD78F9316 only Data Sheet U14564EJ1V0DS 11 PD78F9306, 78F9316 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the I/O circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins Pin Name I/O Circuit Type I/O P00/KR0 to P03/KR3 8-A I/O P10 to P13 5-A P20/SCK10 8-A Recommended Connection of Unused Pins Input mode: Independently connect to VDD or VSS via a resistor. Output mode: Leave open. P21/SO10 P22/SI10 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO20 Input mode: Independently connect to VSS via a resistor. Output mode: Leave open. P30/INTP0/CPT20 P31/INTP1/TO30/ TMI40 P32/INTP2/TO40 P33/INTP3 P50 to P53 13-V S0 to S23 17 COM0 to COM3 18 VLC0 to VLC2 - CAPH, CAPL - XT1 - XT2 Input mode: Independently connect to VDD via a resistor. Output mode: Leave open. Output - Input - Connect to VSS. Leave open. RESET 2 Input VPP - - 12 Leave open. - Connect directly to VSS. Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 Figure 3-1. Pin I/O Circuits Type 2 Type 13-V IN/OUT Output data Output disable IN N-ch VSS Schmitt-triggered input with hysteresis characteristics Type 5-A Input enable Middle-voltage input buffer Type 17 VDD VLC0 P-ch Pull-up enable P-ch VLC1 VDD P-ch N-ch P-ch Data P-ch IN/OUT Output disable N-ch SEG data OUT N-ch P-ch VLC2 VSS N-ch N-ch Input enable Type 8-A Type 18 VDD VLC0 Pull-up enable P-ch VLC1 VDD Data P-ch N-ch P-ch N-ch P-ch IN/OUT Output disable P-ch OUT COM data N-ch P-ch P-ch VLC2 VSS N-ch N-ch N-ch Data Sheet U14564EJ1V0DS 13 PD78F9306, 78F9316 4. MEMORY SPACE Figure 4-1 shows the memory map. Figure 4-1. Memory Map FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH Reserved FA18H FA17H Data memory space LCD display RAM 24 x 4 bits FA00H F9FFH 4000H 3FFFH 3FFFH Reserved Program area Program memory space Internal flash memory 16384 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 0022H 0021H 0000H 0000H 14 Data Sheet U14564EJ1V0DS Vector table area PD78F9306, 78F9316 5. FLASH MEMORY PROGRAMMING The program memory that is incorporated in the PD78F9306 and 78F9316 is flash memory. With flash memory, it is possible to write programs on-board. Writing is performed by connecting a dedicated flash programmer (Flashpro III (Part No. FL-PR3, PG-FP3)) to the host machine and the target system. Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd. 5.1 Selecting Communication Mode Writing to flash memory is performed using the Flashpro III in a serial communication mode. Select one of the communication modes in Table 5-1. The selection of the communication mode is made by using the format shown in Figure 5-1. Each communication mode is selected using the number of VPP pulses shown in Table 5-1. Table 5-1. List of Communication Mode Communication Mode 3-wire serial I/O UART Pins VPP Pulses SCK10/P20 SO10/P21 SI10/P22 0 P00/KR0 (serial clock input) P01/KR1 (serial data output) P02/KR2 (serial data input) 1 TxD20/SO20/P24 RxD20/SI20/P25 8 Caution Be sure to select a communication mode using the number of VPP pulses shown in Table 5-1. Figure 5-1. Format of Communication Mode Selection 10 V VPP VDD 1 2 n VSS RESET VDD VSS Data Sheet U14564EJ1V0DS 15 PD78F9306, 78F9316 5.2 Function of Flash Memory Programming Operations such as writing to flash memory are performed by various command/data transmission and reception operations according to the selected communication mode. Table 5-2 shows the major functions of flash memory programming. Table 5-2. Major Function of Flash Memory Programming Function Description Batch erase Deletes the entire memory contents. Batch blank check Checks the deletion status of the entire memory. Data write Performs a write operation to the flash memory based on the write start address and the number of data to be written (number of bytes). Batch verify Compares the entire memory contents with the input data. 5.3 Connecting Flashpro III The connection of the Flashpro III and the PD78F9306 and 78F9316 differs according to the communication mode (3-wire serial I/O or UART). The connections for each communication mode are shown in Figures 5-2 and 5-3, respectively. Figure 5-2. Connection Example of Flashpro III When Using 3-Wire Serial I/O Mode (1/2) PD78F9306, 78F9316 Flashpro III VPPnNote 1 VPP VDD VDD RESET RESET CLK X1 (P03/KR03)Note 2 SCK SCK10 SO SI10 SI SO10 GND VSS Notes 1. n = 1, 2 2. Pin names enclosed in parentheses apply when using the PD78F9316. 16 Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 Figure 5-2. Connection Example of Flashpro III When Using 3-Wire Serial I/O Mode (2/2) PD78F9306, 78F9316 Flashpro III VPPnNote 1 VPP VDD VDD RESET RESET CLK X1 (P03/KR03)Note 2 SCK P00/KR0 (Serial clock) SO P02/KR2 (Serial input) SI P01/KR1 (Serial output) VSS GND Notes 1. n = 1, 2 2. Pin names enclosed in parentheses apply when using the PD78F9316. Figure 5-3. Connection Example of Flashpro III When Using UART Mode PD78F9306, 78F9316 Flashpro III VPPnNote 1 VPP VDD VDD RESET RESET X1 (P03/KR03)Note 2 CLK SO RxD20 SI TxD20 VSS GND Notes 1. n = 1, 2 2. Pin names enclosed in parentheses apply when using the PD78F9316. Data Sheet U14564EJ1V0DS 17 PD78F9306, 78F9316 5.4 Example of Settings for Flashpro III (PG-FP3) When writing to flash memory using Flashpro III (PG-FP3), make the following settings. <1> Load a parameter file. <2> Select the mode of serial communication and serial clock with a type command. <3> Make the settings according to the example of settings for PG-FP3 shown below. Table 5-3. Example of Settings for PG-FP3 Communication Mode 3-wire serial I/O Note 1 VPP Pulse Number Example of Settings for PG-FP3 COMM PORT SIO-ch0 CPU CLK On Target Board 0 In Flashpro On Target Board 4.1943 MHz SIO CLK 1.0 MHz In Flashpro 4.0 MHz SIO CLK 1.0 MHz COMM PORT SIO-ch1 CPU CLK On Target Board 1 In Flashpro UART On Target Board 4.1943 MHz SIO CLK 1.0 MHz In Flashpro 4.0 MHz SIO CLK 1.0 MHz COMM PORT UART-ch0 CPU CLK On Target Board On Target Board 4.1943 MHz UART BPS 9600 bps 8 Note 2 Notes 1. This is the number of VPP pulses that are supplied by the Flashpro III at serial communication initialization. The pins that will be used for communication are determined according to this number. 2. Select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps. Remark COMM PORT: Serial port selection 18 SIO CLK: Serial clock frequency selection CPU CLK: Input CPU clock source selection Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 6. OVERVIEW OF INSTRUCTION SET This section lists the instruction set for the PD78F9306 and 78F9316. 6.1 Conventions 6.1.1 Operand expressions and description methods Operands are described in "Operand" column of each instruction in accordance with the description method of the instruction operand expression (see the assembler specifications for details). When there are two or more description methods, select one of them. Uppercase letters and symbols, #, !, $, and [ ] are key words and are described as they are. The meaning of each symbol is described below. * # : Immediate data specification * $ : Relative address specification * ! : Absolute address specification * [ ] : Indirect address specification For immediate data, enter an appropriate numeric value or a label. When using a label, be sure to enter the #, !, $ and [ ] symbols. For operand register expressions, r and rp, either function names (X, A, C, etc.) or absolute names (names in parenthesis in the table below, R0, R1, R2, etc.) can be used for the description. Table 6-1. Operand Expressions and Description Methods Expression Description Method r rp sfr X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol saddr saddrp FE20H to FF1FH: immediate data or label FE20H to FF1FH: immediate data or label (even addresses only) addr16 addr5 0000H to FFFFH: immediate data or label (even addresses only for 16-bit data transfer instruction) 0040H to 007FH: immediate data or label (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label Data Sheet U14564EJ1V0DS 19 PD78F9306, 78F9316 6.1.2 Description of "Operation" column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag NMIS: Flag indicating non-maskable interrupt servicing in progress ( ): Memory contents indicated by address or register contents in parenthesis XH, XL: Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : Exclusive logical sum (exclusive OR) : Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 6.1.3 Description of "Flag" column (Blank): 20 Unchanged 0: Cleared to 0 1: Set to 1 x: Set/cleared according to the result R: Previously saved value is restored Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 6.2 List of Operations Mnemonic Operand Bytes Clocks Operation Flags Z MOV r, #byte XCH 3 3 6 (saddr) byte sfr, #byte 3 6 sfr byte A, r Note 1 2 4 Ar r, A Note 1 2 4 rA A, saddr 2 4 A (saddr) saddr, A 2 4 (saddr) A A, sfr 2 4 A sfr sfr, A 2 4 sfr A A, !addr16 3 8 A (addr16) !addr16, A 3 8 (addr16) A PSW, #byte 3 6 PSW byte A, PSW 2 4 A PSW PSW, A 2 4 PSW A A, [DE] 1 6 A (DE) [DE], A 1 6 (DE) A A, [HL] 1 6 A (HL) [HL], A 1 6 (HL) A A, [HL + byte] 2 6 A (HL + byte) [HL + byte], A 2 6 (HL + byte) A 1 4 AX 2 6 Ar A, saddr 2 6 A (saddr) A, sfr 2 6 A (sfr) A, [DE] 1 8 A (DE) A, [HL] 1 8 A (HL) A, [HL + byte] 2 8 A (HL + byte) rp, #word 3 6 rp word A, r XCHW Notes 1. Note 2 AX, saddrp 2 6 AX (saddrp) saddrp, AX 2 8 (saddrp) AX AX, rp Note 3 1 4 AX rp rp, AX Note 3 1 4 rp AX AX, rp Note 3 1 8 AX rp x x x x x x Except r = A 2. Except r = A, X 3. rp = BC, DE and HL only Remark r byte saddr, #byte A, X MOVW 6 AC CY One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). Data Sheet U14564EJ1V0DS 21 PD78F9306, 78F9316 Mnemonic Operand Bytes Clocks Operation Flags Z ADD ADDC SUB SUBC AND Remark A, #byte 2 4 A, CY A + byte x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte x x x A, r 2 4 A, CY A + r x x x A, saddr 2 4 A, CY A + (saddr) x x x A, !addr16 3 8 A, CY A + (addr16) x x x A, [HL] 1 6 A, CY A + (HL) x x x A, [HL + byte] 2 6 A, CY A + (HL + byte) x x x A, #byte 2 4 A, CY A + byte + CY x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte + CY x x x A, r 2 4 A, CY A + r + CY x x x A, saddr 2 4 A, CY A + (saddr) + CY x x x A, !addr16 3 8 A, CY A + (addr16) + CY x x x A, [HL] 1 6 A, CY A + (HL) + CY x x x A, [HL + byte] 2 6 A, CY A + (HL + byte) + CY x x x A, #byte 2 4 A, CY A - byte x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte x x x A, r 2 4 A, CY A - r x x x A, saddr 2 4 A, CY A - (saddr) x x x A, !addr16 3 8 A, CY A - (addr16) x x x A, [HL] 1 6 A, CY A - (HL) x x x A, [HL + byte] 2 6 A, CY A - (HL + byte) x x x A, #byte 2 4 A, CY A - byte - CY x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte - CY x x x A, r 2 4 A, CY A - r - CY x x x A, saddr 2 4 A, CY A - (saddr) - CY x x x A, !addr16 3 8 A, CY A - (addr16) - CY x x x A, [HL] 1 6 A, CY A - (HL) - CY x x x A, [HL + byte] 2 6 A, CY A - (HL + byte) - CY x x x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). 22 AC CY Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 Mnemonic Operand Bytes Clocks Operation Flags Z AC CY A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x A, #byte 2 4 A - byte x x x saddr, #byte 3 6 (saddr) - byte x x x A, r 2 4 A-r x x x A, saddr 2 4 A - (saddr) x x x A, !addr16 3 8 A - (addr16) x x x A, [HL] 1 6 A - (HL) x x x A, [HL + byte] 2 6 A - (HL + byte) x x x ADDW AX, #word 3 6 AX, CY AX + word x x x SUBW AX, #word 3 6 AX, CY AX - word x x x CMPW AX, #word 3 6 AX - word x x x INC r 2 4 rr+1 x x saddr 2 4 (saddr) (saddr) + 1 x x r 2 4 rr-1 x x saddr 2 4 (saddr) (saddr) - 1 x x INCW rp 1 4 rp rp + 1 DECW rp 1 4 rp rp - 1 ROR A, 1 1 2 (CY, A7 A0, Am - 1 Am) x 1 time x ROL A, 1 1 2 (CY, A0 A7, Am + 1 Am) x 1 time x RORC A, 1 1 2 (CY A0, A7 CY, Am - 1 Am) x 1 time x ROLC A, 1 1 2 (CY A7, A0 CY, Am + 1 Am) x 1 time x OR XOR CMP DEC Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). Data Sheet U14564EJ1V0DS 23 PD78F9306, 78F9316 Mnemonic Operand Bytes Clocks Operation Flags Z AC CY saddr. bit 3 6 (saddr. bit) 1 sfr. bit 3 6 sfr. bit 1 A. bit 2 4 A. bit 1 PSW. bit 3 6 PSW. bit 1 [HL]. bit 2 10 (HL). bit 1 saddr. bit 3 6 (saddr. bit) 0 sfr. bit 3 6 sfr. bit 0 A. bit 2 4 A. bit 0 PSW. bit 3 6 PSW. bit 0 [HL]. bit 2 10 (HL). bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY x CALL !addr16 3 6 (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 CALLT [addr5] 1 8 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 RET 1 6 PCH (SP + 1), PCL (SP), SP SP + 2 RETI 1 8 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 PSW 1 2 (SP - 1) PSW, SP SP - 1 rp 1 4 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW 1 4 PSW (SP), SP SP + 1 rp 1 6 rpH (SP + 1), rpL (SP), SP SP + 2 SP, AX 2 8 SP AX AX, SP 2 6 AX SP !addr16 3 6 PC addr16 $addr16 2 6 PC PC + 2 + jdisp8 AX 1 6 PCH A, PCL X SET1 CLR1 PUSH POP MOVW BR Remark x x x x x R R R R R R One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). 24 x Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 Mnemonic Operand Bytes Clocks Operation Flags Z BC $addr16 2 6 PC PC + 2 + jdisp8 if CY = 1 BNC $addr16 2 6 PC PC + 2 + jdisp8 if CY = 0 BZ $addr16 2 6 PC PC + 2 + jdisp8 if Z = 1 BNZ $addr16 2 6 PC PC + 2 + jdisp8 if Z = 0 BT saddr. bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr. bit = 1 A. bit, $addr16 3 8 PC PC + 3 + jdisp8 if A. bit = 1 PSW. bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW. bit = 1 saddr. bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr. bit = 0 A. bit, $addr16 3 8 PC PC + 3 + jdisp8 if A. bit = 0 PSW. bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW. bit = 0 B, $addr16 2 6 B B - 1, then PC PC + 2 + jdisp8 if B 0 C, $addr16 2 6 C C - 1, then PC PC + 2 + jdisp8 if C 0 saddr, $addr16 3 8 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 NOP 1 2 No Operation EI 3 6 IE 1 (Enable Interrupt) DI 3 6 IE 0 (Disable Interrupt) HALT 1 2 Set HALT Mode STOP 1 2 Set STOP Mode BF DBNZ Remark AC CY One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). Data Sheet U14564EJ1V0DS 25 PD78F9306, 78F9316 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Power supply voltage Input voltage Symbol Ratings Unit VDD -0.3 to +6.5 V VPP -0.3 to +10.5 V VI1 P00 to P03, P10 to P13, P20 to P26, P30 to P33, X1 (CL1), X2 (CL2), XT1, XT2, RESET VI2 P50 to P53 Output voltage VO Output current, high IOH Output current, low IOL Operating ambient temperature Conditions TA Note -0.3 to VDD + 0.3 N-ch open drain -0.3 to +13 V Note -0.3 to VDD + 0.3 V 1 pin -10 mA Total for all pins -30 mA 1 pin 30 mA Total for all pins 160 mA -40 to +85 C 10 to 40 C -40 to +125 C In normal operation mode During flash memory programming Storage temperature V Tstg Note 6.5 V or less Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Pin names enclosed in parentheses apply when using the PD78F9316. 2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 26 Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 Main System Clock Oscillator Characteristics Ceramic/crystal oscillation (PD78F9306) (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit VPP X2 Ceramic resonator C2 IC Crystal resonator X2 C2 External clock X2 X2 OPEN Notes 1. 2. X1 Parameter Conditions Note 1 Oscillation frequency (fX) Oscillation stabilization Note 2 time C1 X1 X1 X1 1.0 After VDD reaches oscillation voltage range MIN. Note 1 Oscillation frequency Oscillation stabilization Note 2 time C1 MIN. 1.0 VDD = 4.5 to 5.5 V Note 1 TYP. MAX. Unit 5.0 MHz 4 ms 5.0 MHz 10 ms 30 ms X1 input frequency (fX) 1.0 5.0 MHz X1 input high-/low-level width (tXH, tXL) 85 500 ns Note 1 X1 input frequency (fX) VDD = 2.7 to 5.5 V 1.0 5.0 MHz X1 input high-/low-level width (tXH, tXL) VDD = 2.7 to 5.5 V 85 500 ns Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Time required to stabilize oscillation after reset or STOP mode release. Use a resonator whose oscillation stabilizes within the oscillation stabilization wait time. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U14564EJ1V0DS 27 PD78F9306, 78F9316 RC oscillation (PD78F9316) (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit RC resonator CL1 CL2 Parameter Conditions Note 1 Oscillation frequency (fCC) Oscillation stabilization Note 2 time 2.0 VDD = 2.7 to 5.5 V Note 1 External clock CL1 CL1 Notes 1. CL2 MIN. TYP. MAX. Unit 4.0 MHz 32 ms 128 ms CL1 input frequency (fCC) 1.0 4.0 MHz CL1 input high-/low-level width (tXH, tXL) 100 500 ns Note 1 CL2 CL1 input frequency (fCC) VDD = 2.7 to 5.5 V 1.0 4.0 MHz CL1 input high-/low-level width (tXH, tXL) VDD = 2.7 to 5.5 V 100 500 ns OPEN Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. The error of capacitor (C) and resistor (R) is not included. 2. Time required to stabilize oscillation after reset or STOP mode release. Use a resonator whose oscillation stabilizes within the oscillation stabilization wait time. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. 28 Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 RC Oscillation Frequency Characteristics (TA = -40 to +85C) Parameter Symbol Oscillation frequency Conditions MIN. TYP. MAX. Unit fCC1 R = 11.0 k, VDD = 2.7 to 5.5 V 1.5 2.0 2.5 MHz fCC2 C = 22 pF VDD = 1.8 to 3.6 V 0.5 2.0 2.5 MHz fCC3 Target: 2 MHz VDD = 1.8 to 5.5 V 0.5 2.0 2.5 MHz fCC4 R = 6.8 k, VDD = 2.7 to 5.5 V 2.5 3.0 3.5 MHz fCC5 C = 22 pF VDD = 1.8 to 3.6 V 0.75 3.0 3.5 MHz fCC6 Target: 3 MHz VDD = 1.8 to 5.5 V 0.75 3.0 3.5 MHz fCC7 R = 4.7 k, VDD = 2.7 to 5.5 V 3.5 4.0 4.7 MHz fCC8 C = 22 pF VDD = 1.8 to 3.6 V 1.0 4.0 4.7 MHz fCC9 Target: 4 MHz VDD = 1.8 to 5.5 V 1.0 4.0 4.7 MHz Remarks 1. Set RC to one of the above nine values so that the typical value of the oscillation frequency is within 2.0 to 4.0 MHz. 2. The resistor (R) and capacitor (C) error is not included. Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit Crystal resonator VPP XT1 C3 External clock XT1 XT2 R C4 XT2 Parameter Conditions Oscillation frequency Note 1 (fXT) Oscillation stabilization Note 2 time 2. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s VDD = 4.5 to 5.5 V XT1 input frequency Note 1 (fXT) XT1 input high-/low-level width (tXTH, tXTL) Notes 1. MIN. 10 32 35 kHz 14.3 15.6 s Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U14564EJ1V0DS 29 PD78F9306, 78F9316 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (1/4) Parameter Symbol Output current, low IOL Output current, high IOH Input voltage, high VIH1 VIH2 VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high Output voltage, low VOH VOL1 VOL2 Conditions MAX. Unit 1 pin 10 mA All pins 80 mA 1 pin -1 mA All pins -15 mA 0.7VDD VDD V 0.9VDD VDD V 0.7VDD 12 V 0.9VDD 12 V 0.8VDD VDD V 0.9VDD VDD V VDD - 0.5 VDD V VDD - 0.1 VDD V 0 0.3VDD V 0 0.1VDD V 0 0.3VDD V 0 0.1VDD V 0 0.2VDD V 0 0.1VDD V 0 0.4 V 0 0.1 V P10 to P13 P50 to P53 VDD = 2.7 to 5.5 V N-ch open drain VDD = 2.7 to 5.5 V RESET, P00 to P03, P20 to P26, P30 to P33 VDD = 2.7 to 5.5 V X1 (CL1), X2 (CL2), XT1, XT2 VDD = 4.5 to 5.5 V P10 to P13 VDD = 2.7 to 5.5 V P50 to P53 VDD = 2.7 to 5.5 V MIN. TYP. RESET, P00 to P03, P20 to P26, P30 to P33 VDD = 2.7 to 5.5 V X1 (CL1), X2 (CL2), XT1, XT2 VDD = 4.5 to 5.5 V IOH = -1 mA VDD = 4.5 to 5.5 V VDD - 1.0 V IOH = -100 A VDD = 1.8 to 5.5 V VDD - 0.5 V P00 to P03, P10 to P13, P20 to P26, P30 to P33 4.5 VDD 5.5 V, IOL = 10 mA 1.0 V 1.8 VDD < 4.5 V, IOL = 400 A 0.5 V 4.5 VDD < 5.5 V, IOL = 10 mA 1.0 V 1.8 VDD < 4.5 V, IOL = 1.6 mA 0.4 V P50 to P53 Remarks 1. Pin names enclosed in parentheses apply when using the PD78F9316. 2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 30 Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (2/4) Parameter Symbol Input leakage current, high ILIH1 Conditions VIN = VDD ILIH2 Input leakage current, low MIN. TYP. MAX. Unit P00 to P03, P10 to P13, P20 to P26, P30 to P33, RESET 3 A X1 (CL1), X2 (CL2), XT1, XT2 20 A ILIH3 VIN = 12 V P50 to P53 (N-ch open drain) 20 A ILIL1 VIN = 0 V P00 to P03, P10 to P13, P20 to P26, P30 to P33, RESET -3 A ILIL2 X1 (CL1), X2 (CL2), XT1, XT2 -20 A ILIL3 P50 to P53 (N-ch open drain) Note A -3 Output leakage current, ILOH high VOUT = VDD 3 A Output leakage current, ILOL low VOUT = 0 V -3 A Software pull-up resistor VIN = 0 V 200 k R1 P00 to P03, P10 to P13, P20 to P26, P30 to P33 50 100 Note If P50 to P53 have been set to input mode when a read instruction is executed to read from P50 to P53, a low-level input leakage current of up to -30 A flows during only one cycle. At all other times, the maximum leakage current is -3 A. Remarks 1. Pin names enclosed in parentheses apply when using the PD78F9316. 2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U14564EJ1V0DS 31 PD78F9306, 78F9316 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (3/4) Parameter Symbol Power supply Note 1 current IDD1 (Ceramic/crystal oscillation) IDD2 IDD3 IDD4 IDD5 Notes 1. Conditions 5.0 MHz crystal oscillation operation mode (C1 = C2 = 22 pF) 5.0 MHz crystal oscillation HALT mode (C1 = C2 = 22 pF) TYP. MAX. Unit VDD = 5.0 V 10% Note 2 MIN. 4.5 9 mA VDD = 3.0 V 10% Note 3 1 2 mA VDD = 2.0 V 10% Note 3 0.65 1.5 mA VDD = 5.0 V 10% Note 2 1.4 2 mA VDD = 3.0 V 10% Note 3 0.4 0.8 mA VDD = 2.0 V 10% Note 3 0.19 0.42 mA 32.768 kHz crystal oscillation operation Note 4 mode VDD = 5.0 V 10% 100 230 A VDD = 3.0 V 10% 70 160 A (C3 = C4 = 22 pF, R1 = 220 k) VDD = 2.0 V 10% 58 120 A 32.768 kHz crystal oscillation HALT Note 4 mode VDD = 5.0 V 10% 25 65 A VDD = 3.0 V 10% 7 29 A VDD = 2.0 V 10% 4 20 A LCD VDD = 5.0 V 10% Note 5 (C3 = C4 = operating VDD = 3.0 V 10% 22 pF, R1 = VDD = 2.0 V 10% 220 k) 28 70 A 9.6 34 A 6 25 A VDD = 5.0 V 10% 0.1 17 A VDD = 3.0 V 10% 0.05 5.5 A VDD = 2.0 V 10% 0.05 3.5 A LCD not operating Note 6 STOP mode The port current (including the current that flows to the on-chip pull-up resistors) is not included. 2. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 3. Low-speed mode operation (when PCC is set to 02H) 4. When the main system clock is stopped 5. This is the total current that flows when the LCD controller/driver is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1). The power supply current when the LCD is not operating (LCDON0 = 0, VAON0 = 1, LIPS0 = 0) is included in IDD2. 6. Remark This is the current when the LCD booster circuit is stopped (LCDON0 = 0, VAON0 = 1). Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 32 Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (4/4) Parameter Symbol Power supply Note 1 current IDD1 (RC oscillation) Conditions TYP. MAX. Unit VDD = 5.0 V 10% Note 2 6 9 mA VDD = 3.0 V 10% Note 3 2.0 2.5 mA VDD = 2.0 V 10% Note 3 1.2 1.6 mA VDD = 5.0 V 10% Note 2 2.5 3.5 mA VDD = 3.0 V 10% Note 3 1.5 2 mA VDD = 2.0 V 10% Note 3 0.8 1.5 mA VDD = 5.0 V 10% 100 230 A VDD = 3.0 V 10% 70 160 A VDD = 2.0 V 10% 58 120 A VDD = 5.0 V 10% 25 65 A VDD = 3.0 V 10% 7 29 A VDD = 2.0 V 10% 4 20 A LCD VDD = 5.0 V 10% Note 5 operating VDD = 3.0 V 10% 28 70 A 9.6 34 A VDD = 2.0 V 10% 6 25 A VDD = 5.0 V 10% 0.1 17 A VDD = 3.0 V 10% 0.05 5.5 A VDD = 2.0 V 10% 0.05 3.5 A 4.0 MHz RC oscillation operation mode (R = 4.7 k, C = 22 pF) IDD2 4.0 MHz RC oscillation HALT mode (R = 4.7 k, C = 22 pF) IDD3 32.768 kHz crystal oscillation operation Note 4 mode (C3 = C4 = 22 pF, R1 = 220 k) IDD4 32.768 kHz crystal oscillation HALT Note 4 mode LCD not operating (C3 = C4 = 22 pF, R1 = 220 k) IDD5 Notes 1. Note 6 STOP mode MIN. The port current (including the current that flows to the on-chip pull-up resistors) is not included. 2. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 3. Low-speed mode operation (when PCC is set to 02H) 4. When the main system clock is stopped 5. This is the total current that flows when the LCD controller/driver is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1). The power supply current when the LCD is not operating (LCDON0 = 0, VAON0 = 1, LIPS0 = 0) is included in IDD2. 6. Remark This is the current when the LCD booster circuit is stopped (LCDON0 = 0, VAON0 = 1). Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U14564EJ1V0DS 33 PD78F9306, 78F9316 AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Cycle time (minimum instruction execution time) Symbol TCY Conditions Operating with main system clock MIN. VDD = 2.7 to 5.5 V Operating with subsystem clock TMI40 input frequency TMI40 input high-/lowlevel width fTMI tTIMH, MAX. Unit 0.4 8.0 s 1.6 8.0 s 125 s 0 4 MHz 0 275 kHz 114 VDD = 2.7 to 5.5 V TYP. 122 0.1 s 1.8 s INTP0 to INTP3 10 s KR00 to KR03 10 s VDD = 2.7 to 5.5 V tTIML Interrupt input high/low-level width tINTH, Key return input lowlevel width tKRL RESET low-level width tRSL 10 s CPT20 input high-/lowlevel width tCPH, 10 s tINTL tCPL TCY vs VDD (main system clock) 60 Cycle time TCY1 [ s] 20 10 Guaranteed operation range 2.0 1.0 0.5 0.4 0.1 1 2 3 4 5 Power supply voltage VDD (V) 34 Data Sheet U14564EJ1V0DS 6 PD78F9306, 78F9316 (2) Serial interface 10, 20 (SIO10, SIO20) (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (internal clock output) Parameter SCKn0 cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V SCKn0 high-/low-level width tKH1, tKL1 VDD = 2.7 to 5.5 V SIn0 setup time (to SCKn0) tSIK1 VDD = 2.7 to 5.5 V SIn0 hold time (from SCKn0) tKSI1 Delay time from SCKn0 to SOn0 output tKSO1 VDD = 2.7 to 5.5 V R = 1 k, C = 100 pF Note VDD = 2.7 to 5.5 V MIN. TYP. MAX. Unit 800 ns 3200 ns tKCY1/2-50 ns tKCY1/2-150 ns 150 ns 500 ns 400 ns 600 ns 0 250 ns 0 1000 ns MAX. Unit Note R and C are the load resistance and load capacitance of the SOn0 output lines. Remark n = 1, 2 (b) 3-wire serial I/O mode (external clock input) Parameter SCKn0 cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V SCKn0 high-/low-level width tKH2, tKL2 VDD = 2.7 to 5.5 V SIn0 setup time (to SCKn0) tSIK2 VDD = 2.7 to 5.5 V SIn0 hold time (from SCKn0) tKSI2 Delay time from SCKn0 to SOn0 output tKSO2 VDD = 2.7 to 5.5 V R = 1 k, C = 100 pF Note VDD = 2.7 to 5.5 V MIN. TYP. 800 ns 3200 ns 400 ns 1600 ns 100 ns 150 ns 400 ns 600 ns 0 300 ns 0 1000 ns Note R and C are the load resistance and load capacitance of the SOn0 output lines. Remark n = 1, 2 Data Sheet U14564EJ1V0DS 35 PD78F9306, 78F9316 (c) UART mode (SIO20 only) (dedicated baud rate generator output) Parameter Symbol Transfer rate Conditions MIN. TYP. VDD = 2.7 to 5.5 V MAX. Unit 78125 bps 19531 bps MAX. Unit (d) UART mode (SIO20 only) (external clock input) Parameter ASCK20 cycle time ASCK20 high-/lowlevel width Symbol tKCY3 tKH3, tKL3 Transfer rate ASCK20 rise/fall time 36 Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tR, tF Data Sheet U14564EJ1V0DS MIN. TYP. 800 ns 3200 ns 400 ns 1600 ns 39063 bps 9766 bps 1 s PD78F9306, 78F9316 AC Timing Test Points (excluding X1 (CL1) and XT1 inputs) 0.8VDD 0.2VDD 0.8VDD Test points 0.2VDD Clock Timing 1/fCLK tXL tXH VIH4 (MIN.) X1 (CL1) input VIL4 (MAX.) 1/fXT tXTL tXTH VIH5 (MIN.) XT1 input Remark VIL5 (MAX.) fCLK: fX or fCC TMI Timing 1/fTMI tTIL tTIH TMI40 input Interrupt Input Timing tINTL tINTH INTP0 to INTP3 Key Return Input Timing tKRL KR00 to KR03 Data Sheet U14564EJ1V0DS 37 PD78F9306, 78F9316 RESET Input Timing tRSL RESET CPT20 Input Timing tCPL tCPH CPT20 Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCKn0 tSIKm SIn0 tKSIm Input data tKSOm Output data SOn0 Remark n, m = 1, 2 UART mode (external clock input): tKCY3 tKL3 tKH3 tR ASCK20 38 Data Sheet U14564EJ1V0DS tF PD78F9306, 78F9316 LCD Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Symbol LCD output voltage variation range VLCD2 Doubler output VLCD1 Conditions MIN. TYP. MAX. Unit c1 to c4 = 0.47 F GAIN = 1 0.84 1.0 1.165 V GAIN = 0 1.26 1.5 1.74 V 2 VLCD2 2.0 VLCD2 2.0 VLCD2 V 3.0 VLCD2 3.0 VLCD2 V c1 to c4 = 0.47 F - 0.1 Tripler output VLCD0 c1 to c4 = 0.47 F 3 VLCD2 - 0.15 Note 1 Voltage boost wait time tVAWAIT GAIN = 0 GAIN = 1 0.5 s 5.0 VDD 5.5 V 2.0 s 4.5 VDD < 5.0 V 1.0 s 1.8 VDD < 4.5 V 0.5 s LCD output voltage Note 2 differential (common) VODC IO = 5 A 0 0.2 V LCD output voltage Note 2 differential (segment) VODS IO = 1 A 0 0.2 V Notes 1. This is the wait time from when voltage boost is started (VAON0 = 1) until display is enabled (LCDON0 = 0). 2. The voltage differential is the difference between the segment and common signal output's actual and ideal output voltages. Remark c1: Capacitor connected between CAPH and CAPL c2: Capacitor connected between VLC0 and ground c3: Capacitor connected between VLC1 and ground c4: Capacitor connected between VLC2 and ground Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Conditions MIN. Data retention power supply voltage VDDDR 1.8 Release signal set time tSREL 0 Data Sheet U14564EJ1V0DS TYP. MAX. Unit 5.5 V s 39 PD78F9306, 78F9316 Data Retention Timing Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 40 Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 Oscillation Stabilization Wait Time (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Symbol Oscillation stabilization wait Note 1 time (ceramic/crystal tWAIT oscillation) Oscillation stabilization wait time (RC oscillation) Notes 1. tWAIT Conditions MIN. TYP. MAX. Unit 15 Release by RESET 2 /fX s Release by interrupt Note 2 s Release by RESET 2 /fCC 7 s 7 2 /fCC Release by interrupt s Use a resonator whose oscillation stabilizes within the oscillation stabilization wait time. 12 2. 15 17 Selection of 2 /fX, 2 /fX, or 2 /fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: Main system clock oscillation frequency (RC oscillation) Flash Memory Write/Erase Characteristics (TA = 10 to 40C, VDD = 1.8 to 5.5 V) Parameter Operating frequency Write current Note 1 Symbol fX, fCC IDDW (VDD pin) Write current Note 1 Conditions MAX. Unit 1.0 5 MHz 1.0 1.25 MHz RC oscillation During fCC = 4.0 MHz Note 2 operation 9 mA Ceramic oscillation During fX = 5.0 MHz operation 7 mA VDD = 2.7 to 5.5 V When VPP supply voltage = VPP1 MIN. TYP. IPPW When VPP supply voltage = VPP1 12 mA IDDE When VPP supply voltage = VPP1 RC oscillation During fCC = 4.0 MHz Note 2 operation 9 mA Ceramic oscillation During fX = 5.0 MHz operation 7 mA 100 mA 1 s 20 s 20 Times 0.2VDD V 10.3 V (VPP pin) Erase current Note 1 (VDD pin) Erase current Note 1 IPPE When VPP supply voltage = VPP1 (VPP pin) Unit erase time ter Total erase time tera Write count 0.5 1 Erase/write are regarded as 1 cycle VPP supply voltage Notes 1. 2. VPP0 In normal operation VPP1 During flash memory programming 0 9.7 10.0 The port current (including the current that flows to the on-chip pull-up resistors) is not included. When an external clock is input Data Sheet U14564EJ1V0DS 41 PD78F9306, 78F9316 8. CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES) (1) Characteristics curves of voltage boost stabilization time The following shows the characteristics curves of the time from the start of voltage boost (VAON0 = 1) and the changes in the LCD output voltage (when GAIN is set as 1 (using the 3 V display panel)). LCD Output Voltage/Voltage Boost Time 5.5 VDD = 4.5 V 5 VDD = 5 V VDD = 5.5 V 4.5 LCD output voltage [V] 4 3.5 VLCD0 3 2.5 VLCD1 2 1.5 VLCD2 1 0.5 0 0 500 1000 1500 2000 Voltage boost time [ms] 42 Data Sheet U14564EJ1V0DS 2500 3000 3500 4000 PD78F9306, 78F9316 (2) Temperature characteristics of LCD output voltage The following shows the temperature characteristics curves of LCD output voltage. LCD Output Voltage/Temperature (When GAIN = 1) VLCD2 5 VLCD1 VLCD0 LCD output voltage [V] 4 3 2 1 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [C] LCD Output Voltage/Temperature (When GAIN = 0) VLCD2 5 VLCD1 VLCD0 LCD output voltage [V] 4 3 2 1 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [C] Data Sheet U14564EJ1V0DS 43 PD78F9306, 78F9316 9. PACKAGE DRAWINGS 64-PIN PLASTIC QFP (14x14) A B 33 32 48 49 detail of lead end S C D Q 64 1 R 17 16 F J G H I M P K S N S L M NOTE ITEM Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 17.60.4 B 14.00.2 C 14.00.2 D 17.60.4 F 1.0 G 1.0 H 0.37 +0.08 -0.07 I J 0.15 0.8 (T.P.) K 1.80.2 L 0.80.2 M 0.17 +0.08 -0.07 N 0.10 P 2.550.1 Q 0.10.1 R 55 S 2.85 MAX. P64GC-80-AB8-5 44 Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 64-PIN PLASTIC TQFP (12x12) A B 48 detail of lead end 33 32 49 S P T C D R L U 64 Q 17 16 1 F G J H I M ITEM K S M N S NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A B 14.00.2 12.00.2 C 12.00.2 D F 14.00.2 1.125 G 1.125 H 0.32 +0.06 -0.10 I 0.13 J 0.65 (T.P.) K 1.00.2 L 0.5 M 0.17 +0.03 -0.07 N 0.10 P 1.0 Q 0.10.05 R 3 +4 -3 S 1.10.1 T 0.25 U 0.60.15 P64GK-65-9ET-3 Data Sheet U14564EJ1V0DS 45 PD78F9306, 78F9316 10. RECOMMENDED SOLDERING CONDITIONS The PD78F9306 and 78F9316 should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 10-1. Surface Mounting Type Soldering Conditions PD78F9306GC-AB8: 64-pin plastic QFP (14 x 14) PD78F9316GC-AB8: 64-pin plastic QFP (14 x 14) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less IR35-00-3 VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Three times or less VP15-00-3 Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300C max. Time: 3 seconds max. (per pin row) -- Caution Do not use different soldering methods together (except for partial heating). PD78F9306GK-9ET: 64-pin plastic TQFP (12 x 12) PD78F9316GK-9ET: 64-pin plastic TQFP (12 x 12) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or Note higher), Count: Two times or less, Exposure limit: 7 days (after that, prebake at 125C for 10 hours) IR35-107-2 VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or Note higher), Count: Two times or less, Exposure limit: 7 days (after that, prebake at 125C for 10 hours) VP15-107-2 Partial heating Pin temperature: 300C max. Time: 3 seconds max. (per pin row) -- Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). 46 Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 APPENDIX A. DIFFERENCES BETWEEN PD78F9306, 78F9316 AND MASK ROM VERSIONS The PD78F9306 and 78F9316 have flash memory in place of the internal ROM of the mask ROM versions. Differences between the PD78F9306 and 78F9316 and the mask ROM versions are shown in Table A-1. Table A-1. Differences Between PD78F9306, 78F9316 and Mask ROM Versions Part Number PD78F9306 Item Internal memory Flash Memory Versions ROM 16 KB High-speed RAM 512 bytes LCD display RAM 24 bytes PD78F9316 RC oscillation Mask ROM Versions PD789304 PD789306 PD789314 PD789316 8 KB 16 KB 8 KB 16 KB Ceramic/crystal oscillation RC oscillation Main system clock Ceramic/ crystal oscillation IC pin Not available Available VPP pin Available Not available Pull-up resistors 19 (software control: 19) 23 (software control: 19, mask option control: 4) Electrical specifications Refer to the relevant data sheet. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version. Data Sheet U14564EJ1V0DS 47 PD78F9306, 78F9316 APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for system development using the PD78F9306 and 78F9316. Language Processing Software RA78K0S Notes 1, 2, 3 Assembler package common to 78K/0S Series Notes 1, 2, 3 C compiler package common to 78K/0S Series CC78K0S Notes 1, 2, 3 DF789306 Notes 1, 2, 3 CC78K0S-L Device file for PD789306, 789316 Subseries C compiler library source file common to 78K/0S Series Flash Memory Writing Tools Flashpro III Note 4 (Part No. FL-PR3 , PG-FP3) Note 4 Flash memory writing adapter for 64-pin plastic QFP (GC-AB8 type) Note 4 Flash memory writing adapter for 64-pin plastic TQFP (GK-9ET type) FA-64GC FA-64GK Flash programmer dedicated to on-chip flash memory microcontroller Debugging Tools IE-78K0S-NS In-circuit emulator This is an in-circuit emulator for debugging hardware and software of application system using the 78K/0S Series. It supports the integrated debugger (ID78K0S-NS) and is used with an AC adapter, emulation probe, and interface adapter for connecting the host machine. IE-70000-MC-PS-B AC adapter This is the adapter for supplying power from an AC-100 to 240 V outlet. IE-70000-98-IF-C Interface adapter This adapter is needed when a PC-9800 series PC (except notebook type) is used as the host machine for the IE-78K0S-NS (supports C bus). IE-70000-CD-IF-A PC card interface This PC card and interface cable are needed when a PC-9800 series notebook-type PC is used as the host machine for the IE-78K0S-NS (supports PCMCIA socket). IE-70000-PC-IF-C Interface adapter This adapter is needed when an IBM PC/ATTM or compatible PC is used as the host machine for the IE-78K0S-NS (supports ISA bus). IE-70000-PCI-IF Interface adapter This adapter is needed when a PC that includes a PCI bus is used as the host machine for the IE-78K0S-NS. IE-789306-NS-EM1 Emulation board This is an emulation board for emulating the peripheral hardware inherent to the device. It is used with an in-circuit emulator. Note 4 This is a board that is used to connect an in-circuit emulator to the target system. It is for a 64-pin plastic QFP (GC-AB8 type). Note 4 This is a board that is used to connect an in-circuit emulator to the target system. It is for a 64-pin plastic TQFP (GK-9ET type). NP-64GC NP-64GK SM78K0S Notes 1, 2 ID78K0S-NS Notes 1, 2 Notes 1, 2 DF789306 System simulator common to 78K/0S Series Integrated debugger common to 78K/0S Series Device file for PD789306, 789316 Subseries Real-Time OS MX78K0S 48 Notes 1, 2 OS for 78K/0S Series Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 Notes 1. Based on PC-9800 Series (Japanese Windows) 2. Based on IBM PC/AT compatibles (Japanese/English Windows) 3. Based on HP9000 Series 700TM (HP-UXTM), SPARCstationTM (SunOSTM, SolarisTM), or NEWSTM (NEWS-OSTM) 4. Remark This product is manufactured by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-44-822-3813). The RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789306. Data Sheet U14564EJ1V0DS 49 PD78F9306, 78F9316 APPENDIX C. RELATED DOCUMENTS Documents Related to Devices Document Name Document No. PD789304, 789306, 789314, 789316 Data Sheet To be prepared PD78F9306, 78F9316 Data Sheet This document PD789306, 789316 Subseries User's Manual U14800E 78K/0S Series User's Manual Instructions U11047E 78K/0, 78K/0S Series Application Note Flash Memory Write U14458E Documents Related to Development Tools (User's Manuals) Document Name RA78K0S Assembler Package Document No. Operation U11622E Language U11599E Structured Assembly Language U11623E Operation U11816E Language U11817E SM78K0S, SM78K0 System Simulator Ver.2.10 or Later Windows Based Operation U14611E SM78K Series System Simulator Ver.2.10 or Later External Part User Open Interface Specifications U15006E ID-78K0-NS, ID78K0S-NS Integrated Debugger Ver.2.20 or Later Windows Based Operation U14910E CC78K0S C Compiler IE-78K0S-NS In-circuit Emulator U13549E IE-789306-NS-EM1 Emulation Board To be prepared Documents Related to Embedded Software (User's Manuals) Document Name 78K/0S Series OS MX78K0S Fundamental Document No. U12938E Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 50 Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 [MEMO] Data Sheet U14564EJ1V0DS 51 PD78F9306, 78F9316 [MEMO] 52 Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 [MEMO] Data Sheet U14564EJ1V0DS 53 PD78F9306, 78F9316 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. EEPROM is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. 54 Data Sheet U14564EJ1V0DS PD78F9306, 78F9316 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 Data Sheet U14564EJ1V0DS 55 PD78F9306, 78F9316 * The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4