UPD78F9316GK-9ET-A - NEC - Datasheet.Directory

DATA SHEET

8-BIT SINGLE-CHIP MICROCONTROLLERS

MOS INTEGRATED CIRCUIT

µµ

PD78F9306, 78F9316

Document No. U14564EJ1V0DS00 (1st edition)

Date Published March 2001 N CP(K)

Printed in Japan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

The mark shows major revised points.

DESCRIPTION

The

PD78F9306 and 78F9316 belong to the

PD789306, 789316 Subseries (for LCD drivers) in the 78K/0S

Series.

The

PD78F9306 has flash memory in place of the internal ROM of the

PD789304 and 789306, and the

PD78F9316 has flash memory in place of the internal ROM of the

PD789314 and 789316.

Because flash memory allows the program to be written and erased electrically with the device mounted on the

board, this product is ideal for the evaluation stages of system development, small-scale production, and rapid

development of new products.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before

designing.

µµ

PD789306, 789316 Subseries User’s Manual: U14800E

78K/0S Series User’s Manual Instructions: U11047E

FEATURES

•Pin compatible with mask ROM version (except VPP pin)

•Flash memory: 16 KB

•Main system clock

Ceramic/crystal oscillation:

PD78F9306

RC oscillation:

PD78F9316

•I/O ports: 23

•Serial interface: 2 channels

Switchable between 3-wire serial I/O mode and UART mode: 1 channel

3-wire serial I/O mode: 1 channel

•LCD controller/driver

Segment signals: 24, common signals: 4

•Timer: 5 channels

•Power supply voltage: VDD = 1.8 to 5.5 V

APPLICATIONS

Remote control devices, healthcare equipment, etc.

2001

µµ

PD78F9306, 78F9316

2Data Sheet U14564EJ1V0DS

ORDERING INFORMATION

Part Number Package

PD78F9306GC-AB8 64-pin plastic QFP (14 × 14)

PD78F9306GK-9ET 64-pin plastic TQFP (12 × 12)

PD78F9316GC-AB8 64-pin plastic QFP (14 × 14)

PD78F9316GK-9ET 64-pin plastic TQFP (12 × 12)

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 3

78K/0S SERIES LINEUP

The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.

Products under development

Products in mass production

PD789014

Small-scale package, general-purpose applications

78K/0S

Series

28-pin

PD789014 with enhanced timer and increased ROM, RAM capacity

On-chip UART and capable of low voltage (1.8 V) operation

PD789074 with added subsystem clock

LCD drive

Inverter control

44-pin PD789842 On-chip inverter controller and UART

ASSP

80-pin

PD789446

PD789456

PD789436

PD789417A

PD789407A

PD789426

PD789306

PD789316

PD789426 with enhanced A/D converter

PD789446 with enhanced A/D converter

A/D converter and resistance division type LCD (28 × 4)

A/D converter and on-chip voltage booster type LCD (15 × 4)

PD789407A with enhanced A/D converter

A/D converter and on-chip voltage booster type LCD (5 × 4)

RC oscillation version of the PD789306

On-chip voltage booster type LCD (24 × 4)

64-pin

PD789146

PD789156

44-pin

Small-scale package, general-purpose applications and A/D converter

44-pin

30-pin

PD789124A

PD789134A

PD789177

PD789167

30-pin

PD789104A

PD789114A

PD789167 with enhanced A/D converter

PD789104A with enhanced timer

PD789124A with enhanced A/D converter

RC oscillation version of the PD789104A

PD789104A with enhanced A/D converter

PD789026 with added A/D converter and multiplier

PD789104A with added EEPROM

PD789146 with enhanced A/D converter

PD789177Y

PD789167Y

Y Subseries products support SMB.

Dot LCD drive

20-pin PD789860

PD789840

44-pin

44-pin PD789800

20-pin PD789861 For keyless entry, on-chip POC and key return circuit

For keypad, on-chip POC

For PC keyboard, on-chip USB function

RC oscillation version of the PD789860

52-pin

52-pin For remote controller, with SIO and resistance division type LCD

For remote controller, with A/D converter and on-chip voltage booster type LCD

88-pin PD789830

PD789835

144-pin Segments: 40, commons: 16

Segment/common outputs: 96

42-/44-pin

44-pin PD789046

PD789074

PD789026

30-pin PD789026 with enhanced timer

VFD drive

52-pin PD789871 Total display outputs: 25

PD789488 A/D converter and on-chip voltage booster type LCD (28 × 4)

80-pin

PD789488 with added remote control receiver and resistance division type LCD

80-pin

PD789327

PD78980364-pin

PD789467

PD789477

For PC keyboard, on-chip USB HUB function

µµ

PD78F9306, 78F9316

4Data Sheet U14564EJ1V0DS

The major functional differences among the subseries are listed below.

VDD

Function

Subseries Name

ROM

Capacity 8-Bit 16-Bit Watch WDT 8-Bit

A/D

10-Bit

A/D

Serial

Interface I/O MIN.

Value

Remarks

PD789046 16 K 1 ch

PD789026 4 K to 16 K

PD789074 2 K to 8 K

1 ch 1 ch

Small-scale

package,

general-

purpose

applications

PD789014 2 K to 4 K 2 ch −

−

−−

1 ch (UART:

1 ch)

−

PD789177 −8 ch

PD789167

16 K to 24 K 3 ch 1 ch

8 ch −

31 −

PD789156 −4 ch

PD789146

8 K to 16 K

4 ch −

On-chip

EEPROM

PD789134A −4 ch

PD789124A 4 ch −

RC-oscillation

version

PD789114A −4 ch

Small-scale

package,

general-

purpose

applications

and A/D

converter

PD789104A

2 K to 8 K

1 ch

−

1 ch

4 ch −

1 ch (UART:

1 ch)

1.8 V

−

Inverter

control

PD789842 8 K to 16 K 3 ch Note 1 ch 1 ch 8 ch −1 ch (UART:

1 ch)

30 4.0 V −

VFD drive

PD789871 4 K to 8 K 3 ch – 1 ch 1 ch – – 1 ch 33 2.7 V –

PD789488 32 K 8 ch 2 ch (UART:

1 ch)

PD789417A

−

7 ch

PD789407A

12 K to

24 K

3 ch

7 ch −

PD789456 – 6 ch

PD789446 6 ch –

PD789436 – 6 ch

PD789426

12 K to

16 K

6 ch

1 ch (UART:

1 ch)

−

PD789316 RC-oscillation

version

LCD drive

PD789306

8 K to 16 K

2 ch

1 ch 1 ch 1 ch

–

2 ch (UART:

1 ch)

1.8 V

–

PD789835 24 K to

60 K

6 ch – 3 ch 28 1.8 VDot LCD

drive

PD789830 24 K 1 ch 1 ch

1 ch 1 ch

–

–1 ch (UART:

1 ch)

30 2.7 V

−

PD789477 24 K 3 ch 1 ch 8 ch 2 ch (UART:

1 ch)

PD789467 1 ch – 18

PD789327

4 K to 24 K

1 ch

1 ch 21

1.8 V On-chip LCD

PD789803 8 K to 16 K 41 3.6 V

PD789800

–

2 ch (USB:

1 ch) 31 4.0 V

PD789840

8 K

4 ch 1 ch 29 2.8 V

−

PD789861 RC-oscillation

version,

on-chip

EEPROM

ASSP

PD789860

4 K

2 ch –

−

1 ch

−

–

–141.8 V

On-chip

EEPROM

Note 10-bit timer: 1 channel

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 5

OVERVIEW OF FUNCTIONS

Item

PD78F9306

PD78F9316

Flash memory 16 KB

High-speed RAM 512 bytes

Internal

memory

LCD display RAM 24 bytes

Main system clock

(oscillation frequency)

Ceramic/crystal oscillation (1.0 to 5.0 MHz) RC oscillation (2.0 to 4.0 MHz)

Subsystem clock

(oscillation frequency)

Crystal oscillation (32.768 kHz)

0.4

s/1.6

(@ 5.0 MHz operation with main system

clock)

0.5

s/2.0

(@ 4.0 MHz operation with main system

clock)

Minimum instruction execution time

122

s (@ 32.768 kHz operation with subsystem clock)

General-purpose registers 8 bits × 8 registers

Instruction set • 16-bit operation

• Bit manipulation (set, reset, test)

I/O ports Total: 23

• CMOS I/O: 19

• N-ch open drain: 4

Timers • 16-bit timer: 1 channel

• 8-bit timer/event counter: 2 channels

• Watch timer: 1 channel

• Watchdog timer: 1 channel

Serial interface • Switchable between 3-wire serial I/O mode and UART mode: 1 channel

• 3-wire serial I/O mode: 1 channel

LCD controller/driver • Segment signal outputs: 24 (Max.)

• Common signal outputs: 4 (Max.)

Maskable Internal: 9, External: 5Vectored interrupt

sources Non-maskable Internal: 1

Power supply voltage VDD = 1.8 to 5.5 V

Operating ambient temperature TA = –40 to +85°C

Package • 64-pin plastic QFP (14 × 14)

• 64-pin plastic TQFP (12 × 12)

µµ

PD78F9306, 78F9316

6Data Sheet U14564EJ1V0DS

CONTENTS

1. PIN CONFIGURATION (Top View)....................................................................................................................... 7

2. BLOCK DIAGRAM ................................................................................................................................................ 9

3. PIN FUNCTIONS ................................................................................................................................................. 10

3.1 Port Pins ...................................................................................................................................................... 10

3.2 Non-Port Pins .............................................................................................................................................. 11

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................................... 12

4. MEMORY SPACE................................................................................................................................................ 14

5. FLASH MEMORY PROGRAMMING ................................................................................................................... 15

5.1 Selecting Communication Mode................................................................................................................ 15

5.2 Function of Flash Memory Programming ................................................................................................. 16

5.3 Connecting Flashpro III .............................................................................................................................. 16

5.4 Example of Settings for Flashpro III (PG-FP3).......................................................................................... 18

6. OVERVIEW OF INSTRUCTION SET .................................................................................................................. 19

6.1 Conventions ................................................................................................................................................ 19

6.2 List of Operations ....................................................................................................................................... 21

7. ELECTRICAL SPECIFICATIONS ....................................................................................................................... 26

8. CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES)............................ 42

9. PACKAGE DRAWINGS ...................................................................................................................................... 44

10. RECOMMENDED SOLDERING CONDITIONS................................................................................................... 46

APPENDIX A. DIFFERENCES BETWEEN

µµ

PD78F9306, 78F9316 AND MASK ROM VERSIONS ................ 47

APPENDIX B. DEVELOPMENT TOOLS ................................................................................................................. 48

APPENDIX C. RELATED DOCUMENTS................................................................................................................. 50

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 7

1. PIN CONFIGURATION (Top View)

64-pin plastic QFP (14 ×

××

× 14) 64-pin plastic TQFP (12 ×

××

× 12)

PD78F9306GC-AB8

PD78F9306GK-9ET

PD78F9316GC-AB8

PD78F9316GK-9ET

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

P50

P51

P52

P53

XT1

XT2

X1 (CL1)

X2 (CL2)

RESET

P00/KR0

P01/KR1

P02/KR2

P03/KR3 32

CAPH

CAPL

LC0

LC1

LC2

COM0

COM1

COM2

COM3

S22

S21

S20

S19

S18

S17

S16

S15

S14

S13

S12

S11

S10

P20/SCK10

P21/SO10

P22/SI10

P23/SCK20/ASCK20

P24/SO20/TxD20

P25/SI20/RxD20

P26/TO20

P30/INTP0/CPT20

P31/INTP1/TO30/TMI40

P32/INTP2/TO40

P33/INTP3

P10

P11

P12

P13

S23

Caution Connect the VPP pin directly to the VSS pin in normal operation mode.

Remark Pin names enclosed in parentheses apply when using the

PD78F9316.

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

ASCK20: Asynchronous serial input S0 to S23: Segment output

CAPH, CAPL: LCD power supply capacitance control SCK10, SCK20: Serial clock

CL1, CL2: RC oscillator SI10, SI20: Serial input

COM0 to COM3: Common output SO10, SO20: Serial output

CPT20: Capture trigger input TMI40: Timer input

INTP0 to INTP3: External interrupt input TO20, TO30, TO40: Timer output

KR0 to KR3: Key return TxD20: Transmit data

P00 to P03: Port 0 VDD: Power supply

P10 to P13: Port 1 VLC0 to VLC2: LCD power supply

P20 to P26: Port 2 VPP: Programming power supply

P30 to P33: Port 3 VSS: Ground

P50 to P53: Port 5 X1, X2: Crystal/ceramic oscillator

RESET: Reset XT1, XT2: Crystal oscillator

RxD20: Receive data

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 9

2. BLOCK DIAGRAM

Remark Pin names enclosed in parentheses apply when using the

PD78F9316.

78K/0S

CPU core Flash

memory

TO30/TMI40/P31 8-bit

timer 30 P00 to P03

Port 0

P10 to P13

Port 1

P20 to P26

Port 2

P30 to P33

Port 3

P50 to P53

Port 5

TMI40/TO30/P31

TO20/P26 16-bit timer 20

Watch timer

Watchdog timer

Serial

interface 20

SCK20/ASCK20/P23

SI20/RxD20/P25

SO20/TxD20/P24

S0 to S23

COM0 to COM3

RAM

RAM space

for

LCD data

8-bit

timer/event

counter 40

Cascaded

16-bit

timer/event

counter

TO40/P32

CPT20/P30

Serial

interface 10

SCK10/P20

SI10/P22

SO10/P21

LC0

to V

LC2

CAPH

CAPL

LCD

controller driver

System control

RESET

X1 (CL1)

X2 (CL2)

XT1

XT2

Interrupt control

INTP0/P30

INTP1/P31

INTP2/P32

INTP3/P33

KR0/P00 to

KR3/P03

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

3. PIN FUNCTIONS

3.1 Port Pins

Pin Name I/O Function After Reset Alternate Function

P00 to P03 I/O Port 0.

4-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, use of an on-chip pull-up resistor

can be specified in port units by pull-up resistor option register

0 (PU0) or key return mode register 00 (KRM00).

Input KR0 to KR3

P10 to P13 I/O Port 1.

4-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, use of an on-chip pull-up resistor

can be specified in port units by pull-up resistor option register

0 (PU0).

Input –

P20 SCK10

P21 SO10

P22 SI10

P23 SCK20/ASCK20

P24 SO20/TxD20

P25 SI20/RxD20

P26

I/O Port 2.

7-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, use of an on-chip pull-up resistor

can be specified in bit units by pull-up resistor option register

B2 (PUB2).

Input

TO20

P30 INTP0/CPT20

P31 INTP1/TO30/TMI40

P32 INTP2/TO40

P33

I/O Port 3.

4-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, use of an on-chip pull-up resistor

can be specified in bit units by pull-up resistor option register

B3 (PUB3).

Input

INTP3

P50 to P53 I/O Port 5.

4-bit I/O port.

Input/output can be specified in 1-bit units.

Input –

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 11

3.2 Non-Port Pins

Pin Name I/O Function After Reset Alternate Function

INTP0 P30/CPT20

INTP1 P31/TO30/TMI40

INTP2 P32/TO40

INTP3

Input External interrupt input for which the valid edge (rising edge,

falling edge, or both rising and falling edges) can be specified

Input

P33

KR0 to KR3 Input Key return signal detection Input P00 to P03

SCK10 Serial clock input/output for serial interface 10 (SIO10) P20

SCK20

Input/

output Serial clock input/output for serial interface 20 (SIO20)

Input

P23/ASCK20

SI10 Serial data input for serial interface 10 (SIO10) P22

SI20

Input

Serial data input for serial interface 20 (SIO20)

Input

P25/RxD20

SO10 Serial data output for serial interface 10 (SIO10) P21

SO20

Output

Serial data output for serial interface 20 (SIO20)

Input

P24/TxD20

ASCK20 Input Serial clock input for asynchronous serial interface Input P23/SCK20

RxD20 Input Serial data input for asynchronous serial interface Input P25/SI20

TxD20 Output Serial data output for asynchronous serial interface Input P24/SO20

TO20 Output 16-bit timer 20 (TM20) output Input P26

CPT20 Input Capture edge input Input P30/INTP0

TO30 Output 8-bit timer 30 (TM30) output Input P31/INTP1/TMI40

TO40 Output 8-bit timer 40 (TM40) output Input P32/INTP2

TMI40 Input External count clock input to 8-bit timer 40 (TM40) Input P31/INTP1/TO30

S0 to S23 Output Segment signal output for LCD controller/driver Low-level

output

–

COM0 to COM3 Output Common signal output for LCD controller/driver Low-level

output

–

VLC0 to VLC2 – LCD drive voltage – –

CAPH – ––

CAPL –

Connection pin for LCD driver’s capacitor

––

X1Note 1 Input ––

X2Note 1 –

Connecting crystal resonator for main system clock oscillation

––

CL1Note 2 Input ––

CL2Note 2 –

Connections to resistor (R) and capacitor (C) for main system

clock oscillation ––

XT1 Input ––

XT2 –

Connecting crystal resonator for subsystem clock oscillation

––

RESET Input System reset input Input –

VDD – Positive power supply – –

VSS – Ground potential – –

VPP – Flash memory programming mode setting. High-voltage

application for program write/verify. In normal operation mode,

connect directly to VSS.

––

Notes 1.

PD78F9306 only

PD78F9316 only

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.

For the I/O circuit configuration of each type, refer to Figure 3-1.

Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins

Pin Name I/O

Circuit Type

I/O Recommended Connection of Unused Pins

P00/KR0 to P03/KR3 8-A

P10 to P13 5-A

P20/SCK10

P21/SO10

P22/SI10

P23/SCK20/ASCK20

P24/SO20/TxD20

P25/SI20/RxD20

P26/TO20

Input mode: Independently connect to VDD or VSS via a resistor.

Output mode: Leave open.

P30/INTP0/CPT20

P31/INTP1/TO30/

TMI40

P32/INTP2/TO40

P33/INTP3

8-A

Input mode: Independently connect to VSS via a resistor.

Output mode: Leave open.

P50 to P53 13-V

I/O

Input mode: Independently connect to VDD via a resistor.

Output mode: Leave open.

S0 to S23 17

COM0 to COM3 18

Output

VLC0 to VLC2 –

CAPH, CAPL –

–

Leave open.

XT1 Input Connect to VSS.

XT2

–

– Leave open.

RESET 2 Input –

VPP – – Connect directly to VSS.

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 13

Figure 3-1. Pin I/O Circuits

Type 2 Type 13-V

Schmitt-triggered input with hysteresis characteristics

Output data

Output disable

IN/OUT

N-ch

Middle-voltage input buffer

Input enable

Type 5-A Type 17

Pull-up

enable

P-ch

IN/OUT

Data

Output

disable

Input

enable

N-ch

P-ch

N-ch

P-ch

N-ch

data OUT

VLC0

VLC1

SEG

VLC2

P-ch

Type 8-A Type 18

Pull-up

enable

VDD

P-ch

Data

VDD

P-ch

Output

disable

IN/OUT

N-ch

VSS

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch P-ch

N-ch

P-ch N-ch

VLC1

COM

data

VLC0

VLC2

OUT

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

4. MEMORY SPACE

Figure 4-1 shows the memory map.

Figure 4-1. Memory Map

4000H

3FFFH

Special function registers

(SFR)

256 × 8 bits

Internal high-speed RAM

512 × 8 bits

LCD display RAM

24 × 4 bits

FFFFH

FF00H

FEFFH

FD00H

FCFFH

0000H

Program memory

space

Data memory

space 3FFFH

0000H

Program area

0080H

007FH

Program area

0040H

003FH

CALLT table area

Reserved

0022H

0021H Vector table area

Internal flash memory

16384 × 8 bits

FA18H

FA17H

FA00H

F9FFH Reserved

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 15

5. FLASH MEMORY PROGRAMMING

The program memory that is incorporated in the

PD78F9306 and 78F9316 is flash memory.

With flash memory, it is possible to write programs on-board. Writing is performed by connecting a dedicated flash

programmer (Flashpro III (Part No. FL-PR3, PG-FP3)) to the host machine and the target system.

Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd.

5.1 Selecting Communication Mode

Writing to flash memory is performed using the Flashpro III in a serial communication mode. Select one of the

communication modes in Table 5-1. The selection of the communication mode is made by using the format shown in

Figure 5-1. Each communication mode is selected using the number of VPP pulses shown in Table 5-1.

Table 5-1. List of Communication Mode

Communication Mode Pins VPP Pulses

SCK10/P20

SO10/P21

SI10/P22

3-wire serial I/O

P00/KR0 (serial clock input)

P01/KR1 (serial data output)

P02/KR2 (serial data input)

UART TxD20/SO20/P24

RxD20/SI20/P25

Caution Be sure to select a communication mode using the number of VPP pulses shown in

Table 5-1.

Figure 5-1. Format of Communication Mode Selection

12 n

RESET

10 V

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

5.2 Function of Flash Memory Programming

Operations such as writing to flash memory are performed by various command/data transmission and reception

operations according to the selected communication mode. Table 5-2 shows the major functions of flash memory

programming.

Table 5-2. Major Function of Flash Memory Programming

Function Description

Batch erase Deletes the entire memory contents.

Batch blank check Checks the deletion status of the entire memory.

Data write Performs a write operation to the flash memory based on the write start address and the number of

data to be written (number of bytes).

Batch verify Compares the entire memory contents with the input data.

5.3 Connecting Flashpro III

The connection of the Flashpro III and the

PD78F9306 and 78F9316 differs according to the communication

mode (3-wire serial I/O or UART). The connections for each communication mode are shown in Figures 5-2 and 5-3,

respectively.

Figure 5-2. Connection Example of Flashpro III When Using 3-Wire Serial I/O Mode (1/2)

Note 1

RESET

CLK

SCK

GND

RESET

X1 (P03/KR03)

Note 2

SCK10

SI10

SO10

Flashpro III PD78F9306, 78F9316

Notes 1. n = 1, 2

2. Pin names enclosed in parentheses apply when using the

PD78F9316.

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 17

Figure 5-2. Connection Example of Flashpro III When Using 3-Wire Serial I/O Mode (2/2)

Note 1

RESET

CLK

SCK

GND

RESET

X1 (P03/KR03)

Note 2

P00/KR0 (Serial clock)

P02/KR2 (Serial input)

P01/KR1 (Serial output)

Flashpro III PD78F9306, 78F9316

Notes 1. n = 1, 2

2. Pin names enclosed in parentheses apply when using the

PD78F9316.

Figure 5-3. Connection Example of Flashpro III When Using UART Mode

Note 1

RESET

CLK

GND

RESET

X1 (P03/KR03)

Note 2

RxD20

TxD20

Flashpro III PD78F9306, 78F9316

Notes 1. n = 1, 2

2. Pin names enclosed in parentheses apply when using the

PD78F9316.

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

5.4 Example of Settings for Flashpro III (PG-FP3)

When writing to flash memory using Flashpro III (PG-FP3), make the following settings.

<1> Load a parameter file.

<2> Select the mode of serial communication and serial clock with a type command.

<3> Make the settings according to the example of settings for PG-FP3 shown below.

Table 5-3. Example of Settings for PG-FP3

Communication Mode Example of Settings for PG-FP3 VPP Pulse NumberNote 1

COMM PORT SIO-ch0

On Target BoardCPU CLK

In Flashpro

On Target Board 4.1943 MHz

SIO CLK 1.0 MHz

In Flashpro 4.0 MHz

SIO CLK 1.0 MHz

COMM PORT SIO-ch1

On Target BoardCPU CLK

In Flashpro

On Target Board 4.1943 MHz

SIO CLK 1.0 MHz

In Flashpro 4.0 MHz

3-wire serial I/O

SIO CLK 1.0 MHz

COMM PORT UART-ch0

CPU CLK On Target Board

On Target Board 4.1943 MHz

UART

UART BPS 9600 bpsNote 2

Notes 1. This is the number of VPP pulses that are supplied by the Flashpro III at serial communication

initialization. The pins that will be used for communication are determined according to this number.

2. Select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps.

Remark COMM PORT: Serial port selection

SIO CLK: Serial clock frequency selection

CPU CLK: Input CPU clock source selection

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 19

6. OVERVIEW OF INSTRUCTION SET

This section lists the instruction set for the

PD78F9306 and 78F9316.

6.1 Conventions

6.1.1 Operand expressions and description methods

Operands are described in “Operand” column of each instruction in accordance with the description method of the

instruction operand expression (see the assembler specifications for details). When there are two or more description

methods, select one of them. Uppercase letters and symbols, #, !, $, and [ ] are key words and are described as they

are. The meaning of each symbol is described below.

•# : Immediate data specification •$ : Relative address specification

•! : Absolute address specification •[ ] : Indirect address specification

For immediate data, enter an appropriate numeric value or a label. When using a label, be sure to enter the #, !, $

and [ ] symbols.

For operand register expressions, r and rp, either function names (X, A, C, etc.) or absolute names (names in

parenthesis in the table below, R0, R1, R2, etc.) can be used for the description.

Table 6-1. Operand Expressions and Description Methods

Expression Description Method

sfr

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)

AX (RP0), BC (RP1), DE (RP2), HL (RP3)

Special function register symbol

saddr

saddrp

FE20H to FF1FH: immediate data or label

FE20H to FF1FH: immediate data or label (even addresses only)

addr16

addr5

0000H to FFFFH: immediate data or label

(even addresses only for 16-bit data transfer instruction)

0040H to 007FH: immediate data or label (even addresses only)

word

byte

bit

16-bit immediate data or label

8-bit immediate data or label

3-bit immediate data or label

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

6.1.2 Description of “Operation” column

A: A register; 8-bit accumulator

X: X register

B: B register

C: C register

D: D register

E: E register

H: H register

L: L register

AX: AX register pair; 16-bit accumulator

BC: BC register pair

DE: DE register pair

HL: HL register pair

PC: Program counter

SP: Stack pointer

PSW: Program status word

CY: Carry flag

AC: Auxiliary carry flag

Z: Zero flag

IE: Interrupt request enable flag

NMIS: Flag indicating non-maskable interrupt servicing in progress

( ): Memory contents indicated by address or register contents in parenthesis

XH, XL: Higher 8 bits and lower 8 bits of 16-bit register

∧: Logical product (AND)

∨: Logical sum (OR)

∨: Exclusive logical sum (exclusive OR)

: Inverted data

addr16: 16-bit immediate data or label

jdisp8: Signed 8-bit data (displacement value)

6.1.3 Description of “Flag” column

(Blank): Unchanged

0: Cleared to 0

1: Set to 1

×: Set/cleared according to the result

R: Previously saved value is restored

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 21

6.2 List of Operations

FlagsMnemonic Operand Bytes Clocks Operation

ZACCY

r, #byte 3 6 r ← byte

saddr, #byte 3 6 (saddr) ← byte

sfr, #byte 3 6 sfr ← byte

A, r Note 1 24A

← r

r, A Note 1 24r

← A

A, saddr 2 4 A ← (saddr)

saddr, A 2 4 (saddr) ← A

A, sfr 2 4 A ← sfr

sfr, A 2 4 sfr ← A

A, !addr16 3 8 A ← (addr16)

!addr16, A 3 8 (addr16) ← A

PSW, #byte 3 6 PSW ← byte ×××

A, PSW 2 4 A ← PSW

PSW, A 2 4 PSW ← A ×××

A, [DE] 1 6 A ← (DE)

[DE], A 1 6 (DE) ← A

A, [HL] 1 6 A ← (HL)

[HL], A 1 6 (HL) ← A

A, [HL + byte] 2 6 A ← (HL + byte)

MOV

[HL + byte], A 2 6 (HL + byte) ← A

A, X 1 4 A ↔ X

A, r Note 2 26A

↔ r

A, saddr 2 6 A ↔ (saddr)

A, sfr 2 6 A ↔ (sfr)

A, [DE] 1 8 A ↔ (DE)

A, [HL] 1 8 A ↔ (HL)

XCH

A, [HL + byte] 2 8 A ↔ (HL + byte)

rp, #word 3 6 rp ← word

AX, saddrp 2 6 AX ← (saddrp)

saddrp, AX 2 8 (saddrp) ← AX

AX, rp Note 3 14AX

← rp

MOVW

rp, AX Note 3 14rp

← AX

XCHW AX, rp Note 3 18AX

↔ rp

Notes 1. Except r = A

2. Except r = A, X

3. rp = BC, DE and HL only

Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

FlagsMnemonic Operand Bytes Clocks Operation

ZACCY

A, #byte 2 4 A, CY ← A + byte ×××

saddr, #byte 3 6 (saddr), CY ← (saddr) + byte ×××

A, r 2 4 A, CY ← A + r ×××

A, saddr 2 4 A, CY ← A + (saddr) ×××

A, !addr16 3 8 A, CY ← A + (addr16) ×××

A, [HL] 1 6 A, CY ← A + (HL) ×××

ADD

A, [HL + byte] 2 6 A, CY ← A + (HL + byte) ×××

A, #byte 2 4 A, CY ← A + byte + CY ×××

saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY ×××

A, r 2 4 A, CY ← A + r + CY ×××

A, saddr 2 4 A, CY ← A + (saddr) + CY ×××

A, !addr16 3 8 A, CY ← A + (addr16) + CY ×××

A, [HL] 1 6 A, CY ← A + (HL) + CY ×××

ADDC

A, [HL + byte] 2 6 A, CY ← A + (HL + byte) + CY ×××

A, #byte 2 4 A, CY ← A – byte ×××

saddr, #byte 3 6 (saddr), CY ← (saddr) – byte ×××

A, r 2 4 A, CY ← A – r ×××

A, saddr 2 4 A, CY ← A – (saddr) ×××

A, !addr16 3 8 A, CY ← A – (addr16) ×××

A, [HL] 1 6 A, CY ← A – (HL) ×××

SUB

A, [HL + byte] 2 6 A, CY ← A – (HL + byte) ×××

A, #byte 2 4 A, CY ← A – byte – CY ×××

saddr, #byte 3 6 (saddr), CY ← (saddr) – byte – CY ×××

A, r 2 4 A, CY ← A – r – CY ×××

A, saddr 2 4 A, CY ← A – (saddr) – CY ×××

A, !addr16 3 8 A, CY ← A – (addr16) – CY ×××

A, [HL] 1 6 A, CY ← A – (HL) – CY ×××

SUBC

A, [HL + byte] 2 6 A, CY ← A – (HL + byte) – CY ×××

A, #byte 2 4 A ← A ∧ byte ×

saddr, #byte 3 6 (saddr) ← (saddr) ∧ byte ×

A, r 2 4 A ← A ∧ r ×

A, saddr 2 4 A ← A ∧ (saddr) ×

A, !addr16 3 8 A ← A ∧ (addr16) ×

A, [HL] 1 6 A ← A ∧ (HL) ×

AND

A, [HL + byte] 2 6 A ← A ∧ (HL + byte) ×

Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 23

FlagsMnemonic Operand Bytes Clocks Operation

ZACCY

A, #byte 2 4 A ← A ∨ byte ×

saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte ×

A, r 2 4 A ← A ∨ r ×

A, saddr 2 4 A ← A ∨ (saddr) ×

A, !addr16 3 8 A ← A ∨ (addr16) ×

A, [HL] 1 6 A ← A ∨ (HL) ×

A, [HL + byte] 2 6 A ← A ∨ (HL + byte) ×

A, #byte 2 4 A ← A ∨ byte ×

saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte ×

A, r 2 4 A ← A ∨ r ×

A, saddr 2 4 A ← A ∨ (saddr) ×

A, !addr16 3 8 A ← A ∨ (addr16) ×

A, [HL] 1 6 A ← A ∨ (HL) ×

XOR

A, [HL + byte] 2 6 A ← A ∨ (HL + byte) ×

A, #byte 2 4 A – byte ×××

saddr, #byte 3 6 (saddr) – byte ×××

A, r 2 4 A – r ×××

A, saddr 2 4 A – (saddr) ×××

A, !addr16 3 8 A – (addr16) ×××

A, [HL] 1 6 A – (HL) ×××

CMP

A, [HL + byte] 2 6 A – (HL + byte) ×××

ADDW AX, #word 3 6 AX, CY ← AX + word ×××

SUBW AX, #word 3 6 AX, CY ← AX – word ×××

CMPW AX, #word 3 6 AX – word ×××

r24r

← r + 1 ××

INC

saddr 2 4 (saddr) ← (saddr) + 1 ××

r24r

← r – 1 ××

DEC

saddr 2 4 (saddr) ← (saddr) – 1 ××

INCW rp 1 4 rp ← rp + 1

DECW rp 1 4 rp ← rp – 1

ROR A, 1 1 2 (CY, A7 ← A0, Am – 1 ← Am) × 1 time ×

ROL A, 1 1 2 (CY, A0 ← A7, Am + 1 ← Am) × 1 time ×

RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am – 1 ← Am) × 1 time ×

ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am + 1 ← Am) × 1 time ×

Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

FlagsMnemonic Operand Bytes Clocks Operation

ZACCY

saddr. bit 3 6 (saddr. bit) ← 1

sfr. bit 3 6 sfr. bit ← 1

A. bit 2 4 A. bit ← 1

PSW. bit 3 6 PSW. bit ← 1 ×××

SET1

[HL]. bit 2 10 (HL). bit ← 1

saddr. bit 3 6 (saddr. bit) ← 0

sfr. bit 3 6 sfr. bit ← 0

A. bit 2 4 A. bit ← 0

PSW. bit 3 6 PSW. bit ← 0 ×××

CLR1

[HL]. bit 2 10 (HL). bit ← 0

SET1 CY 1 2 CY ← 11

CLR1 CY 1 2 CY ← 00

NOT1 CY 1 2 CY ← CY ×

CALL !addr16 3 6 (SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L,

PC ← addr16, SP ← SP – 2

CALLT [addr5] 1 8 (SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L,

PCH ← (00000000, addr5 + 1),

PCL ← (00000000, addr5),

SP ← SP – 2

RET 1 6 PCH ← (SP + 1), PCL ← (SP),

SP ← SP + 2

RETI 1 8 PCH ← (SP + 1), PCL ← (SP),

PSW ← (SP + 2), SP ← SP + 3,

NMIS ← 0

RRR

PSW 1 2 (SP – 1) ← PSW, SP ← SP – 1PUSH

rp 1 4 (SP – 1) ← rpH, (SP – 2) ← rpL,

SP ← SP – 2

PSW 1 4 PSW ← (SP), SP ← SP + 1 R R RPOP

rp 1 6 rpH ← (SP + 1), rpL ← (SP),

SP ← SP + 2

SP, AX 2 8 SP ← AXMOVW

AX, SP 2 6 AX ← SP

!addr16 3 6 PC ← addr16

$addr16 2 6 PC ← PC + 2 + jdisp8

AX 1 6 PCH ← A, PCL ← X

Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 25

FlagsMnemonic Operand Bytes Clocks Operation

ZACCY

BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1

BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0

BZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1

BNZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0

saddr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8

if (saddr. bit) = 1

sfr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr. bit = 1

A. bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A. bit = 1

PSW. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW. bit = 1

saddr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8

if (saddr. bit) = 0

sfr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr. bit = 0

A. bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A. bit = 0

PSW. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW. bit = 0

B, $addr16 2 6 B ← B – 1, then

PC ← PC + 2 + jdisp8 if B ≠ 0

C, $addr16 2 6 C ← C – 1, then

PC ← PC + 2 + jdisp8 if C ≠ 0

DBNZ

saddr, $addr16 3 8 (saddr) ← (saddr) – 1, then

PC ← PC + 3 + jdisp8 if (saddr) ≠ 0

NOP 1 2 No Operation

EI 3 6 IE ← 1 (Enable Interrupt)

DI 3 6 IE ← 0 (Disable Interrupt)

HALT 1 2 Set HALT Mode

STOP 1 2 Set STOP Mode

Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

7. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°

°°

°C)

Parameter Symbol Conditions Ratings Unit

VDD –0.3 to +6.5 VPower supply voltage

VPP –0.3 to +10.5 V

VI1 P00 to P03, P10 to P13, P20 to P26, P30 to

P33, X1 (CL1), X2 (CL2), XT1, XT2, RESET

–0.3 to VDD + 0.3Note VInput voltage

VI2 P50 to P53 N-ch open drain –0.3 to +13 V

Output voltage VO–0.3 to VDD + 0.3Note V

1 pin –10 mAOutput current, high IOH

Total for all pins –30 mA

1 pin 30 mAOutput current, low IOL

Total for all pins 160 mA

In normal operation mode –40 to +85 °COperating ambient temperature TA

During flash memory programming 10 to 40 °C

Storage temperature Tstg –40 to +125 °C

Note 6.5 V or less

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product is

on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

Remarks 1. Pin names enclosed in parentheses apply when using the

PD78F9316.

2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of

port pins.

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 27

Main System Clock Oscillator Characteristics

Ceramic/crystal oscillation (

µµ

PD78F9306)

(TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit

Oscillation frequency (fX)Note 1 1.0 5.0 MHzCeramic

resonator

X1X2V

C1C2

Oscillation stabilization

timeNote 2

After VDD reaches

oscillation voltage

range MIN.

4ms

Oscillation frequencyNote 1 1.0 5.0 MHz

VDD = 4.5 to 5.5 V 10 ms

Crystal

resonator

X1X2IC

C1C2

Oscillation stabilization

timeNote 2

30 ms

X1 input frequency (fX)Note 1 1.0 5.0 MHz

X2 X1

X1 input high-/low-level width

(tXH, tXL)

85 500 ns

X1 input frequency (fX)Note 1 VDD = 2.7 to 5.5 V 1.0 5.0 MHz

External

clock

OPEN

X1 input high-/low-level width

(tXH, tXL)

VDD = 2.7 to 5.5 V 85 500 ns

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

2. Time required to stabilize oscillation after reset or STOP mode release. Use a resonator whose

oscillation stabilizes within the oscillation stabilization wait time.

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as VSS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the device is operating on the subsystem

clock, wait until the oscillation stabilization time has been secured by the program before

switching back to the main system clock.

Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

RC oscillation (

µµ

PD78F9316)

(TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit

Oscillation frequency (fCC)Note 1 2.0 4.0 MHz

VDD = 2.7 to 5.5 V 32 ms

resonator

CL2CL1

Oscillation stabilization

timeNote 2

128 ms

CL1 input frequency (fCC)Note 1 1.0 4.0 MHz

CL1 CL2

CL1 input high-/low-level

width (tXH, tXL)

100 500 ns

CL1 input frequency (fCC)Note 1 VDD = 2.7 to 5.5 V 1.0 4.0 MHz

External

clock

CL1

OPEN

CL2

CL1 input high-/low-level

width (tXH, tXL)

VDD = 2.7 to 5.5 V 100 500 ns

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

The error of capacitor (C) and resistor (R) is not included.

2. Time required to stabilize oscillation after reset or STOP mode release. Use a resonator whose

oscillation stabilizes within the oscillation stabilization wait time.

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figure to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as VSS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the device is operating on the subsystem

clock, wait until the oscillation stabilization time has been secured by the program before

switching back to the main system clock.

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 29

RC Oscillation Frequency Characteristics (TA = –40 to +85°

°°

°C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

fCC1 VDD = 2.7 to 5.5 V 1.5 2.0 2.5 MHz

fCC2 VDD = 1.8 to 3.6 V 0.5 2.0 2.5 MHz

fCC3

R = 11.0 kΩ,

C = 22 pF

Target: 2 MHz VDD = 1.8 to 5.5 V 0.5 2.0 2.5 MHz

fCC4 VDD = 2.7 to 5.5 V 2.5 3.0 3.5 MHz

fCC5 VDD = 1.8 to 3.6 V 0.75 3.0 3.5 MHz

fCC6

R = 6.8 kΩ,

C = 22 pF

Target: 3 MHz VDD = 1.8 to 5.5 V 0.75 3.0 3.5 MHz

fCC7 VDD = 2.7 to 5.5 V 3.5 4.0 4.7 MHz

fCC8 VDD = 1.8 to 3.6 V 1.0 4.0 4.7 MHz

Oscillation

frequency

fCC9

R = 4.7 kΩ,

C = 22 pF

Target: 4 MHz VDD = 1.8 to 5.5 V 1.0 4.0 4.7 MHz

Remarks 1. Set RC to one of the above nine values so that the typical value of the oscillation frequency is

within 2.0 to 4.0 MHz.

2. The resistor (R) and capacitor (C) error is not included.

Subsystem Clock Oscillator Characteristics (TA = –40 to +85°

°°

°C, VDD = 1.8 to 5.5 V)

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit

Oscillation frequency

(fXT)Note 1

32 32.768 35 kHz

VDD = 4.5 to 5.5 V 1.2 2

Crystal

resonator

XT2XT1VPP

Oscillation stabilization

timeNote 2

XT1 input frequency

(fXT)Note 1

32 35 kHzExternal

clock

XT1 XT2

XT1 input high-/low-level

width (tXTH, tXTL)

14.3 15.6

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figure to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as VSS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current

consumption, and is more prone to malfunction due to noise than the main system clock

oscillator. Particular care is therefore required with the wiring method when the subsystem

clock is used.

Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

DC Characteristics (TA = –40 to +85°

°°

°C, VDD = 1.8 to 5.5 V) (1/4)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

1 pin 10 mAOutput current, low IOL

All pins 80 mA

1 pin –1 mAOutput current, high IOH

All pins –15 mA

VDD = 2.7 to 5.5 V 0.7VDD VDD VVIH1 P10 to P13

0.9VDD VDD V

VDD = 2.7 to 5.5 V 0.7VDD 12 VVIH2 P50 to

P53

N-ch open

drain 0.9VDD 12 V

VDD = 2.7 to 5.5 V 0.8VDD VDD VVIH3 RESET, P00 to P03,

P20 to P26, P30 to P33 0.9VDD VDD V

VDD = 4.5 to 5.5 V VDD – 0.5 VDD V

Input voltage, high

VIH4 X1 (CL1), X2 (CL2), XT1,

XT2 VDD – 0.1 VDD V

VDD = 2.7 to 5.5 V 0 0.3VDD VVIL1 P10 to P13

00.1V

DD V

VDD = 2.7 to 5.5 V 0 0.3VDD VVIL2 P50 to P53

00.1V

DD V

VDD = 2.7 to 5.5 V 0 0.2VDD VVIL3 RESET, P00 to P03,

P20 to P26, P30 to P33 00.1V

DD V

VDD = 4.5 to 5.5 V 0 0.4 V

Input voltage, low

VIL4 X1 (CL1), X2 (CL2), XT1,

XT2 00.1V

IOH = –1 mA VDD = 4.5 to 5.5 V VDD – 1.0 VOutput voltage, high VOH

IOH = –100

DD = 1.8 to 5.5 V VDD – 0.5 V

4.5 ≤ VDD ≤ 5.5 V,

IOL = 10 mA

1.0 V

VOL1 P00 to P03, P10 to P13,

P20 to P26, P30 to P33

1.8 ≤ VDD < 4.5 V,

IOL = 400

0.5 V

4.5 ≤ VDD < 5.5 V,

IOL = 10 mA

1.0 V

Output voltage, low

VOL2 P50 to P53

1.8 ≤ VDD < 4.5 V,

IOL = 1.6 mA

0.4 V

Remarks 1. Pin names enclosed in parentheses apply when using the

PD78F9316.

2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of

port pins.

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 31

DC Characteristics (TA = –40 to +85°

°°

°C, VDD = 1.8 to 5.5 V) (2/4)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

ILIH1 P00 to P03, P10 to

P13, P20 to P26, P30

to P33, RESET

ILIH2

VIN = VDD

X1 (CL1), X2 (CL2),

XT1, XT2

Input leakage current,

high

ILIH3 VIN = 12 V P50 to P53

(N-ch open drain)

ILIL1 P00 to P03, P10 to

P13, P20 to P26, P30

to P33, RESET

–3

ILIL2 X1 (CL1), X2 (CL2),

XT1, XT2

–20

Input leakage current,

low

ILIL3

VIN = 0 V

P50 to P53

(N-ch open drain)

–3Note

Output leakage current,

high

ILOH VOUT = VDD 3

Output leakage current,

low

ILOL VOUT = 0 V –3

Software pull-up

resistor

R1VIN = 0 V P00 to P03, P10 to

P13, P20 to P26,

P30 to P33

50 100 200 kΩ

Note If P50 to P53 have been set to input mode when a read instruction is executed to read from P50 to P53, a

low-level input leakage current of up to –30

A flows during only one cycle. At all other times, the

maximum leakage current is –3

Remarks 1. Pin names enclosed in parentheses apply when using the

PD78F9316.

2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of

port pins.

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

DC Characteristics (TA = –40 to +85°

°°

°C, VDD = 1.8 to 5.5 V) (3/4)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 5.0 V ±10%Note 2 4.5 9 mA

VDD = 3.0 V ±10%Note 3 12mA

IDD1 5.0 MHz crystal oscillation

operation mode

(C1 = C2 = 22 pF)

VDD = 2.0 V ±10%Note 3 0.65 1.5 mA

VDD = 5.0 V ±10%Note 2 1.4 2 mA

VDD = 3.0 V ±10%Note 3 0.4 0.8 mA

IDD2 5.0 MHz crystal oscillation

HALT mode

(C1 = C2 = 22 pF)

VDD = 2.0 V ±10%Note 3 0.19 0.42 mA

VDD = 5.0 V ±10% 100 230

VDD = 3.0 V ±10% 70 160

IDD3 32.768 kHz crystal

oscillation operation

modeNote 4

(C3 = C4 = 22 pF,

R1 = 220 kΩ)

VDD = 2.0 V ±10% 58 120

VDD = 5.0 V ±10% 25 65

VDD = 3.0 V ±10% 7 29

LCD not

operating

VDD = 2.0 V ±10% 4 20

VDD = 5.0 V ±10% 28 70

VDD = 3.0 V ±10% 9.6 34

IDD4 32.768 kHz

crystal

oscillation

HALT

modeNote 4

(C3 = C4 =

22 pF, R1 =

220 kΩ)

LCD

operatingNote 5

VDD = 2.0 V ±10% 6 25

VDD = 5.0 V ±10% 0.1 17

VDD = 3.0 V ±10% 0.05 5.5

Power supply

currentNote 1

(Ceramic/crystal

oscillation)

IDD5 STOP modeNote 6

VDD = 2.0 V ±10% 0.05 3.5

Notes 1. The port current (including the current that flows to the on-chip pull-up resistors) is not included.

2. High-speed mode operation (when processor clock control register (PCC) is set to 00H)

3. Low-speed mode operation (when PCC is set to 02H)

4. When the main system clock is stopped

5. This is the total current that flows when the LCD controller/driver is operating (LCDON0 = 1, VAON0 =

1, LIPS0 = 1). The power supply current when the LCD is not operating (LCDON0 = 0, VAON0 = 1,

LIPS0 = 0) is included in IDD2.

6. This is the current when the LCD booster circuit is stopped (LCDON0 = 0, VAON0 = 1).

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 33

DC Characteristics (TA = –40 to +85°

°°

°C, VDD = 1.8 to 5.5 V) (4/4)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 5.0 V ±10%Note 2 69mA

VDD = 3.0 V ±10%Note 3 2.0 2.5 mA

IDD1 4.0 MHz RC oscillation

operation mode

(R = 4.7 kΩ, C = 22 pF) VDD = 2.0 V ±10%Note 3 1.2 1.6 mA

VDD = 5.0 V ±10%Note 2 2.5 3.5 mA

VDD = 3.0 V ±10%Note 3 1.5 2 mA

IDD2 4.0 MHz RC oscillation

HALT mode

(R = 4.7 kΩ, C = 22 pF) VDD = 2.0 V ±10%Note 3 0.8 1.5 mA

VDD = 5.0 V ±10% 100 230

VDD = 3.0 V ±10% 70 160

IDD3 32.768 kHz crystal

oscillation operation

modeNote 4

(C3 = C4 = 22 pF, R1 = 220

kΩ)

VDD = 2.0 V ±10% 58 120

VDD = 5.0 V ±10% 25 65

VDD = 3.0 V ±10% 7 29

LCD not

operating

VDD = 2.0 V ±10% 4 20

VDD = 5.0 V ±10% 28 70

VDD = 3.0 V ±10% 9.6 34

IDD4 32.768 kHz

crystal

oscillation

HALT

modeNote 4

(C3 = C4 =

22 pF, R1 =

220 kΩ)

LCD

operatingNote 5

VDD = 2.0 V ±10% 6 25

VDD = 5.0 V ±10% 0.1 17

VDD = 3.0 V ±10% 0.05 5.5

Power supply

currentNote 1

(RC oscillation)

IDD5 STOP modeNote 6

VDD = 2.0 V ±10% 0.05 3.5

Notes 1. The port current (including the current that flows to the on-chip pull-up resistors) is not included.

2. High-speed mode operation (when processor clock control register (PCC) is set to 00H)

3. Low-speed mode operation (when PCC is set to 02H)

4. When the main system clock is stopped

5. This is the total current that flows when the LCD controller/driver is operating (LCDON0 = 1, VAON0 =

1, LIPS0 = 1). The power supply current when the LCD is not operating (LCDON0 = 0, VAON0 = 1,

LIPS0 = 0) is included in IDD2.

6. This is the current when the LCD booster circuit is stopped (LCDON0 = 0, VAON0 = 1).

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

AC Characteristics

(1) Basic operation (TA = –40 to +85°

°°

°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 2.7 to 5.5 V 0.4 8.0

sOperating with main

system clock 1.6 8.0

Cycle time (minimum

instruction execution

time)

TCY

Operating with subsystem clock 114 122 125

VDD = 2.7 to 5.5 V 0 4 MHzTMI40 input frequency fTMI

0 275 kHz

VDD = 2.7 to 5.5 V 0.1

TMI40 input high-/low-

level width

tTIMH,

tTIML 1.8

Interrupt input high-

/low-level width

tINTH,

tINTL

INTP0 to INTP3 10

Key return input low-

level width

tKRL KR00 to KR03 10

RESET low-level width tRSL 10

CPT20 input high-/low-

level width

tCPH,

tCPL

TCY vs VDD (main system clock)

Power supply voltage VDD (V)

123456

0.1

0.4

0.5

1.0

2.0

Cycle time TCY1 [ s]

Guaranteed

operation range

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 35

(2) Serial interface 10, 20 (SIO10, SIO20) (TA = –40 to +85°

°°

°C, VDD = 1.8 to 5.5 V)

(a) 3-wire serial I/O mode (internal clock output)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 2.7 to 5.5 V 800 nsSCKn0 cycle time tKCY1

3200 ns

VDD = 2.7 to 5.5 V tKCY1/2–50 nsSCKn0 high-/low-level

width

tKH1,

tKL1 tKCY1/2–150 ns

VDD = 2.7 to 5.5 V 150 nsSIn0 setup time

(to SCKn0↑)

tSIK1

500 ns

VDD = 2.7 to 5.5 V 400 nsSIn0 hold time

(from SCKn0↑)

tKSI1

600 ns

VDD = 2.7 to 5.5 V 0 250 nsDelay time from

SCKn0↓ to SOn0

output

tKSO1 R = 1 kΩ, C = 100 pFNote

0 1000 ns

Note R and C are the load resistance and load capacitance of the SOn0 output lines.

Remark n = 1, 2

(b) 3-wire serial I/O mode (external clock input)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 2.7 to 5.5 V 800 nsSCKn0 cycle time tKCY2

3200 ns

VDD = 2.7 to 5.5 V 400 nsSCKn0 high-/low-level

width

tKH2,

tKL2 1600 ns

VDD = 2.7 to 5.5 V 100 nsSIn0 setup time

(to SCKn0↑)

tSIK2

150 ns

VDD = 2.7 to 5.5 V 400 nsSIn0 hold time

(from SCKn0↑)

tKSI2

600 ns

VDD = 2.7 to 5.5 V 0 300 nsDelay time from

SCKn0↓ to SOn0

output

tKSO2 R = 1 kΩ, C = 100 pFNote

0 1000 ns

Note R and C are the load resistance and load capacitance of the SOn0 output lines.

Remark n = 1, 2

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 2.7 to 5.5 V 78125 bpsTransfer rate

19531 bps

(d) UART mode (SIO20 only) (external clock input)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 2.7 to 5.5 V 800 nsASCK20 cycle time tKCY3

3200 ns

VDD = 2.7 to 5.5 V 400 nsASCK20 high-/low-

level width

tKH3,

tKL3 1600 ns

VDD = 2.7 to 5.5 V 39063 bpsTransfer rate

9766 bps

ASCK20 rise/fall time tR,

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 37

AC Timing Test Points (excluding X1 (CL1) and XT1 inputs)

0.8V

0.2V

Test points 0.8V

0.2V

Clock Timing

1/fCLK

tXL tXH

X1 (CL1) input VIH4 (MIN.)

VIL4 (MAX.)

1/f

XTL

XTH

XT1 input V

IH5

(MIN.)

IL5

(MAX.)

Remark fCLK: fX or fCC

TMI Timing

1/fTMI

tTIL tTIH

TMI40 input

Interrupt Input Timing

INTP0 to INTP3

INTL

INTH

Key Return Input Timing

KR00 to KR03

KRL

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

RESET Input Timing

RESET

RSL

CPT20 Input Timing

Serial Transfer Timing

3-wire serial I/O mode:

KCYm

KLm

KHm

SCKn0

SIKm

KSIm

KSOm

Input data

Output data

SIn0

SOn0

Remark n, m = 1, 2

UART mode (external clock input):

KCY3

KL3

KH3

ASCK20

CPT20

CPL

CPH

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 39

LCD Characteristics (TA = –40 to +85°

°°

°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

GAIN = 1 0.84 1.0 1.165 VLCD output voltage

variation range

VLCD2 c1 to c4 = 0.47

GAIN = 0 1.26 1.5 1.74 V

Doubler output VLCD1 c1 to c4 = 0.47

F2 V

LCD2

– 0.1

2.0 VLCD2 2.0 VLCD2 V

Tripler output VLCD0 c1 to c4 = 0.47

F3 V

LCD2

– 0.15

3.0 VLCD2 3.0 VLCD2 V

GAIN = 0 0.5 s

5.0 ≤ VDD ≤ 5.5 V 2.0 s

4.5 ≤ VDD < 5.0 V 1.0 s

Voltage boost wait timeNote 1 tVAWAIT

GAIN = 1

1.8 ≤ VDD < 4.5 V 0.5 s

LCD output voltage

differentialNote 2 (common)

VODC IO = ±5

±0.2 V

LCD output voltage

differentialNote 2 (segment)

VODS IO = ±1

±0.2 V

Notes 1. This is the wait time from when voltage boost is started (VAON0 = 1) until display is enabled

(LCDON0 = 0).

2. The voltage differential is the difference between the segment and common signal output’s actual and

ideal output voltages.

Remark c1: Capacitor connected between CAPH and CAPL

c2: Capacitor connected between VLC0 and ground

c3: Capacitor connected between VLC1 and ground

c4: Capacitor connected between VLC2 and ground

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°

°°

°C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Data retention power

supply voltage

VDDDR 1.8 5.5 V

Release signal set time tSREL 0

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

Data Retention Timing

Data retention mode

STOP mode

HALT mode

Internal reset operation

Operation mode

SREL

WAIT

STOP instruction execution

DDDR

RESET

VDD

Data retention mode

STOP mode

HALT mode

Operation mode

tSREL

tWAIT

STOP instruction execution

VDDDR

Standby release signal

(interrupt request)

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 41

Oscillation Stabilization Wait Time (TA = –40 to +85°

°°

°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Release by RESET 215/fXsOscillation stabilization wait

timeNote 1 (ceramic/crystal

oscillation)

tWAIT

Release by interrupt Note 2 s

Release by RESET 27/fCC sOscillation stabilization wait

time (RC oscillation)

tWAIT

Release by interrupt 27/fCC s

Notes 1. Use a resonator whose oscillation stabilizes within the oscillation stabilization wait time.

2. Selection of 212/fX, 215/fX, or 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation

stabilization time select register (OSTS).

Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)

2. fCC: Main system clock oscillation frequency (RC oscillation)

Flash Memory Write/Erase Characteristics (TA = 10 to 40°

°°

°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 2.7 to 5.5 V 1.0 5 MHzOperating frequency fX, fCC

1.0 1.25 MHz

RC oscillation

During fCC = 4.0 MHz

operationNote 2

9mA

Write currentNote 1

(VDD pin)

IDDW When VPP supply

voltage = VPP1

Ceramic oscillation

During fX = 5.0 MHz

operation

7mA

Write currentNote 1

(VPP pin)

IPPW When VPP supply voltage = VPP1 12 mA

RC oscillation

During fCC = 4.0 MHz

operationNote 2

9mA

Erase currentNote 1

(VDD pin)

IDDE When VPP supply

voltage = VPP1

Ceramic oscillation

During fX = 5.0 MHz

operation

7mA

Erase currentNote 1

(VPP pin)

IPPE When VPP supply voltage = VPP1 100 mA

Unit erase time ter 0.5 1 1 s

Total erase time tera 20 s

Write count Erase/write are regarded as 1 cycle 20 Times

VPP0 In normal operation 0 0.2VDD VVPP supply voltage

VPP1 During flash memory programming 9.7 10.0 10.3 V

Notes 1. The port current (including the current that flows to the on-chip pull-up resistors) is not included.

2. When an external clock is input

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

8. CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES)

(1) Characteristics curves of voltage boost stabilization time

The following shows the characteristics curves of the time from the start of voltage boost (VAON0 = 1) and

the changes in the LCD output voltage (when GAIN is set as 1 (using the 3 V display panel)).

LCD Output Voltage/Voltage Boost Time

VDD = 4.5 V

5.5

4.5

3.5

2.5

1.5

0.5

VDD = 5 V VDD = 5.5 V

0 500 1000 1500 2000

Voltage boost time [ms]

LCD output voltage [V]

2500 3000 3500 4000

VLCD0

VLCD1

VLCD2

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 43

(2) Temperature characteristics of LCD output voltage

The following shows the temperature characteristics curves of LCD output voltage.

LCD Output Voltage/Temperature (When GAIN = 1)

LCD Output Voltage/Temperature (When GAIN = 0)

LCD2

−40

0−30 −20 −10 0 10 20

Temperature [˚C]

LCD output voltage [V]

30 40 50 60 70 80

LCD1

LCD0

VLCD2

−40

0−30 −20 −10 0 10 20

Temperature [˚C]

LCD output voltage [V]

30 40 50 60 70 80

VLCD1 VLCD0

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

9. PACKAGE DRAWINGS

49 32

117

64-PIN PLASTIC QFP (14x14)

NOTE

Each lead centerline is located within 0.15 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

17.6±0.4

14.0±0.2

0.8 (T.P.)

1.0

17.6±0.4

P64GC-80-AB8-5

C 14.0±0.2

I 0.15

1.8±0.2

L0.8±0.2

F 1.0

0.10

2.55±0.1

0.1±0.1

S5°±5°

2.85 MAX.

H 0.37+0.08

−0.07

M 0.17+0.08

−0.07

detail of lead end

C D

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 45

64 117

64-PIN PLASTIC TQFP (12x12)

ITEM MILLIMETERS

G 1.125

A 14.0±0.2

C 12.0±0.2

F 1.125

14.0±0.2

B 12.0±0.2

N 0.10

Q 0.1±0.05

1.0

R3°+4°

−3°

detail of lead end

NOTE

Each lead centerline is located within 0.13 mm of

its true position (T.P.) at maximum material condition.

H0.32+0.06

−0.10

I 0.13

K 1.0±0.2

0.65 (T.P.)

L 0.5

M0.17+0.03

−0.07

P64GK-65-9ET-3

U 0.6±0.15

0.25

1.1±0.1

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

10. RECOMMENDED SOLDERING CONDITIONS

The

PD78F9306 and 78F9316 should be soldered and mounted under the following recommended conditions.

For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales

representative.

Table 10-1. Surface Mounting Type Soldering Conditions

µµ

PD78F9306GC-AB8: 64-pin plastic QFP (14 ×

××

× 14)

µµ

PD78F9316GC-AB8: 64-pin plastic QFP (14 ×

××

× 14)

Soldering Method Soldering Conditions Recommended

Condition Symbol

Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or

higher), Count: Three times or less

IR35-00-3

VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or

higher), Count: Three times or less

VP15-00-3

Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count:

Once, Preheating temperature: 120°C max. (package surface temperature)

WS60-00-1

Partial heating Pin temperature: 300°C max. Time: 3 seconds max. (per pin row) —

Caution Do not use different soldering methods together (except for partial heating).

µµ

PD78F9306GK-9ET: 64-pin plastic TQFP (12 ×

××

× 12)

µµ

PD78F9316GK-9ET: 64-pin plastic TQFP (12 ×

××

× 12)

Soldering Method Soldering Conditions Recommended

Condition Symbol

Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or

higher), Count: Two times or less, Exposure limit: 7 daysNote (after that,

prebake at 125°C for 10 hours)

IR35-107-2

VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or

higher), Count: Two times or less, Exposure limit: 7 daysNote (after that,

prebake at 125°C for 10 hours)

VP15-107-2

Partial heating Pin temperature: 300°C max. Time: 3 seconds max. (per pin row) —

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 47

APPENDIX A. DIFFERENCES BETWEEN

µµ

PD78F9306, 78F9316 AND MASK ROM VERSIONS

The

PD78F9306 and 78F9316 have flash memory in place of the internal ROM of the mask ROM versions.

Differences between the

PD78F9306 and 78F9316 and the mask ROM versions are shown in Table A-1.

Table A-1. Differences Between

µµ

PD78F9306, 78F9316 and Mask ROM Versions

Flash Memory Versions Mask ROM VersionsPart Number

Item

PD78F9306

PD78F9316

PD789304

PD789306

PD789314

PD789316

ROM 16 KB 8 KB 16 KB 8 KB 16 KB

High-speed

RAM

512 bytes

Internal

memory

LCD display

RAM

24 bytes

Main system clock Ceramic/

crystal

oscillation

Ceramic/crystal oscillation RC oscillation

IC pin Not available Available

VPP pin Available Not available

Pull-up resistors 19 (software control: 19) 23 (software control: 19, mask option control: 4)

Electrical specifications Refer to the relevant data sheet.

Caution There are differences in noise immunity and noise radiation between the flash memory and

mask ROM versions. When pre-producing an application set with the flash memory version and

then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations

for the commercial samples (not engineering samples) of the mask ROM version.

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

APPENDIX B. DEVELOPMENT TOOLS

The following development tools are available for system development using the

PD78F9306 and 78F9316.

Language Processing Software

RA78K0SNotes 1, 2, 3 Assembler package common to 78K/0S Series

CC78K0SNotes 1, 2, 3 C compiler package common to 78K/0S Series

DF789306Notes 1, 2, 3 Device file for

PD789306, 789316 Subseries

CC78K0S-LNotes 1, 2, 3 C compiler library source file common to 78K/0S Series

Flash Memory Writing Tools

Flashpro III

(Part No. FL-PR3Note 4, PG-FP3)

Flash programmer dedicated to on-chip flash memory microcontroller

FA-64GCNote 4 Flash memory writing adapter for 64-pin plastic QFP (GC-AB8 type)

FA-64GKNote 4 Flash memory writing adapter for 64-pin plastic TQFP (GK-9ET type)

Debugging Tools

IE-78K0S-NS

In-circuit emulator

This is an in-circuit emulator for debugging hardware and software of application system

using the 78K/0S Series. It supports the integrated debugger (ID78K0S-NS) and is used

with an AC adapter, emulation probe, and interface adapter for connecting the host

machine.

IE-70000-MC-PS-B

AC adapter

This is the adapter for supplying power from an AC-100 to 240 V outlet.

IE-70000-98-IF-C

Interface adapter

This adapter is needed when a PC-9800 series PC (except notebook type) is used as the

host machine for the IE-78K0S-NS (supports C bus).

IE-70000-CD-IF-A

PC card interface

This PC card and interface cable are needed when a PC-9800 series notebook-type PC is

used as the host machine for the IE-78K0S-NS (supports PCMCIA socket).

IE-70000-PC-IF-C

Interface adapter

This adapter is needed when an IBM PC/AT™ or compatible PC is used as the host

machine for the IE-78K0S-NS (supports ISA bus).

IE-70000-PCI-IF

Interface adapter

This adapter is needed when a PC that includes a PCI bus is used as the host machine for

the IE-78K0S-NS.

IE-789306-NS-EM1

Emulation board

This is an emulation board for emulating the peripheral hardware inherent to the device. It is

used with an in-circuit emulator.

NP-64GCNote 4 This is a board that is used to connect an in-circuit emulator to the target system. It is for a

64-pin plastic QFP (GC-AB8 type).

NP-64GKNote 4 This is a board that is used to connect an in-circuit emulator to the target system. It is for a

64-pin plastic TQFP (GK-9ET type).

SM78K0SNotes 1, 2 System simulator common to 78K/0S Series

ID78K0S-NSNotes 1, 2 Integrated debugger common to 78K/0S Series

DF789306Notes 1, 2 Device file for

PD789306, 789316 Subseries

Real-Time OS

MX78K0SNotes 1, 2 OS for 78K/0S Series

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS 49

Notes 1. Based on PC-9800 Series (Japanese Windows)

2. Based on IBM PC/AT compatibles (Japanese/English Windows)

3. Based on HP9000 Series 700™ (HP-UX™), SPARCstation™ (SunOS™, Solaris™), or NEWS™

(NEWS-OS™)

4. This product is manufactured by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-44-822-3813).

Remark The RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789306.

µµ

PD78F9306, 78F9316

Data Sheet U14564EJ1V0DS

APPENDIX C. RELATED DOCUMENTS

Documents Related to Devices

Document Name Document No.

PD789304, 789306, 789314, 789316 Data Sheet To be prepared

PD78F9306, 78F9316 Data Sheet This document

PD789306, 789316 Subseries User’s Manual U14800E

78K/0S Series User’s Manual Instructions U11047E

78K/0, 78K/0S Series Application Note Flash Memory Write U14458E

Documents Related to Development Tools (User’s Manuals)

Document Name Document No.

Operation U11622E

Language U11599E

RA78K0S Assembler Package

Structured Assembly Language U11623E

Operation U11816ECC78K0S C Compiler

Language U11817E

SM78K0S, SM78K0 System Simulator Ver.2.10 or

Later Windows Based

Operation U14611E

SM78K Series System Simulator Ver.2.10 or Later External Part User Open Interface

Specifications

U15006E

ID-78K0-NS, ID78K0S-NS Integrated Debugger

Ver.2.20 or Later Windows Based

Operation U14910E

IE-78K0S-NS In-circuit Emulator U13549E

IE-789306-NS-EM1 Emulation Board To be prepared

Documents Related to Embedded Software (User’s Manuals)

Document Name Document No.

78K/0S Series OS MX78K0S Fundamental U12938E