SCLS391I - APRIL 1998 - REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Typical VOLP (Output Ground Bounce) SN54LV05A . . . J OR W PACKAGE SN74LV05A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) <0.8 V at VCC = 3.3 V, TA = 25C D Typical VOHV (Output VOH Undershoot) D D D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 6A 6Y 5A 5Y 4A 4Y SN54LV05A . . . FK PACKAGE (TOP VIEW) 1Y 1A NC VCC 6A D 1A 1Y 2A 2Y 3A 3Y GND >2.3 V at VCC = 3.3 V, TA = 25C Support Mixed-Mode Voltage Operation on All Ports Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) 2A NC 2Y NC 3A description/ordering information The 'LV05A devices contain six independent inverters designed for 2-V to 5.5-V VCC operation. 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 6Y NC 5A NC 5Y 3Y GND NC 4Y 4A These devices perform the Boolean function Y = A. 4 The open-drain outputs require pullup resistors to perform correctly and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. NC - No internal connection This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TOP-SIDE MARKING Tube of 50 SN74LV05AD Reel of 2500 SN74LV05ADR SOP - NS Reel of 2000 SN74LV05ANSR 74LV05A SSOP - DB Reel of 2000 SN74LV05ADBR LV05A Tube of 90 SN74LV05APW Reel of 2000 SN74LV05APWR Reel of 250 SN74LV05APWT TVSOP - DGV Reel of 2000 SN74LV05ADGVR LV05A CDIP - J Tube of 25 SNJ54LV05AJ SNJ54LV05AJ CFP - W Tube of 150 SNJ54LV05AW SNJ54LV05AW SOIC - D -40C to 85C TSSOP - PW -55C -55 C to 125 125C C ORDERABLE PART NUMBER PACKAGE TA LV05A LV05A LCCC - FK Tube of 55 SNJ54LV05AFK SNJ54LV05AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2005, Texas Instruments Incorporated !" "#" $ "%&#" &&!" # % '()#" #!* & "%& '!%#" '!& ! !& % !+# "&!" #"#& ,#&&#"-* &" '&!". ! " "!!#&)- ")! !". % #)) '#&#!!&* POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCLS391I - APRIL 1998 - REVISED APRIL 2005 FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H L L H logic diagram (positive logic) A Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS391I - APRIL 1998 - REVISED APRIL 2005 recommended operating conditions (see Note 4) SN54LV05A VCC VIH Supply voltage High-level input voltage VIL Low-level input voltage VI VO Input voltage IOL t/v VCC = 2 V VCC = 2.3 V to 2.7 V MIN MAX 2 5.5 1.5 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MAX 2 5.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 VCC x 0.7 VCC x 0.7 VCC x 0.7 V 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 0 Output voltage UNIT V 0.5 VCC x 0.3 VCC x 0.3 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 5.5 VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Input transition rise or fall rate MIN 1.5 VCC = 2 V VCC = 2.3 V to 2.7 V Low-level output current SN74LV05A VCC x 0.3 5.5 0 V V 5.5 V 50 50 A 2 2 6 6 12 12 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 200 200 100 100 VCC = 4.5 V to 5.5 V 20 20 mA ns/V TA Operating free-air temperature -55 125 -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV05A PARAMETER VOL TEST CONDITIONS IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA II ICC VI = 5.5 V or GND VI = VCC or GND, Ioff Ci VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 VCC MIN TYP SN74LV05A MAX MIN TYP MAX 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V 0.55 0.55 UNIT V 0 to 5.5 V 1 1 A 5.5 V 20 20 A 0 5 5 A 3.3 V 2.5 2.5 pF $ "%&#" "!&" '& " ! %&#/! & !." '#! % !/!)'!"* $#&#!& ## #" !& '!%#" #&! !." .#)* !+# "&!" &!!&/! ! &. #".! & ""! !! '& , "!* POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SCLS391I - APRIL 1998 - REVISED APRIL 2005 switching characteristics over recommended operating VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF A Y CL = 50 pF tPLH tPHL MIN free-air TA = 25C TYP MAX temperature SN54LV05A range, SN74LV05A MIN MAX MIN MAX 3.6* 10.4* 1* 13* 1 13 5.8* 12.2* 1* 15* 1 15 6.1 15.2 1 18 1 18 8.1 16.6 1 19.5 1 19.5 UNIT ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF A Y CL = 50 pF tPLH tPHL MIN free-air TA = 25C TYP MAX temperature SN54LV05A range, SN74LV05A MIN MAX MIN MAX 2.9* 7.1* 1* 8.5* 1 8.5 4* 7.1* 1* 8.5* 1 8.5 4.7 10.6 1 12 1 12 5.8 10.6 1 12 1 12 UNIT ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF A Y CL = 50 pF tPLH tPHL MIN free-air TA = 25C TYP MAX temperature SN54LV05A range, SN74LV05A MIN MAX MIN MAX 2.2* 5.5* 1* 6.5* 1 6.5 2.9* 5.5* 1* 6.5* 1 6.5 3.4 7.5 1 8.5 1 8.5 4.2 7.5 1 8.5 1 8.5 UNIT ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25C (see Note 5) SN74LV05A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.55 0.8 V Quiet output, minimum dynamic VOL -0.04 -0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 3.12 High-level dynamic input voltage V 2.31 V VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. 0.97 V VCC 3.3 V TYP UNIT 5V 3 operating characteristics, TA = 25C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, $ "%&#" "!&" '& " ! %&#/! & !." '#! % !/!)'!"* $#&#!& ## #" !& '!%#" #&! !." .#)* !+# "&!" &!!&/! ! &. #".! & ""! !! '& , "!* 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 f = 10 MHz 2.5 pF SCLS391I - APRIL 1998 - REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC VCC RL = 1 k From Output Under Test 50% VCC Input Test Point 50% VCC tPHL 0V tPLH VCC CL (see Note A) 50% VCC Output VOL + 0.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES LOAD CIRCUIT FOR OPEN-DRAIN OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. C. The outputs are measured one at a time, with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) SN74LV05AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05ADGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05ADGVRE4 ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05ADGVRG4 ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 74LV05A SN74LV05ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 74LV05A SN74LV05ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 74LV05A SN74LV05APW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) SN74LV05APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05APWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A SN74LV05APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV05A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 Samples PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74LV05ADGVR TVSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DGV 14 2000 330.0 12.4 6.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 4.0 1.6 8.0 12.0 Q1 SN74LV05ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LV05ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV05APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV05APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV05ADGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74LV05ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LV05ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LV05APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LV05APWT TSSOP PW 14 250 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MPDS006C - FEBRUARY 1996 - REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0-8 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins - MO-153 14/16/20/56 Pins - MO-194 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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