NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM 200pin Two Bank Unbuffered DDR SO-DIMM Features * 64Mx64 Double Unbuffered DDR SO-DIMM based on 32Mx8 * DRAM DLL aligns DQ and DQS transitions with clock DDR SDRAM. transitions. * Performance: * Address and control signals are fully synchronous to positive PC1600 clock edge PC2100 Speed Sort - 8B - 75B - 7K DIMM CAS Latency 2 2.5 2 * Programmable Operation: Unit - DIMM CAS Latency: 2, 2.5 f CK Clock Frequency 100 133 133 MHz t CK Clock Cycle 10 7.5 7.5 ns f DQ DQ Burst Frequency 200 266 266 MHz - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write * Auto-Refresh (CBR) and Self-Refresh Modes * Intended for 100 MHz and 133 MHz applications * Automatic and controlled precharge commands * Inputs and outputs are SSTL-2 compatible * 13/10/2 Addressing (row/column/bank) * VDD = 2.5Volt 0.2, VDDQ = 2.5Volt 0.2 * 7.8 s Max. Average Periodic Refresh Interval * SDRAMs have 4 internal banks for concurrent operation * Serial Presence Detect * Module has two physical banks * Gold contacts * Differential clock inputs * SDRAMs in 60-ball CSP Package * Data is read or written on both clock edges Description NT512D64S8HAKWM is an unbuffered 200-Pin Double Data Rate (DDR) SDRAM Small-Outline memory module (SODIMM), organized as a two-bank high-speed memory array. The 64Mx64 module is a dual-bank DIMM that uses sixteen 32Mx8 DDR SDRAMs in 60-ball CSP packages. The SODIMM achieves high-speed data transfer rates of up to 266MHz. The SODIMM is intended for use in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. The SODIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The last 128 bytes are available to the customer. All NANYA 200pin DDR SODIMMs provide a high-performance, flexible 8-byte interface in a 2.66" long space-saving footprint. Ordering Information Part Number NT512D64S8HAKWM-7K NT512D64S8HAKWM-75B NT512D64S8HAKWM-8B REV 1.1 08/2002 Speed 143MHz (7ns @ CL = 2.5) Organization Leads Power 64Mx64 Gold 2.5V PC2100 133MHz (7.5ns @ CL= 2) 133MHz (7.5ns @ CL= 2.5) PC2100 100MHz (10ns @ CL = 2) 125MHz (8ns @ CL = 2.5) PC1600 100MHz (10ns @ CL = 2) 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Pin Description CK0, CK1, CK2, Differential Clock Inputs. DQ0-DQ63 CKE0, CKE1 Clock Enable DQS0-DQS7, RAS Row Address Strobe DQS9-DQS16 CAS Column Address Strobe VDD Power (2.5V) WE Write Enable VDDQ Supply voltage for DQs (2.5V) CK0, CK1, CK2 Data input/output Bidirectional data strobes S0, S1 Chip Selects VSS Ground A0-A9, A11, A12 Address Inputs NC No Connect A10/AP Address Input/Autoprecharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output VREF Ref. Voltage for SSTL_2 inputs SA0-2 Serial Presence Detect Address Inputs VDDID VDD Identification flag. VDDSPD Serial EEPROM positive power supply (2.5V) Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 2 VREF 51 VSS 52 VSS 101 A9 102 A8 151 DQ42 152 DQ46 3 VSS 4 VSS 53 DQ19 54 DQ23 103 VSS 104 VSS 153 DQ43 154 DQ47 5 DQ0 6 DQ4 55 DQ24 56 DQ28 105 A7 106 A6 155 VDD 156 VDD 7 DQ1 8 DQ5 57 VDD 58 VDD 107 A5 108 A4 157 VDD 158 CK1 9 VDD 10 VDD 59 DQ25 60 DQ29 109 A3 110 A2 159 VSS 160 CK1 11 DQS0 12 DM0 61 DQS3 62 DM3 111 A1 112 A0 161 VSS 162 VSS 13 DQ2 14 DQ6 63 VSS 64 VSS 113 VDD 114 VDD 163 DQ48 164 DQ52 15 VSS 16 VSS 65 DQ26 66 DQ30 115 A10/AP 116 BA1 165 DQ49 166 DQ53 17 DQ3 18 DQ7 67 DQ27 68 DQ31 117 BA0 118 RAS 167 VDD 168 VDD 19 DQ8 20 DQ12 69 VDD 70 VDD 119 WE 120 CAS 169 DQS6 170 DM6 21 VDD 22 VDD 71 NC 72 NC 121 S0 122 S1 171 DQ50 172 DQ54 23 DQ9 24 DQ13 73 NC 74 NC 123 DU 124 DU 173 VSS 174 VSS 25 DQS1 26 DM1 75 VSS 76 VSS 125 VSS 126 VSS 175 DQ51 176 DQ55 27 VSS 28 VSS 77 NC 78 NC 127 DQ32 128 DQ36 177 DQ56 178 DQ60 29 DQ10 30 DQ14 79 NC 80 NC 129 DQ33 130 DQ37 179 VDD 180 VDD 31 DQ11 32 DQ15 81 VDD 82 VDD 131 VDD 132 VDD 181 DQ57 182 DQ61 33 VDD 34 VDD 83 NC 84 NC 133 DQS4 134 DM4 183 DQS7 184 DM7 35 CK0 36 VDD 85 DU 86 DU 135 DQ34 136 DQ38 185 VSS 186 VSS 37 CK0 38 VSS 87 VSS 88 VSS 137 VSS 138 VSS 187 DQ58 188 DQ62 39 VSS 40 VSS 89 CK2 90 VSS 139 DQ35 140 DQ39 189 DQ59 190 DQ63 41 DQ16 42 DQ20 91 CK2 92 VDD 141 DQ40 142 DQ44 191 VDD 192 VDD 43 DQ17 44 DQ21 93 VDD 94 VDD 143 VDD 144 VDD 193 SDA 194 SA0 45 VDD 46 VDD 95 CKE1 96 CKE0 145 DQ41 146 DQ45 195 SCL 196 SA1 47 DQS2 48 DM2 97 DU 98 DU 147 DQS5 148 DM5 197 VDDSPD 198 SA2 49 DQ18 50 DQ22 99 A12 100 A11 149 VSS 150 VSS 199 VDDID 200 DU Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV 1.1 08/2002 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Input/Output Functional Description Symbol Type CK0, CK1, CK2 (SSTL) CK0, CK1, CK2 (SSTL) CKE0, CKE1 (SSTL) Positive Edge The positive line of the differential pair of system clock inputs which drives the input to the on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising edge of their associated clocks. Negative The negative line of the differential pair of system clock inputs which drives the input to the Edge Active High (SSTL) Active Low RAS, CAS, WE (SSTL) Active Low VREF Supply VDDQ Supply BA0, BA1 (SSTL) S0, S1 Function Polarity on-DIMM PLL. Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self-Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) A0 - A9 A10/AP A11, A12 when sampled at the rising clock edge. In addition to the column address, AP is used to (SSTL) - invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63, (SSTL) - DQS0 - DQS7, DQS9 - DQS16 (SSTL) Active High VDD, VSS Supply - SDA - SCL - REV 1.1 08/2002 Supply DRAMs. Data strobes: Output with read data, input with write data. Edge aligned with read data, centered on write data. Used to capture write data. Power and ground for the DDR SDRAM input buffers and core logic SA0 - SA2 VDDSPD Data and Check Bit input/output pins operate in the same manner as on conventional Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pullup. Serial EEPROM positive power supply. 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Functional Block Diagram (2 Bank, 32Mx8 DDR SDRAMs) S1 S0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS4 DM4 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D0 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D8 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D1 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D9 BA0-BA1 A0-A12 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D2 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS D3 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D10 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D11 BA0-BA1 : SDRAMs D0-D15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D5 DQS D6 RAS : SDRAMs D0-D15 CKE0 CKE : SDRAMs D0-D7 CKE1 CKE : SDRAMs D8-D15 DQS D7 VDDSPD VDD/VDDQ VREF VSS VDDID A0-A12 : SDRAMs D0-D15 CAS : SDRAMs D0-D15 REV 1.1 08/2002 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 RAS Notes : 1. 2. 3. 4. CS D4 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D12 DQS D13 DQS D14 DQS7 DM7 CAS WE DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS DQS6 DM6 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS DQS5 DM5 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS D15 SPD D0-D15 D0-D15 D0-D15 Strap: see Note 4 Serial PD SCL WP WE : SDRAMs D0-D15 DQ-to-I/O wring may be changed within a byte. DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22 Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. CK CK PLL A0 A1 A2 SA0 SA1 SA2 SDA DDR SDRAM: D0, D1, D8, D9 DDR SDRAM: D2, D3, D10, D11 DDR SDRAM: D4, D5, D12, D13 DDR SDRAM: D6, D7, D14, D15 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Serial Presence Detect -- Part 1 of 2 SPD Entry Value Byte Description DDR266A DDR266B -7K 0 -75B Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 Serial PD Data Entry (Hexadecimal) Note DDR200 -8B DDR266A DDR266B -7K -75B 128 80 256 08 SDRAM DDR 07 Number of Row Addresses on Assembly 13 0D 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Bank 2 02 6 Data Width of Assembly X64 40 7 Data Width of Assembly (cont') 8 Voltage Interface Level of this Assembly 9 10 DDR SDRAM Device Cycle Time at CL=2.5 DDR SDRAM Device Access Time from Clock at CL=2.5 11 DIMM Configuration Type 12 Refresh Rate/Type 04 7ns 7.5ns 8ns 70 75 80 0.75ns 0.75ns 0.8ns 75 75 80 Non-Parity 00 SR/1x(7.8us) 82 Primary DDR SDRAM Width X8 08 14 Error Checking DDR SDRAM Device Width N/A 00 1 Clock 01 2,4,8 0E 4 04 16 17 18 DDR SDRAM Device Attr: Min CLk Delay, Random Col Access DDR SDRAM Device Attributes: Burst Length Supported DDR SDRAM Device Attributes: Number of Device Banks DDR SDRAM Device Attributes: CAS Latencies Supported 2/2.5 2/2.5 2/2.5 0C 0C 19 DDR SDRAM Device Attributes: CS Latency 0 01 20 DDR SDRAM Device Attributes: WE Latency 1 02 Differential Clock 20 21 DDR SDRAM Device Attributes: 22 DDR SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=2 24 25 26 27 28 Maximum Data Access Time from Clock at CL=2 +/-0.2V Voltage Tolerance 10ns 75 A0 A0 0.75ns 0.75ns 0.8ns 75 75 80 CL=1 (tRRD) 00 10ns Minimum Clock Cycle Time at CL=1 Minimum Row Precharge Time (tRP) 0C 7.5ns Maximum Data Access Time from Clock at Minimum Row Active to Row Active delay -8B 00 SSTL 2.5V 13 15 DDR200 N/A 00 N/A 00 20ns 20ns 20ns 50 50 50 15ns 15ns 15ns 3C 3C 3C 29 Minimum RAS to CAS delay (tRCD) 20ns 20ns 20ns 50 50 50 30 Minimum RAS Pulse Width (tRAS) 45ns 45ns 50ns 2D 2D 32 31 Module Bank Density 32 33 Address and Command Setup Time Before Clock Address and Command Hold Time After Clock 256MB 40 0.9ns 0.9ns 1.1ns 90 90 B0 0.9ns 0.9ns 1.1ns 90 90 B0 34 Data Input Setup Time Before Clock 0.5ns 0.5ns 0.6ns 50 50 60 35 Data Input Hold Time After Clock 0.5ns 0.5ns 0.6ns 50 50 60 Initial 00 00 00 90 C0 46 36-61 Reserved 62 SPD Revision 63 Checksum Data REV 1.1 08/2002 Undefined Initial Initial 00 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Serial Presence Detect -- Part 2 of 2 SPD Entry Value Byte Description DDR266A DDR266B -7K 64-71 Manufacturer's JEDEC ID Code 72 Module Manufacturing Location 73-90 Module Part number 91-92 Module Revision Code 93-94 Module Manufacturing Data 95-98 Module Serial Number 99-255 Reserved -75B DDR266A DDR266B -7K N/A 00 00 00 Year/Week Code yy/ww Serial Number 00 Undefined 00 ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex) Note -8B 00 N/A N/A 2. DDR200 -75B 7F7F7F0B00000000 N/A N/A yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex) 08/2002 -8B NANYA 1. REV 1.1 Serial PD Data Entry (Hexadecimal) DDR200 00 1, 2 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Absolute Maximum Ratings Symbol VIN, VOUT Voltage on I/O pins relative to Vss Rating Units -0.5 to VDDQ+0.5 V VIN Voltage on Input relative to Vss -0.5 to +3.6 V VDD Voltage on VDD supply relative to Vss -0.5 to +3.6 V Voltage on VDDQ supply relative to Vss -0.5 to +3.6 V 0 to+70 C VDDQ TA TSTG PD IOUT Note: Parameter Operating Temperature (Ambient) Storage Temperature (Plastic) -55 to +150 C Power Dissipation 16 W Short Circuit Output Current 50 mA Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance Parameter Max Units Notes CI1 24 pF 1 CI2 60 pF 1 Input Capacitance: CKE0, CKE1, S0, S1 CI5 30 pF 1 Input Capacitance: SA0-SA2, SCL CI4 9 pF 1 CIO1 14 pF 1 Input/Output Capacitance: SDA CIO3 11 1. VDDQ = VDD = 2.5V 0.2V, f = 100 MHz, TA = 25 C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V. pF 1, 2 Input Capacitance: CK0, CK0, CK1, CK1, CK2, CK2 Input Capacitance: A0-A12, BA0, BA1, WE, RAS, CAS Symbol Input/Output Capacitance: DQ0-63; DQS0-7, DM0-7 2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level. REV 1.1 08/2002 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM DC Electrical Characteristics and Operating Conditions (TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol VDD VDDQ VSS, VSSQ Parameter Min Max Units Notes Supply Voltage 2.3 2.7 V 1 I/O Supply Voltage 2.3 2.7 V 1 0 0 V Supply Voltage, I/O Supply Voltage /O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 1, 3 VIH (DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF- 0.15 V 1 VIN (DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3 V 1 VID (DC) Input Differential Voltage, CK and CK Inputs 0.30 V DDQ + 0.6 V 1, 4 -5 5 uA 1 -5 5 uA 1 -16.8 - mA 1 16.8 - mA 1 VREF VTT II IOZ IOH IOL Input Leakage Current Any input 0V VIN VDD; (All other pins not under test = 0V) Output Leakage Current (DQs are disabled; 0V Vout VDDQ Output High Current (VOUT = VDDQ -0.373V, min VREF, min VTT) Output Low Current (VOUT = 0.373, max VREF, max VTT) 1. Inputs are not recognized as valid until V REF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of V REF . 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. REV 1.1 08/2002 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and I DD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. AC Output Load Circuits VTT 50 ohms Output Timing Reference Point VOUT 30 pF AC Operating Conditions (TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol Parameter/Condition Min VIH (AC) Input High (Logic 1) Voltage. VIL (AC) Input Low (Logic 0) Voltage. VID (AC) Input Differential Voltage, CK and CK Inputs VIX (AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs Max Unit Notes V 1, 2 V REF - 0.31 V 1, 2 0.62 V DDQ + 0.6 V 1, 2, 3 (0.5*VDDQ) - 0.2 (0.5*VDDQ) + 0.2 V 1, 2, 4 V REF + 0.31 1. Input slew rate = 1V/ ns. 2. Inputs are not recognized as valid until VREF stabilizes. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. REV 1.1 08/2002 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Operating, Standby, and Refresh Currents (TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol Parameter/Condition PC1600 PC2100 Unit Notes 1024 1160 mA 1, 2 1760 1920 mA 1, 2 400 400 mA 1, 2 480 560 mA 1, 2 400 400 mA 1, 2 800 960 mA 1, 2 1418 1800 mA 1, 2 1288 1680 mA 1, 2 t RC = t RFC (MIN) 2256 2400 mA 1, 2 t RC = 7.8 s 264 264 mA 1, 2, 4 48 48 mA 1-3 4000 4800 mA 1 Operating Current : one bank; active / precharge; tRC = tRC (MIN) ; I DD0 tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current : one bank; active / read / precharge; Burst = 2; I DD1 tRC = tRC (MIN) ; CL=2.5; tCK = tCK (MIN) ; IOUT = 0mA; address and control inputs changing once per clock cycle I DD2P I DD2N I DD3P Precharge Power-Down Standby Current : all banks idle; power-down mode; CKE VIL (MAX) ; tCK = tCK (MIN) Idle Standby Current : CS VIH (MIN) ; all banks idle; CKE VIH(MIN) ; tCK = tCK (MIN) ; address and control inputs changing once per clock cycle Active Power-Down Standby Current : one bank active; power-down mode; CKE VIL (MAX) ; tCK = tCK (MIN) Active Standby Current : one bank; active / precharge; CS VIH (MIN) ; I DD3N CKE VIH (MIN) ; tRC = tRAS (MAX) ; tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current : one bank; Burst = 2; reads; continuous burst; I DD4R address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN) ; IOUT = 0mA Operating Current : one bank; Burst = 2; writes; continuous burst; I DD4W address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) I DD5 Auto-Refresh Current : I DD6 Self-Refresh Current : CKE 0.2V I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1. I DD specifications are tested after the device is properly initialized. 2. Input slew rate = 1V/ ns. 3. Enables on-chip refresh and address counters. 4. Current at 7.8 s is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 s. REV 1.1 08/2002 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module (TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) (Part 1 of 2) Symbol -7K Parameter -75B -8B Unit Notes +0.8 ns 1-4 +0.8 ns 1-4 0.45 0.55 tCK 1-4 0.55 0.45 0.55 tCK 1-4 7.5 12 8 12 ns 1-4 10 12 10 12 ns Min. Max. Min. Max. Min. Max. DQ output access time from CK/CK -0.75 +0.75 -0.75 +0.75 -0.8 DQS output access time from CK/CK -0.75 +0.75 -0.75 +0.75 -0.8 tCH CK high-level width 0.45 0.55 0.45 0.55 tCL CK low-level width 0.45 0.55 0.45 CL=2.5 7 12 CL=2 7.5 12 tAC tDQSCK tCK tCK Clock cycle time tDH DQ and DM input hold time 0.5 0.5 0.6 ns tDS DQ and DM input setup time 0.5 0.5 0.6 ns 1-4, 15, 16 DQ and DM input pulse width (each input) 1.75 ns 1-4 tHZ Data-out high-impedance time from CK/CK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 1-5 tLZ Data-out low-impedance time from CK/CK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 1-5 tDQSQA tHP tQH tDQSS tDQSL,H tDSS tDSH tMRD tWPRES DQS-DQ skew (DQS & associated DQ signals) DQS-DQ skew (DQS & all DQ signals) 1-4 0.5 0.5 0.6 ns 1-4 tCK 1-4 tCK 1-4 tCK 1-4 tCH or or or clk low (tCL) time tCL tCL tCL Data output hold time from DQS Write command to 1st DQS latching transition DQS input low (high) pulse width tCH tHP - tHP - tHP - 0.75ns 0.75ns 1.0ns 0.75 1.25 0.75 1.25 0.75 1.25 0.35 0.35 0.35 tCK 1-4 0.2 0.2 0.2 tCK 1-4 0.2 0.2 0.2 tCK 1-4 Mode register set command cycle time 14 15 16 ns 1-4 Write preamble setup time 0 0 0 ns 1-4, 7 tCK 1-4, 6 (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) 0.40 0.25 08/2002 ns or Write preamble REV 1.1 0.6 tCH Write postamble tIH 0.5 cycle; defined by clk high (tCH) tWPST tIS 0.5 Minimum half clk period for any given tWPRE tIH 2 15, 16 tDIPW tDQSQ 1.75 1-4 1-4, Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) 0.60 0.40 0.25 0.9 1.1 0.60 0.40 0.25 1.1 0.60 tCK ns 0.9 1.1 1.1 ns 1.0 1.1 1.1 ns 1-4 2-4, 9, 11, 12 2-4, 9, 11, 12 2-4, 10-12, 14 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module (TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) (Part 2 of 2) Symbol tIS Parameter Address and control input setup time (slow slewrate) -7K Min. -75B Max. Min. -8B Max. Min. Unit Notes ns 10-12, - ns 2-4, 12 Max. 2-4, 1.0 1.0 1.1 14 tIPW Input pulse width 2.2 tRPRE Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 tCK 1-4 tRPST Read postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK 1-4 tRAS Active to Precharge command 45 120,000 45 120,000 50 120,000 ns 1-4 tRC tRFC tRCD tRAP tRP tRRD tWR tDAL tWTR tXARD tXSNR Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Active to Read Command with Autoprecharge Precharge command period Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Power down exit time Exit self-refresh to non-read command tXSRD Exit self-refresh to read command tREFI Average Periodic Refresh Interval REV 1.1 08/2002 2.2 65 65 70 ns 1-4 75 75 80 ns 1-4 20 20 20 ns 1-4 20 20 20 ns 1-4 20 20 20 ns 1-4 15 15 15 ns 1-4 15 15 15 ns 1-4 (tWR/tCK) (tWR/tCK) (tWR/tCK) + + + tCK 1-4, 13 (tRP/tCK) (tRP/tCK) (tRP/tCK) 1 1 1 tCK 1-4 7.5 7.5 8 ns 1-4 75 75 80 ns 1-4 200 200 200 tCK 1-4 s 1-4, 8 7.8 7.8 7.8 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM AC Timing Specification Notes 1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. 8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 11. CK/CK slew rates are >= 1.0 V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns. Input Slew Rate Delta (tIS) Delta (tIH) Unit Note 0.5 V/ns 0 0 ps 1, 2 0.4 V/ns +50 0 ps 1, 2 0.3 V/ns +100 0 ps 1, 2 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns. Input Slew Rate Delta (tDS) Delta (tDH) Unit Note 0.5 V/ns 0 0 ps 1, 2 0.4 V/ns +75 +75 ps 1, 2 0.3 V/ns +150 +150 ps 1, 2 1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ. Delta Rise and Fall Rate Delta (tDS) Delta (tDH) Unit Note 0.0 ns/V 0 0 ps 1-4 0.25 ns/V +50 +50 ps 1-4 0.5 ns/V +100 +100 ps 1-4 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. 3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in t DS and t DH of 100 ps. 4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. REV 1.1 08/2002 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Package Dimensions FRONT 67.60 (2X) 1.80 2.15 1 39 41 11.40 31.75 20.00 6.00 4.00 63.60 199 Detail A Detail B 4.20 47.40 1.80 2.45 BACK SIDE 3.80 MAX 1.00+/- 0.10 Detail A 0.45 0.60 1.00+/- 0.1 2.55 4.00+/-0.10 0.25 MAX Detail B Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. Units: Millimeters (Inches) REV 1.1 08/2002 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512D64S8HAKWM 512MB : 64M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Revision Log Rev Date 1.0 06/2002 1.1 08/2002 Modification Official Release Fixed typo in Ordering Information Added tXARD (Power down exit time) to AC Timing Table Added tolerance specification of +/- 0.15 to Package Dimensions REV 1.1 08/2002 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.