Integrated
Circuit
Systems, Inc.
ICS932S801
0959C—03/13/06
Functionality
Pin Configuration
Recommended Application:
Serverworks GC-HT systems using AMD K8 processors
Output Features:
• 4 - Pairs of AMD K8 clocks
• 1 - Pair of SRC/PCI Express* clock
• 2 - 14.318 MHz REF clocks
• 2 - USB_48MHz clocks
• 4 - HyperTransport 66 MHz clocks
• 4 - PCI 33 MHz clocks
Features:
• Spread Spectrum for EMI reduction
• Outputs may be disabled via SMBus
• M/N programming via SMBus
K8 Clock Chip for Serverworks GC-HT 2-Way Servers
Power Groups
*Other names and brands may be claimed as the property of others.
VDD GND
3 6 48MHz
9 14 66MHz HTT Clocks
15 20 33 MHz PCI Clocks
22 23 IREF, Analo
g
Core
27 28 SRC PLL, SRCCLK
33,37,41 32,36,40 K8 CPU Clocks, CPU PLL
48 44 REF Clocks, Xtal Oscillator
Pin Number Description CPU HTT PCI
MHz MHz MHz
0 0 0 Hi-Z Hi-Z Hi-Z
001 X X/3 X/6
0 1 0 180.00 60.00 30.00
0 1 1 220.00 73.12 36.56
1 0 0 100.00 66.66 33.33
1 0 1 133.33 66.66 33.33
1 1 0 166.67 66.66 33.33
1 1 1 200.00 66.66 33.33
FS0FS2 FS1
X1 148VDDREF
X2 247FS0/REF0
VDD48 346FS1/REF1
48MHz_0 445FS2
48MHz_1 544GND
GND 643CPUCLK8T0
SCLK 742CPUCLK8C0
SDATA 841VDDCPU
VDDHTT 940GNDCPU
HTTCLK0 10 39 CPUCLK8T1
HTTCLK1 11 38 CPUCLK8C1
HTTCLK2 12 37 VDDCPU
HTTCLK3 13 36 GNDCPU
GNDHTT 14 35 CPUCLK8T2
VDDPCI 15 34 CPUCLK8C2
PCICLK0 16 33 VDDCPU
PCICLK1 17 32 GNDCPU
PCICLK2 18 31 CPUCLK8T3
PCICLK3 19 30 CPUCLK8C3
GNDPCI 20 29 SPREAD_EN
PD# 21 28 GNDSRC
VDDA 22 27 VDDSRC
GNDA 23 26 SRCCLKT0
IREF 24 25 SRCCLKC0
48-SSOP, TSSOP
ICS932S801
2
ICS932S801
0959C—03/13/06
Pin Descriptions
PIN # PIN NAME PIN TYPE DESCRIPTION
1X1 IN Crystal input, Nominally 14.318MHz.
2 X2 OUT Cr
y
stal output, Nominall
y
14.318MHz
3 VDD48 PWR Power pin for the 48MHz output.3.3V
4 48MHz_0 OUT 48MHz clock output.
5 48MHz_1 OUT 48MHz clock output.
6 GND PWR Ground pin.
7 SCLK I/O Clock pin of SMBus circuitry, 5V tolerant.
8 SDATA I/O Data pin for SMBus circuitr
y
, 5V tolerant.
9 VDDHTT PWR Supply for HTT clocks, nominal 3.3V.
10 HTTCLK0 OUT 3.3V H
y
per Transport output
11 HTTCLK1 OUT 3.3V Hyper Transport output
12 HTTCLK2 OUT 3.3V H
y
per Transport output
13 HTTCLK3 OUT 3.3V Hyper Transport output
14 GNDHTT PWR Ground pin for the HTT outputs
15 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V
16 PCICLK0 OUT PCI clock output.
17 PCICLK1 OUT PCI clock output.
18 PCICLK2 OUT PCI clock output.
19 PCICLK3 OUT PCI clock output.
20 GNDPCI PWR Ground pin for the PCI outputs
21 PD# IN Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the cr
y
stal are stopped.
22 VDDA PWR 3.3V power for the PLL core.
23 GNDA OUT Ground pin for the PLL core.
24 IREF OUT
This pin establishes the reference current for the differential current-mode output
pairs. This pin requires a fixed precision resistor tied to ground in order to establish
the appropriate current. 475 ohms is the standard value.
25 SRCCLKC0 OUT Complement clock of differential SRC clock pair.
26 SRCCLKT0 OUT True clock of differential SRC clock pair.
27 VDDSRC PWR Suppl
y
for SRC clocks, 3.3V nominal
28 GNDSRC PWR Ground pin for the SRC outputs
29 SPREAD_EN IN As
y
nchronous, active hi
g
h input to enable spread spectrum functionalit
y
.
30 CPUCLK8C3 OUT Complementary clock of differential 3.3V push-pull K8 pair.
31 CPUCLK8T3 OUT True clock of differential 3.3V push-pull K8 pair.
32 GNDCPU PWR Ground pin for the CPU outputs
33 VDDCPU PWR Suppl
y
for CPU clocks, 3.3V nominal
34 CPUCLK8C2 OUT Complementary clock of differential 3.3V push-pull K8 pair.
35 CPUCLK8T2 OUT True clock of differential 3.3V push-pull K8 pair.
36 GNDCPU PWR Ground pin for the CPU outputs
37 VDDCPU PWR Suppl
y
for CPU clocks, 3.3V nominal
38 CPUCLK8C1 OUT Complementary clock of differential 3.3V push-pull K8 pair.
39 CPUCLK8T1 OUT True clock of differential 3.3V push-pull K8 pair.
40 GNDCPU PWR Ground pin for the CPU outputs
41 VDDCPU PWR Suppl
y
for CPU clocks, 3.3V nominal
42 CPUCLK8C0 OUT Complementary clock of differential 3.3V push-pull K8 pair.
43 CPUCLK8T0 OUT True clock of differential 3.3V push-pull K8 pair.
44 GND PWR Ground pin.
45 FS2 IN Frequenc
y
select pin.
46 FS1/REF1 I/O Frequency select latch input pin / 14.318 MHz reference clock.
47 FS0/REF0 I/O Frequenc
y
select latch input pin / 14.318 MHz reference clock.
48 VDDREF PWR Ref, XTAL power supply, nominal 3.3V
3
ICS932S801
0959C—03/13/06
General Description
The ICS932S801 is a main clock synthesizer chip that, when paired with ICS9DB108, provides all clocks required by
Serverworks GC-HT-based servers.
An SMBus interface allows full control of the device.
Block Diagram
IREF
CPU PLL
PCICLK(3:0)
CONTROL
LOGIC
XTAL
OSC.
CPUCLK8(3:0)
FIXED PLL 48MHz(1:0)
REF(1:0)
HTTCLK(3:0)
X1
X2
PCI33
DIV
HTT66
DIV
SRC PLL
CPU
DIV
SDATA
SCLK
FS(2:0)
SPREAD
SRC
DIV1 SRCCLK(0)
PD#
Skew Characteristics
Parameter Description Test Conditions Skew
Window Unit
Tsk_CPU_CPU CPU to CPU Skew Measured at crossing points
of CPUCLKT rising edges 250 ps
Tsk_CPU_PCI CPU to PCI skew
Meastured at crossing point
for CPUCLKT and 1.5V for
PCI clock
2000 ps
Tsk_PCI33-HT66 PCI33 to HT66 skew Measured between rising
edges at 1.5V 500 ps
Tsk_CPU_HT66 CPU to HT66 skew
Meastured at crossing point
for CPUCLKT and 1.5V for
HT66 clock
2000 ps
Tsk_CPU_CPU CPU to CPU Skew Measured at crossing points
of CPUCLKT rising edges 200 ps
Tsk_CPU_PCI CPU to PCI skew
Meastured at crossing point
for CPUCLKT and 1.5V for
PCI clock
200 ps
Tsk_PCI33-HT66 PCI33 to HT66 skew Measured between rising
edges at 1.5V 200 ps
Tsk_CPU_HT66 CPU to HT66 skew
Meastured at crossing point
for CPUCLKT and 1.5V for
HT66 clock
200 ps
T
i
m
e
V
a
r
i
a
n
t
T
i
m
e
I
n
d
e
p
e
n
e
n
t
4
ICS932S801
0959C—03/13/06
0 0 100.00
0 1 101.00
1 0 102.00
1 1 104.00
SRCFS1
B5b3
SRCFS0
B5b2
SRCCLK
(MHz)
Table1: SRC Frequency Selection Table
Table 2: CPU Divider Ratios
Bit 00 01 10 11 MSB
00 0000 20100 41000 81100 16
01 0001 30101 61001 12 1101 24
10 0010 50110 10 1010 20 1110 40
11 0011 15 0111 30 1011 60 1111 120
LSB Address Div Address Div Address Div Address Div
Divider (3:2)
Divider (1:0)
Table 3: HTT Divider Ratios
Bit 00 01 10 11 MSB
00 0000 40100 81000 16 1100 32
01 0001 30101 61001 12 1101 24
10 0010 50110 10 1010 20 1110 40
11 0011 15 0111 30 1011 60 1111 120
LSB Address Div Address Div Address Div Address Div
Divider (1:0)
Divider (3:2)
Table 4: SRC Divider Ratios
Bit 00 01 10 11 MSB
00 0000 20100 41000 81100 16
01 0001 30101 61001 12 1101 24
10 0010 50110 10 1010 20 1110 40
11 0011 70111 14 1011 28 1111 56
LSB Address Div Address Div Address Div Address Div
Divider (1:0)
Divider (3:2)
5
ICS932S801
0959C—03/13/06
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 3.8V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +3.8 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V1
Input Low Voltage VIL 3.3 V +/-5% VSS - 0.3 0.8 V 1
Input High Current IIH VIN = VDD -5 5 uA 1
IIL1
VIN = 0 V; Inputs with no pull-up
resistors -5 uA 1
IIL2 VIN = 0 V; Inputs with pull-up resistors -200 uA 1
Operating Current IDD3.3OP all outputs driven 325 mA
Powerdown Current IDD3.3PD 100 mA
In
ut Fre
uenc
3FiVDD = 3.3 V 14.31818 MHz 3
Pin Inductance1Lpin 7nH1
CIN Logic Inputs 5 pF 1
COUT Output pin capacitance 6 pF 1
CINX X1 & X2 pins 5 pF 1
Clk Stabilization1,2 TSTAB
From VDD Power-Up or de-assertion of
PD# to 1st clock 3ms1,2
Modulation Fre
q
uenc
y
Trian
g
ular Modulation 30 33 kHz 1
SMBus Voltage VDD 2.7 5.5 V 1
Low-level Output Voltage VOL @ IPULLUP 0.4 V 1
Current sinking at VOL = 0.4 V IPULLUP 4mA1
SCLK/SDATA
Clock/Data Rise Time3TRI2C (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA
Clock/Data Fall Time3TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
1Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
2See timin
g
dia
g
rams for timin
g
re
q
uirements.
3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
Input Low Current
Input Capacitance1
6
ICS932S801
0959C—03/13/06
Electrical Characteristics - K8 Push Pull Differential Pair
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=AMD64 Processor Test Load
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Rising Edge Rate δV/δt210V/ns1
Falling Edge Rate δV/δt210V/ns1
Differential Voltage V
DIFF
0.4 1.25 2.3 V 1
Change in V
DIFF_DC
Ma
g
nitude ∆V
DIFF
-150 150 mV 1
Common Mode Voltage V
CM
1.05 1.25 1.45 V 1
Chan
g
e in Common
Mode Volta
g
e∆V
CM
-200 200 mV 1
Jitter, Cycle to cycle t
jcyc-cyc
Measurement from differential
wavefrom. Maximum difference of cycle
time between 2 adjacent cycles.
0 100 200 ps 1
Jitter, Accumulated t
ja
Measured usin
g
the JIT2 software
package with a Tek 7404 scope.
TIE (Time Interval Error) measurement
technique:
Sample resolution = 50 ps,
Sam
p
le Duration = 10
µ
s
-1000 1000 1,2,3
Duty Cycle d
t3
Measurement from differential
wavefrom 45 53 % 1
Output Impedance R
ON
Avera
g
e value durin
g
switchin
g
transition. Used for determining series
termination value.
15 35 55 Ω1
Group Skew t
src-skew
Measurement from differential
wavefrom 250 ps 1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
2
All accumulated
j
itter s
p
ecifications are
g
uaranteed assumin
g
that REF is at 14.31818MHz
3
S
p
read S
p
ectrum is off
Measured at the AMD64 processor's
test load. 0 V +/- 400 mV (differential
measurement)
Measured at the AMD64 processor's
test load. (single-ended measurement)
7
ICS932S801
0959C—03/13/06
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2Ω, R
P
=49.9Ω, Ι
REF
= 475Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output
Im
p
edance Zo V
O
= V
x
3000 Ω1
Voltage High VHigh 660 850 1,3
Voltage Low VLow -150 150 1,3
Max Volta
g
e Vovs 1150 1
Min Volta
g
e Vuds -300 1
Crossing Voltage (abs) Vcross(abs) 250 350 550 mV 1
Crossing Voltage (var) d-Vcross Variation of crossing over all
ed
g
es 12 140 mV 1
Lon
g
Accurac
y
pp
msee T
p
eriod min-max values -300 300
pp
m1,2
100.00 MHz nominal 9.9970 10.0000 10.0030 ns 2
100.00 MHz s
p
read 9.9970 10.0530 ns 2
Absolute min
p
eriod Tabsmin @100.00MHz nominal/s
p
read 9.8720 ns 1,2
Rise Time t
r
V
OL
= 0.175V, V
OH
= 0.525V 175 700 ps 1
Fall Time t
f
V
OH
= 0.525V V
OL
= 0.175V 175 700 ps 1
Rise Time Variation d-t
r
30 125 ps 1
Fall Time Variation d-t
f
30 125 ps 1
Duty Cycle d
t3
Measurement from differential
wavefrom 45 55 % 1
Group Skew t
src-skew
Measurement from differential
wavefrom N/A ps
PCI Express Gen 1 phase jitter
CPU=200MHz, S
p
read off 38 86 ps 1, 4
PCI Express Gen 1 phase jitter
CPU=200MHz, S
p
read on 52 86 ps 1, 4
Jitter, Cycle to cycle t
jcyc-cyc
Measurement from differential
wavefrom 100 ps 1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
2
All Lon
g
Term Accurac
y
and Clock Period s
p
ecifications are
g
uaranteed assumin
g
that REF is at 14.31818MHz
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475Ω (1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50Ω.
4
Per PCI SIG method for PCI Ex
p
ress Gen 1. Visit htt
p
://www.
p
cisi
g
.com for details.
mV
Measurement on single ended
signal using absolute value. mV
Statistical measurement on
single ended signal using
oscilloscope math function.
Jitter, Phase t
jphase-pcie1
TperiodAverag e per i od
8
ICS932S801
0959C—03/13/06
Electrical Characteristics - PCICLK 33 MHz, HTTCLK 66 MHz Clocks
T
A
= 0 - 70°C; VDD=3.3V +/-5%; C
L
= 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Lon
g
Accurac
y
pp
m see T
p
eriod min-max values -300 300
pp
m1,2
33.33MHz out
p
ut nominal 29.9910 30.0090 ns 2
33.33MHz out
p
ut s
p
read 29.9910 30.1598 ns 2
66.67MHz out
p
ut nominal 14.9955 15.0045 ns 2
66.67MHz out
p
ut s
p
read 14.9955 15.0799 ns 2
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.55 V 1
V
OH
@MIN = 1.0 V -33 mA 1
V
OH
@ MAX = 3.135 V -33 mA 1
V
OL
@ MIN = 1.95 V 30 mA 1
V
OL
@ MAX = 0.4 V 38 mA 1
Edge Rate δV/δtRising edge rate 1 4 V/ns 1
Ed
g
e Rate δV/δtFallin
g
ed
g
e rate 1 4 V/ns 1
Duty Cycle d
t1
V
T
= 1.5 V 45 55 % 1
Skew t
sk1
V
T
= 1.5 V 200 ps 1
Jitter, Cycle to cycle t
jcyc-cyc
V
T
= 1.5 V 250 ps 1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 14.31818MHz
Output High Current I
OH
Output Low Current I
OL
PCI33 Clock period T
period
HTT66 Clock period T
period
Electrical Characteristics - 48MHz
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
= 20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Lon
g
Accurac
y
pp
m see T
p
eriod min-max values -100 100
pp
m1,2
Clock
p
eriod T
p
eriod
48.00MHz out
p
ut nominal 20.8257 20.8340 ns 2
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.55 V 1
V
OH
@ MIN = 1.0 V -33 mA 1
V
OH
@ MAX = 3.135 V -33 mA 1
V
OL
@MIN = 1.95 V 30 mA 1
V
OL
@ MAX = 0.4 V 38 mA 1
Ed
g
e Rate δV/δtRisin
g
ed
g
e rate 1 4 V/ns 1
Edge Rate δV/δtFalling edge rate 1 4 V/ns 1
Duty Cycle d
t1
V
T
= 1.5 V 45 55 % 1
Skew t
sk1
V
T
= 1.5 V 50 ps 1
Jitter, Cycle to cycle t
jcyc-cyc
V
T
= 1.5 V 200 ps 1
1
Guaranteed b
y
desi
g
n and characterization
,
not 100% tested in
p
roduction.
Output Low Current I
OL
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at
14.31818MHz
Output High Current I
OH
9
ICS932S801
0959C—03/13/06
Electrical Characteristics - REF-14.318MHz
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
= 27 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1
Clock period T
p
eriod
14.318MHz output nominal 69.8270 69.8550 ns 2
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.4 V 1
Output High Current I
OH
V
OH
@MIN = 1.0 V,
V
OH
@MAX = 3.135 V -29 -23 mA 1
Output Low Current I
OL
V
OL
@MIN = 1.95 V,
V
OL
@MAX = 0.4 V 29 27 mA 1
Ed
g
e Rate δV/δtRisin
g
ed
g
e rate 1 2 V/ns 1
Edge Rate δV/δtFalling edge rate 1 2 V/ns 1
Duty Cycle d
t1
V
T
= 1.5 V 45 55 % 1
Skew t
sk1
V
T
= 1.5 V 50 ps 1
Jitter, Cycle to cycle t
jcyc-cyc
V
T
= 1.5 V 1000 ps 1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is
at 14.31818MHz
10
ICS932S801
0959C—03/13/06
General SMBus serial interface information
How to Write:
•Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR ACK
ACK
ACK
ACK
ACK
PstoP bit
X Byte
Index Block Wri te Oper ation
Slave Address D2(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3(H)
Index Block Read Operation
Slave Address D2(H)
Beginning Byte = N ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
11
ICS932S801
0959C—03/13/06
SMBus Table: Frequency Select and Spread Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7 FS Source Latched Input or SMBus
Frequency Select RW Latched
Inputs SMBus 0
Bit 6 CPU SS_EN RW OFF ON 0
Bit 5 SRC SS_EN RW OFF ON 0
Bit 4 Reserved Reserved RW Reserved Reserved 0
Bit 3 FS3 Freq Select Bit 3 RW 0
Bit 2 FS2 Freq Select Bit 2 RW Latched
Bit 1 FS1 Freq Select Bit 1 RW Latched
Bit 0 FS0 Freq Select Bit 0 RW Latched
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7 PCICLK3 Output Enable RW Disable (Low) Enable 1
Bit 6 PCICLK2 Output Enable RW Disable (Low) Enable 1
Bit 5 PCICLK1 Output Enable RW Disable (Low) Enable 1
Bit 4 PCICLK0 Output Enable RW Disable (Low) Enable 1
Bit 3 HTTCLK3 Output Enable RW Disable (Low) Enable 1
Bit 2 HTTCLK2 Output Enable RW Disable (Low) Enable 1
Bit 1 HTTCLK1 Output Enable RW Disable (Low) Enable 1
Bit 0 HTTCLK0 Output Enable RW Disable (Low) Enable 1
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7 48MHz_1 Output Enable RW Disable (Low) Enable 1
Bit 6 48MHz_0 Output Enable RW Disable (Low) Enable 1
Bit 5 REF1 Output Enable RW Disable (Low) Enable 1
Bit 4 REF0 Output Enable RW Disable (Low) Enable 1
Bit 3 CPUCLK8(3) R
W
Disable Enable 1
Bit 2 CPUCLK8(2) R
W
Disable Enable 1
Bit 1 CPUCLK8(1) R
W
Disable Enable 1
Bit 0 CPUCLK8(0) RW Disable Enable 1
Output Enable
When Disabled
CPUCLKT = 0
CPUCLKC = 1
-
-
-
-
-
B
y
te 1
Spread Enable for CPU
and SRC PLLs. Setting
SPREAD_EN to '1',
forces Spread ON for
both PLLs.
B
y
te 0
-
-
-
B
y
te 2
See Functionality Table on
Page 1
12
ICS932S801
0959C—03/13/06
SMBus Table: SRCCLK(0) Output Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 Reserved Reserved RW Reserved Reserved 0
Bit 6 Reserved Reserved RW Reserved Reserved 0
Bit 5 Reserved Reserved RW Reserved Reserved 0
Bit 4 Reserved Reserved RW Reserved Reserved 0
Bit 3 Reserved Reserved RW Reserved Reserved 0
Bit 2 Reserved Reserved RW Reserved Reserved 0
Bit 1 SRCCLK0 PD SRCCLK Power Down
Drive Mode RW Driven Hi-Z 0
Bit 0 SRCCLK0 Output Enable RW Disable (Hi-Z) Enable 1
SMBus Table: 48MHz Drive Strength Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 Reserved Reserved RW Reserved Reserved 0
Bit 6 Reserved Reserved RW Reserved Reserved 0
Bit 5 Reserved Reserved RW Reserved Reserved 0
Bit 4 Reserved Reserved RW Reserved Reserved 0
Bit 3 Reserved Reserved RW Reserved Reserved 0
Bit 2 Reserved Reserved RW Reserved Reserved 0
Bit 1 48MHz_1 DS Drive Stren
g
th Control RW 1X 2X 0
Bit 0 48MHz_0 DS Drive Strength Control RW 1X 2X 0
SMBus Table: SRC Frequency Select Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 Reserved Reserved RW Reserved Reserved 0
Bit 6 Reserved Reserved RW Reserved Reserved 0
Bit 5 Reserved Reserved RW Reserved Reserved 0
Bit 4 Reserved Reserved RW Reserved Reserved 0
Bit 3 SRCFS1 SRC FS bit 1 RW 0
Bit 2 SRCFS0 SRC FS bit 0 RW 0
Bit 1 Reserved Reserved RW Reserved Reserved 0
Bit 0 Reserved Reserved RW Reserved Reserved 0
SMBus Table: Device ID Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 DevID 7 Device ID MSB R - - 1
Bit 6 DevID 6 Device ID 6 R - - 0
Bit 5 DevID 5 Device ID 5 R - - 0
Bit 4 DevID 4 Device ID4 R - - 0
Bit 3 DevID 3 Device ID3 R - - 0
Bit 2 DevID 2 Device ID2 R - - 0
Bit 1 DevID 1 Device ID1 R - - 0
Bit 0 DevID 0 Device ID LSB R - - 1
-
-
-
-
-
See Table 1:
SRC Frequency Select
Byte 5
-
-
-
-
5
4
Byte 6
-
-
-
-
-
-
-
-
Byte 4
-
-
-
-
Byte 3
-
-
-
-
-
-
-
-
13
ICS932S801
0959C—03/13/06
SMBus Table: Vendor ID Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 RID3 R - - X
Bit 6 RID2 R - - X
Bit 5 RID1 R - - X
Bit 4 RID0 R - - X
Bit 3 VID3 R - - 0
Bit 2 VID2 R - - 0
Bit 1 VID1 R - - 0
Bit 0 VID0 R - - 1
SMBus Table: Byte Count Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 BC7 RW 0
Bit 6 BC6 RW 0
Bit 5 BC5 RW 0
Bit 4 BC4 RW 0
Bit 3 BC3 RW 1
Bit 2 BC2 RW 0
Bit 1 BC1 RW 0
Bit 0 BC0 RW 1
SMBus Table: Reserved Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7 Reserved Reserved RW Reserved Reserved 0
Bit 6 Reserved Reserved RW Reserved Reserved 0
Bit 5 Reserved Reserved RW Reserved Reserved 0
Bit 4 Reserved Reserved RW Reserved Reserved 0
Bit 3 Reserved Reserved RW Reserved Reserved 0
Bit 2 Reserved Reserved RW Reserved Reserved 0
Bit 1 Reserved Reserved RW Reserved Reserved 0
Bit 0 Reserved Reserved RW Reserved Reserved 0
SMBus Table: M/N Programming Enable
Pin # Name Control Function Type 0 1 PWD
Bit 7 M/N_EN CPU and SRC PLL M/N
Pro
g
rammin
g
Enable RW Disable Enable 0
Bit 6 Reserved Reserved RW - - 0
Bit 5 Reserved Reserved RW - - 0
Bit 4 Reserved Reserved RW - - 0
Bit 3 Reserved Reserved RW - - 0
Bit 2 Reserved Reserved RW - - 0
Bit 1 Reserved Reserved RW - - 0
Bit 0 Reserved Reserved RW - - 0
Byte 8
Byte 7
-
-
-
Writing to this register will
configure how many bytes
will be read back, default is
9 bytes.
-
-
-
-
-
-
-
-
-
-
-
Byte 10
Byte 9
-
-
-
-
-
-
-Revision ID
VENDOR ID
(0001 = ICS)
-
Byte Count Programming
b(7:0)
-
-
-
-
-
-
-
-
-
-
14
ICS932S801
0959C—03/13/06
SMBus Table: CPU Frequency Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7 N Div8 N Divider Prog bit 8 RW X
Bit 6 N Div9 N Divider Prog bit 9 RW X
Bit 5 M Div5 RW X
Bit 4 M Div4 RW X
Bit 3 M Div3 RW X
Bit 2 M Div2 RW X
Bit 1 M Div1 RW X
Bit 0 M Div0 RW X
SMBus Table: CPU Frequency Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7 N Div7 RW X
Bit 6 N Div6 RW X
Bit 5 N Div5 RW X
Bit 4 N Div4 RW X
Bit 3 N Div3 RW X
Bit 2 N Div2 RW X
Bit 1 N Div1 RW X
Bit 0 N Div0 RW X
SMBus Table: CPU Spread Spectrum Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7 SSP7 RW X
Bit 6 SSP6 RW X
Bit 5 SSP5 RW X
Bit 4 SSP4 RW X
Bit 3 SSP3 RW X
Bit 2 SSP2 RW X
Bit 1 SSP1 RW X
Bit 0 SSP0 RW X
SMBus Table: CPU Spread Spectrum Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7 Reserved Reserved R - - 0
Bit 6 SSP14 RW X
Bit 5 SSP13 RW X
Bit 4 SSP12 RW X
Bit 3 SSP11 RW X
Bit 2 SSP10 RW X
Bit 1 SSP9 RW X
Bit 0 SSP8 RW X
Spread Spectrum
Programming bit(7:0)
-
-
-
-
-
-
B
y
te 11
-
-
M Divider Programming
bit (5:0)
-
-
-
-
-
N Divider Programming
Byte12 bit(7:0) and
Byte11 bit(7:6)
-
-
Spread Spectrum
Programming bit(14:8)
-
-
-
-
-
-
-
-
-
-
B
y
te 14
-
-
-
B
y
te 13
B
y
te 12
-
-
-
-
These Spread Spectrum
bits in Byte 13 and 14 will
program the spread
pecentage of CPU
These Spread Spectrum
bits in Byte 13 and 14 will
program the spread
pecentage of CPU
The decimal representation
of M and N Divier in Byte
11 and 12 will configure
the CPU VCO frequency.
Default at power up = latch
-
in or Byte 0 Rom table.
VCO Frequency = 14.318
x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
The decimal representation
of M and N Divier in Byte
11 and 12 will configure
the CPU VCO frequency.
Default at power up = latch
-
in or Byte 0 Rom table.
VCO Frequency = 14.318
x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
15
ICS932S801
0959C—03/13/06
SMBus Table: SRC Frequency Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7 N Div8 N Divider Prog bit 8 RW X
Bit 6 N Div9 N Divider Prog bit 9 RW X
Bit 5 M Div5 RW X
Bit 4 M Div4 RW X
Bit 3 M Div3 RW X
Bit 2 M Div2 R
W
X
Bit 1 M Div1 R
W
X
Bit 0 M Div0 RW X
SMBus Table: SRC Frequency Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7 N Div7 RW X
Bit 6 N Div6 RW X
Bit 5 N Div5 RW X
Bit 4 N Div4 RW X
Bit 3 N Div3 RW X
Bit 2 N Div2 R
W
X
Bit 1 N Div1 R
W
X
Bit 0 N Div0 RW X
SMBus Table: SRC Spread Spectrum Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7 SSP7 RW X
Bit 6 SSP6 RW X
Bit 5 SSP5 RW X
Bit 4 SSP4 R
W
X
Bit 3 SSP3 R
W
X
Bit 2 SSP2 R
W
X
Bit 1 SSP1 R
W
X
Bit 0 SSP0 RW X
SMBus Table: SRC Spread Spectrum Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7 Reserved Reserved R - - 0
Bit 6 SSP14 RW X
Bit 5 SSP13 RW X
Bit 4 SSP12 RW X
Bit 3 SSP11 RW X
Bit 2 SSP10 RW X
Bit 1 SSP9 R
W
X
Bit 0 SSP8 RW X
-
-
M Divider Programming
bits
-
-
B
y
te 16
Spread Spectrum
Programming b(7:0)
-
-
-
Spread Spectrum
Programming b(14:8)
-
-
-
-
-
-
These Spread Spectrum
bits in Byte 17 and 18 will
program the spread
pecentage of SRC
N Divider Programming
b(7:0)
-
These Spread Spectrum
bits in Byte 17 and 18 will
program the spread
pecentage of SRC
-
-
-
-
-
-
-
-
-
B
y
te 18
B
y
te 17
-
-
-
-
-
-
-
-
B
y
te 15
-
The decimal representation
of M and N Divier in Byte
15 and 16 will configure
the SRC VCO frequency.
Default at power up = latch
-
in or Byte 0 Rom table.
VCO Frequency = 14.318
x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
The decimal representation
of M and N Divier in Byte
15 and 16 will configure
the SRC VCO frequency.
Default at power up = latch
-
in or Byte 0 Rom table.
VCO Frequency = 14.318
x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
16
ICS932S801
0959C—03/13/06
SMBus Table: Programmable Output Divider Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 CPUDiv3 RW X
Bit 6 CPUDiv2 RW X
Bit 5 CPUDiv1 RW X
Bit 4 CPUDiv0 RW X
Bit 3 HTTDiv3 RW X
Bit 2 HTTDiv2 RW X
Bit 1 HTTDiv1 RW X
Bit 0 HTTDiv0 RW X
SMBus Table: Programmable Output Divider Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 Reserved Reserved R - - X
Bit 6 Reserved Reserved R - - X
Bit 5 Reserved Reserved R - - X
Bit 4 Reserved Reserved R - - X
Bit 3 SRC_Div3 RW X
Bit 2 SRC_Div2 RW X
Bit 1 SRC_Div1 RW X
Bit 0 SRC_Div0 RW X
SMBusTable: Test Byte Register
Test T
yp
ePWD
Bit 7 RW 0
Bit 6 RW 0
Bit 5 RW 0
Bit 4 RW 0
Bit 3 RW 0
Bit 2 RW 0
Bit 1 RW 0
Bit 0 RW 0
ICS ONLY TEST Reserved
Byte 21
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
Test Function Test Result
` ICS ONLY TEST Reserved
-
-
Byte 19
-
-
-
-
-
-
-
-
Byte 20
-
-
-
-
-
-
See Table 2:
CPU Divider Ratios
See Table 3:
HTT Divider Ratios
See Table 4:
SRC Divider Ratios
CPU Divider Ratio
Programming Bits
HTT Divider Ratio
Programming Bits (PCI
divider is always 2x the
HTT divider or 1/2 freq.)
SRC_ Divider Ratio
Programming Bits
17
ICS932S801
0959C—03/13/06
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the
ICS932S801 serve as dual signal functions to the device.
During initial power-up, they act as input pins. The logic
level (voltage) that is present on these pins at this time
is read and stored into a 5-bit internal data latch. At the
end of Power-On reset, (see AC characteristics for timing
values), the device changes the mode of operations for
these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K W
8.2K W
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
18
ICS932S801
0959C—03/13/06
Ordering Information
ICS932S801yFLFT
Example:
INDEX
AREA
INDEX
AREA
12
1 2
N
D
h x 45°
h x 45°
E1 E
α
SEATING
PLANE
SEATING
PLANE
A1
A
e
-C-
- C -
b
.10 (.004) C
.10 (.004) C
c
L
Designation for tape and reel packaging
RoHS Compliant
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS XXXX y F - LF T
MIN MAX MIN MAX
A2.412.80.095.110
A1 0.20 0.40 .008 .016
b 0.20 0.34 .008 .0135
c0.130.25.005.010
D
E 10.03 10.68 .395 .420
E1 7.40 7.60 .291 .299
e
h0.380.64.015.025
L0.501.02.020.040
N
a 0°8°0°8°
VARIATIONS
MIN MAX MIN MAX
48 15.75 16.00 .620 .630
10-0034
0.635 BASIC 0.025 BASIC
COMMON DIMENSIONS
In Millimeters In Inches
COMMON DIMENSIONS
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP
N
SEE VARIATIONS SEE VARIATIONS
D mm. D (inch)
SYMBOL
SEE VARIATIONS SEE VARIATIONS
19
ICS932S801
0959C—03/13/06
Ordering Information
ICS932S801yGLFT
Example:
Designation for tape and reel packaging
RoHS Compliant
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS XXXX y G - LF T
INDEX
AREA
INDEX
AREA
12
12
N
D
E1 E
a
SEATING
PLANE
SEATING
PLANE
A1
A
A2
A2
e
-C-
-C-
b
c
L
aaa
C
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
a0°8°0°8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
48 12.40 12.60 .488 .496
10-0039
ND mm. D (inch)
Reference Doc.: JEDEC Publication 95, MO-153
0.50 BASIC 0.020 BASIC
SEE VARIATIONS SEE VARIATIONS
SEE VARIATIONS SEE VARIATIONS
8.10 BASIC 0.319 BASIC
(240 mil) (20 mil)
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
20
ICS932S801
0959C—03/13/06
Revision History
Rev. Issue Date Description Page #
B 5/18/2005
1. Updated Electrical Characteristics Tables:
i) Changed SRC jitter from 125ps to 100ps;
ii) Changed PCI/HTT Skew from 500ps to 200ps;
iii) Added USB Skew, 50ps.
iv) Change REF Skew from 500ps to 50ps.
2. Updated LF Orderin
g
Information from "Lead Free" to "RoHS Compliant".
14-16
18-19
C 3/13/2006
1. Correct pin description of PD# (Pin 21). It does not contain a pull up resistor.
2. Added PCIe Gen 1 phase noise numbers to SRC output characterisitics 2, 7