FEATURES
DDIGITALLY-CONTROLLED ANALOG VOLUME
CONTROL:
Two Independent Audio Channels
Serial Control Interface
Zero Crossing Detection
Mute Function
DWIDE GAIN AND ATTENUATION RANGE:
+31.5dB to −95.5dB with 0.5dB Steps
DLOW NOISE AND DISTORTION:
120dB Dynamic Range
0.0004% THD+N at 1kHz
DLOW INTERCHANNEL CROSSTALK:
−126dBFS
DNOISE-FREE LEVEL TRANSITIONS
DPOWER SUPPLIES: +15V Analog, +5V Digital
DAVAILABLE IN DIP−16 AND SOL−16
PACKAGES
DPIN AND SOFTWARE COMPATIBLE WITH
THE PGA2311 AND CIRRUS LOGIC CS3310E
APPLICATIONS
DAUDIO AMPLIFIERS
DMIXING CONSOLES
DMULTI-TRACK RECORDERS
DBROADCAST STUDIO EQUIPMENT
DMUSICAL INSTRUMENTS
DEFFECTS PROCESSORS
DA/V RECEIVERS
DCAR AUDIO SYSTEMS
DESCRIPTION
The PGA2310 is a high-performance, stereo audio volume
control designed for professional and high-end consumer
audio systems. The ability to operate from ±15V analog
power supplies enables the PGA2310 to process input
signals with large voltage swings, thereby preserving the
dynamic range available in the overall signal path. Using
high performance operational amplifier stages internal to
the PGA2310 yields low noise and distortion, while
providing the capability to drive 600Ω loads directly
without buffering. The three-wire serial control interface
allows for connection to a wide variety of host controllers,
in addition to support for daisy-chaining of multiple
PGA2310 devices.
PGA2310
SBOS207B − OCTOBER 2001 − REVISED JUNE 2004
Stereo Audio Volume Control
www.ti.com
Copyright 2001 − 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
! !
"#$%&
SBOS207B − OCTOBER 2001 − REVISED JUNE 2004
www.ti.com
2
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over o p e r a t i n g f ree-air temperature range unless otherwise noted(1)
PGA2310 UNIT
VA+ +16.0 V
Supply voltage VA− −16.0 V
Supply voltage
VD+ +6.5 V
Analog input voltage 0 to VA+, V A− V
Digital input voltage −0.3 to VD+ V
Operating temperature range −55 to +125 °C
Storage temperature range −65 to +150 °C
Junction temperature +150 °C
Lead temperature (soldering, 10s) +300 °C
Package temperature (IR, reflow, 10s) +235 °C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those specified is not implied.
ORDERING INFORMATION(1)
PRODUCT PACKAGE−LEAD PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING ORDERING
NUMBER TRANSPORT
MEDIA, QUANTITY
DIP-16 N PGA2310PA PGA2310PA Rails, 25
PGA2310
SOL-16
DW
−40°C to +85°CPGA2310UA PGA2310UA Rails, 48
PGA2310
SOL-16
DW
−40 C to +85 C
PGA2310UA PGA2310UA/1K Tape and Reel, 1000
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
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SBOS207B − OCTOBER 2001 − REVISED JUNE 2004
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3
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VA+ = +15V, VA− = −15V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted.
PGA2310
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC CHARACTERISTICS
Step Size 0.5 dB
Gain Error Gain Setting = 31.5dB ±0.05 dB
Gain Matching ±0.05 dB
Input Resistance 10 kΩ
Input Capacitance 7 pF
AC CHARACTERISTICS
THD+N VIN = 10VPP, f = 1kHz 0.0004 0.001 %
Dynamic Range VIN = AGND, Gain = 0dB 116 120 dB
Voltage Range, Input and Output (VA−) + 1.5 (VA−) − 1.5 V
Output Noise VIN = AGND, Gain = 0dB 9.5 13.5 µVRMS
Interchannel Crosstalk f = 1kHz −126 dBFS
OUTPUT BUFFER
Of fset Voltage VIN = AGND, Gain = 0dB 0.5 3 mV
Load Capacitance Stability 1000 pF
Short-Circuit Current 35 mA
Unity-Gain Bandwidth, Small Signal 1.5 MHz
DIGITAL CHARACTERISTICS
High-Level Input Voltage, VIH +2.0 VD+ V
Low-Level Input Voltage, VIL −0.3 0.8 V
High-Level Output Voltage, VOH IO = 200µA (VD+) − 1.0 V
Low-Level Output Voltage, VOL IO = −3.2mA 0.4 V
Input Leakage Current 1 10 µA
SWITCHING CHARACTERISTICS
Serial Clock (SCLK) Frequency tSCLK 0 6.25 MHz
Serial Clock (SCLK) Pulse Width Low tPH 80 ns
Serial Clock (SCLK) Pulse Width High tPL 80 ns
MUTE Pulse Width Low tMI 2.0 ms
Input Timing
SDI Setup Time tSDS 20 ns
SDI Hold Time tSDH 20 ns
CS Falling to SCLK Rising tCSCR 90 ns
SCLK Falling to CS Rising tCFCS 35 ns
Output Timing
CS Low to SDO Active tCSO 35 ns
SCLK Falling to SDO Data Valid tCFDO 60 ns
CS High to SDO High Impedance tCSZ 100 ns
POWER SUPPLY
Operating Voltage
VA+ +4.5 +15 +15.5 V
VA− −4.5 −15 −15.5 V
VD+ +4.5 +5 +5.5 V
Quiescent Current
IA+ VA+ = +15V 7.5 10 mA
IA− VA− = −15V 7.7 10 mA
ID+ VD+ = +5V 0.8 1.5 mA
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SBOS207B − OCTOBER 2001 − REVISED JUNE 2004
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4
ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, VA+ = +15V, VA− = −15V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted.
PGA2310
PARAMETER UNITMAXTYPMINTEST CONDITIONS
TEMPERATURE RANGE
Specified Range −40 +85 °C
Operating Range −55 +125 °C
Storage Range −65 +150 °C
Thermal Resistance, θJC
DIP−16 60 °C/W
SOL−16 50 °C/W
PIN CONFIGURATION
Top View
ZCEN
CS
SDI
VD+
DGND
SCLK
SDO
MUTE
VINL
AGNDL
VOUTL
VA−
VA+
VOUTR
AGNDR
VINR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGA2310
PIN ASSIGNMENTS
PIN NAME FUNCTION
1 ZCEN Zero Crossing Enable Input (Active High)
2 CS Chip Select Input (Active Low)
3 SDI Serial Data input
4 VD+Digital Power Supply, +5V
5 DGND Digital Ground
6 SCLK Serial Clock Input
7 SDO Serial Data Output
8 MUTE Mute Control Input (Active Low)
9 VINRAnalog Input, Right Channel
10 AGNDR Analog Ground, Right Channel
11 VOUTRAnalog Output, Right Channel
12 VA+Analog Power Supply, +15V
13 VA−Analog Power Supply, −15V
14 VOUTLAnalog Output, Left Channel
15 AGNDL Analog Ground, Left Channel
16 VINLAnalog Input, Left Channel
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SBOS207B − OCTOBER 2001 − REVISED JUNE 2004
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5
TYPICAL CHARACTERISTICS
At TA = +25°C, VA+ = +15V, VA− = −15V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted.
1
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
FREQUENCY RESPONSE
10 1k 10k100 200k
Frequency (Hz)
Amplitude (dB)
1
0.1
0.01
0.001
0.0001
THD+N vs AMPLITUDE
100m 1 9
Amplitude (VRMS)
THD+N (%)
0.05
0.01
0.001
0.000120 1k 10k100 20k
Frequency (Hz)
THD+N (%)
THD+N vs FREQUENCY
(VIN = 3.0VRMS, Load = 100kΩ)0.05
0.01
0.001
0.000120 1k 10k100 20k
Frequency (Hz)
THD+N (%)
THD+N vs FREQUENCY
(VIN = 3.0VRMS, Load = 600Ω)
0.05
0.01
0.001
0.000120 1k 10k100 20k
Frequency (Hz)
THD+N (%)
THD+N vs FREQUENCY
(VIN = 8.5VRMS, Load = 100kΩ)0.05
0.01
0.001
0.000120 1k 10k100 20k
Frequency (Hz)
THD+N (%)
THD+N vs FREQUENCY
(VIN = 8.5VRMS, Load = 600Ω)
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SBOS207B − OCTOBER 2001 − REVISED JUNE 2004
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6
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VA+ = +15V, VA− = −15V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted.
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
AMPLITUDE vs FREQUENCY
(Crosstalk with fIN =1kHz)
20 4k 6k2k 10k 12k8k 16k 18k 20k14k 22k
Frequency (Hz)
Amplitude (dBFS)
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
AMPLITUDE vs FREQUENCY
(Crosstalk with fIN =10kHz)
04k6k2k 10k 12k8k 16k 18k 20k14k 22k
Frequency (Hz)
Amplitude (dBFS)
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
AMPLITUDE vs FREQUENCY
(Crosstalk with fIN = 20kHz)
04k 6k2k 10k 12k8k 16k 18k 20k14k 22k
Frequency (Hz)
Amplitude (dBFS)
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SBOS207B − OCTOBER 2001 − REVISED JUNE 2004
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7
GENERAL DESCRIPTION
The PGA2310 is a stereo audio volume control. It may be
used in a wide array of professional and consumer audio
equipment. The PGA2310 is fabricated in a mixed-signal
BiCMOS process, as to take advantage of the superior
analog characteristics for which it offers.
The heart of the PGA2310 is a resistor network, an analog
switch array, and a high-performance bipolar op amp
stage. The switches are used to select taps in the resistor
network that, in turn, determine the gain of the amplifier
stage. Switch selections are programmed using a serial
control port. The serial port allows connection to a wide
variety of host controllers. Figure 1 shows a functional
block diagram of the PGA2310.
POWER-UP STATE
On power up, all internal flip-flops are reset. The gain byte
value for both the left and right channels are set to 00HEX,
or mute condition. The gain will remain at this setting until
the host controller programs new settings for each channel
via the serial control port.
ANALOG INPUTS AND
OUTPUTS
The PGA2310 includes two independent channels,
referred t o a s the left and right channels. Each channel has
a corresponding input and output pin. The input and output
pins are unbalanced, or referenced to analog ground
(either AGNDR or AGNDL). The inputs are named VINR
(pin 9) and VINL (pin 16), while the outputs are named
VOUTR (pin 11) and VOUTL (pin 14).
The input and output pins may swing within 1.5V of the
analog power supplies, VA+ (pin 12) and VA− (pin 13).
Given VA+ = +15V and V A− = −15V, the maximum input or
output voltage range is 27VPP.
It is important to drive the PGA2310 with a low source
impedance. If a source impedance of greater than 600Ω is
used, the distortion performance of the PGA2310 will
begin to degrade.
MUX
Serial
Control
Port
MUX
ZCEN
CS
SCLK
SDI
SDO
MUTE
VOUTR
VOUTL
VINL
AGNDL
AGNDR
VINR
VA+VA−VD+DGND
12 13 4 5
11
7
3
6
2
1
8
14
16
15
10
9
8
8
88
Figure 1. PGA2310 Block Diagram
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SBOS207B − OCTOBER 2001 − REVISED JUNE 2004
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8
SERIAL CONTROL PORT
The serial control port is utilized to program the gain
settings for the PGA2310. The serial control port includes
three input pins and one output pin. The inputs include CS
(pin 2), SDI (pin 3), and SCLK (pin 6). The sole output pin
is SDO (pin 7).
The CS pin functions as the chip select input. Data may be
written to the PGA2310 only when CS is low. SDI is the
serial data input pin. Control data is provided as a 16-bit
word at the SDI pin, 8 bits each for the left and right channel
gain settings. Data is formatted as MSB first, straight
binary code. SCLK is the serial clock input. Data is clocked
into SDI on the rising edge of SCLK.
SDO is the serial data output pin, and is used when
daisy-chaining multiple PGA2310 devices. Daisy-chain
operation is described in detail later in this section. SDO
is a tristate output, and assumes a high impedance state
when CS is high.
The protocol for the serial control port is shown in Figure 2.
See Figure 3 for detailed timing specifications of the serial
control port.
Gain Byte Format is MSB First, Straight Binary
R0 is the Least Significant Bit of the Right Channel Gain Byte
R7 is the Most Significant Bit of the Right Channel Gain Byte
L0 is the Least Significant Bit of the Left Channel Gain Byte
L7 is the Most Significant Bit of the Left Channel Gain Byte
SDI is latched on the rising edge of SCLK.
SDO transitions on the falling edge of SCLK.
CS
SCLK
SDI
SDO
R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0
R7
R7
R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0
Figure 2. Serial Interface Protocol
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SBOS207B − OCTOBER 2001 − REVISED JUNE 2004
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9
GAIN SETTINGS
The gain for each channel is set by its corresponding 8-bit
code, either R[7:0] or L[7:0], see Figure 2. The gain code
data is straight binary format. If we let N equal the decimal
equivalent of R[7:0] or L[7:0], then the following
relationships exist for the gain settings:
For N = 0:
Mute Condition. The input multiplexer is connected to
analog ground (AGNDR or AGNDL).
For N = 1 to 255:
Gain (dB) = 31.5 − [0.5 • (255 − N)]
This results in a gain range of +31.5dB (with N = 255) to
−95.5dB (with N = 1).
Changes in g a i n se t t i n g m a y b e m a d e w i t h o r w i t h o u t z e r o
crossing detection. The operation of the zero crossing
detector and timeout circuitry is discussed later in this data
sheet.
tCSCR tSDS tCFCS
tSDH
tCSO tCFDO tCSZ
MSB
CS
SCLK
SDI
SDO
Figure 3. Serial Interface Timing Requirements
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SBOS207B − OCTOBER 2001 − REVISED JUNE 2004
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10
DAISY-CHAINING MULTIPLE
PGA2310 DEVICES
In order to reduce the number of control signals required
to support multiple PGA2310 devices on a printed circuit
board, the serial control port supports daisy-chaining of
multiple PGA2310 devices. Figure 4 shows the
connection requirements for daisy-chain operation. This
arrangement allows a three-wire serial interface to control
many PGA2310 devices.
As shown in Figure 4, the SDO pin from device #1 is
connected to the SDI input of device #2, and is repeated
for additional devices. This in turn forms a large shift
register, in which gain data may be written for all
PGA2310s connected to the serial bus. The length of the
shift register is 16 x N bits, where N is equal to the number
of PGA2310 devices included in the chain. The CS input
must remain low for 16 x N SCLK periods, where N is the
number of devices connected in the chain, in order to allow
enough SCLK cycles to load all devices.
ZERO CROSSING DETECTION
The PGA2310 includes a zero crossing detection function
that can provide for noise-free level transitions. The
concept is t o change gain settings on a zero crossing of the
input signal, thus minimizing audible glitches. This
function is enabled or disabled using the ZCEN input
(pin 1). When ZCEN is low, zero crossing detection is
disabled. When ZCEN is high, zero crossing detection will
be enabled.
The zero crossing detection takes effect with a change in
gain setting for a corresponding channel. The new gain
setting will not be latched until either two zero crossings
are detected, or a timeout period of 16ms has elapsed
without detecting two zero crossings. In the case of a
timeout, the new gain setting takes effect with no attempt
to minimize audible artifacts.
SDI
VINL
VINR
SDO
SCLK
CS
VOUTL
VOUTR
PGA2310
#1
SDI
VINL
VINR
SDO
SCLK
CS
VOUTL
VOUTR
PGA2310
#2
SDI
VINL
VINR
SDO
SCLK
CS
VOUTL
VOUTR
PGA2310
#3
Audio
Input
Audio
Input
Audio
Input
100kΩ
100kΩ
Controller
Figure 4. Daisy-Chaining Multiple PGA2310 Devices
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SBOS207B − OCTOBER 2001 − REVISED JUNE 2004
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11
MUTE FUNCTION
The PGA2310 includes a mute function. This function may
be activated by either the MUTE input (pin 8), or by setting
the gain byte value for one or both channels to 00HEX. The
MUTE pin may be used to mute both channels, while the
gain setting may be used to selectively mute the left and
right channels. Muting is accomplished by switching the
input multiplexer to analog ground (AGNDR or AGNDL)
with zero crossing enabled.
The MUTE pin is active low. When MUTE is low, each
channel will be muted following the next zero crossing
event or timeout that occurs on that channel. If MUTE
becomes active while CS is also active, the mute will take
effect once the CS pin goes high. When the MUTE pin is
high, the PGA2310 operates normally, with the mute
function disabled.
APPLICATIONS INFORMATION
This section includes additional information that is
pertinent to designing the PGA2310 into an end
application.
RECOMMENDED CONNECTION DIAGRAM
Figure 5 depicts the recommended connections for the
PGA2310. Power-supply bypass capacitors should be
placed as close to the PGA2310 package as physically
possible.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGA2310Controller C2
C3C4
C5C6
C1
To
Additional
PGA2310s
+5V Digital
SDO
DGND AGND
MUTE
SCLK +15V Analog
−15V Analog
VINL
VOUTL
VOUTR
VINR
SDI
CS
ZCEN
C2,C
3,C
5=0.1
µF ceramic or metal film.
C1,C
4,C
6=10
µF tantalum or aluminum electrolytic.
Figure 5. Recommended Connection Diagram
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SBOS207B − OCTOBER 2001 − REVISED JUNE 2004
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12
PRINTED CIRCUIT BOARD LAYOUT
GUIDELINES
It is recommended that the ground planes for the digital
and analog sections of the printed circuit board (PCB) be
separate from one another. The planes should be
connected at a single point. Figure 6 shows the
recommended PCB floor plan for the PGA2310.
The PGA2310 is mounted so that it straddles the split be-
tween the digital and analog ground planes. Pins 1 through
8 are oriented to the digital side of the board, while pins 9
through 16 are on the analog side of the board.
Analog
Ground
Digital
Ground
PGA2310
DIGITAL GROUND PLANE ANALOG GROUND PLANE
Host
Digital Power
+5V DGND
Analog Power
−15V +15VAGND
Analog
Inputs
and
Outputs
Figure 6. Typical PCB Layout Floor Plan
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PGA2310PA ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
PGA2310PAG4 ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
PGA2310UA ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PGA2310UA/1K ACTIVE SOIC DW 16 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PGA2310UA/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PGA2310UAG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PGA2310UA/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PGA2310UA/1K SOIC DW 16 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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