ASAHI KASEI [AK93C85A/95A/10A]
DAM02E-03 2004/05
- 1 -
AK93C85A / 95A / 10A
16K / 32K / 64Kbit Serial CMOS EEPROM
Features
ADVANCED CMOS EEPROM TECHNOLOGY
READ/WRITE NON-VOLATILE MEMORY
WIDE VCC OPERATION : VCC = 1.8V to 5.5V
AK93C85A ・・16384 bits, 1024 x 16 organization
AK93C95A ・・32768 bits, 2048 x 16 organization
AK93C10A ・・65536 bits, 4096 x 16 organization
SERIAL INTERFACE
- Interfaces with popular microcontrollers and standard microprocessors
LOW POWER CONSUMPTION
- 0.4mA Max. Read Operation
- 0.8µA Max. Standby
High Reliability
- Endurance : 100K cycles
- Data Retention : 10 years
Automatic address increment (READ)
Automatic write cycle time-out with auto-ERASE (Max. 8ms: VCC=4.5V to 5.5V)
Busy/Ready status signal
Software controlled write protection
IDEAL FOR LOW DENSITY DATA STORAGE
- Low cost, space saving, 8-pin package (SOP, SSOP)
Block Diagram
93C10A=65536bit
93C85A=16384bit
93C95A=32768bit
VPP
GENERATOR
DATA
REGISTER
INSTRUCTION
DECODE,
CONTROL
AND
CLOCK
GENERATION
INSTRUCTION
REGISTER EEPROM
DI
CS
SK
ADD.
BUFFERS
VREF
VPP SW
DECODER
R/W AMPS
AND
AU TO ERAS E
DO
16 16
ASAHI KASEI [AK93C85A/95A/10A]
DAM02E-03 2004/05
- 2 -
General Description
The AK93C85A/95A/10A is a 16384/32768/65536-bit serial CMOS EEPROM divided into
1024/2048/4096 registers of 16 bits each. The AK93C85A/95A/10A has 4 instructions such as
READ, WRITE, EWEN and EWDS. Those instructions control the AK93C85A/95A/10A.
The AK93C85A/95A/10A can operate full function under wide operating voltage range from 1.8V to
5.5V. The charge up circuit is integrated for high voltage generation that is used for write
operation.
A serial interface of AK93C85A/95A/10A, consisting of chip select (CS), serial clock (SK), data-in
(DI) and data-out (DO), can easily be controlled by popular microcontrollers or standard
microprocessors. AK93C85A/95A/10A takes in the write data from data input pin (DI) to a register
synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation,
AK93C85A/95A/10A takes out the read data from a register to data output pin (DO) synchronously
with rising edge of SK.
The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data
output or Busy/Ready signal output.
x Software controlled write protection
When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable
state. In the ERASE/WRITE disable state, execution of WRITE instruction is disabled. Before
WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable
state continues until EWDS instruction is executed or VCC is removed from the part.
Execution of a read instruction is independent of both EWEN and EWDS instructions.
x Busy/Ready status signal
After a write instruction, the DO output serves as a Busy/Ready status indicator. After the falling
edge of the CS initiates the self-timed programming cycle, the DO indicates the Busy/Ready status
of the chip if the CS is brought high after a minimum of 250ns (tCS). DO=logical "0" indicates that
programming is still in progress. DO=logical "1" indicates that the register at the address specified
in the instruction has been written with the new data pattern contained in the instruction and the part
is ready for a next instruction.
The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO
output goes into a high impedance state.
The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part.
Type of Products
Model Memory size Temp. Range VCC Package
AK93C85AM 16K bits -40°C to +85° C 1.8V to 5.5V 8pin Plastic SSOP
AK93C95AF 32K bits -40°C to +85°C 1.8V to 5.5V 8pin Plastic SOP
AK93C10AF 64K bits -40°C to +85°C 1.8V to 5.5V 8pin Plastic SOP
ASAHI KASEI [AK93C85A/95A/10A]
DAM02E-03 2004/05
- 3 -
Pin Arrangement
Pin Name Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
VCC Power Supply
NC Not Connected *1
*1: Please Open NC pin.
AK93C95AF/10AF
8pin SOP
DO
DI
CS
S
K
2
1
3
4
VCC
7
8
6
5GND
NC
NC
8
7
6
5
CS
SK
DI
DO
VCC
GND
1
2
3
4NC
AK93C85AM
8pin SSOP
NC
ASAHI KASEI [AK93C85A/95A/10A]
DAM02E-03 2004/05
- 4 -
Functional Description
The AK93C85A/95A/10A has 4 instructions such as READ, WRITE, EWEN and EWDS. A valid
instruction consists of a Start Bit (Logic"1"), the appropriate Op Code and the desired memory
Address location.
The CS pin must be brought low for a minimum of 250ns (tCS) between each instruction when the
instruction is continuously executed.
Instructi
on Start
Bit Op
Code Address Data Comments
READ 01 10 A9-A0 D15-D0 Reads data stored in memory, at specified address.
WRITE 01 01 A9-A0 D15-D0 Writes register.
EWEN 01 00 11XXXXXXXX Write enable must precede all programming modes.
EWDS 01 00 00XXXXXXXX Disables all programming instructions.
WRAL 01 00 01XXXXXXXX D15-D0 Writes all registers. X: Don't care
table1. Instruction Set for the AK93C85A
Instructi
on Start
Bit Op
Code Address Data Comments
READ 1 10 A10-A0 D15-D0 Reads data stored in memory, at specified address.
WRITE 1 01 A10-A0 D15-D0 W rites register.
EWEN 1 00 11XXXXXXXXX Write enable must precede all programm ing modes.
EWDS 1 00 00XXXXXXXXX Disables all programming instructions.
WRAL 1 00 01XXXXXXXXX D15-D0 Writes all registers. X: Don't care
table2. Instruction Set for the AK93C95A
Instructi
on Start
Bit Op
Code Address Data Comments
READ 1 10 A11-A0 D15-D0 Reads data stored in memory, at specified address.
WRITE 1 01 A11-A0 D15-D0 Writes register.
EWEN 1 00 11XXXXXXXXXX Write enable must precede all programming modes.
EWDS 1 00 00XXXXXXXXXX Disables all programming instructions.
WRAL 1 00 01XXXXXXXXXX D15-D0 Writes all registers. X: Don't care
table3. Instruction Set for the AK93C10A
(Note) x The WRAL instruction are used for factory function test only.
User can't use the WRAL instruction.
x The AK93C85A perceives the start bit in the logic"01" and also "001".
x The AK93C95A/10A perceives the start bit in the logic"1" and also "01".
ASAHI KASEI [AK93C85A/95A/10A]
DAM02E-03 2004/05
- 5 -
WRITE
The write instruction is followed by 16 bits of data to be written into the specified address.
AK93C85A: After the last bit of data is put on the DI pin, the CS pin must be brought low before the
next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming
cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a
minimum of 250ns (Tcs).
AK93C95A/10A: The self-timed programming cycle is initiated on the rising edge of the SK clock as
the last data bit (D0) is clocked in. The DO indicates the Busy/Ready status of the chip after the
self-timed programming cycle is initiated.
The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO
output goes into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1")
of the next instruction is given to the part.
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the
register at the address specified in the instruction has been written with the new data pattern
contained in the instruction and the part is ready for a next instruction.
WRITE (AK93C85A)
WRITE (AK93C95A)
WRITE (AK93C10A)
17
Busy
16
Hi-Z
0
tE/W
CS
SK
DI
DO
Start Bit Op code
Ready
A
K93C10A output a logic "1 " (Ready status),
if previous instruction is WRITE.
D0
1 2 3 4 5 1415 293031
D1D2D14D15A0A1A101010 A11
Busy
16
Hi-Z
0
tE/W
CS
SK
DI
DO
Start Bit Op code
Ready
A
K93C95A output a logic "1 " (Ready status),
if previous instruction is WRITE.
D0
1 2 3 4 5 1415 282930
D1D2D14D15A0A1A91010 A10
13
Hi-Z
0
tE/W
CS
SK
DI
DO
Start Bit Op code
tCS
Busy Ready
A
K93C85A output a logic "1 " (Ready status),
if previous instruction is WRITE.
D0
1 2 3 4 5 1415 272829
D1D2D14D15A0A1A81010 A9
12 13
ASAHI KASEI [AK93C85A/95A/10A]
DAM02E-03 2004/05
- 6 -
READ
The read instruction is the only instruction which outputs serial data on the DO pin.
Following the Start bit, first Op code and address are decoded, then the data from the selected
memory location is available at the DO pin. A dummy bit (logical "0") precedes the 16-bit data from
the selected memory location. The output data changes are synchronized with the rising edges of
the serial clock (SK).
The data in the next address can be read sequentially by continuing to provide clock. The address
automatically cycles to the next higher address after the 16bit data shifted out.
AK93C85A・・When the highest address is reached ($3FF), the address counter rolls over
to address $000 allowing the read cycle to be continued indefinitely.
AK93C95A・・When the highest address is reached ($7FF), the address counter rolls over
to address $000 allowing the read cycle to be continued indefinitely.
AK93C10A・・When the highest address is reached ($FFF), the address counter rolls over
to address $000 allowing the read cycle to be continued indefinitely.
READ (AK93C85A)
READ (AK93C95A)
READ (AK93C10A)
1716
address[A11–A0]+1
A
K93C10A output a logic "1" (Ready s t atus),
if previous in st ruction is W R ITE.
Hi-ZHi-Z
Dummy
Bit address[A11–A0]
0
CS
SK
DI
DO
Start bit Op code
D0
12345 1415
D14D15
A0A1A10A110110
31 32 46 47
D15 D1 D00
16
address[A10–A0]+1
A
K93C95A output a logic "1" (Ready s t atus),
if previous in st ruction is W R ITE.
Hi-ZHi-Z
Dummy
Bit address[A10–A0]
0
CS
SK
DI
DO
Start bit Op code
D0
12345 131415
D14D15
A0A1A9A100110
30 31 45 46
D15 D1 D00
address[A9–A0]+1
A
K93C85A output a logic "1" (Ready s t atus),
if previous in st ruction is W R ITE.
Hi-ZHi-Z
Dummy
Bit address[A9–A0]
0
CS
SK
DI
DO
Start bit Op code
D0
1 2 3 4 5 12131415
D14D15
A0A1A8A90110
29 30 44 45
D15 D1 D00
ASAHI KASEI [AK93C85A/95A/10A]
DAM02E-03 2004/05
- 7 -
EWEN / EWDS
When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable
state. In the ERASE/WRITE disable state, execution of WRITE instruction is disable. Before
WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable
state continues until EWDS instruction is executed or VCC is removed from the part.
Execution of a read instruction is independent of both EWEN and EWDS instructions.
EWEN / EWDS (AK93C85A)
EWEN / EWDS (AK93C95A)
EWEN / EWDS (AK93C10A)
A
K93C10A output a logic "1" (Ready statu s),
if previous instruction is WRITE.
Start bit
Hi-Z
X: Don't care
EWDS=00
0
CS
SK
DI
DO
12345 12 15
0010
67
XXXX
EWEN=11 XX
89
XX
10 11 13
X
14
X
A
K93C95A output a log ic "1" (Ready status),
if previo us i n st ruction is WRITE.
Start bit
Hi-Z
X: Don't care
EWDS=00
0
CS
SK
DI
DO
12345 12 14
0010
67
XXXX
EWEN=11 XX
89
XX
10 11 13
X
A
K93C85A output a logic "1" (Ready s tatus),
if previous instruction is WRITE.
Start bit
Hi-Z
X: Don't care
EWDS=00
0
CS
SK
DI
DO
12345 1213
0010
67
XXXX
EWEN=11 XX
89
XX
10 11
ASAHI KASEI [AK93C85A/95A/10A]
DAM02E-03 2004/05
- 8 -
Absolute Maximum Ratings
Parameter Symbol Min Max Unit
Power Supply VCC -0.6 +7.0 V
All Input Voltages
with Respect to Ground VIO
-0.6
VCC+0.6
V
Ambient storage temperature Tst -65 +150 °C
Stress above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
Recommended Operating Condition
Parameter Symbol Min Max Unit
Power Supply VCC 1.8 5.5 V
Ambient Operating Temperature Ta -40 +85 °C
ASAHI KASEI [AK93C85A/95A/10A]
DAM02E-03 2004/05
- 9 -
Electrical Characteristics
(1) D.C. ELECTRICAL CHARACTERISTICS
( 1.8V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Parameter Symbol Condition Min. Max. Unit
ICC1 VCC=5.5V, tSKP=1.0µs, *1 5.5 mA
Current Dissipation
(WRITE) ICC2 VCC=1.8V, tSKP=4.0µs, *1 3.0 mA
ICC3 VCC=5.5V, tSKP=1.0µs, *1 0.4 mA
Current Dissipation
(READ, EWEN, EWDS) ICC4 VCC=1.8V, tSKP=4.0µs, *1 0.1 mA
Current Dissipation
(Standby) ICCSB
VCC=5.5V *2
0.8
µA
Input High Vo ltage VIH 0.8 x VCC VCC + 0.5 V
Input Low Vo ltage VIL -0.1 0.2 x VCC V
Output High Voltage
VOH1
2.5V ≤ VCC ≤ 5.5V
IOH=-0.1mA 0.8 x VCC
V
VOH2
1.8V ≤ VCC < 2.5V
IOH=-0.1mA 0.8 x VCC
V
Output Low Voltage
VOL1
2.5V ≤ VCC ≤ 5.5V
IOL=1.0mA
0.4
V
VOL2
1.8V ≤ VCC < 2.5V
IOL=0.1mA
0.4
V
Input Leakage
ILI
VCC=5.5V, VIN=5.5V
±1.0
µA
Output Leakage
ILO
VCC=5.5V,
VOUT=5.5V, CS=GND
±1.0
µA
*1 : VIN=VIH/VIL, DO=Open
*2 : VIN=VCC/GND, CS=GND, DO=Open
ASAHI KASEI [AK93C85A/95A/10A]
DAM02E-03 2004/05
- 10 -
(2) A.C. ELECTRICAL CHARACTERISTICS
( 1.8V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Parameter Symbol Condition Min. Max. Unit
tSKP1 4.5V ≤ VCC ≤ 5.5V 1.0 µs
SK Cycle Time
tSKP2 2.0V ≤ VCC < 4.5V 2.0 µs
tSKP3
1.8V ≤ VCC < 2.0V 4.0 µs
tSKW1 4.5V ≤ VCC ≤ 5.5V 500 ns
SK Pulse Width
tSKW2 2.0V ≤ VCC < 4.5V 1.0 µs
tSKW3
1.8V ≤ VCC < 2.0V 2.0 µs
CS Setup Time tCSS 100 ns
CS Hold Time tCSH 0 ns
Data Setup Time tDIS 200 ns
Data Hold Time tDIH 200 ns
tPD1 4.5V ≤ VCC ≤ 5.5V 500 ns
Output delay *3
tPD2 2.0V ≤ VCC < 4.5V 1.0
µs
tPD3
1.8V ≤ VCC < 2.0V 2.0
µs
tE/W1 4.5V ≤ VCC ≤ 5.5V 8 ms
Selftimed
Programming T ime tE/W2 1.8V ≤ VCC < 4.5V 10 ms
Min CS Low Time tCS 250 ns
CS to Status Valid1 tSV CL=100pF 500 ns
CS to Status Valid2 tSVV CL=100pF 1000 ns
tOZ1 2.0V ≤ VCC ≤ 5.5V 100 ns
CS to Output High-Z
tOZ2 1.8V ≤ VCC < 2.0V 250 ns
*3 : CL=100pF
ASAHI KASEI [AK93C85A/95A/10A]
DAM02E-03 2004/05
- 11 -
Synchronous Data timing
The Start of Instruction
The End of Instruction
Hi-Z
CS tCSS
tDIS tDIH
1
DI
DO
SK
tSKW tSKW
0
tSKP
tSV
A
K93C85A/95A/10A output a logical "1" (Ready status),
if previous instruction is WRITE.
tCS
Hi-Z
CS
DI
DO
SK
tCSH
tPD tPD tPD tOZ
D2D3 D1 D0
ASAHI KASEI [AK93C85A/95A/10A]
DAM02E-03 2004/05
- 12 -
Busy/Ready Signal Output (AK93C85A)
Busy/Ready Signal Output (AK93C95A/10A)
Hi-Z
CS
tDIS tDIH
D1
DI
DO
SK
D0
tSVV
tE/W
Busy Ready
tOZ
Hi-Z
CS tCSH
tDIS tDIH
D1
DI
DO
SK
D0
tSV
tCS
tE/W
Busy Ready
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to an y
such use, except with the express written consent of the Representative Director of AKM. As used
here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or propert y.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
