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SC2440
2.5 MHz Dual Switching Regulator
with Integrated 2A Switches
POWER MANAGEMENT
Revision: March 5, 2007
Description Features
Applications
Typical Application Circuit
uUp to 2.5 MHz/Channel Programmable Switching
Frequency
uFixed Frequency Current-mode Control
uWide Input Voltage Range 2.8V to 20V
uOut of Phase Switching Reduces Ripple
uCycle-by-cycle Current-limiting
uIndependent Shutdown/soft-start Pins
uIndependent Hiccup Overload Protection
uIndependent Power-Good Indicators
uTwo 2A Integrated Switches
uExternal Synchronization
uThermal Shutdown
uThermally Enhanced 16-pin TSSOP Package
The SC2440 is an adjustable frequency dual current-
mode switching regulator with 2A integrated switches.
Its high frequency operation allows the use of small
inductors and capacitors, resulting in very compact power
supplies. The SC2440 is suitable for next generation XDSL
modems requiring operating frequencies in excess of 1.5
MHz. The two channels operate at 180° out of phase
for reduced input voltage ripples. Separate soft start/
shutdown pins allow independent control and output
sequencing for latch-up prevention. The SC2440 can also
be externally synchronized up to 2.5 MHz per channel.
Current-mode PWM control allows fast transient
response with simple loop compensation. Cycle-by-cycle
current limiting and hiccup overload protection reduce
power dissipation during overload. uXDSL and Cable Modems
uSet-up Boxes
uPoint of Load Applications
uCPE Equipment
uDSP Power Supplies
uDisk Drives
C15
10µF
R3
40.2K
SC2440
GND
SS2
IN
SW1
FB2
ROSC
COMP2
C9
10pF
R7
24.3K
BOOST1
C1
10µF
BOOST2
SW2
L1
3.3µH
C2
0.1µF
L2
4.4µH
C4
0.1µF
PGOOD2
SS1
PGOOD1
COMP1
FB1
C3
10µF
D1
UPS120
D2
UPS120
R8
100K
R6
100K
R9
15K
OUT1
3.3V/2A
10K
R4
10K
R2
R1
23.3K
C7
22nF
C10
22nF
C8
220pF
C6
10pF
R5
15.4K
C5
470pF
D4
1N4148
SYNC
L1: Sumida CR43
L2: Falco D04012
OUT2
5V/2A
D3
1N4148
VIN
12V
Efficiency vs Load Current
Figure 1. 1.3MHz 12V to 3.3V and 5V Step-down Converter
50
55
60
65
70
75
80
85
90
95
00.5 11.5 2
Load Current (A)
Efficiency (%)
VOUT2 = 5V
VOUT1 = 3.3V
VIN = 12V
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SC2440
POWER MANAGEMENT
Absolute Maximum Ratings
Electrical Characteristics
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter Symbol Max Units
Input Voltage VIN -0.3 to 20 V
Boost Pin VBST 40 V
Boost Pin Above SW VBST-VSW 20 V
PGOOD Pin Voltage VPGOOD VIN V
SS Pins VSS 3V
FB Pins VFB -0.3 to VIN V
SYNC Pin Current ISYNC 5mA
SW Voltage VSW -0.6 to VIN V
SW Transient Spikes (<10ns Duration) VSW
VIN +1.5 V
-2.5
Operating Ambient Temperature Range TA-40 to 85 °C
Thermal Resistance Junction to Ambient θJA 45 °C/W
Maximum Junction Temperature TJ150 °C
Storage Temperature Range TSTG -65 to +150 °C
Lead Temperature (Soldering)10 sec TLEAD 300 °C
Parameter Conditions Min Typ Max Units
VIN Start Voltage 2.45 2.62 2.78 V
VIN Start Hysteresis 75 mV
Quiescent Current Not switching, PGOOD Open 3.3 4.3 mA
Shutdown Current VSS1 = VSS2 = 0V, PGOOD Open 38 60 µA
Feedback Voltage 0.980 1.000 1.020 V
Feedback Voltage Line
Regulation VIN = 3V to 20V 0.005 %/V
FB Pin Input Bias Current VFB = 1V, VCOMP = 1.5V -15 -30 nA
Error Amplifier Transconductance 280 µΩ-1
Error Amplifier Open-loop Gain 53 dB
COMP Source Current VFB = 0.8V, VCOMP = 1.5V 20 µA
COMP Sink Current VFB = 1.2V, VCOMP = 1.5V 20 µA
COMP Pin to Switch Current Gain 5.7 A/V
Unless specified: -40°C < TA < 85°C, -40°C < TJ< 105°C, ROSC = 12.1KΩ, VSYNC = 0, VIN = 5V, VBOOST = 8V
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SC2440
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: -40°C < TA < 85°C, -40°C < TJ< 105°C, ROSC = 12.1KΩ, VSYNC = 0, VIN = 5V, VBOOST = 8V
Parameter Conditions Min Typ Max Units
COMP Switching Threshold 0.7 1.1 1.3 V
COMP Maximum Voltage VFB = 0.9V 2.2 V
Channel Switching Frequecy 1.2 1.4 1.6 MHz
Maximum Duty Cycle (Note 2) 80 90 %
Switch Current Limit VFB = 0.9V, VSS = 2.3V, COMP Pin Open 22.6 A
Switch Saturation Voltage ISW = -2A 0.3 0.48 V
Switch Leakage Current 10 µA
Minimum Boost Voltage ISW = -2A 1.8 2.5 V
Boost Pin Current ISW = -0.5A 20 30 mA
ISW = -2A 60 80 mA
Minimum Soft-Start Voltage to Exit
Shutdown SS1 Tied to SS2 0.2 0.4 0.7 V
Soft-start Charging Current VSS = 0V 2µA
VSS = 1.5V 1.8 µA
Soft-start Discharging Current VSS = 1.5V 0.8 µA
Minimum Soft-start Voltage to
Enable Overload Shutoff VSS Rising 2V
FB Overload Threshold VSS = 2.3V, VFB Falling 0.74 V
Soft-start Voltage to Restart
Switching After Overload Shutoff VSS Falling 0.7 11.3 V
Power Good Threshold Below FB VFB Rising 80 100 120 mV
Power Good Output Low Voltage VFB = 0.8V, IPGOOD = 250µA 0.2 0.4 V
Power Good Pin Leakage Current VPGOOD = 5V 0.1 1µA
SYNC Input High Voltage 2V
SYNC Input Low Voltage (Note 1) 0.8 V
SYNC Frequency SYNC Frequency = 2 X Channel
Frequency. (Note 1) 3.4 5MHz
SYNC Pin Input Current VSYNC = 2V 60 75 µA
Thermal Shutdown Temperature 155 °C
Thermal Shutdown Hysteresis 10 °C
Notes: (1) Guaranteed by design, not tested in production.
(2) The maximum duty cycle specified corresponds to 1.4MHz switching frequency. Duty cycles higher than those specified can be
achieved by lowering the operating frequency.
(3) This device is ESD sensitive. Use of standard ESD handling precautions is required.
42005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Pin Configuration Ordering Information
Underside metal must be soldered to ground.
Pin # Pin Name Pin Function
1, 8 BOOST1,
BOOST2 Supply pins to the power transistor drivers.Tie to external diode-capacitor charge pumps to
generate drive voltages higher than VIN in order to fully saturate the internal NPN power switches.
2, 7 SW1, SW2 Emitters of the internal power NPN transistors. Connect to the inductors, the freewheeling diodes
and the boost capacitors.
3, 6 IN Input power supply pins of the SC2440 and also the common collector of the internal power
NPNs. Pins 3 and 6 are internally tied together and must be locally bypassed.
4SYNC Driving the SYNC pin with an external clock synchronizes both step-down converters. The
external clock frequency must be at least twice the individual regulator set (or free-running)
frequency. Tie this pin to ground if not used.
5ROSC An external resistor between this pin and the ground sets the master oscillator free-running
frequency. The set frequency is twice that of the individual switching regulator.
9, 16 FB1, FB2 The inverting inputs of the error amplifiers. Each FB pin is tied to a resistive divider between its
output and the ground for setting the channel output voltage.
10, 15 COMP1,
COMP2
These are the outputs of the internal error amplifiers. The voltages on these pins control the peak
switch currents. RC networks at these pins compensate the control loops. Pulling either pin below
0.7V stops the corresponding switching regulator.
11, 14 PGOOD1,
PGOOD2
Open collector outputs of the Power Good comparators. Tie to external pull-up resistors from the
input or the output of the converter. The PGOOD outputs become valid as soon as VIN rises
above 1 VBE during power-up. PGOOD is actively pulled low until the corresponding FB pin rises
to within 10% of the final regulation voltage.
12, 13 SS1, SS2
A capacitor from either SS pin to the ground provides soft-start and overload hiccup functions
for that channel. Pulling either SS pin below 0.8V with an open drain or collector transistor shuts
off the corresponding regulator. To completely shut off the SC2440 to low-current state, pull both
SS pins to the ground. Soft-start is recommended for all applications.
Underside
Metal GND The exposed pad at the bottom of the package is the electrical ground connection of the
SC2440. It also provides a thermal contact to the circuit board. It is to be soldered to the ground
plane of the board.
Pin Descriptions
Part Number Package(1)(2)
SC2440TETRT TSSOP-16 EDP
SC2440EVB Evaluation Board
Notes:
(1) Only available in tape and reel packaging. A reel contains
2500 devices.
(2) Lead free product. This product is fully WEEE and RoHS
compliant.
1
2
3
4
5
6
7
8
FB1
BOOST1
TOP VIEW
(16 Pin TSSOP
-
EDP)
13
12
14
15
16
11
10
9
COMP1
SW1
PGOOD1
IN
SS1
SYNC
SS2
ROSC
PGOOD2
IN
COMP2
SW2
FB2
BOOST2
52005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Block Diagrams
PGOOD1
COMP1
TRANSISTOR
ROSC
IN
3
FB1
SW1
EA R Q
S
PWM
-
+
+
-
POWER
SLOPE
COMP 1
+
+ +
-
ISEN
ILIM
+
-
20mV
ΣΣ
7.7mΩ
BOOST1
SS1
OSCILLATOR CLK2
CLK1
FREQUENCY
DIVIDER
SLOPE COMP
SYNC
SLOPE
COMP 2
SLOPE
COMP 1
SS2 REFERENCE
& THERMAL
SHUTDOWN
1V
FAULT
OVLD
Soft-Start
And
Overload
Hiccup
Control 1
0.74V
FB1
POWER
GOOD
-
+
100mV
1
2
16
5
4
12
13
15
14
Figure 2. SC2440 Functional Diagram (One of Two Converters Shown)
FAULT
SS
OVLD
1V/2V
S
Q
R
+
-
1.8µA
2.6µA
FB
0.74V
Figure 3. Details of the Soft-Start and Overload Hiccup Control Circuit
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SC2440
POWER MANAGEMENT
Typical Characteristics
Frequency Setting Resistor
vs Channel Frequency
1
10
100
1000
00.5 11.5 22.5 3
Frequency (MHz)
ROSC (KΩ
Ω)
VIN = 5V
Feedback Voltage vs Temperature
0.97
0.98
0.99
1.00
1.01
1.02
-50 -25 0 25 50 75 100 125
Temperature (°C)
VFB (V)
VIN = 5V
Switch Saturation Voltage
vs Switch Current
100
200
300
400
0.0 0.5 1.0 1.5 2.0 2.5
Switch Current (A)
VCESAT (mV)
25°C
125°C
-40°C
VIN Start Threshold vs Temperature
2.4
2.5
2.6
2.7
2.8
-50 -25 025 50 75 100 125
Temperature (°C)
VIN Threshold (V)
SYNC Input Logic Thresholds
vs Temperature
1.0
1.2
1.4
1.6
1.8
-50 -25 025 50 75 100 125
Temperature (°C)
VIH
VIL
Channel Frequency vs Temperature
1.2
1.3
1.4
1.5
1.6
-50 -25 0 25 50 75 100 125
Temperature (°C)
Frequency (MHz)
ROSC =12.1KΩ
SS Shutdown Threshold
vs Temperature
0.20
0.25
0.30
0.35
0.40
-50 -25 025 50 75 100 125
Temperature (°C)
SS Threshold (V)
VSS1 = VSS2
Boost Pin Current
vs Switch Current
0
20
40
60
80
0.0 0.5 1.0 1.5 2.0 2.5
Switch Current (A)
Boost Pin Current (mA)
125°C
-40°C
VIN = 5V
VBST = 8V
Switch Current Limit
vs Temperature
2.0
2.2
2.4
2.6
2.8
3.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Current Limit (A)
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SC2440
POWER MANAGEMENT
Typical Characteristics
Soft-Start Pin Current
vs Soft-Start Voltage
-120
-100
-80
-60
-40
-20
0
0.0 0.5 1.0 1.5 2.0
VSS (V)
ISS (µ
µA)
ISS of the Other
Channel (V SS = 0)
ISS of the
Swept Channel
T = 25°C
VIN =5V
FB Overload Threshold
vs Temperature
0.5
0.6
0.7
0.8
0.9
1.0
-50 -25 025 50 75 100 125
Temperature (°C)
FB Threshold (V)
VIN Quiescent Current vs VIN
0
1
2
3
4
0 5 10 15 20
VIN (V)
VIN Current (mA)
25°C
-40°C
105°C
VIN Shutdown Current vs VIN
0
25
50
75
100
125
150
0 5 10 15 20
VIN (V)
VIN Current (µ
µA)
105°C
-40°C
SS1 = SS2 = 0
PGOOD Threshold to Feedback
Difference Voltage vs Temperature
-100
-98
-96
-94
-92
-90
-50 -25 025 50 75 100
125
Temperature (°C)
Voltage (mV)
VIN Supply Current
vs Soft-Start Voltage
0
1
2
3
4
0.0 0.5 1.0 1.5 2.0
V
SS
(V)
IIN (mA)
VSS1 = V SS2
TA = 25°C
VIN = 5V
VCOMP1 = 0
VCOMP2 = 0
82005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Operation
The SC2440 is a 2-channel constant-frequency peak
current-mode step-down switching regulator with
integrated 2A power transistors. Both regulators of the
SC2440 operate from a common input power supply and
share the same voltage reference, the master oscillator
and the synchronizing circuit. Turn-on of the power
transistors are phase-shifted by 180°. The two regulators
are otherwise completely identical, independent and are
capable of producing two separate outputs from the
same input.
The master oscillator of the SC2440 runs at twice the
channel frequency. The free-running frequency of the
master oscillator can be programmed with an external
resistor from the ROSC pin to ground. Frequency
adjustability makes switching regulator design flexible.
Peak current-mode control is utilized for the SC2440.
The double reactive poles of the output LC filter are
reduced to a single real pole by the inner current loop,
easing loop compensation. Fast transient response can
be achieved with a simple Type-2 compensation network.
Switch collector current is sensed with an integrated 7.7mΩ
sense resistor. The sensed current is summed with slope-
compensating ramp before it is compared with the
transconductance error amplifier output. The PWM
comparator tripping instant determines the switch turn-
on pulse width (Figure 2). The current-limit comparator
ILIM turns off the power switch when the sensed-signal
exceeds the 20mV current-limit threshold. ILIM therefore
provides cycle-by-cycle limit. Current-limit does not vary
with duty-cycle.
Driving the base of the power transistor above the input
power supply rail minimizes the power transistor turn-on
voltage and maximizes efficiency. An external charge
pump (formed by the capacitor C2 and the diode D3 in
Figure 1) generates a voltage higher than the input rail
at the BOOST pin. The bootstrapped voltage generated
becomes the supply voltage for the power transistor
driver.
The SS pin is a multiple-function pin. An external capacitor
connected from the SS pin to the ground together with
the internal 1.8µA and 2.6µA current sources set the
soft-start and overload shutoff times of the regulator (Figure
3). The SS pin can also be used to shut off the corresponding
regulator. When either SS pin is pulled below 0.8V, that
regulator is turned off. If both SS pins are pulled below
0.2V, then the SC2440 undergoes overall shutdown. The
current draw from the input power supply reduces to 38µA.
When either SS pin is released, the corresponding soft-
start capacitor is charged with a 2µA current source (not
shown in Figure 3). As either SS voltage exceeds 0.3V, the
internal bias circuit of the SC2440 is enabled. The SC2440
draws 3.3mA from VIN. An internal fast charge circuit
quickly charges the soft-start capacitor to 1V. At this
juncture, the fast charge circuit turns off and the 1.8µA
current source slowly charges the soft-start capacitor. The
output of the error amplifier is forced to track the slow
soft-start ramp at the SS pin. When the COMP voltage
exceeds 1.1V, the switching regulator starts to switch.
During soft-start, the current limit of the converter is
gradually increased until the converter output comes into
regulation.
Hiccup overload protection is utilized in the SC2440.
Overload shutdown is disabled during soft-start (VSS <
2V). In Figure 3 the reset input of the overload latch will
remain high if the SS voltage is below 2V. Once the soft-
start capacitor is charged above 2V, the overload
shutdown latch is enabled. As the load draws more current
from the regulator, the current-limit comparator will limit
the peak inductor current. This is cycle-by-cycle current
limiting. Further increase in load current will cause the
output voltage to decrease. If the output voltage falls
below 74% of its set point, then the overload latch will be
set and the soft-start capacitor will be discharged with a
net current of 0.8µA. The switching regulator is shut off
until the soft-start capacitor is discharged below 1V. At
this moment, the overload latch is reset. The soft-start
capacitor is recharged and the converter again undergoes
soft-start. The regulator will go through soft-start, overload
shutdown and restart until it is no longer overloaded.
Each regulator of the SC2440 has its own power good
comparator. The open collector output of the power good
comparator will be actively pulled low if the corresponding
feedback voltage is below 0.9V.
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SC2440
POWER MANAGEMENT
Applications Information
Setting the Output Voltage
The regulator output voltage is set with an external
resistive divider (Figure 4) with its center tap tied to the
FB pin.
)1V(RR OUT21 −= (1)
The percentage error due the input bias current of the
error amplifier is
V1
)RR(100nA15
V
V21
OUT
OUT ⎪⎢⋅⋅−
=
∆.
Example: Determine the output voltage error of a
V5VOUT =converter with Ω= K1.51R2.
From (1),
Ω=−⋅Ω= K205)15(K1.51R1
%061.0
V1
)K205K1.51(100nA15
V
V
OUT
OUT −=
⎪⎢⋅⋅−
=
∆.
This error is at least an order of magnitude lower than
the ratio tolerance resulting from the use of 1% resistors
in the divider string.
Choosing the Operating Frequency
The free-running frequency of the mastermaster
mastermaster
master oscillator is
set with an external resistor from the ROSC pin to ground.
Channel frequency is one-half of that of the master
oscillator. A graph of channelchannel
channelchannel
channel frequency against ROSC is
shown in the “Typical Performance Characteristics”.
Before choosing the operating frequency, tradeoffs
among efficiency, operating duty cycle, component size
and EMI interferences must be considered. High
frequency operation reduces the size of passive
components but switching losses are higher. Lowering
the switching frequency improves efficiency. However the
required inductor and capacitor are larger. Channel
frequencies between 1 and 2MHz are good compromises.
In order to quantify the tradeoff between switching
frequency and efficiency, the 12V to 5V DC-DC converter
in Figure 1 is modified to run at 500KHz and 2.5MHz
while keeping the inductor ripple current constant. The
modified component values are tabulated in Table 1 and
efficiencies at these frequencies are shown in Figure 5.
The efficiency of the 1.3MHz 5V regulator in Figure 1 is
also plotted for the ease of comparison. The efficiency
at 500KHz is only marginally higher than that at 1.3MHz.
The peak efficiency at 2.5MHz is only 2% lower compared
to those at lower frequencies.
VOUT
R2
R1
15nA
FB
SC2440
Figure 4. VOUT is set with a Resistive Divider
f)zHM(R
9
K( Ω)L
2
(µ)HR
7
K( Ω)C
8
)Fp(C
9
)Fp(
5.06.35)001-37RDscinortlioC(014.2107422
3.10.51)21040DoclaF(44.43.4202201
5.220.4)7R2-34RCadimuS(7.24.2302201
Table 1. The 12V to 5V Converter in Figure 1 is modified
to run at Different Frequencies.
Eff iciency vs Load Curr ent
75
80
85
90
0.0 0.5 1.0 1.5 2.
0
Load Current (A)
Efficiency (%)
V
IN=12V
V
OUT=5V
2.5MHz
1.3MHz
500KHz
Figure 5. Efficiencies of 500KHz, 1.3MHz and 2.5MHz
12V to 5V Step-down Converters.
102005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Minimum On Time Consideration
The operating duty cycle of a step-down switching
regulator with diode rectifier in continuous-conduction
mode (CCM) is given by
CESATDIN
DOUT VVV
V
V
D−+
+
= (2)
where VCESAT is the switch saturation voltage and VD is
voltage drop across the rectifying diode.
Duty cycle decreases with increasing OUT
IN
V
V
ratio. In peak
current-mode control, the PWM modulating ramp is the
sensed current ramp of the power switch. This current
ramp is absent unless the switch is turned on. The
intersection of this ramp with the output of the voltage
feedback error amplifier determines the switch pulse
width. The propagation delay time required to
immediately turn off the switch after it is turned on is
the minimum switch on time (TON(MIN)). Closed-loop
measurement of the SC2440 with low IN
OUT
V
V
ratios shows
that the minimum on time is about 105ns at room
temperature. TON(MIN) also exhibits a slight positive
temperature coefficient (Figure 6). The power switch in
the SC2440 is either not turned on at all or for at least
TON(MIN). If the required switch on time (=
) is shorter
than the minimum on time, the regulator will either skip
cycles or it will jitter.
Example: Determine the maximum operating frequency
of a dual 12V to 1.0V and 12V to 3.3V switching
regulator using the SC2440.
Assuming that VD = 0.45V, VCESAT = 0.25V and VIN = 13.2V
(10% high line), the corresponding duty ratios, D1 and
D2, of the 1.0V and 3.3V converters can be calculated
using (2).
11.0
25
.
0
45
.
0
2
.
13
45
.
0
1
D1=
−+
+
=
Applications Information
28.0
25
.
0
45
.
0
2
.
13
45
.
0
3
.
3
D2=
−+
+
=
If the ambient temperature can be as high as 85°C, then
the maximum operating frequencies of the 1.0V and the
3.3V converters will be KHz920
ns
120
D
1= and
MHz3.2
ns
120
D
2= respectively..
Channel frequency should be set below 920KHz to allow
margin for load transient.
Minimum Off Time Limitation
The PWM latch in Figure 2 is reset every period by the
clock. The clock also turns off the power transistor to
refresh the bootstrap capacitor. This minimum off time
limits the attainable duty cycle of the regulator at a given
switching frequency. Measurement shows that the power
transistor needs to be turned off for at least 120ns every
switching period to properly reset the latch and to refresh
the bootstrap capacitor. For a step-down converter, D
increases with increasing IN
OUT
V
V
ratio. If the required duty
cycle is higher than the attainable maximum, then the
Figure 6. Variation of Minimum On Time with
Temperature.
Minimum On Time vs Temperature
80
90
100
110
120
130
-40 -20 020 40 60 80 100
Temperature (°C)
TON(MIN) (ns)
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SC2440
POWER MANAGEMENT
output voltage will not be able to reach its set value in
continuous-conduction mode.
Example: Determine the maximum operating frequency
of a dual 3.3V to 1.8V and 3.3V to 2.5V switching
regulator using the SC2440.
Assuming that VD = 0.45V, VCESAT = 0.25V and VIN = 2.97V
(10% low line), the duty ratios
1
D
and
2
D
of the 1.8V
and 2.5V converters can be calculated using (2).
71.0
25
.
0
45
.
0
97
.
2
45
.
0
8
.
1
D1=
−+
+
=
93.0
25
.
0
45
.
0
97
.
2
45
.
0
5
.
2
D2=
−+
+
=.
The maximum operating frequencies of the 1.8V and the
2.5V converters are therefore MHz4.2
ns
120
D
1
1=
−
and
KHz580
ns
120
D
1
2=
−
respectively..
Transient headroom requires that channel frequency be
lower than 580KHz.
External Synchronization
The SYNC input buffer is positive-edge triggered and TTL-
compatible (
V
8
.
0
V
IL
<
and
V
2
V
IH
>
). The free-running
master oscillator generates a periodic sawtooth ramp
between two threshold voltages. A faster external clock
applied to the SYNC pin discharges the internal ramp
before it reaches its upper threshold, thus locking the
internal oscillator. As shown in Figure 2, the master
oscillator is being synchronized not the individual phases
(see Figure 2). The synchronizing frequency should be
twicetwice the desired channelchannel frequency. Bench test shows
that an external clock with frequency ranging from slightly
below twice to at least 3.5 times the channelchannel free-
running frequency is capable of locking the master
oscillator. To ensure frequency locking, the external clock
frequency should be at least twicetwice the highesthighest free-
running channel channel frequency. The frequency of the
synchronizing clock should not be higher than 1.6 times
Applications Information the set frequency of master oscillator because the
amplitudes of the internal sawtooth ramp and slope
compensation ramp will both be significantly reduced.
Example: Choose the value of ROSC to externally
synchronize the SC2440 to 2MHz per channelchannel.
The required synchronizing clock frequency = 2 times
the channel frequency = 4MHz.
For a given ROSC, the free-running channelchannel frequency
has a tolerance of ±15%.
Set the nominal free-running channelchannel frequency to
MHz73.1
15
.
1
MHz
2
= to ensure locking.
Looking up the graph “Channel Frequency vs. ROSC” in
the Typical Characteristics, ROSC = 9.31KΩ for a set
frequency of 1.73MHz.
With ±15% tolerance, the set channel frequency can vary
from
(
)
MHz
47
.
1
73
.
1
85
.
0
=
⋅
to
(
)
MHz
2
73
.
1
15
.
1
=
⋅
.
Therefore
36.1
47.1
2
FrequencyrunningFreeLowest
Frequency
ing
Synchroniz
==
−.
Inductor Selection
The inductor ripple current ∆IL for a non-synchronous
step-down converter in continuous-conduction mode is
fL)VVV()VVV)(VV(
fL )D1)(VV(
ICESATDIN
CESATOUTINDOUTDOUT
L−+
−
−
+
=
−
+
=∆
(3)
where f is the switching frequency and L is the
inductance.
In current-mode control, the slope of the modulating
(sensed switch current) ramp should be steep enough
to lessen jittery tendency but not so steep that large
flux swing decreases efficiency. Inductor ripple current
∆IL between 25-40% of the peak inductor current limit is
a good compromise. Inductors so chosen are optimized
122005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Applications Information
in size and DCR. Setting
A
6
.
0
)
2
(
3
.
0
I
L
=
=
∆
,
V
45
.
0
V
D
=
and
V
25
.
0
V
CESAT
=
in (3),
f)6.0)(2.0V(
)
25
.
0
V
V
)(
45
.
0
V
(
LIN
OUTInOUT +
−
−
+
= (4)
where L is in µH and f is in MHz.
Equation (3) shows that for a given
,
V
OUT
L
I
∆
increases
as D decreases. If
IN
V
varies over a wide range, then
choose L based on the nominal input voltage. Always
verify converter operation at the input voltage extremes.
The peak current limits of both SC2440 power transistors
are internally set at 2.6A. The peak current limits are
duty-cycle invariant and are guaranteed higher than 2A.
The maximum load current is therefore conservatively
2
I
A2
2
I
II LL
LM)MAX(OUT
∆
−=
∆
−= (5)
If LML
I
3
.
0
I
⋅
=
∆
, then
LM
LM
LM
L
LM)MAX(OUT I85.0
2
I
3
.
0
I
2
I
II ⋅=−=
∆
−= .
The saturation current of the inductor should be 20-30%
higher than the peak current limit (2A). Low-cost powder
iron cores are not suitable for high-frequency switching
power supplies due to their high core losses. Inductors
with ferrite cores should be used.
Input Capacitor
A buck converter draws pulse current with peak-to-peak
amplitude equal to its output current IOUT from its input
supply. An input capacitor placed between the supply
and the buck converter filters the AC current and keeps
the current drawn from the supply to a DC constant. The
input capacitance CIN should be high enough to filter the
pulse input current. Its equivalent series resistance (ESR)
should be low so that power dissipated in the capacitor
does not result in significant temperature rise and
degrade reliability. For a single channel buck converter,
the RMS ripple current in the input capacitor is
)D1(DII OUTRMS )CIN(−= . (6)
Power dissipated in the input capacitor is )ESR(I2
RMS )CIN(⋅.
Equation (6) has a maximum value of
2
IOUT ( at
2
1
D=),
corresponding to the worst-case power dissipation
4
ESRI2
OUT ⋅ in CIN.
A dual-channel step-down converter with interleaved
switching reduces the RMS ripple current in the input
capacitor to a fraction of that of a single-phase buck
converter. If both power transistors in the SC2440 were
to switch on in phase, the current drawn by the SC2440
would consist of current pulses with amplitude equal to
the sum of the channel output currents. If each channel
were delivering IOUT and operating at 50% duty cycle, then
the input current would switch from zero to 2IOUT. The
RMS ripple current in the input capacitor would then be
IOUT. Power dissipated in CIN would be ESRI2
OUT ⋅, 4 times
that of a single-channel converter. The SC2440 produces
the highest RMS ripple current in CIN when only one
channel is running and delivering the maximum output
current (
A
2
5
.
1
−
≈
). The input capacitor therefore should
have a RMS ripple current rating of at least 1A.
Multi-layer ceramic capacitors, which have very low ESR
(a few mΩ) and can easily handle high RMS ripple current,
are the ideal choice for input filtering. A single 4.7µF or
10µF X5R ceramic capacitor is adequate. For high voltage
applications, a small ceramic (1µF or 2.2µF) can be placed
in parallel with a low ESR electrolytic capacitor to satisfy
both the ESR and bulk capacitance requirements.
Output Capacitor
The output ripple voltage ∆VOUT of a buck converter can
be expressed as
+∆=∆OUT
LOUT fC81
ESRIV (7)
where COUT is the output capacitance.
Inductor ripple current ∆IL increases as D decreases
(Equation (3)). The output ripple voltage is therefore the
highest when VIN is at its maximum. The first term in (7)
132005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Applications Information
results from the ESR of the output capacitor while the
second term is due to the charging and discharging of
COUT by the inductor ripple current. Substituting ∆IL = 0.6A,
f = 1MHz and COUT = 10µF ceramic with ESR = 3mΩ in
(7),
mV3.9mV5.7mV8.1
)
m
5
.
12
m
3
(
A
6
.
0
V
OUT =+=
Ω
+
Ω
⋅
=
∆
Depending on operating frequency and the type of
capacitor, ripple voltage resulting from charging and
discharging of COUT may be higer than that due to ESR. A
10µF or 22µF X5R ceramic capacitor is found adequate
for output filtering in most applications. Ripple current
in the output capacitor is not a concern because the
inductor current of a buck converter directly feeds COUT,
resulting in very low ripple current. Avoid using Z5U and
Y5V ceramic capacitors for output filtering because these
types of capacitors have high temperature and high
voltage coefficients.
Freewheeling Diode
Use of Schottky barrier diodes as freewheeling rectifiers
reduces diode reverse recovery input current spikes,
easing high-side current sensing in the SC2440. These
diodes should have a RMS current rating between 1A
and 2A and a reverse blocking voltage of at least 5V
higher than the input voltage. For switching regulators
operating at low duty cycles (i.e. low output voltage to
input voltage conversion ratios), it is beneficial to use
freewheeling diodes with somewhat higher RMS current
ratings (thus lower forward voltages). This is because the
diode conduction interval is much longer than that of
the transistor. Converter efficiency will be improved if
the voltage drop across the diode is lower.
The freewheeling diodes should be placed close to the
SW pins of the SC2440 to minimize ringing due to trace
inductance. Surface-mount equivalents of 1N5817 and
1N5819, MBRM120LT3 (ON Semi), UPS120 and
UPS140 (Micro-Semi) are all suitable.
Bootstrapping the Power Transistors
To maximize efficiency, the turn-on voltage across the
internal power NPN transistors should be minimized. If
these transistors are to be driven into saturation, then
their bases will have to be driven from a power supply
higher in voltage than VIN. The required driver supply
voltage (at least 2.5V higher than the SW voltage over
the industrial temperature range) is generated with a
bootstrap circuit (the diode DBST and the capacitor CBST in
Figure 8). The bootstrapped output (the common node
between DBST and CBST) is connected to the BOOST pin of
the SC2440. The power transistor in the SC2440 is first
switched on to build up current in the inductor. When
the transistor is switched off, the inductor current pulls
the SW node low, allowing CBST to be charged through
DBST. When the power switch is again turned on, the SW
voltage goes high. This brings the BOOST voltage to
BST
CSW
V
V
+
, thus back-biasing DBST. CBST voltage increases
with each subsequent switching cycle, as does the
bootstrapped voltage at the BOOST pin. After a number
of switching cycles, CBST will be fully charged to a voltage
approximately equal to that applied to the anode of DBST.
Figure 7 shows the typical minimum BOOST to SW voltage
required to fully saturate the power transistor. This
differential voltage (BST
C
V
=
) must be at least 1.8V at
room temperature. This is also specified in the “Electrical
Characteristics” as “Minimum Bootstrap Voltage”. The
minimum required VCBST increases as temperature
decreases. The bootstrap circuit reaches equilibrium
when the base charge drawn from CBST during transistor
on time is equal to the charge replenished during the off
interval.
Figure 7. Typical Minimum Bootstrap Voltage Re-
quired to Maintain Saturation at ISW = 2A.
Minimum Bootstrap Voltage
vs Temperature
1.4
1.6
1.8
2.0
2.2
2.4
-50 -25 025 50 75 100
Temperature (°C)
Voltage (V)
142005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Applications Information
The switch base current â
I
1â
I
SWSW ≈
+
=, where ISW and β
are the switch emitter current and current gain
respectively, is drawn from the bootstrap capacitor CBST.
Charge â
T
I
ONSW is drawn from CBST during the switch on
time, resulting in a voltage droop of BST
ONSW
âC
T
I
. If ISW = 2A,
TON = 1µs, β = 35 and CBST = 0.1 µF, then the BST
C
V
droop
will be 0.57V. CBST is refreshed to RECTBST DDA
V
V
V
+
−
everyy
cycle, where A
V
is the applied DBST anode voltage. Switch
base current discharges the bootstrap capacitor to
BST
ONSW
DDAC
T
I
VVV RECTBST β
−+− at the end of conduction. The
difference between this voltage and that at SW must be
higher than the minimum shown in Figure 7 to maximize
efficiency. DBST can be tied either to the input or to the
output of the DC/DC converter.
If DBST is tied to the input, then the charge drawn from
the input power supply will be βONSWTI (the base charge
of the switch). The energy loss due to base charge per
cycle is βONINSW TVIfor a power loss of β
≈
βOUTSWINSW VIVDI .
If DBST is tied to the output, then the charge drawn from
the output capacitor will still be βONSWTI. The energy loss
due to base charge per cycle is βONOUTSW TVI for a power
Figure 8.Methods of Bootstrapping the SC2440.
MAX VBST = 2VIN
MAX VBST = VIN+ VOUT
MAX VBST = VIN + VSMAX VBST = VS
(a)
SC2440
BOOST
GND
IN
SW
DBST
VOUT
CBST
VIN
D
RECT
(b)
SC2440
BOOST
GND
IN
SW
DBST
VOUT
CBST
VIN
D
RECT
(d)
SC2440
BOOST
GND
IN
SW
DBST
VOUT VIN
VS > VIN + 2.5V
D
RECT
SC2440
BOOST
GND
IN
SW
DBST
VOUT
CBST
VIN
VS > 2.5V
(c)
D
RECT
152005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Applications Information
loss of βOUTSW VDI .
Since VOUT < VIN, DBST should always be tied to VOUT (if
>2.5V) to maximize efficiency. Measurement of the 2-
channel regulator in Figure 1 shows that the efficiency
penalties are about 1.3% (VOUT = 5V) and 2.2% (VOUT =
3.3V) with input bootstrapping. In general efficiency
penalty increases as D decreases.
Figure 8 summarizes various ways of bootstrapping the
SC2440. A fast switching PN diode (such as 1N4148 or
1N914) and a small (0.1µF – 0.47µF) ceramic capacitor
can be used. In Figure 8(a) the power switch is
bootstrapped from the output. This is the most efficient
configuration and it also results in the least voltage stress
at the BOOST pin. The maximum BOOST pin voltage is
about OUTIN
V
V
+
. If the output is below 2.8V, then DBSTT
will preferably be a small Schottky diode (such as BAT-
54) to maximize bootstrap voltage. A 0.33-0.47µF
bootstrap capacitor may be needed to reduce droop.
Bench measurement shows that using Schottky
bootstrapping diode has no noticeable efficiency benefit.
The SC2440 can also be bootstrapped from the input
(Figure 8(b)). This configuration is not as efficient as Figure
8(a). However this may be only option if the output
voltage is less than 2.5V and there is no other supply
with voltage higher than 2.5V. Voltage stress at the
BOOST pin can be somewhat higher than 2VIN. The BOOST
pin voltage should not exceed its absolute maximum
rating of 40V.
Figures 8(c) and (d) show how to bootstrap the SC2440
from a second independent power supply VS with voltage
> 2.5V. DBST in Figure 8(d) prevents start up difficulty if
VIN comes up before VS.
Since the inductor current charges CBST, the bootstrap
circuit requires some minimum load current to get going.
Figures 9(a) and 9(b) show the dependence of the
minimum input voltage required to properly bootstrap a
5V and a 3.3V converters on the load current. Once
started the bootstrap circuit is able to sustain itself down
to zero load.
Shutdown and Soft-Start
Each regulating channel of the SC2440 has its own soft-
start circuit. Pulling its soft-start pin below 0.8V with an
open-collector NPN or an open-drain NMOS transistor
turns off the corresponding regulator. The other regulator
continues to operate. With one channel turned off, the
internal bias circuit is kept alive. In the “Typical
Characteristics”, the soft-start pin current is plotted
against the soft-start voltage with VIN = 5V. When one of
Figure 9. Minimum Input Voltage Required to Start and to Maintain Bootstrap.(TA = 25°C).
Minimum Starting and
Sustaining VIN vs Load Current
4.5
5.0
5.5
6.0
6.5
7.0
7.5
1 10 100 1000
Load Current (mA)
Minimum Input Voltage (V)
DBST TIED
TO OUTPUT
DBST TIED
TO INPUT
VOUT = 5V
STARTING
SUSTAINING
MA729
(a) (b)
Minimum Starting and
Sustaining VIN vs Load Current
3.5
4.0
4.5
5.0
5.5
0.1 1.0 10.0 100.0 1000.0
Load Current (mA)
Minimum Input Voltage (V)
DBST TIED
TO OUTPUT
DBST TIED
TO INPUT
VOUT = 3.3V
STARTING
SUSTAINING
MA729
162005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Applications Information
the soft-start pins is pulled low, 105µA flows out of that
pin. Pulling both soft-start pins below 0.2V shuts off the
internal bias circuit of the SC2440. The total VIN current
decreases to 38µA. In shutdown either SS pin sources
only 2µA. A fast charging circuit (enabled by the internal
bias circuit), which charges the soft-start capacitor below
1V, causes the difference in the soft-start pin currents.
If either SS pin is released in shutdown, the internal
current source pulls up on the SS pin. When this SS
voltage reaches 0.3V, the SC2440 turns on and the VIN
quiescent current increases to 3.3mA. The current
flowing out of the other SS pin (which is still pulled low)
increases to 105µA. The fast charging circuit quickly pulls
the released soft-start capacitor to 1V (slightly below the
switching threshold). The fast charging circuit is then
disabled. A 1.8µA current source continues to charge
the soft-start capacitor (Figure 3). The soft-start voltage
ramp at the SS pin clamps the error amplifier output
(Figure 2). During regulator start-up, COMP voltage follows
the SS voltage. The converter starts to switch when its
COMP voltage exceeds 1.1V. The peak inductor current
gradually increases until the converter output comes into
regulation. Proper soft-start prevents output overshoot
during start-up. Current drawn from the input supply is
also well controlled. Notice that the inductor current, not
the converter output voltage, is ramped during soft-start.
Both soft-start capacitors are charged to a final voltage
of about 2.4V.
Figure 10(a).Normal Soft-start.
Fast
Charge
Output must be at
least 74% of its set
voltage in this
interval or the
regulator will
undergo shutdown
and restart
(hiccup).
Hiccup
Enabled
0.3V
1V
0
2V
2.4V
Switching Starts
V
SS
1V
0.74V
V
FB
0
1V
1V
2V
0.3V
0 Switching Not Switching Switching Not Switching
0
0.74V
1V
V
FB
V
SS V
COMP
Figure 10(b). Start-up Fails due to (i) Short Soft-start Duration or (ii) Output Overload or (iii)
Output Short-circuited.
172005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Applications Information
Overload / Short-Circuit Protection
Each current limit comparator in the SC2440 limits the
peak inductor current to 2.6A. The regulator output
voltage will fall if the load is increased above the current
limit. If overload is detected (the output voltage falls
below 74% of the set voltage), then the regulator will be
shut off. An internal 0.8µA current sink starts to
discharge the soft-start capacitor. As the soft-start
capacitor is discharged below 1V, the discharge current
source turns off and the soft-start capacitor is recharged
with a 1.8µA current source. The regulator undergoes
soft-start. During soft-start (1V < VSS < 2V), the overload
shutdown latch in Figure 3 cannot be set. When VSS
exceeds 2V, the set input of the overload latch is no
longer blanked. If VFB is still below 0.74V, then the
regulator will undergo shutdown and restart. The soft-
start process should allow the output voltage to reach
74% of its final value before CSS is charged above 2V.
Figures 10(a) and 10(b) show the timing diagrams of
successful and failed start-up waveforms respectively.
The soft-start interval should also be made sufficiently
long so that the output voltage rises monotonically and
it does not overshoot its final voltage by more than 5%.
When starting into a shorted output, the SC2440 will
repeatedly start and shut off (“hiccup”). VSS and VCOMP
will appear as asymmetrical triangular waves [Figure
10(b)].
Power Good Indicators
The PGOOD pins (Pins 11 and 14) are the open-collector
outputs of the power good comparators. These slow
comparators are incorporated with small amount of
hysteresis. The FB low-to-high trip voltage of the power
good comparators is 90% of the final regulation voltage.
A pull-up resistor from each PGOOD pin to the input supply
or the regulator output set the logic high level of the
comparator.
The power good comparator output becomes valid
provided that VIN is above 0.9V. In shutdown the power
good output is actively pulled low. A power good pull-up
resistor tied to the input will therefore increase current
drain during shutdown. Tying the power good pull-up
resistor to the regulator output is preferred, as this will
minimize the shutdown supply current. In shutdown there
(b)
ON
OFF SC2440
PGOOD1
SS1
SS2
CSS1
CSS2
PGOOD2
(a)
SC2440
PGOOD1
SS1
SS2
CSS1
PGOOD2
CSS2
CONTROL1
CONTROL2
ON
OFF
CONTROL1
ON
OFF
CONTROL2
T
D
Figure 11. Sequencing the Outputs by (a) Delaying Release of one Channel Relative to
the Other and (b) Using the PGOOD of one Channel to Control the Other.
182005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Applications Information
is no voltage at the switching regulator output or current
in the PGOOD pull-up resistor. If the PGOOD output high
level (= VOUT) is unacceptably low, then power good pull-
up from the input or a separate power supply will be the
only choice.
Sequencing the Outputs
As mentioned above, pulling either soft-start pin low with
an external transistor shuts off the corresponding
regulator (Figure 11). Releasing the soft-start pin enables
that channel and allows it to start. Delaying the release
of the soft-start pin of one channel with respect to the
other is a straightforward way of sequencing the outputs.
Figure 11(a) shows this method using two external
transistors M1 and M2. M1 is turned off first, allowing
channel 1 to start. Channel 2 is then enabled after time
TD.
The PGOOD output of one channel can also be used in
conjunction with the soft-start pin of the other channel
to delay start of that regulator. This method is depicted
in Figure 11(b). SS2 is pulled low and channel 2 is kept
off until channel 1 output rises to 90% of its set voltage.
A drawback of this approach is that only PGOOD2 is
available as a logic output.
Loop Compensation
Figure 12 shows a simplified equivalent circuit of a step-
down converter. The power stage, which consists of the
current-mode PWM comparator, the power switch, the
freewheeling diode and the inductor, feeds the output
network. The power stage can be modeled as a voltage-
controlled current source, producing an output current
proportional to its controlling input V
COMP. Its
transconductance GMP is 5.7Ω-1. With the current loop
closed, the control-to-output transfer function COMP
OUT
v
v
has
a dominant-pole p2 located at a frequency slightly higher
than that of the output filter pole.
1OUT1OUT
OUT
2pCR
n
CV
nI
−=−≈ω (8)
where C1 is the output capacitor, ROUT is the equivalent
load resistance and n (depending on duty ratio, slope
compensation, frequency and passive components) is
usually between 1 and 2.
If C1 is ceramic, then its ESR zero can be neglected as it
situates well beyond half the switching frequency. The
low frequency gain of the control-to-output transfer
function is simply the product of power stage
transconductance and the equivalent load resistance
(Figure 13).
The transfer functions of the feedback network and the
error amplifier are:
POWER
STAGE
GMP = 5.7Ω
REFERENCE
VOLTAGE
1V
+
-
R5
C5
C6
RO
R2
COMP
R1
FB
C11
ESR
C1
R
OUT
V
OUT
V
IN
I OUT
-1
GMA =
280µΩ
-1
V
Figure 12. Simplified Control Loop Equivalent Circuit
192005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Applications Information
( )
++
+
=1121
111
21
2
OUT
FB CRRs1RsC1
RR R
v
v (9)
and
(
)
( ) ( )
56O5
55OMA
FB
COMP RsC1RsC1
R
sC
1
R
G
v
v
+⋅+
+
≈ (10)
provided that 65
C
C
>>
and 5O
R
R
>>
.
In Equation (10), C5 forms a low frequency pole p1 with
the output resistance RO of the error amplifier and C6
forms a high frequency pole p3 with R5. Using the
component values shown in Figure 1 for the 12V to 3.3V
regulator (1.3MHz),
Ω=
Ωµ
== −M6.1
280
dB
53
cetancTranscondu
Gain
Loop
Open
Amplifier
R1
O
Hz210Krads3.1pF470M6.1
1
CR
1
1
5O
1p
−=−= •Ω
−=−=ω
−
MHz0.1Mrads5.6
pF10K4.15
1
CR
1
1
65
3p
−=−=
•Ω
−=−=ω
−
Bode Plots of Control-to-Ouput, Output-to-Control and the Overall Loop
Gain. Control-to-output transfer function is shown with two poles near
half the switching frequency ωS.
Figure 13.
2p
ω
1OUTCR
n
5OCR
1
1p
ω
3p
ω
65CR
1
55CR
1
1Z
ω
C
ω
ω
Gain
2
S
ω
OUTMP
R
G
+21
2
OMA RR R
RG
+21
2
5MA RR R
RG
n
RCOUT1C
ω
)j(Tω
OUT
COMP
v
v
Control-to-Output
Transfer Function
202005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Applications Information
In addition C5 and R5 form a zero with angular frequency:
KHz22Krads140
pF470K4.15
1
CR
1
1
55
1Z
−=−=
⋅Ω
−=−=ω
−
The output-to-control transfer function
OUT
FB
FB
COMP
OUT
COMP v
v
v
v
v
v
⋅=is also shown in Figure 13. Its mid-
band gain (between z1 and p3) is
+21
2
5MA RR R
RG. The
overall loop gain T(s) is the product of the control-to-
output and the output-to-control transfer functions. To
simplify )j(Tω Bode plot, the feedback network is
assumed to be resistive. If the overall loop gain is to
cross 0dB at one tenth of the switching frequency
(
5
f
10
S
C
π
=
ω
=ω) at –20dB/decade, then its mid-band gain
(between z1 and p2) will be
n10
RC
RCn
10 OUT1S
OUT1
S
2p
cω
=
ω
=
ω
ω.
This is also equal to
+21
2
5MAOUTMP RR R
RGRG. Therefore
n10
RC
RR R
RGRGOUT1
21
2
5MAOUTMP ω
=
+.
Re-arranging,
MAMP
1S
2
1
5GnG10 C
R
R
1Rω
+= (11)
ωz1 is shown to be less than ωp2 in Figure 13. Making
2p1z
ω
=
ω
gives a first-order estimate of C5:
5
)MIN(
OUT1
5nR
R
C
C= (12)
Notice that R5 determines the mid-band loop gain of the
converter. Increasing R5 increases the mid-band gain and
the crossover frequency. However it reduces the phase
margin. An estimate of R5 and C5 can be obtained from
(11) and (12) with n=1. The compensation is then checked
by measuring the loop gain and the phase or by observing
the inductor current and the output voltage during load
transient. Choose the largest R5 and the smallest C5 to
give at least 45° of phase margin. The corresponding
load transient should not show any ringing or excessive
overshoot (see Figures 14(c), 14(d), 17(b) and 17(c)). C6
is a small ceramic capacitor (10-47pF) to roll off the loop
gain at high frequency. Feedforward capacitor C11 boosts
phase margin over a limited frequency range and is
sometimes used to improve loop response. C11 will be
more effective if 211 RRR >> .
Example: Determine the compensation components for
the 1.3MHz 12V to 5V and 3.3V converter in Figure 1.
For both channels, 1
SMrads2.8−
=ω,
A
2
I
)MAX(
OUT
=
and
F
10
C
1
µ
=
. n is assumed to be 1 in (11) and (12).
For the 3.3V output:
Ω=×⋅⋅⋅ ⋅×
+= −
−
K9.16 )108.2()7.5()1(10 10102.8
K10 K3.23
1R4
56
5
nF1
)A2(K9.16)1(V3.310
C5
5=
⋅⋅ ⋅
=−
For the 5V channel:
Ω=×⋅⋅⋅ ⋅×
+= −
−
K5.25 )108.2()7.5()1(10 10102.8
K10 K2.40
1R4
56
7
nF1
)A2(K5.25)1(V510
C5
8=
⋅⋅ ⋅
=−
C6 and C9 (both 10pF) are then added to increase gain
margin. Load transient responses of both channels are
observed using these values. There is very little inductor
current overshoot even with C5 and C8 reduced to 470pF
and 220pF respectively (Figure 14). The measured overall
loop gain and phase plots of the converter are also
shown.
212005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Applications Information
Board Layout Considerations
In a step-down switching regulator, the input bypass
capacitor, the main power switch and the freewheeling
diode carry switched currents with high
dt
di
(Figure 15).
For jitter-free operation, the size of the loop formed by
these components should be minimized. Since the power
switches are already integrated within the SC2440,
connecting the anodes of both freewheeling diodes close
to the negative terminal of the input bypass capacitor
minimizes size of the switched current loop. The input
bypass capacitors should also be placed close to the
Figure 14. Overall Loop Gain and Phase versus Frequency for (a) Channel 1 and (b) Channel 2 of the Dual
DC-DC Converter in Figure 1. (c) Channel 1 Load Transient Response, IOUT1 is switched between
0.3A and 1.7A. (d) Channel 2 Load Transient Response, IOUT2 is switched between 0.45A and
1.7A.
Upper Trace : OUT1 Voltage, AC Coupled, 0.5V/div
Lower Trace : L1 Inductor Current, 0.5A/div Upper Trace : OUT2 Voltage, AC Coupled, 0.5V/div
Lower Trace : L2 Inductor Current, 0.5A/div
(d)
(c)
40µs/div
VOUT=5V
40µs/div
VOUT=3.3V
(a)
VIN=12V, VOUT=3.3V at 1.7A,
C5=470pF, R5=15.4KΩ and C6=10pF
(b)
VIN=12V, VOUT=5V at 1.7A,
C7=220pF, R8=24.3KΩ and C9=10pF
222005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Applications Information input pins. Shortening the traces of the SW and BOOST
nodes reduces the parasitic trace inductance at these
nodes. This not only reduces EMI but also decreases
switching voltage spikes at these nodes.
Figures 16(a) and 16(b) shows how various external
components are placed around the SC2440. The
frequency-setting resistor is placed next to the ROSC pin
on the backside. The resistor is grounded to the ground
plane, which is then tied to anodes of the freewheeling
diodes with vias. These precautions reduce switching
noise pickup at the ROSC pin.
To ensure proper adhesion to the ground plane, avoid
using vias directly under the device. In figure 15 two
12mil vias are placed at the edge of the underside pad.
IN
V
OUT
V
L
Z
Fast Switching Current Paths in a Buck
Regulator. Minimize the size of this loop
to reduce parasitic trace inductance.
Figure 15.
Suggested PCB Layout for the SC2440. Notice that there is no via directly under
the device and that the only component on the backside is the frequency-setting
resistor. All vias are 12mil in diameter.
Figure 16.
(a)
R9
GND
R9
GND
(b)
GND
VIN
C2
L2
D3
L1
C4
D4
D1 D2
C15
C1 C3
R3R4
C9
C8 R7
R8C7R6
C6
C5R5
R2R1
VOUT2
VOUT1
VIN or VOUT2
VIN or VOUT1
GND
U1
C10
GND
GND
VIN
C2
L2
D3
L1
C4
D4
D1 D2
C15
C1 C3
R3R4
C9
C8 R7
R8C7R6
C6
C5R5
R2R1
VOUT2
VOUT1
VIN or VOUT2
VIN or VOUT1
GND
U1
C10
GND
232005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Typical Application Circuits
C15
4.7µF
R3
8.06K
SC2440
GND
SS2
IN
SW1
FB2
ROSC
COMP2
C9
22pF
R7
13.4K
BOOST1
C1
10µF
BOOST2
SW2
L1
1.4µH
C2
0.1µF
L2
1.8µH
C4
0.1µF
PGOOD2
SS1
PGOOD1
COMP1
FB1
C3
20µF
D1
UPS120
D2
UPS120
R8
100K
R6
100K
R9
15K
OUT1
3.3V/2A
10K
R4
10K
R2
R1
23.2K
C7
22nF
C10
22nF
C8
390pF
R5
15.4K
C5
390pF
D4
1N4148
SYNC
L1 & L2: Sumida CR43
OUT2
1.8V/2A
D3
1N4148
VIN
5V
Figure 17(a). 1.3MHz 5V to 3.3V and 1.8V Step-down
Converter
Figures 17(b) and 17(c). Load Transient Response. IOUT is switched between 0.3A and 1.75A.
20µs/div
Upper Trace : OUT1 Voltage, AC Coupled, 0.2V/div
Lower Trace : L1 Inductor Current, 0.5A/div
(b)
OUT1
20µs/div
Upper Trace : OUT2 Voltage, AC Coupled, 0.2V/div
Lower Trace : L2 Inductor Current, 0.5A/div
(c)
OUT2
Efficiency vs Load Current
50
55
60
65
70
75
80
85
90
95
00.5 11.5 2
Load Current (A)
Efficiency (%)
VOUT2 = 1.8V
VOUT1 = 3.3V
VIN = 5V
242005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Typical Application Circuits
C15
4.7µF
SC2440
GND
SS2
IN
SW1
FB2
ROSC
COMP2
C9
10pF
R7
11.8K
BOOST1
C1
10µF
BOOST2
SW2
L1
1.8µH
C2
0.1µF
L2
1µH
C4
0.1µF
PGOOD2
SS1
PGOOD1
COMP1
FB1
C3
22µF
D1
UPS120
D2
UPS120
R8
100K
R9
12.1K
OUT1
2.5V/2A
4.02K
R11
R3
8.06K
20K
R2
R1
30.1K
C7
22nF
C10
22nF
C8
470pF
R5
14.7K
C5
470pF
D4
1N4148
SYNC
L1 & L2: Sumida CR43
OUT2
0.8V/2A
D3
BAT-54
VIN
5V
C6
10pF
30.1K
R10
Figure 18(a). Producing an Output Lower than FB Voltage. 1.5MHz 5V to 2.5V and 0.8V Step-down Converter
R3 is a pre-load to shunt the current from R10 and R11 before PGOOD1 releases SS2.
Figure 18(b). VIN Start-up Transient (IOUT1 = IOUT2 = 1A).
2ms/div
CH1
CH2
CH3
CH4
Load Regulation
-2.0
-1.5
-1.0
-0.5
0.0
0.0 0.5 1.0 1.5 2.0
Load Current (A)
Percentage Deviation (%)
CH1 : OUT1 Voltage, 0.5V/div
CH4 : PGOOD2, 1V/div
CH2 : OUT2 Voltage, 1V/div
CH3 : SS2 Voltage, 1V/div
OUT1
OUT2
252005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Typical Application Circuits
C16
1µF
R3
40.2K
SC2440
GND
SS2
IN
SW1
FB2
ROSC
COMP2
C9
10pF
R7
11.8K
BOOST1
C1
10µF
X 2
BOOST2
SW2
L1
15µH
C2
0.1µF
L2
6.8µH
C4
0.1µF
PGOOD2
SS1
PGOOD1
COMP1
FB1
C3
D1
UPS140
D2
UPS140
R8
100K
R6
100K
R9
51.1K
OUT1
5V/2A
49.9K
R4
51.1K
R2
R1
205K
C7
33nF
C10
33nF
C8
4.7nF
R5
22.1K
C5
2.2nF
D4
1N4148
SYNC
L1 : Coiltronic DR74
OUT2
1.8V/2A
D3
1N4148
VIN
20V
L2 : Coiltronic DR73
10µF
X 2
C13
68pF
C12
10pF
C11
33pF
C6
10pF C15
47µF
C15 : 25V Electrolytic
All Other Capacitor are Ceramic.
Figure 19(a). 540KHz 20V to 5V and 1.8V Step-down Converter. Notice that Channel 2 is Bootstrapped
from OUT1. This Bootstrapping Scheme Requires OUT1 to be Present at All Times (i.e. No Hiccup
or Shutdown). Channel 2 will still Run if OUT1 is Absent. However its Power Disspation will be High.
1µs/div
CH1 : SW1 Voltage, 10V/div
CH2 : SW2 Voltage, 10V/div
Figure 19(b). Switching Waveforms.
VIN = 20V IOUT1 = 1A
IOUT2 = 1A
CH1 CH2
4ms/div
Upper Trace : VIN, 10V/div
Middle Trace : VOUT1, 2V/div
Lower Trace : VOUT2 , 1V/div
Figure 19(c). VIN Start Up Transient. IOUT1= IOUT2= 1.5A.
262005 Semtech Corp. www.semtech.com
SC2440
POWER MANAGEMENT
Outline Drawing - TSSOP-16 w/EDP
Land Pattern - TSSOP-16 w/EDP
(.222) (5.65)
Z
G
Y
P
(C) 4.10 .161 0.65 .026 0.40
.016 1.55
.061 7.20
.283
X
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
NOTES:
1.
INCHES
DIMENSIONS
Z
P
Y
X
DIM
C
G
MILLIMETERS
F .126 3.20
F
F
L
(L1)
c
01
GAGE
PLANE
SEE DETAIL
DETAIL A
A
0.25
.026 BSC
.252 BSC
16
.004
.169
.193 .173
.197
.007 -
16
0.10
0.65 BSC
6.40 BSC
4.40
5.00
-
.177
.201 4.30
4.90
.012 0.19
4.50
5.10
0.30
bxN
2X N/2 TIPS
SEATING
aaa C
E/2
INDICATOR
PIN 1
2X
1 32
N
A
A2
A1
E1
bbb CA-B D
ccc C
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
3. OR GATE BURRS.
DATUMS AND TO BE DETERMINED AT DATUM PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
-B-
NOTES:
1.
2. -A- -H-
SIDE VIEW
(.039)
.004
.008
-
.024
-
-
-
-
0°
.018
.003
.031
.002
-
8° 0°
0.20
0.10
-8°
0.45
0.09
0.80
0.05
.030
.007
.047
.042
.006 -
(1.0)
0.60
-
0.75
0.20
-
-
-1.20
1.05
0.15
A
B
C
D
e
e/2
H
PLANE
D
REFERENCE JEDEC STD MO-153, VARIATION AB.4.
INCHES
b
N
ccc
aaa
bbb
01
E1
E
L
L1
e
D
c
A2
A1
DIM
AMIN MAX
MILLIMETERS
MIN
DIMENSIONS
NOM MAX NOM
E
F.118 3.00
2.85
.122 3.10
BOTTOM VIEW
EXPOSED PAD
F
F
.112
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012-8790
Phone: (805)498-2111 FAX (805)498-3804
Contact Information