PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 6-A, 12-V INPUT NON-ISOLATED WIDE-OUTPUT ADJUST POWER MODULE FEATURES APPLICATIONS * Up to 6-A Output Current * 12-V Input Voltage * Wide-Output Voltage Adjust (1.2 V to 5.5 V)/(0.8 V to 1.8 V) * Efficiencies up to 93% * 200 W/in3 Power Density * On/Off Inhibit * Undervoltage Lockout * Operating Temperature: -40C to 85C * Auto-TrackTM Sequencing * Output Overcurrent Protection (Nonlatching, Auto-Reset) * Safety Agency Approvals: UL/IEC/CSA-22.2 60950-1 * Point-of-Load Alliance (POLATM) Compatible * 1 2 Telecom, Industrial, and General-Purpose Circuits NOMINAL SIZE = 0.87 i x 0.5 i (22,1 mm x 12,57 mm) DESCRIPTION The PTH12050 series is the smallest non-isolated power modules that features Auto-TrackTM Sequencing. Auto-Track simplifies the sequencing of supply voltages in power systems by enabling modules to track each other, or any other external voltage, during power up and power down. Although small in size (0.87 inches x 0.5 inches), these modules are rated for up to 6 A of output current, and are an ideal choice in applications where space, performance, and a power-up sequencing capability are important attributes. The series operates from an input voltage of 12-V to provide step-down conversion to a wide range of output voltages. The output voltage of the W-suffix device may set to any voltage over the adjust range, 1.2 V to 5.5 V. The L-suffix device has an adjustment range of 0.8 V to 1.8 V. The output voltage is set within the adjustment range using a single external resistor. Other operating features include an on/off inhibit, output voltage adjust (trim), and output overcurrent protection. For high efficiency, these parts employ a synchronous rectifier output stage. Target applications include telecom, industrial, and general purpose circuits, including low-power dual-voltage systems that use the TMS320TM DSP family, microprocessor, ASIC, or FPGA. For start-up into a non-prebiased output, review page 14 in the Application Information section. For start-up into a prebiased output, review page 18 in the Application Information section. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Auto-Track, POLA, TMS320 are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2007, Texas Instruments Incorporated PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. STANDARD APPLICATION 2 VI 3 PTH12050 (Top View) 4 C1 100 mF (Required) C2 10 mF Ceramic VO 6 1 Track 5 RSET, 1% (Required) C3 100 mF (Optional) Inhibit GND GND A. RSET = Required to set the output voltage higher than the minimum value. See the Application Information section for values. B. C2 = 10 F ceramic capacitor. Required for output voltages 3.3 V or higher. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperatur range unless otherwise noted All voltages are with respect to GND UNIT VI Track input voltage TA Operating temperature range Over VI range -0.3 V to VI+0.3 V Twave Wave solder temperature Surface temperature of module body or pins (5seconds) Treflow Solder reflow temperature Surface temperature of module body or pins Tstg Storage temperature 2 260C (1) PTH12050WAS 235C (1) PTH12050WAZ 260C (1) Mechanical shock Per Mil-STD-883D, Method 2002.3, 1 msec, Sine, mounted 500 G Mechanical vibration Mil-STD-883D, Method 2007.2, 20-2000 Hz 20 G Flammability (2) PTH12050WAH -55C to 125C Weight (1) -40C to 85C (2) 2.9 grams Meets UL 94V-O During soldering of package version, do not elevate peak temperature of the module, pins or internal components above the stated maximum. The shipping tray or tape and reel cannot be used to bake parts at temperatures higher than 65C. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS TA = 25C; VI = 12 V; VO = 3.3 V; C1 = 100 F, C2 = 10 F, C3 = 0 F, and IO = IO(max) (unless otherwise stated) PARAMETER TEST CONDITIONS PTH12050W MIN IO Output current VI Input voltage range Vo Over Vadj range 85C, 400 LFM airflow TYP 0 60C, natural convection Over IO range 10.8 Set-point voltage tolerance tol UNIT MAX 6 (1) A 6 (1) A 13.2 V 2 (2) %Vo Regtemp Temperature variation -40C <TA < 85C 0.5 %Vo Regline Line regulation Over VI range 5 mV Regload Load regulation Over IO range 5 Regtot Total output variation Includes set-point, line, load, -40C TA 85C Vadj Output voltage adjust range Over VI range Efficiency IO = 5 A 1.2 RSET = 280 , VO = 5 V (1) 93% RSET = 2 k, VO = 3.3 V (1) 91% RSET = 4.32 k, VO = 2.5 V 89% RSET = 8.06 k, VO = 2 V 88% RSET = 11.5 k, VO = 1.8 V 87% RSET = 24.3 k, VO = 1.5 V 86% RSET = open circuit, VO = 1.2 V Vr VO ripple (peak-to-peak) 20-MHz bandwidth Iotrip Overcurrent threshold Reset, followed by auto-recovery Transient response 1 A/s load step, 50 to 100% IOmax, C3 = 100 F IIL track Track input current (pin 2) Pin to GND dVtrack/dt Track slew rate capability CO CO(max) UVLO Under-voltage lockout ttr Vtr %Vo 5.5 (1) V 84% VO 2.5 V 25 mVpp VO > 2.5 V 1 %Vo 14 A Recovery time 70 s VO over/undershoot 100 mV -0.13 (3) 1 VI increasing 9.5 8.8 10.4 9 Open (3) Input high voltage, Referenced to GND V VIL Inhibit Control (pin 4) IIL Input low voltage, Referenced to GND -0.2 Input low current, Pin 4 to GND II Input standby current Inhibit (pin 4) to GND, Track (pin 2) open fs Switching frequency Over VI and IO ranges 0.5 0.24 mA 10 260 mA 320 380 100 (5) 3300 (6) 100 (4) External input capacitance, C1 Nonceramic 0 MTBF (3) (4) (5) (6) (7) Reliability kHz F Capacitance value External output capacitance, C3 (1) (2) mA V/ms V VI decreasing VIH mV 3 (2) F Ceramic 0 300 (7) Equivalent series resistance (nonceramic) 4 Per Bellcore TR-332 50% stress, TA = 40C, ground benign 5.9 106 Hr See the Temperature Derating (SOA) curves in the Typical Characteristics section for appropriate derating. The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a tolerance of 1% with 100 ppm/C or better temperature stability. This control pin has an internal pull-up to the input voltage VI (7.5 V for pin 2). If it is left open-circuit, the module operates when input power is applied. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do not place an external pull-up on this pin. For further information, see the related application note. A 100 F electrolytic input capacitor is required for proper operation. The electrolytic capacitor must be rated for a minimum of 750 mA rms of ripple current. An additional 10 F ceramic capacitor is required for output voltages 3.3 V and higher. For further information, see the related application information on capacitor selection. An external output capacitor is not required for basic operation. Adding 100 F of distributed capacitance at the load improves the transient response. This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using a voltage supervisor, CO(max) is reduced to 2200 F. See the application notes for further guidance. This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 m as the minimum when using max-ESR values to calculate. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L 3 PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS TA = 25C; VI = 12 V; VO = 1.8 V; C1 = 100 F, C2 = 10 F, C3 = 0 F, and IO = IO(max) (unless otherwise stated) PARAMETER TEST CONDITIONS PTH12050L MIN Over Vadj range 85C, 400 LFM airflow TYP 0 UNIT MAX 6 (1) A 6 (1) A IO Output current VI Input voltage range VOtol Set-point voltage tolerance Regtemp Temperature variation -40C <TA < 85C 0.5 %Vo Regline Line regulation Over VI range 5 mV Regload Load regulation Over IO range 5 Regtot Total output variation Includes set-point, line, load, -40C TA 85C Regadj Output voltage adjust range Over VI range Efficiency 60C, natural convection Over IO range IO = 5 A 10.8 0.8 RSET = 3.57 k, VO = 1.5 V 87% RSET = 12.1 k, VO = 1.2 V 85% RSET = 32.4 k, VO = 1 V 83% RSET = open circuit, VO = 0.8 V 20-MHz bandwidth Iotrip Overcurrent threshold Reset, followed by auto-recovery Transient response 1 A/s load step, 50 to 100% IO(max), C3 = 100 F IIL track Track input current (pin 2) Pin to GND dVtrack/dt Track slew rate capability CO CO(max) UVLO Undervoltage lockout ttr Vtr mV 30 VO 1 V 20 14 A Recovery time 70 s VO over/undershoot 100 mV -0.13 (3) 1 VI increasing 9.5 10.4 V 8.8 9 Open Input low voltage, Referenced to GND -0.2 Input low current, Pin 4 to GND II Input standby current Inhibit (pin 4) to GND, Track (pin 2) open fs Switching frequency Over VI and IO ranges (3) 0.5 0.24 mA 10 200 mA 250 300 100 (5) 3300 (6) 100 (4) External input capacitance, C1 Nonceramic 0 Ceramic 0 MTBF (5) (6) (7) 4 Reliability kHz F Capacitance value F External output capacitance, C3 (4) mA V/ms V Inhibit control (pin 4) IIL (3) V mVpp Input high voltage, Referenced to GND VIL (1) (2) %Vo 81% VO > 1 V VI decreasing VIH %Vo 1.8 88% Vo ripple (peak-to-peak) V 2 (2) 3 (2) RSET = 130 , VO = 1.8 V Vr 13.2 Equivalent series resistance (nonceramic) 4 (7) Per Bellcore TR-332 50% stress, TA = 40C, ground benign 5.9 300 106 Hr See the Temperature Derating (SOA) curves in the Typical Characteristics section for appropriate derating. The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a tolerance of 1% with 100 ppm/C or better temperature stability. This control pin has an internal pull-up to the input voltage VI (7.5 V for pin 2). If it is left open-circuit, the module operates when input power is applied. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do not place an external pull-up on this pin. For further information, see the related application note. A 100 F electrolytic input capacitor is required for proper operation. The electrolytic capacitor must be rated for a minimum of 750 mA rms of ripple current. An additional 10 F ceramic capacitor is required for output voltages 3.3 V and higher. For further information, see the related application information on capacitor selection. An external output capacitor is not required for basic operation. Adding 100 F of distributed capacitance at the load improves the transient response. This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using a voltage supervisor, CO(max) is reduced to 2200 F. See the application notes for further guidance. This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 m as the minimum when using max-ESR values to calculate. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 DEVICE INFORMATION Terminal Functions TERMINAL NAME NO. DESCRIPTION VI 3 The positive input voltage power node to the module, which is referenced to common GND. VO 6 The regulated positive power output with respect to the GND node. GND 1 This is the common ground connection for the VI and VO power connections. It is also the 0-VDC reference for the control inputs. 5 A 1% resistor must be directly connected between this pin and GND (pin 1) to set the output voltage of the module to a value higher than its lowest value. The temperature stability of the resistor should be 100 ppm/C (or better). The set-point range is 1.2 V to 5.5 V for W-suffix devices, and 0.8 V to 1.8 V for L-suffix devices. The resistor value required for a given output voltage may be calculated using a formula. If left open circuit, the output voltage defaults to its lowest value. For further information on output voltage adjustment, see the related application note. VOAdjust The specification table gives the preferred resistor values for a number of standard output voltages. Inhibit Track 4 The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a low-level ground signal to this input disables the module's output and turns off the output voltage. When the Inhibit control is active, the input current drawn by the regulator is significantly reduced. If the Inhibit pin is left open circuit, the module produces an output whenever a valid input source is applied. Do not place an external pull-up on this pin. For power-up into a non-prebiased output, it is recommended that AutoTrack be utilized for On/Off control. See the Application Information for additional details. 2 This is an analog control input that enables the output voltage to follow an external voltage. This pin becomes active typically 20 ms after the input voltage has been applied, and allows direct control of the output voltage from 0 V up to the nominal set-point voltage. Within this range, the output follows the voltage at the Track pin on a volt-for-volt basis. When the control voltage is raised above this range, the module regulates at its set-point voltage. The feature allows the output voltage to rise simultaneously with other modules powered from the same input bus. If unused, the input should be connected to VI. Note: Due to the under-voltage lockout feature, the output of the module cannot follow its own input voltage during power up. For more information, see the related application note. 1 6 2 3 4 PTHXX050 (Top View) 5 Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L 5 PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 PTH12050W TYPICAL CHARACTERISTICS (VI = 12 V) (1) (2) EFFICIENCY vs LOAD CURRENT OUTPUT RIPPLE vs LOAD CURRENT 10 0 POWER DISSIPATION vs LOAD CURRENT 4 80 VO = 3.3 V VO = 5 V VO = 2.5 V PD - Power Dissipation - W 90 80 VO = 2 V VO = 1.5 V VO = 1.8 V VO = 1.2 V 70 Output Ripple - mV Efficiency - % 60 VOUT = 5 V VOUT = 2 V 40 VOUT = 2.5 V VOUT = 3.3 V 20 60 VOUT = 1.8 V 50 0 0 1 2 3 4 5 0 6 1 2 3 1 VOUT = 1.8 V 4 5 0 6 VOUT = 1.2 V 0 1 2 VOUT = 1.5 V 3 4 IO - Output Current - A IO - Output Current - A Figure 1. Figure 2. Figure 3. 90 400 6 400 80 TA - Ambient Temperature - C TA - Ambient Temperature - C 5 TEMPERATURE DERATING vs OUTPUT CURRENT 80 200 100 70 Natural Convection 60 50 LFM 40 400 200 100 Natural Convection 30 VO= 3.3 V 70 200 60 100 Natural Convection 50 40 LFM 400 200 100 Natural Convection 30 20 VO = 5 V 20 0 1 2 3 4 IO - Output Current - A 5 6 0 1 2 3 4 IO - Output Current - A Figure 4. 6 VOUT = 2.5 V VOUT = 2 V IO - Output Current - A 90 (2) VOUT = 5 V VOUT = 3.3 V 2 VOUT = 1.5 V VOUT = 1.2 V TEMPERATURE DERATING vs OUTPUT CURRENT (1) 3 5 6 Figure 5. Characteristic data has been developed from actual products tested at 25C. This data is considered typical data for the converter. Applies to Figure 1, Figure 2, and Figure 3. SOA graphs represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to modules soldered directly to a 4 inches x 4 inches double-sided PCB with 1-oz. copper. For surface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power pins. Please refer to the mechanical specification for more information. Applies to Figure 4. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 PTH12050L TYPICAL CHARACTERISTICS (VI = 12 V) (1) (2) EFFICIENCY vs LOAD CURRENT OUTPUT RIPPLE vs LOAD CURRENT 100 POWER DISSIPATION vs LOAD CURRENT 1. 8 50 VOUT = 1.8 V VO = 1.5 V 80 VO = 0.8 V 1. 5 40 VOUT = 1.5 V Output Ripple - mV Efficiency - % VO = 1.8 V VO = 1 V 70 VOUT = 1.8 V PD - Power Dissipation - W VO = 1.2 V 90 30 20 VOUT = 1.2 V 10 60 VOUT = 0.8 V 50 VOUT = 1 V 1 2 3 4 5 0 6 1 2 3 4 5 6 VOUT = 1.2 V 1. 2 0. 9 0. 6 VOUT = 1 V VOUT = 0.8 V 0. 3 0 0 0 VOUT = 1.5 V 0 1 2 3 4 IO - Output Current - A IO - Output Current - A IO - Output Current - A Figure 6. Figure 7. Figure 8. 5 6 TEMPERATURE DERATING vs OUTPUT CURRENT TA- Ambient Temperature -5 C 90 Nat Conv 80 100 LFM 70 60 50 40 30 20 VO = 1.8 V 0 1 2 3 4 5 6 IO - Output Current - A Figure 9. (1) (2) Characteristic data has been developed from actual products tested at 25C. This data is considered typical data for the converter. Applies to Figure 6, Figure 7, and Figure 8. SOA graphs represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to modules soldered directly to a 4 inches x 4 inches double-sided PCB with 1-oz. copper. For surface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power pins. Please refer to the mechanical specification for more information. Applies to Figure 9. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L 7 PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 APPLICATION INFORMATION ADJUSTING THE OUTPUT VOLTAGE The VOAdjust control (pin 5) sets the output voltage of the PTH12050 product. The adjustment range is from 1.2 V to 5.5 V for the W-suffix modules and 0.8 V to 1.8 V for L-suffix modules. The adjustment method requires the addition of a single external resistor, RSET, that must be connected directly between the VOAdjust and GND pins. Table 1 gives the standard value of the external resistor for a number of standard voltages, along with the actual output voltage that this resistance value provides. For other output voltages, the value of the required resistor can either be calculated using Equation 1, or simply selected from the range of values given in Table 3.Figure 10 shows the placement of the required resistor. Table 1. Standard Values of RSET for Standard Output Voltages PTH12050W PTH12050L VO (Required) (V) RSET (k) VO (Actual) (V) RSET (k) VO (Actual) (V) 5 0.280 5.009 N/A N/A 3.3 2.0 3.294 N/A N/A 2.5 4.32 2.503 N/A N/A 2 8.06 2.010 N/A N/A 1.8 11.5 1.801 0.130 1.800 1.5 24.3 1.506 3.57 1.499 1.2 Open 1.200 12.1 1.201 1.1 N/A N/A 18.7 1.101 1.0 N/A N/A 32.4 0.999 0.9 N/A N/A 71.5 0.901 0.8 N/A N/A Open 0.800 2 VI Track 3 VI VO PTH12050 VO 6 Inhibit GND Adjust 4 C1 100 mF (Required) 1 5 RSET, C2* 10 mF Ceramic 1% C3 100 mF (Optional) GND * Required with output voltages > 3.3 V (1) A 0.05-W rated resistor can be used. The tolerance should be 1%, with a temperature stability of 100 ppm/C or better. Place the resistor as close to the regulator as possible. Connect the resistor directly between pins 5 and 1 using dedicated PCB traces. (2) Never connect capacitors from VOAdjust to either GND or VO. Any capacitance added to the VOAdjust pin affects the stability of the regulator. Figure 10. VOAdjust Resistor Placement 8 Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 Use Equation 1 to calculate the adjust resistor value. See Table 2 for parameters, Rs and Vmin. Equation 1. Output Voltage Adjust Table 2. Adjust Formula Parameters OUTPUT VOLTAGE ADJUST EQUATION R set + 10 kW 0.8 V V out * V *R min S kW (1) Parameter PTH12050W PTH12050L V(MIN) 1.2 V 0.8 V V(MAX) 5.5 V 1.8 V RS 1.82 k 7.87 k Table 3. Output Voltage Set-Point Resistor Values PTH12050W PTH12050L VO(V) RSET (k) VO (V) RSET (k) VO(V) RSET (k) 1.200 Open 2.7 3.51 0.8 Open 1.225 318 2.75 3.34 0.825 312 1.250 158 2.8 3.18 0.85 152 1.275 105 2.85 3.03 0.875 98.8 1.300 78.2 2.9 2.89 0.9 72.1 1.325 62.2 2.95 2.75 0.925 56.1 1.350 51.1 3.0 2.62 0.95 45.5 1.375 43.9 3.05 2.49 0.975 37.8 1.400 38.2 3.1 2.39 1.0 32.1 1.425 33.7 3.15 2.27 1.025 27.7 1.450 30.2 3.2 2.18 1.05 24.1 1.475 27.3 3.25 2.08 1.075 21.2 1.50 24.8 3.3 1.99 1.1 18.8 1.55 21 3.35 1.91 1.125 16.7 1.60 18.2 3.4 1.82 1.15 15 1.65 16 3.5 1.66 1.175 13.5 1.70 14.2 3.6 1.51 1.2 12.1 1.75 12.7 3.7 1.38 1.225 11 1.80 11.5 3.8 1.26 1.25 9.91 1.85 10.5 3.9 1.14 1.275 8.97 1.90 9.61 4.0 1.04 1.3 8.13 1.95 8.85 4.1 0.939 1.325 7.37 2.00 8.18 4.2 0.847 1.35 6.68 2.05 7.59 4.3 0.761 1.375 6.04 2.10 7.07 4.4 0.680 1.4 5.46 2.15 6.6 4.5 0.604 1.425 4.93 2.20 6.18 4.6 0.533 1.45 4.44 2.25 5.8 4.7 0.466 1.475 3.98 2.30 5.45 4.8 0.402 1.5 3.56 2.35 5.14 4.9 0.342 1.55 2.8 2.40 4.85 5.0 0.285 1.6 2.13 2.45 4.58 5.1 0.231 1.65 1.54 2.50 4.33 5.2 0.180 1.7 1.02 2.55 4.11 5.3 0.131 1.75 0.551 2.60 3.89 5.4 0.085 1.8 0.130 2.65 3.7 5.5 0.041 Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L 9 PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 CAPACITOR RECOMMENDATIONS FOR THE PTH12050 SERIES OF POWER MODULES Input Capacitor The recommended input capacitor(s) is determined by the 100 F minimum capacitance and 750 mArms minimum ripple current rating. A 10-F X5R/X7R ceramic capacitor may also be added to reduce the reflected input ripple current. This is recommended for output voltage set points of 3.3 V and higher. Ripple current, less than 100 m equivalent series resistance (ESR) and temperature are major considerations when selecting input capacitors. Unlike polymer-tantalum capacitors, regular tantalum capacitors have a recommended minimum voltage rating of 2 x (maximum dc voltage + ac ripple). This is standard practice to ensure reliability. Only a few tantalum capacitors have sufficient voltage rating to meet this requirement. At temperatures below 0C, the ESR of aluminum electrolytic capacitors increases. For these applications, Os-Con types , polymer-tantalum, and polymer-aluminum types should be considered. Output Capacitors (Optional) For applications with load transients (sudden changes in load current), regulator response benefits from external output capacitance. The value of 100 F is used to define the transient response specification. For most applications, a high quality computer-grade aluminum electrolytic capacitor is adequate. These capacitors provide decoupling over the frequency range, 2 kHz to 150 kHz, and are suitable for ambient temperatures above 0C. Below 0C, tantalum, ceramic or Os-Con type capacitors are recommended. When using one or more nonceramic capacitors, the calculated equivalent ESR should be no lower than 4 m (7 m using the manufacturer'fs maximum ESR for a single capacitor). A list of preferred low-ESR type capacitors are identified in Table 4. In addition to electrolytic capacitance, adding a 10-F X5R/X7R ceramic capacitor to the output reduces the output ripple voltage and improve the regulator's transient response. The measurement of both the output ripple and transient response is also best achieved across a 10-F ceramic capacitor. Ceramic Capacitors Above 150 kHz the performance of aluminum electrolytic capacitors is less effective. Multilayer ceramic capacitors have very low ESR and a resonant frequency higher than the bandwidth of the regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient response of the output. When used on the output their combined ESR is not critical as long as the total value of ceramic capacitance does not exceed 300 F. Also, to prevent the formation of local resonances, do not place more than five identical ceramic capacitors in parallel with values of 10 F or greater. Tantalum Capacitors Tantalum type capacitors are most suited for use on the output bus, and are recommended for applications where the ambient operating temperature can be less than 0C. The AVX TPS, Sprague 593D/594/595 and Kemet T495/ T510 capacitor series are suggested over other tantalum types due to their higher rated surge, power dissipation, and ripple current capability. As a caution many general purpose tantalum capacitors have considerably higher ESR, reduced power dissipation and lower ripple current capability. These capacitors are also less reliable as they have no surge current rating. Tantalum capacitors that do not have a stated ESR or surge current rating are not recommended for power applications. When specifying Os-con and polymer tantalum capacitors for the output, the minimum ESR limit are encountered well before the maximum capacitance value is reached. Capacitor Table Table 1 identifies the characteristics of capacitors from number of vendors with acceptable ESR and ripple current (rms) ratings. The recommended number of capacitors required at both the input and output buses is identified for each capacitor type. This is not an extensive capacitor list. Capacitors from other vendors are available with comparable specifications. Those listed are for guidance. The RMS ripple current rating and ESR (at 100 kHz) are critical parameters necessary to insure both optimum regulator performance and long capacitor life. 10 Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 Table 4. Input/Output Capacitors (1) Capacitor Characteristics Capacitor Vendor, Type/Series (Style) Working Value Voltage (F) (V) Quantity Max ESR at 100 kHz () Max Ripple Current at 85C (Irms) (mA) Physical Size (mm) Input Bus Output Bus Vendor Number Panasonic, Aluminum 25 330 0.090 775 10 x 12,5 1 1 EEUFC1E331 FC (Radial) 35 180 0.090 775 10 x 12,5 1 1 EEUFC1V181 FK (SMD) 25 470 0.080 850 10 x 10,2 1 1 EEVFK1E471P PXA-Poly-Aluminum (SMD) 16 150 0.026 3430 10 x 7,7 1 4 PXA16VC151MJ80TP PS (Radial) 20 100 0.024 3300 8 x 11,5 1 4 20PS100MH11 LXZ, Aluminum (Radial) 35 220 0.090 760 10 x 12,5 1 1 LXZ35VB221M10X12LL HD (Radial) 25 220 0.072 760 8 x 11,5 1 1 UHD1E221MPR PM (Radial) 35 220 0.090 770 10 x 15 1 1 UPM1V221MHH6 6.3 (2) 180 0.005 4000 7,3 x 4,3 x 4,2 N/R (3) 1 EEFSE0J181R (VO 5.1 V) Sanyo SVP, Os-con (SMD) 20 100 0.024 >3300 8 x 12 1 4 20SVP100M SEQP, Os-con (Radial) 20 100 0.024 >3300 8 x 12 1 4 20SEQP100M TPE, Pos-Cap (SMD) 10 220 0.025 >2400 7,3 x 5,7 N/R (3) 4 10TPE220ML AVX, Tantalum 10 100 0.100 >1090 7,3x4,3x4,1 N/R (3) 5 TPSD107M010R0100 TPS (SMD) 10 220 0.100 >1414 7,3x4,3x4,1 N/R (3) 5 TPSV227M010R0100 25 68 0.095 >1451 7,3x4,3x4,1 2 5 TPSV686M025R0080 T520, Poy-Tant (SMD) 10 100 0.080 1200 7,3x5,7x4 N/R (3) 5 T520D107M010AS T495, Tantalum (SMD) 10 100 0.100 >1100 7,3x5,7x4 N/R (3) 5 T495X107M010AS Vishay-Sprague 10 150 0.090 1100 7,3x6x4,1 N/R (3) 5 594D157X0010C2T 594D, Tantalum (SMD) 25 68 0.095 1600 7,3x6x4,1 2 5 594D686X0025R2T 94SP, Organic (Radial) 16 100 0.070 2890 10 x 10,5 1 5 94SP107X0016FBP 94SVP, Organic (SMD) 20 100 0.025 3260 8 x 12 1 4 94SVP107X0020E12 Kemet, Ceramic X5R (SMD) 16 10 0.002 - 1210 case 1 (4) 5 C1210C106M4PAC 6.3 47 0.002 3225 mm N/R (3) 5 C1210C476K9PAC 6.3 100 0.002 1210 case N/R (3) 3 GRM32ER60J107M 6.3 47 3225 mm N/R (3) 5 GRM32ER60J476M 16 22 1 (4) 5 GRM32ER61C226L (4) United Chemi-Con Nichicon Aluminum Panasonic, Poly-Aluminum S/SE (SMD) Kemet Murata, Ceramic X5R (SMD) TDK, Ceramic X5R (SMD) (1) (2) (3) (4) - 5 GRM32DR61C106K 1210 case N/R (3) 3 C3225X5ROJ107MT 3225 mm N/R (3) 5 C3225X5ROJ476MT 22 1 (4) 5 C3225X5R1C226MT 10 1 (4) 5 C3225X5R1C106MT 16 10 6.3 100 6.3 47 16 16 1 0.002 - Capacitor Supplier Verification Please verify availability of capacitors identified in this table. Capacitor suppliers may recommend alternative part numbers because of limited availability or obsolete products. In some instances, the capacitor product life cycle may be in decline and have short-term consideration for obsolescence. RoHS, Lead-free and Material Details Please consult capacitor suppliers regarding material composition, RoHS status, lead-free status, and manufacturing process requirements. Component designators or part number deviations can occur when material composition or soldering requirements are updated. The voltage rating of this capacitor only allows it to be used for output voltages that are equal to or less than 5.1 V. N/R - Not recommended. The capacitor voltage rating does not meet the minimum operating limits. Ceramic capacitors are required to complement electrolytic types at the input and to reduce high-frequency ripple current. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L 11 PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 Designing for Very Fast Load Transients The transient response of the dc/dc converter has been characterized using a load transient with a di/dt of 1 A/s. The typical voltage deviation for this load transient is given in the data sheet specification table using the optional value of output capacitance. As the di/dt of a transient is increased, the response of a converter's regulation circuit ultimately depends on its output capacitor decoupling network. This is an inherent limitation with any dc/dc converter once the speed of the transient exceeds its bandwidth capability. If the target application specifies a higher di/dt or lower voltage deviation, the requirement can only be met with additional output capacitor decoupling. In these cases special attention must be paid to the type, value and ESR of the capacitors selected. If the transient performance requirements exceed that specified in the data sheet, or the total amount of load capacitance is above 3,000 F, the selection of output capacitors becomes more important. Features of the PTH Family of Non-Isolated Wide Output Adjust Power Modules Introduction The PTH/PTV family of non-isolated, wide-output adjustable power modules are optimized for applications that require a flexible, high performance module that is small in size. Each of these products are POLATM compatible. POLA-compatible products are produced by a number of manufacturers, and offer customers advanced, nonisolated modules with the same footprint and form factor. POLA parts are also ensured to be interoperable, thereby, providing customers with second-source availability. From the basic, Just Plug It In functionality of the 6-A modules, to the 30-A rated feature-rich PTHxx030, these products were designed to be very flexible, yet simple to use. The features vary with each product. Table 5 provides a quick reference to the features by product series and input bus voltage. Table 5. Operating Features by Series and Input Bus Voltage Series PTHxx050 PTHxx060 PTHxx010 PTVxx010 PTHxx020 PTVxx020 PTHxx030 Input Bus (V) IO (A) Adjust (Trim) On/Off Inhibit OverCurrent Prebias Startup AutoTrackTM 3.3 6 * * * * * 5 6 * * * * * Margin Up/Down Output Sense Thermal Shutdown 12 6 * * * * * 3.3 / 5 10 * * * * * * * 12 10 * * * * * * * 3.3 / 5 15 * * * * * * * 12 12 * * * * * * * 5 8 * * * * * 12 8 * * * * * 3.3 / 5 22 * * * * * * * * 12 18 * * * * * * * * 5 18 * * * * * * * 12 16 * * * * * * * 3.3 / 5 30 * * * * * * * * 12 26 * * * * * * * * For simple point-of-use applications, the PTH12050 (6 A) provides operating features such as an on/off inhibit, output voltage trim, prebias start-up and overcurrent protection. The PTH12060 (10 A), and PTH12010 (12 A) include an output voltage sense, and margin up/down controls. Then the higher output current, PTH12020 (18 A) and PTH12030 (26 A) products incorporate overtemperature shutdown protection. The PTV12010 and PTV12020 are similar parts offered in a vertical, single in-line pin (SIP) profile, at slightly lower current ratings. All of the products referenced in Table 5 include Auto-TrackTM. This feature was specifically designed to simplify the task of sequencing the supply voltages in a power system. This and other features are described in the following sections. 12 Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 POWER-UP INTO A NON-PREBIASED OUTPUT -- AUTO-TRACKTM FUNCTION The Auto-Track function is unique to the PTH/PTV family, and is available with all POLA products. Auto-Track was designed to simplify the amount of circuitry required to make the output voltage from each module power up and power down in sequence. The sequencing of two or more supply voltages during power up is a common requirement for complex mixed-signal applications that use dual-voltage VLSI ICs such as the TMS320TM DSP family, microprocessors, and ASICs. Basic Power-Up Using Auto-TrackTM For applications requiring output voltage on/off control, each series of the PTH family incorporates the track control pin. The Auto-Track feature should be used instead of the inhibit feature wherever there is a requirement for the output voltage from the regulator to be turned on/off. Figure 11 shows the typical application for basic start-up. Note the discrete transistor (Q1). The track input has its own internal pull-up to a potential of 5 V to 13.2 V The input is not compatible with TTL logic devices. An open-collector (or open-drain) discrete transistor or supply voltage supervisor (TPS3808 or TPS7712) is recommended for control. 10 Margin Up 9 3 5 Margin Down Inhibit VOSense VO 2 Track GND GND VoAdj 8 1 7 4 + CI 560 F 1=Turn-Off VO PTH12060W VI 6 RSET 2 k 0.1 W 1% Q1 BSS138 L O A D + CO 330 F GND UDG-06074 Figure 11. Basic Start-up Control Circuit Turning on Q1 applies a low voltage to the track control pin and disables the output of the module. If Q1 is then turned off, the output ramps immediately to the regulated output voltage. A regulated output voltage is produced within 35 ms. With the initial application of the input source voltage, the track pin must be held low (Q1 turned ON) for at least 40 ms. Figure 12 shows the typical rise in both the output voltage and input current, following the turn off of Q1. The turn off of Q1 corresponds to the rise in the waveform, Q1 Vds. The waveforms were measured with a 10-A constant current load. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L 13 PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 Q1VDS (2 V/div) VO (2 V/div) II (2 A/div) t - Time - 40 ms/div Figure 12. Power-Up from Track Control NOTE: If a prebias condition is not present, it is highly recommended that the Track control pin be used for controlled power-up and power-down. If Track control is not used, the output voltage starts up and overshoots by as much as 10%, before settling at the output voltage setpoint. How Auto-TrackTM Works Auto-Track works by forcing the module output voltage to follow a voltage presented at the Track control pin (1). This control range is limited to between 0 V and the module set-point voltage. Once the track-pin voltage is raised above the set-point voltage, the module output remains at its set-point (2). As an example, if the Track pin of a 2.5-V regulator is at 1 V, the regulated output is 1 V. If the voltage at the Track pin rises to 3 V, the regulated output does not go higher than 2.5 V. When under Auto-Track control, the regulated output from the module follows the voltage at its Track pin on a volt-for-volt basis. By connecting the Track pin of a number of these modules together, the output voltages follow a common signal during power up and power down. The control signal can be an externally generated master ramp waveform, or the output voltage from another power supply circuit (3). For convenience, the Track input incorporates an internal RC-charge circuit. This operates off the module input voltage to produce a suitable rising waveform at power up. 14 Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 Typical Auto-Track Application The basic implementation of Auto-Track allows for simultaneous voltage sequencing of a number of Auto-Track compliant modules. Connecting the Track inputs of two or more modules forces their track input to follow the same collective RC-ramp waveform, and allows their power-up sequence to be coordinated from a common Track control signal. This can be an open-collector (or open-drain) device, such as a power-up reset voltage supervisor IC. See U3 in Figure 13. To coordinate a power-up sequence, the Track control must first be pulled to ground potential through RTRK as defined in Figure 13. This should be done at or before input power is applied to the modules. The ground signal should be maintained for at least 40 ms after input power has been applied. This brief period gives the modules time to complete their internal soft-start initialization (4), enabling them to produce an output voltage. A low-cost supply voltage supervisor IC, that includes a built-in time delay, is an ideal component for automatically controlling the Track inputs at power up. Figure 13 shows how the TL7712A supply voltage supervisor IC (U3) can be used to coordinate the sequenced power up of two 12-V input Auto-Track modules. The output of the TL7712A supervisor becomes active above an input voltage of 3.6 V, enabling it to assert a ground signal to the common track control well before the input voltage has reached the module's undervoltage lockout threshold. The ground signal is maintained until approximately 43 ms after the input voltage has risen above U3's voltage threshold, which is 10.95 V. The 43-ms time period is controlled by the capacitor C3. The value of 3.3 F provides sufficient time delay for the modules to complete their internal soft-start initialization. The output voltage of each module remains at zero until the track control voltage is allowed to rise. When U3 removes the ground signal, the track control voltage automatically rises. This causes the output voltage of each module to rise simultaneously with the other modules, until each reaches its respective set-point voltage. Figure 14 shows the output voltage waveforms from the circuit of Figure 13 after input voltage is applied to the circuit. The waveforms, VO1 and VO2, represent the output voltages from the two power modules, U1 (3.3 V) and U2 (1.8 V), respectively. VTRK, VO1, and VO2 are shown rising together to produce the desired simultaneous power-up characteristic. The same circuit also provides a power-down sequence. When the input voltage falls below U3's voltage threshold, the ground signal is re-applied to the common track control. This pulls the track inputs to zero volts, forcing the output of each module to follow, as shown in Figure 15. In order for a simultaneous power-down to occur, the track inputs must be pulled low before the input voltage has fallen below the modules' undervoltage lockout. This is an important constraint. Once the modules recognize that a valid input voltage is no longer present, their outputs can no longer follow the voltage applied at their track input. During a power-down sequence, the fall in the output voltage from the modules is limited by the maximum output capacitance and the Auto-Track slew rate. If the Track pin is pulled low at a slew rate greater than 1 V/ms, the discharge of the output capacitors will induce large currents which could exceed the peak current rating of the module. This will result in a reduction in the maximum allowable output capacitance as listed in the Electrical Characteristics table. When controlling the Track pin of the PTH12060W using a voltage supervisor IC, the slew rate is increased, therefore COmax is reduced to 2200 F. Notes on Use of Auto-TrackTM 1. The Track pin voltage must be allowed to rise above the module set-point voltage before the module regulates at its adjusted set-point voltage. 2. The Auto-Track function tracks almost any voltage ramp during power up, and is compatible with ramp speeds of up to 1 V/ms. 3. The absolute maximum voltage that may be applied to the Track pin is the input voltage VI. 4. The module cannot follow a voltage at its track control input until it has completed its soft-start initialization. This takes about 40 ms from the time that a valid voltage has been applied to its input. During this period, it is recommended that the Track pin be held at ground potential. 5. The Auto-Track function is disabled by connecting the Track pin to the input voltage (VI). When Auto-Track is disabled, the output voltage rises at a quicker and more linear rate after input power has been applied. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L 15 PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 2 U1 Track VI = 12 V 3 Vo 1 = 3.3 V 6 VI VO PTH12050W Inhibit GND 4 1 Adjust 5 + + CI1 CO1 RSET1 2.0 k 8 U3 VCC 7 SENSE RESET 2 5 RTRK # RESIN 1 3 50 TL7712A REF 0.1 F 9 Up Dn RESET 8 5 Track Sense CT 2 GND CREF 10 U2 6 CT 3.3 F 4 VI VO PTH12060W Vo 2 = 1.8 V 6 RRST 10 k Inhibit 3 Adjust GND 1 7 4 + # RTRK = 100 / N N = Number of Track pins connected together C I2 RSET2 + CO2 11.5 k Figure 13. Sequenced Power Up and Power Down Using Auto-Track VTRK (1 V/div) VTRK (1 V/div) V01 (1 V/div) V01 (1 V/div) V02 (1 V/div) V02 (1 V/div) t - Time - 400 s/div t - Time - 20 ms/div Figure 14. Simultaneous Power Up With Auto-Track Control 16 Figure 15. Simultaneous Power Down with Auto-Track Control Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 POWER-UP INTO A PREBIASED OUTPUT -- START-UP USING INHIBIT CONTROL The capability to start up into an output prebias condition is now available to all the 12-V input, PTH series of power modules. (Note that this is a feature enhancement for the many of the W-suffix products) [1]. A prebias startup condition occurs as a result of an external voltage being present at the output of a power module prior to its output becoming active. This often occurs in complex digital systems when current from another power source is backfed through a dual-supply logic component, such as an FPGA or ASIC. Another path might be via clamp diodes, sometimes used as part of a dual-supply power-up sequencing arrangement. A prebias can cause problems with power modules that incorporate synchronous rectifiers. This is because under most operating conditions, such modules can sink as well as source output current. The 12-V input PTH modules all incorporate synchronous rectifiers, but does not sink current during startup, or whenever the Inhibit pin is held low. Conditions for Prebias Holdoff In order for the module to allow an output prebias voltage to exist (and not sink current), certain conditions must be maintained. The module holds off a prebias voltage when the Inhibit pin is held low, and whenever the output is allowed to rise under soft-start control. Power up under soft-start control occurs upon the removal of the ground signal to the Inhibit pin (with input voltage applied), or when input power is applied with Auto-Track disabled [2]. To further ensure that the regulator doesn't sink output current, (even with a ground signal applied to its Inhibit), the input voltage must always be greater than the applied prebias source. This condition must exist throughout the power-up sequence [3]. The soft-start period is complete when the output begins rising above the prebias voltage. Once it is complete the module functions as normal, and sinks current if a voltage higher than the nominal regulation value is applied to its output. Note: If a prebias condition is not present, the soft-start period is complete when the output voltage has risen to either the set-point voltage, or the voltage applied at the module's Track control pin, whichever is lowest. to its output. Prebias Demonstration Circuit Figure 16 shows the startup waveforms for the demonstration circuit shown in Figure 17. The initial rise in VO2 is the prebias voltage, which is passed from the VCCIO to the VCORE voltage rail through the ASIC. Note that the output current from the PTH12010L module (IO2) is negligible until its output voltage rises above the applied prebias. VO1 (1 V/div) VO2 (1 V/div) IO2 (5 V/div) t - Time - 10 ms/div Figure 16. Prebias Startup Waveforms Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L 17 PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 10 9 Up VI = 12 V 2 VI 5 Sense GND 1 7 C1 330 mF 10 9 R3 11 k0 TL7702B 8 7 R4 100 kW C5 0.1 mF PTH12010L Inhibit 3 8 VCC SENSE 5 RESET 2 RESIN 1 REF 6 RESET 3 CT GND 4 R5 C6 10 k0 0.68 mF VI GND 1 7 6 Adjust 4 R1 2 kW Tra ck 2 VO PTH12020W Inhibit 3 + 8 Dn Tra ck VO1 = 3.3 V + C2 330 mF 5 Sense VO 6 Vadj 4 VO2 = 1.8 V + IO2 R1 130 W + C3 330 mF VC ORE + C4 330 mF VC CI O ASIC Figure 17. Application Circuit Demonstrating Prebias Startup Notes: 1. Output prebias holdoff is an inherent feature to all PTH120x0L and PTV120x0W/L modules. It has now been incorporated into all modules (including W-suffix modules with part numbers of the form PTH120x0W), with a production lot date code of 0423 or later. 2. The prebias start-up feature is not compatible with Auto-Track. If the rise in the output is limited by the voltage applied to the Track control pin, the output sinks current during the period that the track control voltage is below that of the back-feeding source. For this reason, it is recommended that Auto-Track be disabled when not being used. This is accomplished by connecting the Track pin to the input voltage, VI. This raises the Track pin voltage well above the set-point voltage prior to the module's start up, thereby, defeating the Auto-Track feature. 3. To further ensure that the regulator's output does not sink current when power is first applied (even with a ground signal applied to the Inhibit control pin), the input voltage must always be greater than the applied prebias source. This condition must exist throughout the power-up sequence of the power system. 18 Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 Overcurrent Protection For protection against load faults, all modules incorporate output overcurrent protection. Applying a load that exceeds the regulator's overcurrent threshold causes the regulated output to shut down. Following shutdown, a module periodically attempts to recover by initiating a soft-start power-up. This is described as a hiccup mode of operation, whereby, the module continues in a cycle of successive shutdown and power up until the load fault is removed. During this period, the average current flowing into the fault is significantly reduced. Once the fault is removed, the module automatically recovers and returns to normal operation. Overtemperature Protection (OTP) The PTH12020, PTV12020, and PTH12030 products have overtemperature protection. These products have an on-board temperature sensor that protects the module's internal circuitry against excessively high temperatures. A rise in the internal temperature may be the result of a drop in airflow, or a high ambient temperature. If the internal temperature exceeds the OTP threshold, the module's Inhibit control is internally pulled low. This turns the output off. The output voltage drops as the external output capacitors are discharged by the load circuit. The recovery is automatic, and begins with a soft-start power up. It occurs when the sensed temperature decreases by about 10C below the trip point. Note: The overtemperature protection is a last resort mechanism to prevent thermal stress to the regulator. Operation at or close to the thermal shutdown temperature is not recommended and will reduce the long-term reliability of the module. Always operate the regulator within the specified Safe Operating Area (SOA) limits for the worst-case conditions of ambient temperature and airflow. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L 19 PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 TAPE AND REEL SPECIFICATION 20 Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L PTH12050W/L www.ti.com SLTS214H - MAY 2003 - REVISED OCTOBER 2007 TRAY SPECIFICATION Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): PTH12050W/L 21 PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish PTH12050LAH ACTIVE ThroughHole Module EUU 6 56 Pb-Free (RoHS) SN PTH12050LAS ACTIVE Surface Mount Module EUV 6 56 TBD PTH12050LAST ACTIVE Surface Mount Module EUV 6 250 PTH12050LAZ ACTIVE Surface Mount Module EUV 6 PTH12050LAZT ACTIVE Surface Mount Module EUV PTH12050WAD ACTIVE ThroughHole Module PTH12050WAH ACTIVE PTH12050WAS MSL Peak Temp (3) Samples (Requires Login) N / A for Pkg Type Request Free Samples SNPB Level-1-235C-UNLIM/ Level-3-260C-168HRS Request Free Samples TBD SNPB Level-1-235C-UNLIM/ Level-3-260C-168HRS Purchase Samples 56 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR Request Free Samples 6 250 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR Purchase Samples EUU 6 56 Pb-Free (RoHS) SN Level-1-235C-UNLIM/ Level-3-260C-168HRS Purchase Samples ThroughHole Module EUU 6 56 Pb-Free (RoHS) SN Level-1-235C-UNLIM/ Level-3-260C-168HRS Request Free Samples ACTIVE Surface Mount Module EUV 6 56 TBD SNPB Level-1-235C-UNLIM/ Level-3-260C-168HRS Request Free Samples PTH12050WAST ACTIVE Surface Mount Module EUV 6 250 TBD SNPB Level-1-235C-UNLIM/ Level-3-260C-168HRS Purchase Samples PTH12050WAZ ACTIVE Surface Mount Module EUV 6 56 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR Request Free Samples PTH12050WAZT ACTIVE Surface Mount Module EUV 6 250 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2010 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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