CD74ACT257M96G4 - Texas Instruments High-Performance Analog

Data sheet acquired from Harris Semiconductor

SCHS248A

Features

• ’AC257, ’ACT257. . . . . . . . . . . . . Non-Inverting Outputs

• CD74ACT258 . . . . . . . . . . . . . . . . . . . Inverting Outputs

• Buffered Inputs

• Typical Propagation Delay

- 4.4ns at VCC = 5V, TA = 25oC, CL = 50pF

• Exceeds 2kV ESD Protection MIL-STD-883, Method

3015

• SCR-Latchup-Resistant CMOS Process and Circuit

Design

• Speed of Bipolar FAST™/AS/S with Signiﬁcantly

Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and

Balanced Noise Immunity at 30% of the Supply

•±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

Drives 50Ω Transmission Lines

Pinout

CD54AC257, CD54ACT257

(CERDIP)

CD74AC257, CD74ACT257, CD74ACT258

(PDIP, SOIC)

TOP VIEW

Description

The ’AC257, ’ACT257 and CD74ACT258 are quad 2-input

multiplexers with three-state outputs that utilize Advanced

CMOS Logic technology. Each of these devices selects four

bits of data from two sources under the control of a common

Select input (S). The Output Enable (OE) is active LOW.

When OE is HIGH, all of the outputs (Y or Y) are in the high-

impedance state regardless of all other input conditions.

Moving data from two groups of registers to four common

output buses is a common use of the ’AC257, ’ACT257, and

CD74ACT258. The state of the Select input determines the

particular register from which the data comes. The ’AC257,

’ACT257 and CD74ACT258 can also be used as function

generators.

1I0

1I1

2I0

2I1

GND

VCC

4I0

4I1

3I0

3I1

AC/ACT257ACT258 ACT258AC/ACT257 VCC

4I0

4I1

3I0

3I1

1I0

1I1

2I0

2I1

GND

Ordering Information

PART

NUMBER TEMP.

RANGE (oC) PACKAGE

CD54AC257F3A -55 to 125 16 Ld CERDIP

CD74AC257E 0 to 70oC, -40 to 85,

-55 to 125 16 Ld PDIP

CD74AC257M 0 to 70oC, -40 to 85,

-55 to 125 16 Ld SOIC

CD54ACT257F3A -55 to 125 16 Ld CERDIP

CD74ACT257E 0 to 70oC, -40 to 85,

-55 to 125 16 Ld PDIP

CD74ACT257M 0 to 70oC, -40 to 85,

-55 to 125 16 Ld SOIC

CD74ACT258E 0 to 70oC, -40 to 85,

-55 to 125 16 Ld PDIP

CD74ACT258M 0 to 70oC, -40 to 85,

-55 to 125 16 Ld SOIC

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all

electrical specifications. Please contact your local TI sales office or

customer service for ordering information.

August 1998 - Revised May 2000

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

FAST™ is a Trademark of Fairchild Semiconductor.

CD54/74AC257, CD54/74A CT257,

CD74ACT258

Quad 2-Input Multiplexer

with Three-State Outputs

Functional Diagram

TRUTH TABLE

OUTPUT

ENABLE SELECT

INPUT DATA INPUTS 257

OUTPUTS 258

OUTPUTS

OE S I0I1Y Y

HXXXZZ

LLLXLH

LLHXHL

LHXLLH

LHXHHL

H = High level voltage, L = Low level voltage, Z = High impedance (off) state, X = Don’t Care

1Y 1Y

AC/ACT

257 AC/ACT

258

1I0

2I0

3I0

4I0

1I1

2I1

3I1

4I1

115

CD54/74AC257, CD54/74ACT257, CD74ACT258

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

AC TYPES

High Level Input Voltage VIH - - 1.5 1.2 - 1.2 - 1.2 - V

3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

Low Level Input Voltage VIL - - 1.5 - 0.3 - 0.3 - 0.3 V

3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

High Level Output Voltage VOH VIH or VIL -0.05 1.5 1.4 - 1.4 - 1.4 - V

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

(Note 6, 7) 5.5 - - 3.85 - - - V

-50

(Note 6, 7) 5.5----3.85 - V

CD54/74AC257, CD54/74ACT257, CD74ACT258

Low Level Output Voltage VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V

12 3 - 0.36 - 0.44 - 0.5 V

24 4.5 - 0.36 - 0.44 - 0.5 V

(Note 6, 7) 5.5 - - - 1.65 - - V

(Note 6, 7) 5.5-----1.65 V

Input Leakage Current IIVCC or

GND - 5.5 - ±0.1 - ±1-±1µA

Three-State Leakage

Current IOZ VIH or VIL

VO=V

or GND

- 5.5 - ±0.5 - ±5-±10 µA

Quiescent Supply Current

MSI ICC VCC or

GND 0 5.5 - 8 - 80 - 160 µA

ACT TYPES

High Level Input Voltage VIH - - 4.5 to

5.5 2-2-2-V

Low Level Input Voltage VIL - - 4.5 to

5.5 - 0.8 - 0.8 - 0.8 V

High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

(Note 6, 7) 5.5 - - 3.85 - - - V

-50

(Note 6, 7) 5.5----3.85 - V

Low Level Output Voltage VOL VIH or VIL 0.05 4.5 - 0.1 - 0.1 - 0.1 V

24 4.5 - 0.36 - 0.44 - 0.5 V

(Note 6, 7) 5.5 - - - 1.65 - - V

(Note 6, 7) 5.5-----1.65 V

Input Leakage Current IIVCC or

GND - 5.5 - ±0.1 - ±1-±1µA

Three-State or Leakage

Current IOZ VIH or VIL

VO=V

or GND

- 5.5 - ±0.5 - ±5-±10 µA

Quiescent Supply Current

MSI ICC VCC or

GND 0 5.5 - 8 - 80 - 160 µA

AdditionalSupplyCurrentper

Input Pin TTL Inputs High

1 Unit Load

∆ICC VCC

-2.1 - 4.5 to

5.5 - 2.4 - 2.8 - 3 mA

NOTES:

6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize

power dissipation.

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

CD54/74AC257, CD54/74ACT257, CD74ACT258

ACT Input Load Table

INPUT UNIT LOAD

Data 0.83

S 1.27

OE 1.27

NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications

Table, e.g., 2.4mA max at 25oC.

Switching Speciﬁcations Input tr, tf = 3ns, CL= 50pF (Worst Case)

PARAMETER SYMBOL VCC (V)

-40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN TYP MAX

AC TYPES

Propagation Delay,

In to Y

AC/ACT257

tPLH, tPHL 1.5 - - 106 - - 117 ns

3.3

(Note 9) 3.3 - 11.8 3.3 - 13 ns

(Note 10) 2.4 - 8.5 2.3 - 9.3 ns

Propagation Delay,

S to Y

AC/ACT257

tPLH, tPHL 1.5 - - 153 - - 168 ns

3.3 4.8 - 17.1 4.7 - 18.8 ns

5 3.5 - 12.2 3.4 - 13.4 ns

Propagation Delay,

OE to Y

AC/ACT257

tPLZ, tPHZ,

tPZL, tPZH 1.5 - - 167 - - 184 ns

3.3 5.3 - 18.7 5.2 - 20.6 ns

5 3.8 - 13.4 3.7 - 14.7 ns

Propagation Delay,

In to Y

’AC/CD74ACT258

tPLH, tPHL 1.5 - - 91 - - 100 ns

3.3 2.9 - 10.2 2.8 - 11.2 ns

5 2.1 - 7.3 2 - 8 ns

Propagation Delay,

S to Y

’AC/CD74ACT258

tPLH, tPHL 1.5 - - 153 - - 168 ns

3.3 4.8 - 17.1 4.7 - 18.8 ns

5 3.5 - 12.2 3.4 - 13.4 ns

Propagation Delay,

OE to Y

’AC/CD74ACT258

tPLZ, tPHZ,

tPZL, tPZH 1.5 - - 167 - - 184 ns

3.3 5.3 - 18.7 5.2 - 20.6 ns

5 3.8 - 13.4 3.7 - 14.7 ns

Three-State Output

Capacitance CO- - -15- -15pF

Input Capacitance CI- - -10- -10pF

Power Dissipation Capacitance CPD

(Note 11) - - 130 - - 130 - pF

ACT TYPES

Propagation Delay,

In to Y

AC/ACT257

tPLH, tPHL 5

(Note 10) 2.8 - 9.7 2.7 - 10.7 ns

Propagation Delay,

S to Y

AC/ACT257

tPLH, tPHL 5 4 - 14 3.9 - 15.4 ns

CD54/74AC257, CD54/74ACT257, CD74ACT258

Propagation Delay,

OE to Y

AC/ACT257

tPLZ, tPHZ,

tPZL, tPZH 5 4.1 - 14.6 4 - 16.1 ns

Propagation Delay,

In to Y

’AC/CD74ACT258

tPLH, tPHL 5 2.4 - 8.5 2.3 - 9.3 ns

Propagation Delay,

S to Y

’AC/CD74ACT258

tPLH, tPHL 5 4 - 14 3.9 - 15.4 ns

Propagation Delay,

OE to Y

’AC/CD74ACT258

tPLZ, tPHZ,

tPZL, tPZH 5 4.1 - 14.6 4 - 16.1 ns

Three-State Output

Capacitance CO- - -15- -15pF

Input Capacitance CI- - -10- -10pF

Power Dissipation Capacitance CPD

(Note 11) - - 130 - - 130 - pF

NOTES:

8. Limits tested 100%.

9. 3.3V Min is at 3.6V, Max is at 3V.

10. 5V Min is at 5.5V, Max is at 4.5V.

11. CPD is used to determine the dynamic power consumption per multiplexer.

AC: PD = CPD VCC2 fi + ∑ (CL VCC2 fo)

ACT: PD=C

PD VCC2fi+∑(CLVCC2fo)+V

CC ∆ICC where fi= input frequency, fo= output frequency, CL= output load capacitance,

VCC = supply voltage.

FIGURE 1. THREE-STATE PROPAGATION DELAY TIMES AND TEST CIRCUIT

Switching Speciﬁcations Input tr, tf = 3ns, CL= 50pF (Worst Case) (Continued)

PARAMETER SYMBOL VCC (V)

-40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN TYP MAX

DUT

WITH

THREE-

STATE

OUTPUT

INPUT LEVEL

90%

10%

GND

tf = 3ns

tPZL

tPZH

tPLZ

tPHZ

OUTPUTS

ENABLED OUTPUTS

DISABLED

OUTPUT: LOW

T O OFF TO LOW

OUTPUT: HIGH

T O OFF TO HIGH

OTHER

INPUTS

(TIED HIGH

OR LO W)

OUTPUT

DISABLE

50pF

500Ω†

OUT

0.2VCC VOL (≠GND)

VOH (≠VCC)

0.8 VCC

GND (tPHZ, tPZH)

OUTPUTS

ENABLED

OPEN (tPHL, tPLH)

2 VCC (tPLZ, tPZL)

(OPEN DRAIN)

tr = 3ns

OUTPUT

DISABLE

†FOR A C SERIES ONLY: WHEN VCC = 1.5V, RL = 1kΩ

CD54/74AC257, CD54/74ACT257, CD74ACT258

FIGURE 2. INPUTS OR SELECT TO OUTPUT PROPAGATION

DELAYS (AC/ACT257) FIGURE 3. SELECT TO OUTPUT PROPAGATION DELAYS

(CD74ACT258)

90%

10%

tf = 3nstr = 3ns

nI0, nI1, S

tPLH tPHL

INPUT

LEVEL

GND

INPUT LEVEL

tPLH tPHL

DUT

OUTPUT

RL (NOTE)

OUTPUT

LOAD

500Ω

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

FIGURE 4. PROPAGATION DELAY TIMES

AC ACT

Input Level VCC 3V

Input Switching Voltage, VS0.5 VCC 1.5V

Output Switching Voltage, VS0.5 VCC 0.5 VCC

CD54/74AC257, CD54/74ACT257, CD74ACT258

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PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

CD54AC257F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type

CD54ACT257F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type

CD74AC257E ACTIVE PDIP N 16 25 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74AC257EE4 ACTIVE PDIP N 16 25 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74AC257M ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74AC257M96 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74AC257M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74AC257M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74AC257ME4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74AC257MG4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74ACT257E ACTIVE PDIP N 16 25 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74ACT257EE4 ACTIVE PDIP N 16 25 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74ACT257M ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74ACT257M96 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74ACT257M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74ACT257M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74ACT257ME4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74ACT257MG4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74ACT258M ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

CD74ACT258M96 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

CD74ACT258M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

CD74ACT258M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

CD74ACT258ME4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

CD74ACT258MG4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

PACKAGE OPTION ADDENDUM

www.ti.com 11-Nov-2009

Addendum-Page 1

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 11-Nov-2009

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm) W

(mm) Pin1

Quadrant

CD74AC257M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

CD74ACT257M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

CD74ACT258M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 19-Mar-2008

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74AC257M96 SOIC D 16 2500 333.2 345.9 28.6

CD74ACT257M96 SOIC D 16 2500 346.0 346.0 33.0

CD74ACT257M96 SOIC D 16 2500 333.2 345.9 28.6

CD74ACT258M96 SOIC D 16 2500 333.2 345.9 28.6

PACKAGE MATERIALS INFORMATION

www.ti.com 19-Mar-2008

Pack Materials-Page 2