2004 Microchip Technology Inc. DS21812D-page 1
MCP6291/2/3/4/5
Features
• Gain Bandwidth Product: 10 MHz (typ.)
• Supply Current: IQ = 1.0 mA
• Supply Voltage: 2.4V to 5.5V
• Rail-to-Rail Input/Output
• Extended Temperature Range: -40°C to +125°C
• Available in Single, Dual and Quad Packages
• Single with Chip Select (CS) (MCP6293)
• Dual with Chip Select (CS) (MCP6295)
Applications
• Automotive
• Port ab le Equi pm ent
• Photodiode Amplifier
• Analog Filters
• Notebooks and PDAs
• Battery-Pow e red Sys tem s
Available Tools
• SPICE Macro Model (at www.microchip.com)
•FilterLab
® Software (at www.microchip.com)
Description
The Microchip Technology Inc. MCP6291/2/3/4/5 family
of operational amplifiers (op amps) provide wide
bandwidth for the current. This family has a 10 MHz
Gain Bandwidth Product (GBWP) and a 65° phase
margin. This f amily also operates fro m a single supp ly
voltage as low as 2.4V, while drawing 1 mA (typ.)
quiescent current. In addition, the MCP6291/2/3/4/5
supports rail-to-rail input and output swing, with a
common mode input voltage range of VDD +300mV to
VSS – 300 mV. This family of operational amplifiers is
designed with Microchip’s advanced CMOS process.
The MCP6295 has a Chip Select input (CS) for dual op
amps in an 8-pin package. This device is manufactured
by cascading the two op amps, with the output of
op amp A being connected to the non-inverting input of
op amp B. The CS input puts the device in a Low-power
mode.
The MCP6291/2/3/4/5 family operates over the
Extended Temperature Range of -40°C to +125°C. It
also has a power supply range of 2.4V to 5.5V.
Package Types
1
2
3
4
VIN_
MCP6291
VDD
1
2
3
4
8
7
6
5
-
+
NC
NC
NC
VIN+
VSS
MCP6292
PDIP, SOIC, MSOP
MCP6294
1
2
3
4
14
13
12
11
-+-
+
10
9
8
5
6
7
+
--
+
PDIP, SOIC, TSSOP
1
2
3
4
8
7
6
5
-
+-
+
VOUT
MCP6293
8
7
6
5
-
+
VINA_
VINA+
VSS
VOUTA
VOUTB
VDD
VINB_
VINB+
VSS
VIN+
VIN_
NC CS
VDD
VOUT
NC
VOUTA
VINA_
VINA+
VDD VSS
VOUTB
VINB_
VINB+
VOUTC
VINC_
VINC+
VOUTD
VIND_
VIND+
PDIP, SOIC, MSOP
PDIP, SOIC, MSOP MCP6295
PDIP, SOIC, MSOP
1
2
3
4
8
7
6
5
+-
VINA_
VINA+
VSS
VOUTA/VINB+
VOUTB
VDD
VINB_
CS
-+
MCP6291
SOT-23-5
4
1
2
3-
+
5VDD
VIN–
VOUT
VSS
VIN+
MCP6291R
SOT-23-5
4
1
2
3-
+
5VSS
VIN–
VOUT
VDD
VIN+
MCP6293
SOT-23-6
4
1
2
3-
+
6
5
VSS
VIN+
VOUT CS
VDD
VIN–
1.0 mA, 10 MHz Rail-to-Rail Op Amp
MCP6291/2/3/4/5
DS21812D-page 2 2004 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS ........................................................................7.0V
All Inputs and Outputs ...................VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ......................................|VDD – VSS|
Output Short Circuit Current ................. ......... .... .. .Continuous
Current at Input Pins ....... .. ......... .. .... .. .... ....... .... .. .... .. ...±2 m A
Current at Output and Supply Pins ............................±30 mA
Storage Temperature.......... ..... .... .. .. .. .... .. ..... .-65°C to +150°C
Junction Temperature (TJ) ..........................................+150°C
ESD Protection On All Pins (HBM/MM)................≥ 4 kV/400V
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to m aximum rating conditions for ext ended periods
may affect device reliability.
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2,
RL = 10 kΩ to VDD/2 and VOUT ≈VDD/2.
Parameters Sym Min Typ Max Units Conditions
Input Of fset
Input Offset Voltage VOS -3.0 — +3.0 mV VCM = VSS (Note 1)
Input Offset Voltage
(Extended Temperature) VOS -5.0 — +5.0 mV TA = -40°C to +125°C,
VCM = VSS (Note 1)
Input Offset Temperature Drift ∆VOS/∆TA—±1.7—µV/°CT
A = -40°C to +125°C,
VCM = VSS (Note 1)
Power Supply Rejection Ratio PSRR 70 90 — dB VCM = VSS (Note 1)
Input Bias , Input Offset Current an d Impe da nce
Input Bias Current IB— ±1.0 — pA Note 2
At Temperature IB— 50 200 pA TA = +85°C (Note 2)
At Temperature IB—2 5nAT
A = +125°C (Note 2)
Input Offset Current I OS — ±1.0 — pA Note 3
Common Mode Input Impedance ZCM —10
13||6 — Ω||pF Note 3
Differential Input Impedance ZDIFF —10
13||3 — Ω||pF Note 3
Common Mode (Note 4)
Common Mode Input Range VCMR VSS − 0.3 — VDD + 0.3 V
Common Mode Rejection Ratio CMRR 70 85 — dB VCM = -0. 3 V to 2 .5V, V DD = 5V
Common Mode Rejection Ratio CMRR 65 80 — dB VCM = -0. 3 V to 5 .3V, V DD = 5V
Open-Loop Gain
DC Open-Loop Gain (Large Signal) AOL 90 110 — dB VOUT = 0.2V to VDD – 0.2V,
VCM =V
SS (Note 1)
Output
Maximum Output Voltage Swing VOL, VOH VSS + 15 — VDD – 15 mV
Output Short Circuit Current ISC —±25—mA
Power Supply
Supply Voltage VDD 2.4 — 5.5 V TA = -40°C to +125°C
Quiescent Current per Amplifier IQ0.7 1.0 1.3 mA IO = 0
Note 1: The MCP6295’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
2: The current at the MCP6295’s VINB– pin is specified by IB only.
3: This specification does not apply to the MCP6295’s VOUTA/VINB+ pin.
4: The MCP6295’s VINB– pin (op amp B) has a c o m m on mode range ( VCMR) of VSS + 100 mV to VDD – 100 mV.
The MCP6295’s VOUTA/VINB+ pin (op amp B) h as a voltage range spec ified by VOH and VOL.
2004 Microchip Technology Inc. DS21812D-page 3
MCP6291/2/3/4/5
AC ELECTRICAL SPECIFICATIONS
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 10.0 — MHz
Phase Margin at Unity-Gain PM — 65 — °
Slew Rate SR — 7 — V/µ s
Noise
Input Noise Voltage Eni —3.5—µV
P-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —8.7—nV/√Hz f = 10 kHz
Input Noise Current Density ini —3—fA/√Hz f = 1 kHz
Electrical Characteristics: Unless otherwise indicated, VDD = +2.4V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Tem perat ure Range TA-40 — +125 °C Note
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W
Thermal Resistance, 6L-SOT-23 θJA — 230 — °C/W
Thermal Resistance, 8L-PDIP θJA —85—°C/W
Thermal Resistance, 8L-SOIC θJA — 163 — °C/W
Thermal Resistance, 8L-MSOP θJA — 206 — °C/W
Thermal Resistance, 14L-PDIP θJA —70 —°C/W
Thermal Resistance, 14L-SOIC θJA —120 —°C/W
Thermal Resistance, 14L-TSSOP θJA —100 —°C/W
Note: The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
MCP6291/2/3/4/5
DS21812D-page 4 2004 Microchip Technology Inc.
MCP6293/MCP6295 CHIP SELECT (CS) SPECIFICATIONS
FIGURE 1-1: Timing Diagram for the
Chip Select (CS) pin on the MCP6293 and
MCP6295.
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logic Threshold, Low VIL VSS —0.2V
DD V
CS Input Current, Low ICSL —0.01— µACS = VSS
CS High Specifica t ions
CS Logic Threshold, High VIH 0.8 VDD —V
DD V
CS Input Current, High ICSH —0.7 2 µACS = VDD
GND Current per Amplifier ISS —-0.7— µACS = VDD
Amplifier Output Leakage — — 0.01 — µA CS = V DD
Dynamic Specifications (Note 1)
CS Low to Valid Amplifier Output,
Turn-on Time tON —410µsCS Low ≤ 0.2 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.9 VDD/2,
VDD = 5.0V
CS High to Amplifier Output High-Z tOFF —0.01— µsCS High ≥ 0.8 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.1 VDD/2
Hysteresis VHYST —0.6— VV
DD = 5V
Note 1: The input condition (VIN) specified applies to both op amp A and B of the MCP6295. The dynamic specification is tested
at the output of op amp B (VOUTB).
VIL
Hi-Z
tON
VIH
CS
tOFF
VOUT
-0.7 µA (typ.)
Hi-Z
ISS
ICS 0.7 µA (typ .) 0.7 µA (typ.)
-0.7 µA (typ.
)
-1.0 mA (typ.)
10 nA (typ.)
2004 Microchip Technology Inc. DS21812D-page 5
MCP6291/2/3/4/5
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Bias Current at
TA= +85 °C.
FIGURE 2-3: Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 2.4V.
FIGURE 2-4: Input Offset Voltage Drift.
FIGURE 2-5: Input Bias Current at
TA= +125 °C.
FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 5.5V.
Note: The g r ap hs and t ables prov id ed fol low i ng thi s n ote are a sta tis tic al s umm ary based on a l im ite d n um ber of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
1%
2%
3%
4%
5%
6%
7%
8%
9%
10%
11%
12%
-2.8
-2.4
-2.0
-1.6
-1.2
-0.8
-0.4
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
Input Offset Voltage (mV)
Percentage of Occurrences
840 Samples
VCM = VSS
0%
5%
10%
15%
20%
25%
30%
35%
40%
0 102030405060708090100
Input Bias Current (pA)
Percenta ge of Occu r renc es
210 Samples
TA = 85°C
0
50
100
150
200
250
300
350
400
-0.50.00.51.01.52.02.53.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 2.4V
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
0%
5%
10%
15%
20%
25%
-10
-8
-6
-4
-2
0
2
4
6
8
10
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
840 Samples
VCM = VSS
TA = -40°C to +125°C
0%
5%
10%
15%
20%
25%
30%
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
Input Bias Current (pA)
Percenta ge of Occu r renc es
210 Samples
TA = +125°C
200
250
300
350
400
450
500
550
600
650
700
750
800
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
MCP6291/2/3/4/5
DS21812D-page 6 2004 Microchip Technology Inc.
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-7: Input Offset Voltage vs.
Output Voltage.
FIGURE 2-8: CMRR, PSRR vs.
Frequency.
FIGURE 2-9: Input Bias, Offset Currents
vs. Common Mode Input Voltage at TA=+85°C.
FIGURE 2-10: Input Bias, Input Offset
Currents vs. Ambient Temperature.
FIGURE 2-11: CMRR, PSRR vs. Ambient
Temperature.
FIGURE 2-12: Input Bias, Offset Currents
vs. Common Mode Input V oltage at
TA= +125°C.
100
150
200
250
300
350
400
450
500
550
600
650
700
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Volta ge (V)
Input Offset Voltage (µV)
VCM = VSS
Representati ve Part
VDD = 5.5V
VDD = 2.4V
20
30
40
50
60
70
80
90
100
110
1.E+00 1.E+01 1 .E+02 1.E+ 03 1.E+04 1.E+05 1 .E+06
Frequency (Hz)
CMRR, PSRR (dB)
1 10k 100k 1M10010 1k
PSRR+
PSRR-
CMRR
-25
-15
-5
5
15
25
35
45
55
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(pA)
TA = +85°C
VDD = 5.5V
Input Bias Current
Input Offset Current
1
10
100
1,000
10,000
25 35 45 55 65 75 85 95 105 115 125
Ambient Temper ature (°C)
Input Bias, Offset Currents
(pA)
Input Bias Current
Input Offset Current
VCM = VDD
VDD = 5.5V
60
70
80
90
100
110
120
-50 -25 0 25 50 75 100 12
5
Ambient Temper ature (°C)
PSRR, CMRR (dB)
PSRR
VCM = VSS
CMRR
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(nA)
TA = +125°C
VDD = 5.5V
Input Bias Current
Input Offset Current
2004 Microchip Technology Inc. DS21812D-page 7
MCP6291/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-13: Quiescent Current vs.
Power Supply Voltage.
FIGURE 2-14: Open-Loop Gain, Phase vs.
Frequency.
FIGURE 2-15: Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-16: Output Voltage Headroom
vs. Output Current Magnitude.
FIGURE 2-17: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
FIGURE 2-18: Slew Rate vs. Ambien t
Temperature.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
Quiescent Current
(mA/Amplifier)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
-20
0
20
40
60
80
100
120
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Frequency (Hz)
Open-Loop Gain (dB)
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
Gain
Phase
0.1 1 10 100 1k 10k 100k 1M 10M 100M
0.1
1
10
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequenc y (Hz)
Maximum Output Voltage
Swing (VP-P)
1k 10k 100k 1M 10M
VDD = 5.5V
VDD = 2.4V
1
10
100
1000
0.01 0.1 1 10
Output Curr ent Magni tude (mA)
Ouput Voltage Headroom (mV)
VOL - VSS
VDD - VOH
0
2
4
6
8
10
12
14
16
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Gain Bandwidth Product
(MHz)
50
55
60
65
70
75
80
85
90
Phase Ma r gin (° )
GBWP, VDD = 5.5V
GBWP, VDD
= 2.4V
PM, VDD = 5.5V
PM, VDD = 2.4V
0
2
4
6
8
10
12
-50 -25 0 25 50 75 100 125
Ambient Tempe rat ure (°C)
Slew Rate (V/µs)
Rising Edge , VDD
= 5.5V
VDD
= 2.4V
Falling Edge, VDD
= 5.5V
VDD
= 2.4V
MCP6291/2/3/4/5
DS21812D-page 8 2004 Microchip Technology Inc.
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-19: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-20: Output Short Circuit Current
vs. Power Supply Voltage.
FIGURE 2-21: Quiescent Current vs.
Chip Select (CS) Voltage at VDD = 2.4V
(MCP6293 and MCP6295 only).
FIGURE 2-22: Input Noise Volt age Density
vs. Common Mode Input Voltage at 10 kHz.
FIGURE 2-23: Channel-to-Channel
Separation vs. Frequency (MCP6292, MCP6294
and MCP6295 only).
FIGURE 2-24: Quiescent Current vs.
Chip Select (CS) Voltage at VDD = 5.5V
(MCP6293 and MCP6295 only).
1
10
100
1,000
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
Input Noise Voltage Density
(nV/Hz)
0.1 10010 1k 100k10k 1M1
0
5
10
15
20
25
30
35
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
Ouptut Short Circuit Current
(mA)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
Chip Select Volt age ( V)
Quiescent Current
(mA/Amplifier)
Hysteresis
Op-Amp shuts off here
Op-Amp turns on here
VDD = 2.4V
CS swept
high to low CS swept
low to high
0
1
2
3
4
5
6
7
8
9
10
11
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/¥Hz)
f = 10 kHz
VDD = 5.0V
100
110
120
130
140
1 10 100
Frequency (kHz)
Channel-to-Channel Separation
(dB)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.00.51.01.52.02.53.03.54.04.55.05.5
Chip Select Voltag e (V)
Quies cent Curre nt
(mA/Amplifier)
Hysteresis
VDD
= 5.5V
CS swept
low to high
CS swept
high to low
Op Amp shuts off
Op Amp turns on
2004 Microchip Technology Inc. DS21812D-page 9
MCP6291/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-25: Large-Signal Non-inverting
Pulse Response.
FIGURE 2-26: Small-Signal Non-inverting
Pulse Response.
FIGURE 2-27: Chip Select (CS) to
Amplifier Output Response Time at VDD = 2.4V
(MCP6293 and MCP6295 only).
FIGURE 2-28: Large-Signal Inverting Pulse
Response.
FIGURE 2-29: Small-Signal Inverting Pulse
Response.
FIGURE 2-30: Chip Select (CS) to
Amplifier Output Response Time at VDD = 5.5V
(MCP6293 and MCP6295 only).
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 1.E-06 2. E-06 3.E-06 4. E-06 5.E- 06 6.E-06 7.E -06 8.E-06 9. E-06 1.E-05
Time (1 µs/div)
Output Voltage (V)
G = +1V/V
VDD = 5.0V
Time (200 ns/div)
Output Voltage (10 mV/div)
G = +1V/V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.E+00 5.E-06 1.E-05 2.E -05 2.E-05 3.E-0 5 3.E-05 4.E-05 4.E-0 5 5.E-05 5.E-05
Time (5 µs/di v )
Chip Select, Output Voltages
(V)
VOUT Output On
Output High-Z
VDD
= 2.4V
G = +1V/V
VIN = V
CS Voltage
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 1.E-06 2.E- 06 3.E-06 4.E -06 5.E-06 6.E -06 7.E-06 8.E -06 9.E-06 1. E-05
Time (1 µs/div)
Output Voltage (V)
G = -1V/V
VDD = 5.0V
Time (200 ns/div)
Output Voltage (10 mV/div)
G = -1V/V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0.E+00 5.E-06 1.E-05 2. E-05 2.E- 05 3.E-05 3. E-05 4.E -05 4.E-05 5.E-05 5.E-05
Time (5 µs/div)
Chip Select, Output Voltages
(V)
VOUT
Output High-Z
VDD
= 5.5V
G = +1V/V
VIN = V
CS Voltage
Output On
MCP6291/2/3/4/5
DS21812D-page 10 2004 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS
TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
3.1 Analog Outputs
The output pins are low-impedance voltage sources.
3.2 Analog Inputs
The non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
3.3 MCP6295’s VOUTA/VINB+ Pin
For the MCP6295 only, the output of op amp A is
connected directly to the non-inverting input of
op amp B; this is the VOUTA/VINB+ pi n. This connec tion
makes it pos sible to prov ide a Ch ip Sele ct p in for d uals
in 8-pin packages.
3.4 CS Digital Input
This is a CMOS , Schmitt-triggered inpu t that plac es the
part into a low power mode of operation.
3.5 Power Supply (VSS and VDD)
The pos iti ve pow e r s upp ly (VDD) is 2.4V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configu ra tion). In th is case , VSS is conn ect ed t o
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts need to
use a bulk capacitor (within 100 mm), which can be
shared with nearby analog parts.
MCP6291
(PDIP,
SOIC,
MSOP)
MCP6291
(SOT-23-5) MCP6271R
(SOT-23-5)
MCP6293
(PDIP,
SOIC,
MSOP)
MCP6293
(SOT-23-6) Symbol Description
61 161V
OUT Analog Output
24 424V
IN– Inverting Input
33 333V
IN+ Non-inverting Input
75 276V
DD Positive Power Supply
42 542V
SS Negative Power Supply
—— — 8 5CS
Chip Select
1,5,8 — — 1,5 — NC No Internal Connection
MCP6292 MCP6294 MCP6295 Symbol Description
11—V
OUTA A nalog Output (op amp A)
222V
INA– Inverting Input (op amp A)
333V
INA+ Non-inverting Input (op amp A)
848 V
DD Positive Power Supply
55—V
INB+ Non-inverting Input (op amp B)
666V
INB– Inverting Input (op amp B)
777V
OUTB Analog Output (op amp B)
—8—V
OUTC Analog Output (op amp C)
—9—V
INC– Inverting Input (op amp C)
—10— V
INC+ Non -invertin g Input (op amp C)
4114 V
SS Negative Power Supply
—12— V
IND+ Non -invertin g Input (op amp D)
—13— V
IND– Inverting Input (op amp D)
—14— V
OUTD Analog Output (op amp D)
—— 1V
OUTA/VINB+ Analog Output (op amp A)/Non-inverting Input (op amp B)
—— 5 CS
Chip Select
2004 Microchip Technology Inc. DS21812D-page 11
MCP6291/2/3/4/5
4.0 APPLICATION INFORMATION
The MCP6291/2/3/4/5 family of op amps is manufac-
tured using Microchip’s state-of-the-art CMOS
process, specifically designed for low-cost, low-power
and general purpose applications. The low supply
voltage, low quiescent current and wide bandwidth
makes the MCP6291/2/3/4/5 ideal for battery-powered
applications.
4.1 Rail- to-Rail Inputs
The MCP6291/2/3/4/5 op amp is designed to prevent
phase reversal when the input pins exceed the supply
volt ages. Figure 4-1 shows th e input vol tage exc eeding
the supply voltage without any phase reversal.
FIGURE 4-1: The MCP6291/2/3/4/5 Show
No Phase Reversal.
The input stage of the MCP6291/ 2/3/4/5 op amps use
two differential CMOS input stages in parallel. One
operates at low common mode input voltage (VCM),
while the other operates at high VCM. With this topol-
ogy, the device operates with VCM up to 0.3 mV above
VDD and 0.3 mV below VSS. The Input Offset Voltage
(VOS) is measured at VCM =V
SS –0.3mV and
VDD + 0.3 mV to ensure proper operation.
Input voltages that exceed the absolute maximum volt-
age (VSS – 0.3V to VDD + 0. 3V) can cause excessive
current to flow into or out of the input pins. Current
beyond ± 2 mA can cause reliability problems. Applica-
tions that exceed this rating must be externally limited
with a resistor, as shown in Figure 4-2.
FIGURE 4-2: Input Current Limiting
Resistor (R IN).
4.2 Rail-to-Rail Output
The output voltage range of the MCP6291/2/3/4/5 op
amp is VDD –15mV (min.) and V
SS +15mV (max.)
when RL=10kΩ is connected to VDD/2 and
VDD = 5.5V. Refer to F igu re 2-16 for m ore in fo r m at i on .
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensit ive to c apa citiv e load s, thoug h al l gain s show th e
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The band-
wid th will be g enerally low er than the bandwidth with no
capacitive load.
FIGURE 4-3: Output Resistor, RISO
stabil izes large capacitive loads.
Figure 4-4 gives recommended RISO values for differ-
ent capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit 's noise gain. For non-inverti ng gains, GN an d the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
-1
0
1
2
3
4
5
6
-15 -14 -13 -1 2 -11 -10 -9 -8 -7 -6 -5
Time (1 ms/div)
Input, Output Voltage (V)
VDD = 5.0V
G = +2V/V
VIN VOUT
RIN VSS Minimum expected VIN
()–2 mA
-----------------------------------------------------------------------------------
≥
RIN Maximum expected VIN
()VDD
–
2 mA
-------------------------------------------------------------------------------------
≥
VIN
RIN VOUT
–
+
MCP629X
VIN
RISO VOUT
CL
–
+
MCP629X
MCP6291/2/3/4/5
DS21812D-page 12 2004 Microchip Technology Inc.
FIGURE 4-4: Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation and
simulations with the MCP6291/2/3/4/5 SPICE macro
model are helpful.
4.4 MCP629X Chip Select (C S )
The MCP6293 and MCP6295 are single and dual op
amps with Chip Select (CS), respectively. When CS is
pulled high, the supply current drops to 0.7 µA (typ.)
and flows through the CS pin to VSS. When this
happens, the amplifier output is put into a high-imped-
ance state. By pulling CS low, the amplifier is enabled.
If the CS pin is left floating, the amplifier may not
operate properly. Figure 1-1 shows the output voltage
and supply current response to a CS pulse.
4.5 Cascaded Dual Op Amps
(MCP6295)
The MC P629 5 is a dua l op am p with Ch ip Se lec t (CS).
The Chip Sele ct input is availa ble on what woul d be the
non-inverting input of a standard dual op amp (pin 5).
This is available because the output of op amp A
connects to the non-inverting input of op amp B, as
shown in Fi gure 4-5. The Chip Select input, which can
be connected to a microcontroller I/O line, puts the
device in Low-power mode. Refer to Section 4.3
“MCP6293/5 Chip Select (CS)”.
FIGURE 4-5: Cascaded Gain Amplifier.
The output of op amp A is loaded by the input imped-
ance of op amp B, which is typically 1013Ω||6pF, as
specified in the DC specification table (Refer to
Section 4.3 “Capacitive Loads” for further details
regarding capacitive loads).
The common mode input range of these op amps is
specified in the data sheet as VSS – 300 mV and
VDD + 300 mV. However, since the output of op amp A
is l imite d to V OL and VOH (20 mV from the rails with a
10 kΩ load), the n on-i nv erti ng in pu t range of op amp B
is limited to the common mode input range of
VSS + 20 mV and VDD –20mV.
4.6 Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provi de large, slow curre nts. This b ulk cap acitor can be
shared with other analog parts.
4.7 PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
betwee n nearby traces i s 1012Ω. A 5V dif ferenc e would
cause 5 pA of current to flow, which is greater than the
MCP6291/2/3/4/5 family’s bias current at 25°C (1 pA,
typ.).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive p ins (or t r ace s). The gua rd
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-6.
10
100
10 100 1,000 10,00
0
Normalized Load Capacitance; CL/GN (pF)
Recommended RISO (Ω
)
GN = 1 V/V
GN ≥ 2 V/V
AB
CS
2
3
5
6
7
VINA+
VOUTB
MCP6295
1
VINA–
VOUTA/VINB+VINB–
2004 Microchip Technology Inc. DS21812D-page 13
MCP6291/2/3/4/5
FIGURE 4-6: Example Guard Ring Layout
for Inverting Gain.
1. For Inverting Gain and Transimpedance
Amplifiers (convert current to voltage, such as
photo detectors):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
2. Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (VIN–). This b iases th e g uard ri ng to the
common mode input voltage.
4.8 Application Circuits
4.8.1 MULTIPLE FEEDBACK LOW-PASS
FILTER
The MCP6291/2/3/4/5 op amp can be used in active-
filter applications. Figure 4-7 shows an inverting, third-
order, multiple feedback low-pass filter that can be
used as an anti-aliasing filter.
FIGURE 4-7: Multiple Feedback Low-
Pass Filter.
This filter, and others, can be designed using
Microchip’s FilterLab® software, which is available on
our web site (www.microchip.com).
4.8.2 PHOTODIODE AMPLIFIER
Figure 4-8 shows a photodiode biased in the photovol-
taic mode for high precision. The resistor R converts
the diode current ID to the voltage VOUT. The ca p ac i tor
is used to limit the bandwidth or to stabilize the circuit
against the diode’s capacitance (it is not always
needed).
FIGURE 4-8: Photodiode Amplifier.
Guard Ring
VSS
VIN–V
IN+
MCP6291
VOUT
VIN
VDD/2
R3C3
C1
R1R2
C4
R4
MCP6291
VOUT
ID
VDD/2
R
C
light
MCP6291/2/3/4/5
DS21812D-page 14 2004 Microchip Technology Inc.
4.8.3 CASCADED OP AMP
APPLICATIONS
The MCP6295 provides the flexibility of Low-power
mode for dual op amps in an 8-pin package. The
MCP6295 eliminates the added cost and space in
battery-powered applications by using two single op
amps with Ch ip Select lines or a 1 0-pin dev ice with one
Chip Select line for both op amps. Since the two op
amps are internally cascaded, this device cannot be
used in circuits that requ ire active or passive elements
between the two op amps. However, there are several
applications where this op amp configuration with
Chip Select line becomes suitable. The circuits below
show possible applications for this device.
4.8.3.1 Load Isolation
With the cas caded op amp configuration, op amp B can
be used to isolate the load from op amp A. In applica-
tions w here op amp A is driving c ap acitiv e or low resi s-
ta nce load s in t he feedbac k lo op (such a s an integra tor
circuit or filter circuit), the op amp may not have
suffici e nt s ou rce cu r re nt to dr iv e t he l oad . In th is ca se ,
op amp B can be used as a buffer.
FIGURE 4-9: Isolating the Load with a
Buffer.
4.8.3.2 Cascaded Gain
Figure 4-10 shows a cascaded gain circuit configura-
tion with Chip Sel ect. Op amp s A and B are co nfi gure d
in a no n-inve rtin g amplif ier config uration . I n this confi g-
uration, it is important to note that the input offset volt-
age of op amp A is amplified by the gain of op amp A
and B, as shown below:
Therefore, it is recommended to set most of the gain
with op amp A and use op amp B with relatively small
gain (e.g., a unity-gain buffer).
FIGURE 4-10: Cascaded Gain Circuit
Configuration.
4.8.3.3 Difference Amplifier
Figure 4-11 shows op amp A as a difference amplifier
with Chip Select. In this configuration, it is recom-
mended to use well-matched resistors (e.g., 0.1%) to
incr ease th e Common Mo de Rejec tion Rat io (CMRR ).
Op amp B can b e used for add itional ga in or as a unity -
gain buffer to isolate the load from the difference
amplifier.
FIGURE 4-11: Difference Ampli fie r Circuit .
AB
MCP6295
CS
VOUTB
Load
VOUT VINGAGBVOSAGAGBVOSBGB
++=
Where:
GA= op amp A gain
GB= op amp B gain
VOSA = op amp A input o ffset voltage
VOSB = op amp B input o ffset voltage
AB
CS
R4R3R2R1
VIN
VOU
T
MCP6295
AB
CS
R2R1
VIN2
VIN1 R2
R1
VOU
T
R4R3
MCP6295
2004 Microchip Technology Inc. DS21812D-page 15
MCP6291/2/3/4/5
4.8.3.4 Buffered Non-inverting Integrator
Figure 4-12 shows a lossy no n-in ve rtin g i nteg r ato r th at
is buffered and has a Chip Select input. Op amp A is
configured as a non-inverting integrator. In this config-
uration, matching the impedance at each input is
recommended. RF is used to provide a feedback loop
at frequencies << 1/(2πR1C1) and makes this a lossy
integrato r (it ha s a finit e gain at DC ). Op am p B is used
to isolate the load from the integrator.
FIGURE 4-12: Buffered Non-inverting
Integrator with Chip Select.
4.8.3.5 Inverting Integrator with Active
Compensation and Chip Select
Figure 4-13 us es an a cti ve c om pen sa tor (op a mp B) to
compensate for the non-ideal op amp characteristics
introduced at higher frequencies. This circuit uses
op amp B as a unity-gain buffer to isolate the integra-
tion cap ac ito r C1 from op amp A and drives the capac-
itor with low-impedance source. Since both op amps
are matched very well, they provide a high quality
integrator.
FIGURE 4-13: Integrator Circuit with Active
Compensation.
4.8.3.6 Second-Order MFB Low-Pass Filter
with an Extra Pole-Zero Pair
Figure 4-14 is a second-order multiple feedback low-
pass filter with Chip Select. Use the FilterLab® software
from Micr ochi p to det ermine the R and C valu es for the
op amp A’s second-order filter. Op amp B can be used
to add a pole-zero pair using C3, R6 and R7.
FIGURE 4-14: Second-Order Multiple
Feedback Low-Pass Filter with an Extra Pole-
Zero Pair.
4.8.3.7 Second-Order Sallen-Key Low-Pass
Filter with an Extra Pole-Zero Pair
Figure 4-15 is a second-order, Sallen-Key low-pass
filter with Chi p Select. Use the Filter Lab® software from
Microchip to determine the R and C values for the op
amp A’s second-order filter. Op amp B can be used to
add a pole-zero pair using C3, R5 and R6.
FIGURE 4-15: Second-Order Sallen-Key
Low-Pass Filter with an Extra Pole-Zero Pair and
Chip Select.
AB
CS
RF
C1
R2C2
R1
VIN
VOUT
MCP6295
R1C1R2RF
||
()C2
=
A
CS
B
VIN
VOUT
R1C1
MCP6295
AB
CS
R1
C1
R5
VIN VOUT
C2R4
R3R2
R6C3
MCP6295
R7
AB
CS
R2
C1
R1
VIN
VOUT
R4R3
C2
C3
R5
MCP6295
R6
MCP6291/2/3/4/5
DS21812D-page 16 2004 Microchip Technology Inc.
4.8.3.8 Capacitorless Second-Order
Low-Pass filter with Chip Select
The low-pass filter shown in Figure 4-16 does not
require external capacitors and uses only three exter-
nal resistors; the op amp’s GBWP sets the corner
frequency. R1 and R2 are used to set the circuit gain
and R3 is used to set the Q. To avoid gain peaking in
the frequency response, Q needs to be low (lower
values need to be selected for R3). Note that the
amplifier bandwidth varies greatly over temperature
and process. However, this configuration provides a
low cost solution for applications with high bandwidth
requirements.
FIGURE 4-16: Capacitorless Second-Order
Low-Pass Filter with Chip Select.
5.0 DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6291/2/3/4/5 family of op amps.
5.1 SPICE Macro Model
The latest SPICE macro model for the
MCP6291/2/3/4/5 op amp s is av ailabl e on ou r web site
at www.microchi p.com. This model is int ended to be an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. See the
macro model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro m odel need to be v ali dat ed b y
comparing them to the data sheet specifications and
characteristic curves.
5.2 FilterLab® Software
Microc hip’ s Fi lterLab sof tware is an in novat ive too l that
simplifies analog active-filter (using op amps) design.
Available at no cost from our web site at
www.microc hip .c om, the Filt erLa b design tool pr ovides
full schematic diagrams of the filter circuit with
component values. It also outputs the filter circuit in
SPICE format, which can be used with the macro
model to simulate actual filter performance.
AB
CS
VREF
VIN
VOUT
R2R1
R3
MCP6295
2004 Microchip Technology Inc. DS21812D-page 17
MCP6291/2/3/4/5
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Legend: XX...X Customer specific information*
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the eve nt the full Micro chip p art num ber can not be ma rked on on e line, it will
be carried ov er to the ne xt li ne thus lim iti ng th e nu mb er of av ai lab le c hara ct ers
for customer specific information.
*Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6291
E/P256
0436
MCP6291
E/SN0436
256
8-Lead MSOP
XXXXXX
YWWNNN
6291E
436256
5-Lead SOT-23 (MCP6291 and MCP6291R)Example:
XXNN CJ25
Device Code
MCP6291 CJNN
MCP6291R EVNN
Note: Applies to 5-Lead SOT-23
6-Lead SOT-23 (MCP6283)Example:
XXNN CM25
Example:
MCP6291/2/3/4/5
DS21812D-page 18 2004 Microchip Technology Inc.
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6294) Example:
14-Lead TSSOP (MCP6294) Example:
14-Lead SOIC (150 mil) (MCP6294) Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXX
YYWWNNN
XXXXXX
YYWW
NNN
MCP6294-E/P
0436256
6294EST
0436
256
XXXXXXXXXX MCP6294ESL
0436256
2004 Microchip Technology Inc. DS21812D-page 19
MCP6291/2/3/4/5
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
10501050
β
Mold Draft Angle Bottom
10501050
α
Mold Draft Angle Top
0.500.430.35.020.017.014BLead Width
0.200.150.09.008.006.004
c
Lead Thickness
10501050
φ
Foot Angle
0.550.450.35.022.018.014LFoot Length
3.102.952.80.122.116.110DOverall Length
1.751.631.50.069.064.059E1Molded Package Width
3.002.802.60.118.110.102EOverall Width
0.150.080.00.006.003.000A1Standoff
1.301.100.90.051.043.035A2Molded Package Thickness
1.451.180.90.057.046.035AOverall Height
1.90.075
p1
Outside lead pitch (basic)
0.95.038
p
Pitch
55
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
1
p
D
B
n
E
E1
L
c
β
φ
α
A2
A
A1
p1
exceed .005" (0.127mm) per side.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
Notes:
EIAJ Equivalent: SC-74A
Drawing No. C04-091
*Controlling Parameter
MCP6291/2/3/4/5
DS21812D-page 20 2004 Microchip Technology Inc.
6-Lead Plastic Small Outline Transistor (CH) (SOT-23)
10501050
β
Mold Draft Angle Bottom
10501050
α
Mold Draft Angle Top
0.500.430.35.020.017.014BLead Width
0.200.150.09.008.006.004
c
Lead Thickness
10501050
φ
Foot Angle
0.550.450.35.022.018.014LFoot Length
3.102.952.80.122.116.110DOverall Length
1.751.631.50.069.064.059
E1
Molded Package Width
3.002.802.60.118.110.102EOverall Width
0.150.080.00.006.003.000
A1
Standoff
1.301.100.90.051.043.035
A2
Molded Package Thickness
1.451.180.90.057.046.035AOverall Height
1.90.075
p1
Outside lead pitch (basic)
0.95.038
p
Pitch
66
n
Number of Pins
MAX
NOM
MINMAX
NOM
MINDimension Limits
MILLIMETERSINCHES*Units
1
D
B
n
E
E1
L
c
β
φ
α
A2
A
A1
p1
exceed .005" (0.127mm) per side.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
Notes:
JEITA (formerly EIAJ) equivalent: SC-74A
Drawing No. C04-120
*Controlling Parameter
2004 Microchip Technology Inc. DS21812D-page 21
MCP6291/2/3/4/5
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
D
A
A1
L
c
(F)
α
A2
E1
E
p
B
n 1
2
φ
β
5°
5° -
-
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
.037 REF
FFootprint (Reference)
exceed .010" (0.254mm) per side.
Notes:
Drawing No. C04-111
*Controlling Parameter
Mold Draft Angle Top
Mold Draft Angle Bottom
Foot Angle
Lead Width
Lead Thickness
β
α
c
B
φ
.003
.009
.006
.012
Dimension Limits
Overall Height
Molded Package Thickness
Molded Package Width
Overall Length
Foot Length
Standoff
Overall Width
Number of Pins
Pitch
A
L
E1
D
A1
E
A2
.016 .024
.118 BSC
.118 BSC
.000
.030
.193 TYP.
.033
MIN
p
n
Units
.026 BSC
NOM
8
INCHES
0.95 REF
-
-
.009
.016
0.08
0.22
0°
0.23
0.40
8°
MILLIMETERS*
0.65 BSC
0.85
3.00 BSC
3.00 BSC
0.60
4.90 BSC
.043
.031
.037
.006
0.40
0.00
0.75
MIN
MAX
NOM
1.10
0.80
0.15
0.95
MAX
8
--
-
15°5° -
15°5° -
JEDEC Equivalent: MO-187
0° - 8°
5°
5° -
-
15°
15°
--
-
-
MCP6291/2/3/4/5
DS21812D-page 22 2004 Microchip Technology Inc.
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dime nsion Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoul der Widt h E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
2004 Microchip Technology Inc. DS21812D-page 23
MCP6291/2/3/4/5
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOve ra l l Length 3.993.913.71.157.154.146E1Molded Package Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Molded Package Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 88
n
Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0. 254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
MCP6291/2/3/4/5
DS21812D-page 24 2004 Microchip Technology Inc.
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
n
D
1
2
eB
β
E
c
A
A1
B
B1
L
A2
p
α
Units INCHES* MILLIMETERS
Dimen sion Li mits MIN NOM MAX MI N NOM MAX
Number of Pins n14 14
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Widt h E .300 .313 .3 25 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overal l Length D .740 .75 0 .7 60 1 8.8 0 19.05 19. 30
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .37 0 .430 7.87 9.40 10 .92
Mold Draft Angle Top α5 10 15 5 10 15
β5 10 15 5 10 15
Mold Draft Angle Bottom
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
§ Significant Characteristic
2004 Microchip Technology Inc. DS21812D-page 25
MCP6291/2/3/4/5
14-Lead Plasti c Small Outline (SL) – Narrow, 150 mil (SOIC)
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.510.380.25.020.015.010hChamfer Distance 8.818.698.56.347.342.337DOveral l Length 3.993.903.81.157.154.150
E1
Molded Package Width 6.205.995.79.244.236.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Molded Package Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 1414
n
Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
h
L
c
β
45°
φ
α
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
§ Significa nt Char acte ri stic
MCP6291/2/3/4/5
DS21812D-page 26 2004 Microchip Technology Inc.
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
840840
φ
Foot Angle
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.300.250.19.012.010.007B1Lead Width 0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Length 5.105.004.90.201.197.193DMolded Package Length 4.504.404.30.177.173.169E1Molded Package Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002A1Standoff § 0.950.900.85.037.035.033A2Molded Package Thickness 1.10.043AOverall Height 0.65.026
p
Pitch 1414
n
Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERS*INCHESUnits
L
β
c
φ
2
1
D
n
B
p
E1
E
α
A2A1
A
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing N o. C04- 087
§ Significant Characteristic
2004 Microchip Technology Inc. DS21812D-page 27
MCP6291/2/3/4/5
APPENDIX A: REVISION HISTORY
Revision A (June 2003)
Original data sheet release.
Revision B (October 2003)
Revision C (June 2004)
Revision D (December 2004)
The following is the list of modifications:
1. Added SOT-23-5 packages for the MCP6291
and MCP6291R single op amps.
2. Added SOT-23-6 package for the MCP6293
single op amp.
3. Added Sec tion 3.0 “Pin Descriptions”.
4. Corrected application circuits (Section 4.8
“Application Circuits”).
5. Added SOT-23-5 and SOT-23-6 packages and
corrected package marking information
(Section 6.0 “Packaging Information”).
6. Added A ppendix A: Revision History.
MCP6291/2/3/4/5
DS21812D-page 28 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. DS21812D-page 29
MCP6291/2/3/4/5
PRODUCT IDENTIFICATION SYSTEM
To order or o btain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Device: MCP6291: Single Op Amp
MCP6291T: Single Op Amp
(Ta pe and Reel )
(SOIC, MSOP, SOT-23-5)
MCP6291RT: Single Op Amp
(Tape and Reel) (SOT-23-5)
MCP6292: Dual Op Amp
MCP6292T: Dual Op Amp
(Tape and Reel) (SOIC, MSOP)
MCP6293: Single Op Amp with Chip Select
MCP6293T: Single Op Amp with Chip Select
(Ta pe and Reel )
(SOIC, MSOP, SOT-23-6)
MCP6294: Quad Op Amp
MCP6294T: Quad Op Amp
(Tape and Reel) (SOIC, TSSOP)
MCP6295: Dual Op Amp with Chip Select
MCP6295T: Dual Op Amp with Chip Select
(Tape and Reel) (SOIC, MSOP)
Temperature Range: E = -40°C to +125°C
Package: OT = Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6291, MCP6291R)
CH = Plastic Small Outline Transistor (SOT-23), 6-lead
(MCP6293)
MS = Plastic MSOP, 8-lead
P = Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC, (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
ST = Plastic TSSOP (4.4 mm Body), 14-lead
PART NO. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP6291-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6291-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6291-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6291T -E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
a) MCP6292-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6292-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6292-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6292T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
a) MCP6293-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6293-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6293-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6293T-E/CH: Tape and Reel,
Extended Temperature,
6LD SOT-23 package.
a) MCP6294-E/P: Extended Temperature,
14LD PDIP package.
b) MCP6294T -E/SL: Tape and Reel,
Extended Temperature,
14LD SOIC package.
c) MCP6294-E/SL: Extended Temperature,
14LD SOIC package.
d) MCP6294-E/ST: Extended Temperature,
14LD TSSOP package.
a) MCP6295-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6295-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6295-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6295T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
–
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Worldwide Site (www. microchip.c om)
Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com ) to receive the most current information on our products.
MCP6291/2/3/4/5
DS21812D-page 30 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. DS21812D-page 31
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIN D WHETHER EXPRESS OR IMPLIED ,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. U se of Microc hip’s products as critical com ponents in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Prog ra mming , ICSP, ICEP I C , MPASM, MPLI B, M PL I N K,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its f amily of products is one of the most secure families of its kind on the market today, when used in t he
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microchip are committed to continuously improving t he c ode protect ion f eatures of our
products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, micro peripherals, nonvolat ile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21812D-page 32 2004 Microchip Technology Inc.
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10/20/04