HV5222PJ-G - Supertex, Inc. - Datasheet.Directory

Supertex inc.

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

HV5222

Features

►Processed with HVCMOS® technology

►Output voltages to 225V using a ramped

supply voltage

►SINK current minimum 100mA

►Shift register speed 8.0MHz

►Strobe and enable inputs

►CMOS compatible inputs

►Forward and reverse shifting options

►Hi-Rel processing available

General Description

The HV5222 is a low voltage serial to high voltage parallel converter

with open drain outputs. This device has been designed for use as a

driver for AC electroluminescent displays.They can also be used in

any application requiring multiple output high voltage current sinking

capabilities such as driving inkjet and electrostatic print heads,

plasma panels, vacuum uorescent, or large matrix LCD displays.

This device consists of a 32-bit shift register and control logic to

perform the Output Enable and all-on functions. Data is shifted

through the shift register on the high to low transition of the clock.

The HV5222 shifts in the clockwise direction when viewed from the

top of the package. A data output buffer is provided for cascading

devices. This output reects the current status of the last bit of the

shift register. Operation of the shift register is not affected by the

OE(Output Enable) or the STR (Strobe) inputs.

The HV5222 has been designed to be used in systems which either

switch off the high voltage supply before changing the state of the

high voltage outputs or which limit the current through each output.

Functional Block Diagram

32-Channel Serial to Parallel Converter

With Open Drain Outputs

OUT

•

28 Additional

Outputs

•

OUT

DATA

INPUT

CLK

Data Out

STR HV

OUT

32 bit

Static Shift

HV5222

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

Ordering Information

Device

Package Options

44-Lead Quad

Cerpac Chip Carrier

.650x.650in body

.190in height (max)

.050in pitch

44-Lead Quad

Plastic Gullwing

10.00x10.00mm body

2.35mm height (max)

0.80mm pitch

44-Lead Quad

Plastic Chip Carrier

.653x.653in body

.180in height (max)

.050in pitch

HV5222 HV5222DJ* HV5222PG-G HV5222PJ-G

-G indicates package is RoHS compliant (‘Green’)

* Hi-Rel processing available

Absolute Maximum Ratings

Supply voltage, VDD -0.5V to +15V

Supply voltage, VPP -0.5V to +250V

Logic input levels -0.5V to VDD +0.5V

Ground current11.5A

Continuous total power dissipation2

Plastic

Ceramic

1200W

1500W

Operating temperature range

Plastic

Ceramic

-40OC to +85OC

-55OC to +125OC

Storage temperature range -65OC to +150OC

Parameter Value

Pin Conguration

Notes:

1. Duty cycle is limited by the total power dissipated in the package.

2. For operation above 25°C ambient derate linearly to maximum

operating temperature at 20mW/°C for plastic and at 15mW/°C for

ceramic.

1 44

6 40

Product Marking

Absolute Maximum Ratings are those values beyond which damage to the

device may occur. Functional operation under these conditions is not implied.

Continuous operation of the device at the absolute rating level may affect

device reliability. All voltages are referenced to device ground.

YY = Year Sealed

WW = Week Sealed

L = Lot Number

C = Country of Origin*

A = Assembler ID*

= “Green” Packaging

*May be part of top marking

Top Marking

Bottom Marking

YYWW

HV5222PG

LLLLLLLLL

CCCCCCCC

AAA

YY = Year Sealed

WW = Week Sealed

L = Lot Number

A = Assembler ID

C = Country of Origin*

= “Green” Packaging

*May be part of top marking

Top Marking

Bottom Marking

YYWW AAA

HV5222PJ

LLLLLLLLLL

CCCCCCCCCCC

44-Lead Quad Plastic Gullwing (PG)

44-Lead Quad Plastic Chip Carrier (PJ)

44-Lead Quad Plastic Gullwing

(PG)

44-Lead Quad Plastic Chip Carrier

(PJ)

1 44

6 40

44-Lead Quad Cerpac Chip Carrier (DJ)

YY = Year Sealed

WW = Week Sealed

L = Lot Number

C = Country of Origin*

A = Assembler ID*

*May be part of top marking

Top Marking

Bottom Marking

YYWW

HV5222DJ

LLLLLLLLLL

CCCCCCCCCCC

AAA

44-Lead Quad Plastic Chip Carrier

(DJ)

Packages may or may not include the following marks: Si or

HV5222

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

Sym Parameter Min Max Units Conditions

Electrical Characteristics (Over recommended operating conditions unless otherwise specied)

DC Characteristics

AC Characteristics (VDD = 12V, TA = 25°C)

Sym Parameter Min Max Units Conditions

fCLK Clock frequency - 8.0 MHz ---

tWClock width, high or low 62 - ns ---

tSU Data setup time before CLK falls 25 - ns ---

tHData hold time after CLK falls 10 - ns ---

tON Turn-on time, HVOUT from strobe - 500 ns RL = 2.0KΩ to 200V

tDHL Data output delay after H to L CLK - 100 ns CL = 15pF

tDLH Data output delay after L to H CLK - 100 ns CL = 15pF

IDD VDD supply current - 15 mA fCLK = 8.0MHz, FDATA = 4.0MHz

IDDQ Quiescent VDD supply current - 100 µA All VIN = 0V

IO(OFF) Off-state output current - 10 µA All outputs high, all SWS parallel

IIH High level logic input current - 1.0 µA VIH = 12V

IIL Low level logic input current - -1.0 µA VIL = 0

VOH High level output data out VDD -1.0V - V IDOUT = -100µA

VOL Low level output voltage HVOUT - 15 VIHVOUT = +100mA

Data out - 1.0 IDOUT = +100µA

VOC HVOUT clamp voltage - -1.5 V IOL = -100mA

Power-Up Sequence

Power-up sequence should be the following:

1. Connect ground

2. Apply VDD

3. Set all inputs to a known state

Power-down sequence should be the reverse of the above.

Sym Parameter Min Typ Max Units

Recommended Operating Conditions

VDD Logic voltage supply 10.8 12 13.2 V

HVOUT High voltage output -0.3 - 225 V

VIH High-level input voltage VDD -2.0 - VDD V

VIL Low-level input voltage 0 - 2.0 V

fCLK Clock frequency - - 8.0 MHz

TAOperating free-air temperature Plastic -40 - +85 OC

Ceramic -55 - +125

HV5222

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

Switching Waveforms

DATA

IN Data Valid 1

CLK

DATA

OUT

DATA

OUT

STR

DLH

DHL

OUT

50% 50% 50%

50%

15V

12V

Input and Output Equivalent Circuits

VDD

INPUT

GND

OUT

Logic Inputs

GND

DATA

OUT

Logic Data Output High Voltage Outputs

VDD

GND

Function Table

Function

Inputs Outputs

Data

In CLK OE Strobe

Shift Reg HV Outputs Data

Out

1 2...32 1 2...32

All on X X X L● ●...● ON ON...ON ●

All off X X LH● ●...● OFF OFF...OFF ●

Load S/R H OR L ↓ L HH or L ●...● OFF OFF...OFF -

Output Enable X H OR L H H H or L ●...● ON or OFF ●...● ●

Notes:

H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition

● = dependent on previous stage’s state before the last CLK: High-to-low transition

HV5222

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

HV5222PG

Pin Function Description

1 HVOUT22

High voltage outputs.

2 HVOUT21

3 HVOUT20

4 HVOUT19

5 HVOUT18

6 HVOUT17

7 HVOUT16

8 HVOUT15

9 HVOUT14

10 HVOUT13

11 HVOUT12

12 HVOUT11

13 HVOUT10

14 HVOUT9

15 HVOUT8

16 HVOUT7

17 HVOUT6

18 HVOUT5

19 HVOUT4

20 HVOUT3

21 HVOUT2

22 HVOUT1

23 DATA OUT

Serial data output

Data output for cascading to the data input of the next device.

N/C No connect.

28 OE

Output enable input.

When OE is LOW, all HV outputs are forced into a LOW state, regardless of data in

each channel. When OE is HIGH, all HV outputs reect data latched.

29 CLK Data shift register clock.

Input are shifted into the shift register on the positive edge of the clock.

30 GND Logic and high voltage ground.

31 VDD Low voltage logic power rail.

32 STR Strobe.

33 DATA IN

Serial data input

Data needs to be present before each rising edge of the clock.

44-Lead PQFP Pin Assignment (PG)

HV5222

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

HV5222PG

Pin Function Description

34 N/C No connect

35 HVOUT32

High voltage outputs.

36 HVOUT31

37 HVOUT30

38 HVOUT29

39 HVOUT28

40 HVOUT27

41 HVOUT26

42 HVOUT25

43 HVOUT24

44 HVOUT23

44-Lead PQFP Pin Assignment (PG) (cont.)

HV5222PJ

Pin Function Description

1 HVOUT17

High voltage outputs.

2 HVOUT16

3 HVOUT15

4 HVOUT14

5 HVOUT13

6 HVOUT12

7 HVOUT11

8 HVOUT10

9 HVOUT9

10 HVOUT8

11 HVOUT7

12 HVOUT6

13 HVOUT5

14 HVOUT4

15 HVOUT3

16 HVOUT2

17 HVOUT1

18 DATA OUT Serial data output

Data output for cascading to the data input of the next device.

44-Lead PLCC Pin Assignment (DJ/PJ)

HV5222

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

HV5222PJ

Pin Function Description

N/C No connect.

23 OE

Output enable input.

When OE is LOW, all HV outputs are forced into a LOW state, regardless of data in

each channel. When OE is HIGH, all HV outputs reect data latched.

24 CLK

Data shift register clock.

Input are shifted into the shift register on the positive edge of the clock.

25 GND Logic and high voltage ground.

26 VDD Low voltage logic power rail.

27 STR Strobe.

28 DATA IN

Serial data input

Data needs to be present before each rising edge of the clock.

29 N/C No connect

30 HVOUT32

High voltage outputs.

31 HVOUT31

32 HVOUT30

33 HVOUT29

34 HVOUT28

35 HVOUT27

36 HVOUT26

37 HVOUT25

38 HVOUT24

39 HVOUT23

40 HVOUT22

41 HVOUT21

42 HVOUT20

43 HVOUT19

44 HVOUT18

44-Lead PLCC Pin Assignment (PJ) (cont.)

HV5222

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

44-Lead Quad Cerpac Package Outline (DJ)

.650x.650in body, .190in height (max), .050in pitch

.150 MAX

.040 x 45O

.075 MAX

640

E1 E

Top View

View B

AA2

Seating

Plane

Note 1

(Index Area)

.035 x 45O

0.25 max

3 Places

.025 MIN

View B

Horizontal Side View

Vertical Side View

Symbol A A1 A2 b b1 D D1 E E1 e

Dimension

(inches)

MIN .155 .090 .060

REF

.017 .026 .685 .630 .685 .630 .050

BSC

NOM .172 .100 .019 .029 .690 .650 .690 .650

MAX .190 .120 .021 .032 .695 .665 .695 .665

JEDEC Registration MO-087, Variation AB, Issue B, August, 1991.

Drawings not to scale.

Supertex Doc. #: DSPD-44CERPACDJ, Version D090808.

Note:

1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or

a printed indicator.

HV5222

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

44-Lead PQFP Package Outline (PG)

10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch

Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ

Dimension

(mm)

MIN 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80*

0.80

BSC

0.73

1.95

REF

0.25

BSC

NOM - - 2.00 - 13.90 10.00 13.90 10.00 0.88 3.5O

MAX 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20* 1.03 7O

JEDEC Registration MO-112, Variation AA-2, Issue B, Sep.1995.

* This dimension is not specied in the JEDEC drawing.

Drawings not to scale.

Supertex Doc. #: DSPD-44PQFPPG, Version C041309.

Seating

Plane

Gauge

Plane

View B

Seating

Plane

Top View

Side View

Note 1

(Index Area

D1/4 x E1/4)

Note:

1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or

a printed indicator.

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives

an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability

to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and

specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)

Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888

www.supertex.com

HV5222

(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline information go to http://www.

supertex.com/packaging.html.)

Doc.# DSFP-HV5222

A060811

44-Lead PLCC Package Outline (PJ)

.653x.653in body, .180in height (max), .050in pitch

Symbol A A1 A2 b b1 D D1 E E1 e R

Dimension

(inches)

MIN .165 .090 .062 .013 .026 .685 .650 .685 .650

.050

BSC

.025

NOM .172 .105 - - - .690 .653 .690 .653 .035

MAX .180 .120 .083 .021 .036†.695 .656 .695 .656 .045

JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.

† This dimension differs from the JEDEC drawing.

Drawings not to scale.

Supertex Doc. #: DSPD-44PLCCPJ, Version F031111.

.150 MAX

.048/.042 x 45O

.075 MAX

6 40

E1 E

Top View

Horizontal Side View

View B

A A2

Seating

Plane

Note 1

(Index Area)

.056/.042 x 45O

.020max

(3 Places)

.020 MIN

Vertical Side View

View B

Note 2

Base

Plane

Notes:

1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or

a printed indicator.

2. Actual shape of this feature may vary.