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FEATURES
DESCRIPTION/ORDERING INFORMATION
DB, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
(5 V) VCCA
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND
VCCB (3.3 V)
VCCB (3.3 V)
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
SN74LVC4245AOCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTERWITH 3-STATE OUTPUTS
SCAS375H MARCH 1994 REVISED MARCH 2005
Bidirectional Voltage Translator5.5 V on A Port and 2.7 V to 3.6 V on B PortControl Inputs V
IH
/V
IL
Levels Are Referencedto V
CCA
VoltageLatch-Up Performance Exceeds 250 mA PerJESD 17ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
This 8-bit (octal) noninverting bus transceivercontains two separate supply rails; B port has V
CCB
,which is set at 3.3 V, and A port has V
CCA
, which isset at 5 V. This allows for translation from a 3.3-V toa 5-V environment, and vice versa.<br/>
The SN74LVC4245A is designed for asynchronous communication between data buses. The device transmitsdata from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at thedirection-control (DIR) input. The output-enable ( OE) input can be used to disable the device so the buses areeffectively isolated. The control circuitry (DIR, OE) is powered by V
CCA
.
The SN74LVC4245A pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin '245 devicewithout board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the SN74LVC4245A toalign with the conventional '245 pinout.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube of 25 SN74LVC4245ADWSOIC DW LVC4245AReel of 2000 SN74LVC4245ADWRSSOP DB Reel of 2000 SN74LVC4245ADBR LJ245A–40 °C to 85 °C
Tube of 60 SN74LVC4245APWTSSOP PW Reel of 2000 SN74LVC4245APWR LJ245AReel of 250 SN74LVC4245APWT
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OPERATIONOE DIR
L L B data to A busL H A data to B busH X Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1994–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DIR
OE
A1
B1
To Seven Other Channels
2
3
22
21
Absolute Maximum Ratings
(1)
SN74LVC4245A
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTERWITH 3-STATE OUTPUTS
SCAS375H MARCH 1994 REVISED MARCH 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range for V
CCA
= 4.5 V to 5.5 V (unless otherwise noted)
MIN MAX UNIT
V
CCA
Supply voltage range –0.5 6.5 VA port
(2)
–0.5 V
CCA
+ 0.5V
I
Input voltage range VControl inputs –0.5 6V
O
Output voltage range A port
(2)
–0.5 V
CCA
+ 0.5 VI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output current ±50 mAContinuous current through each V
CCA
or GND ±100 mADB package 63θ
JA
Package thermal impedance
(3)
DW package 46 °C/WPW package 88T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) This value is limited to 6 V maximum.(3) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
Recommended Operating Conditions
(1)
SN74LVC4245AOCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTERWITH 3-STATE OUTPUTS
SCAS375H MARCH 1994 REVISED MARCH 2005
over operating free-air temperature range for V
CCB
= 2.7 V to 3.6 V (unless otherwise noted)
MIN MAX UNIT
V
CCB
Supply voltage range –0.5 4.6 VV
I
Input voltage range B port
(2)
–0.5 V
CCB
+ 0.5 VV
O
Output voltage range B port
(2)
–0.5 V
CCB
+ 0.5 VI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output current ±50 mAContinuous current through V
CCB
or GND ±100 mADB package 63θ
JA
Package thermal impedance
(3)
DW package 46 °C/WPW package 88T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) This value is limited to 4.6 V maximum.(3) The package thermal impedance is calculated in accordance with JESD 51-7.
for V
CCA
= 4.5 V to 5.5 V
MIN MAX UNIT
V
CCA
Supply voltage 4.5 5.5 VV
IH
High-level input voltage 2 VV
IL
Low-level input voltage 0.8 VV
IA
Input voltage 0 V
CCA
VV
OA
Output voltage 0 V
CCA
VI
OH
High-level output current –24 mAI
OL
Low-level output current 24 mAT
A
Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at the associated V
CC
or GND to ensure proper device operation. Refer to the TIapplication report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
for V
CCB
= 2.7 V to 3.6 V
MIN MAX UNIT
V
CCB
Supply voltage 2.7 3.6 VV
IH
High-level input voltage V
CCB
= 2.7 V to 3.6 V 2 VV
IL
Low-level input voltage V
CCB
= 2.7 V to 3.6 V 0.8 VV
IB
Input voltage 0 V
CCB
VV
OB
Output voltage 0 V
CCB
VV
CCB
= 2.7 V –12I
OH
High-level output current mAV
CCB
= 3 V –24V
CCB
= 2.7 V 12I
OL
Low-level output current mAV
CCB
= 3 V 24T
A
Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at the associated V
CC
or GND to ensure proper device operation. Refer to the TIapplication report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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Electrical Characteristics
(1)
Electrical Characteristics
(1)
SN74LVC4245A
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTERWITH 3-STATE OUTPUTS
SCAS375H MARCH 1994 REVISED MARCH 2005
over recommended operating free-air temperature range for V
CCA
= 4.5 V to 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CCA
MIN TYP
(2)
MAX UNIT
4.5 V 4.3I
OH
= –100 µA
5.5 V 5.3V
OH
V4.5 V 3.7I
OH
= –24 mA
5.5 V 4.74.5 V 0.2I
OL
= 100 µA
5.5 V 0.2V
OL
V4.5 V 0.55I
OL
= 24 mA
5.5 V 0.55I
I
Control inputs V
I
= V
CCA
or GND 5.5 V ±1µAI
OZ
(3)
A port V
O
= V
CCA
or GND 5.5 V ±5µAI
CCA
V
I
= V
CCA
or GND, I
O
= 0 5.5 V 80 µAI
CCA
(4)
One input at 3.4 V, Other inputs at V
CCA
or GND 5.5 V 1.5 mAC
i
Control inputs V
I
= V
CCA
or GND Open 5 pFC
io
A port V
O
= V
CCA
or GND 5 V 11 pF
(1) V
CCB
= 2.7 V to 3.6 V(2) All typical values are measured at V
CC
= 5 V, T
A
= 25 °C.(3) For I/O ports, the parameter I
OZ
includes the input leakage current.(4) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associatedV
CC
.
over recommended operating free-air temperature range for V
CCB
= 2.7 V to 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CCB
MIN TYP
(2)
MAX UNIT
I
OH
= –100 µA 2.7 V to 3.6 V V
CC
0.22.7 V 2.2V
OH
I
OH
= –12 mA V3 V 2.4I
OH
= –24 mA 3 V 2I
OL
= 100 µA 2.7 V to 3.6 V 0.2V
OL
I
OL
= 12 mA 2.7 V 0.4 VI
OL
= 24 mA 3 V 0.55I
OZ
(3)
B port V
O
= V
CCB
or GND 3.6 V ±5µAI
CCB
V
I
= V
CCB
or GND, I
O
= 0 3.6 V 50 µAI
CCB
(4)
One input at V
CCB
0.6 V, Other inputs at V
CCB
or GND 2.7 V to 3.6 V 0.5 mAC
io
B port V
O
= V
CCB
or GND 3.3 V 11 pF
(1) V
CCA
= 5 V ±0.5 V(2) All typical values are measured at V
CC
= 3.3 V, T
A
= 25 °C.(3) For I/O ports, the parameter I
OZ
includes the input leakage current.(4) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associatedV
CC
.
4
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Switching Characteristics
Operating Characteristics
Power-Up Considerations
(1)
SN74LVC4245AOCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTERWITH 3-STATE OUTPUTS
SCAS375H MARCH 1994 REVISED MARCH 2005
over recommended operating free-air temperature range, C
L
= 50 pF (unless otherwise noted) (see Figure 1 and Figure 2 )
V
CCA
= 5 V ±0.5 V,FROM TO
V
CCB
= 2.7 V to 3.6 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX
t
PHL
1 6.3A B nst
PLH
1 6.7t
PHL
1 6.1B A nst
PLH
1 5t
PZL
1 9OE A nst
PZH
1 8.1t
PZL
1 8.8OE B nst
PZH
1 9.8t
PLZ
1 7OE A nst
PHZ
1 5.8t
PLZ
1 7.7OE B nst
PHZ
1 7.8
V
CCA
= 4.5 V to 5.5 V, V
CCB
= 2.7 V to 3.6 V, T
A
= 25 °C
PARAMETER TEST CONDITIONS TYP UNIT
Outputs enabled 39.5C
pd
Power dissipation capacitance per transceiver C
L
= 0, f = 10 MHz pFOutputs disabled 5
TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-upsequence always should be followed to avoid excessive supply current, bus contention, oscillations, or otheranomalies caused by improperly biased device pins. Take these precautions to guard against such power-upproblems:
1. Connect ground before any supply voltage is applied.2. Power up the control side of the device (V
CCA
for all four of these devices).3. Tie OE to V
CCA
with a pullup resistor so that it ramps with V
CCA
.4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),ramp it with V
CCA
. Otherwise, keep DIR low.
(1) Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021.
5
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PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 2 × VCC
Open
GND
500
500
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
tPLH tPHL VOH
VOL
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
VCC
0 V
VOL + 0.3 V
VOH - 0.3 V
0 V
3 V
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
VCC
0 V
1.5 V
Input
50% VCC
50% VCC
50% VCC
1.5 V
50% VCC
VCC
0 V
1.5 V 1.5 V
tw
Input
VOLTAGE WA VEFORMS
PULSE DURATION
SN74LVC4245A
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTERWITH 3-STATE OUTPUTS
SCAS375H MARCH 1994 REVISED MARCH 2005
A PORT
Figure 1. Load Circuit and Voltage Waveforms
6
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PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 7 V
Open
GND
500
500
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
tPLH tPHL VOH
VOL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3.5 V
0 V
VOL + 0.3 V
VOH - 0.3 V
0 V
3 V
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
3 V
0 V
1.5 V
Input 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
3 V
0 V
1.5 V 1.5 V
tw
Input
VOLTAGE WA VEFORMS
PULSE DURATION
SN74LVC4245AOCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTERWITH 3-STATE OUTPUTS
SCAS375H MARCH 1994 REVISED MARCH 2005
B PORT
Figure 2. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com 14-Feb-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LVC4245ADBR ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245ADBRE4 ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245ADW ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245ADWE4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245ADWG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245ADWR ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245ADWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245ADWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245APW ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245APWE4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245APWG4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245APWR ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245APWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245APWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245APWT ACTIVE TSSOP PW 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC4245APWTE4 ACTIVE TSSOP PW 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 14-Feb-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LVC4245APWTG4 ACTIVE TSSOP PW 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC4245A :
Enhanced Product: SN74LVC4245A-EP
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC4245ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
SN74LVC4245ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
SN74LVC4245APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
SN74LVC4245APWT TSSOP PW 24 250 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC4245ADBR SSOP DB 24 2000 367.0 367.0 38.0
SN74LVC4245ADWR SOIC DW 24 2000 367.0 367.0 45.0
SN74LVC4245APWR TSSOP PW 24 2000 367.0 367.0 38.0
SN74LVC4245APWT TSSOP PW 24 250 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
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