Industrial Current Out Driver, Single-Supply,
55 V Maximum Supply, Programmable Ranges
Data Sheet
AD5749
Rev. D
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FEATURES
Current output ranges: 0 mA to 24 mA or 4 mA to 20 mA
±0.03% FSR typical total unadjusted error (TUE)
±5 ppm/°C typical output drift
2% overrange
Flexible serial digital interface
On-chip output fault detection
PEC error checking
Asynchronous CLEAR function
Power supply range
AVDD: 12 V (± 10%) to 55 V (maximum)
Output loop compliance to AVDD − 2.75 V
Temperature range: −40°C to +105°C
32-lead, 5 mm × 5 mm LFCSP package
APPLICATIONS
Process control
Actuator control
PLCs
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD5749 is a single channel, low cost, precision, current output
driver with hardware or software programmable output ranges.
The software ranges are configured via an SPI-/MICROWIRE™-
compatible serial interface. The AD5749 targets applications in
PLC and industrial process control. The analog input to the
AD5749 is provided from a low voltage, single-supply digital-to-
analog converter (DAC) and is internally conditioned to provide
the desired output current/voltage range.
The output current range is programmable across two current
ranges: 0 mA to 24 mA, or 4 mA to 20 mA. Current output is
open-circuit protected and can drive inductive loads of 0.1 H.
The device is specified to operate with a power supply range
from 10.8 V to 55 V. Output loop compliance is 0 V to AVDD −
2.75 V.
The flexible serial interface is SPI and MICROWIRE compatible
and can be operated in 3-wire mode to minimize the digital
isolation required in isolated applications. The interface also
features an optional PEC error checking feature using CRC-8
error checking, useful in industrial environments where data
communication corruption can occur.
The device also includes a power-on reset function ensuring
that the device powers up in a known state and an asynchron-
ous CLEAR pin that sets the outputs to the low end of the
selected current range.
An HW SELECT pin is used to configure the part for hardware
or software mode on power-up.
Table 1. Related Devices
Part No. Description
AD5750 Industrial current/voltage output (I/V) driver with
programmable ranges
AD5751 Industrial I/V output driver, single-supply, 55 V maximum
supply, programmable ranges
AD5748 Industrial I/V output driver with programmable ranges
AD5410/
AD5420
Single-channel, 12-/16-bit, serial input, current source
output DAC
AD5412/
AD5422
Single-channel, 12-/16-bit, serial input, I/V output DAC
08923-001
*DENOTES SHARED PIN. SOFTWARE MODE DENOTED BY REGULAR TEXT,
HARDWARE MODE DENOTED BY ITALIC TEXT. FOR EXAMPLE, FOR
FAULT/TEMP PIN, IN SOFTWARE MODE, THIS PIN TAKES ON FAULT
FUNCTION. IN HARDWARE MODE, THIS PIN TAKES ONTEMP FUNCTION.
CLEAR
DVCC GND AVDD GND
CLRSEL
HW SELECT
VIN
VREF
OVERTEMP
IOUT OPEN FAULT
IOUT OPEN FAULT
RESET
R2
R
SET
AVDD
R3
AD5749
IOUT
POWER-
ON RESET IOUT
OPEN FAULT
IOUT RANGE
SCALING
STATUS
REGISTER
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
SCLK/OUTEN*
SDIN/R0*
SYNC/RSET*
SDO
FAULT/TEMP*
NC/IFAULT*
AD2/R1*AD1/R2*AD0/R3*
REXT1
REXT2
AD5749 Data Sheet
Rev. D | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 16
Software Mode ............................................................................ 16
Current Output Architecture .................................................... 18
Driving Inductive Loads ............................................................ 18
Power-On State of the AD5749 ................................................ 18
Default Registers at Power-On ................................................. 18
Reset Function ............................................................................ 18
OUTEN ........................................................................................ 18
Software Control ........................................................................ 18
Hardware Control ...................................................................... 21
Transfer Function ....................................................................... 21
Detailed Description of Features .................................................. 22
Output Fault Alert—Software Mode ....................................... 22
Output Fault Alert—Hardware Mode ..................................... 22
Asynchronous Clear (CLEAR) ................................................. 22
External Current Setting Resistor ............................................ 22
Programmable Overrange Modes ............................................ 22
Packet Error Checking ............................................................... 23
Applications Information .............................................................. 24
Transient Voltage Protection .................................................... 24
Thermal Considerations ............................................................ 24
Layout Guidelines....................................................................... 25
Galvanically Isolated Interface ................................................. 25
Microprocessor Interfacing ....................................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
1/2018—Rev. C to Rev. D
Changed CP-32-7 to CP-32-2 ...................................... Throughout
Changes to Figure 1 .......................................................................... 1
Changed FAULT, IFAULT, TEMP, VFAULT Parameter to
FAULT, IFAULT, TEMP Parameter; Table 2 ................................. 4
Changes to Figure 4 and Table 5 ..................................................... 8
Updates Outline Dimensions ........................................................ 26
Changes to Ordering Guide .......................................................... 26
3/2017—Rev. B to Rev. C
Changed CP-32-2 to CP-32-7 ...................................... Throughout
Changes to Figure 4 .......................................................................... 8
Changes to Theory of Operation Section .................................... 16
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
10/2013—Rev. A to Rev. B
Changes to Table 4 ............................................................................. 7
Changes to Thermal Considerations Section and Table 12 ...... 24
Updated Outline Dimensions ....................................................... 26
7/2012—Rev. 0 to Rev. A
Changes to Figure 3 ........................................................................... 6
Changes to Status Bit Read Operation Section........................... 21
Updated Outline Dimensions ....................................................... 26
7/2010—Revision 0: Initial Version
Data Sheet AD5749
Rev. D | Page 3 of 28
SPECIFICATIONS
AVDD = 12 V (± 10%) to 55 V (maximum), DVCC = 2.7 V to 5.5 V, GND = 0 V. RLOAD = 300 Ω. All specifications TMIN to TMAX,
unless otherwise noted.
Table 2.
Parameter1 Min Typ Max Unit Test Conditions/Comments
INPUT VOLTAGE RANGE 0 to 4.096 V Output unloaded
Input Leakage Current
−1
µA
REFERENCE INPUT
Reference Input Voltage 4.096 V External reference must be exactly as stated;
otherwise, accuracy errors show up as error in output
Input Leakage Current
−1
µA
CURRENT OUTPUT
Output Current Ranges 0 24 mA
4 20 mA
Output Current Overranges2 0 24.5 mA See Detailed Description of Features section
3.92 20.4 mA See Detailed Description of Features section
ACCURACY (INTERNAL RSET)
Total Unadjusted Error (TUE)
A Version2 −0.5 +0.5 % FSR
−0.3 ±0.15 +0.3 % FSR TA = 25°C
Relative Accuracy (INL) −0.02 ±0.01 +0.02 % FSR
Offset Error −16 +16 µA
−10 +5 +10 µA TA = 25°C
Offset Error TC2 ±3 ppm FSR/°C
Dead Band on Output, RTI 8 14 mV Referred to 4.096 V input range
Gain Error −0.2 +0.2 % FSR
−0.125
±0.02
% FSR
T
A
= 25°C
Gain TC2 ±10 ppm FSR/°C
Full-Scale Error −0.2 +0.2 % FSR
−0.125 ±0.02 +0.125 % FSR TA = 25°C
Full-Scale TC2 ±4 ppm FSR/°C
ACCURACY (EXTERNAL RSET)
Total Unadjusted Error (TUE)
A Version2 −0.3 +0.3 % FSR
−0.1 ±0.02 +0.1 % FSR TA = 25°C
Relative Accuracy (INL) −0.02 ±0.01 +0.02 % FSR
Offset Error −14 +14 µA
−11
+5
T
A
= 25°C
Offset Error TC2 ±2 ppm FSR/°C
Dead Band on Output, RTI 8 +14 mV Referred to 4.096 V input range
Gain Error −0.08 +0.08 % FSR
−0.07
±0.02
% FSR
T
A
= 25°C
Gain TC2 ±1 ppm FSR/°C
Full-Scale Error −0.1 +0.1 % FSR
−0.07 ±0.02 +0.07 % FSR TA = 25°C
Full-Scale TC2 ±2 ppm FSR/°C
AD5749 Data Sheet
Rev. D | Page 4 of 28
Parameter1 Min Typ Max Unit Test Conditions/Comments
OUTPUT CHARACTERISTICS2
Current Loop Compliance
Voltage
0 AVDD − 2.75 V
Resistive Load Chosen such that compliance is not exceeded
Inductive Load See the Test Conditions/
Comments column
H Needs appropriate capacitor at higher inductance
values; see the Driving Inductive Loads section
Settling Time
4 mA to 20 mA, Full-Scale
Step
8.5 µs 250 Ω load
120 µA Step, 4 mA to
20 mA Range
1.2 µs 250 Ω load
DC PSRR 1 µA/V
Output Impedance 130 MΩ
DIGITAL INPUTS2 JEDEC compliant
Input High Voltage, VIH 2 V
Input Low Voltage, V
IL
V
Input Current −1 +1 µA Per pin
Pin Capacitance 5 pF Per pin
DIGITAL OUTPUTS2
FAULT, IFAULT, TEMP
VOL, Output Low Voltage 0.4 V 10 kΩ pull-up resistor to DVCC
0.6 V At 2.5 mA
VOH, Output High Voltage 3.6 V 10 kΩ pull-up resistor to DVCC
SDO
VOL, Output Low Voltage 0.5 0.5 V Sinking 200 µA
VOH, Output High Voltage DVCC − 0.5 DVCC − 0.5 V Sourcing 200 µA
High Impedance Output
Capacitance
3 pF
High Impedance Leakage
Current
−1 +1 µA
POWER REQUIREMENTS
AVDD 10.8 55 V
DV
CC
Input Voltage 2.7 5.5 V
AIDD 4.4 5.6 mA Output unloaded, output disabled;
R3, R2, R1, R0 = 0000, RSET = 0
5.2 6.2 mA Output enabled
DICC 0.3 1 mA VIH = DVCC, VIL = GND
Power Dissipation 108 mW AVDD = 24 V, output unloaded
1 Temperature range: −40°C to +105°C; typical at +25°C.
2 Guaranteed by design and characterization, not production tested.
Data Sheet AD5749
Rev. D | Page 5 of 28
TIMING CHARACTERISTICS
AVDD = 12 V (± 10%) to 55 V (maximum), DVCC = 2.7 V to 5.5 V, GND = 0 V. RLOAD = 300 Ω. All specifications TMIN to TMAX, unless
otherwise noted.
Table 3.
Parameter1, 2 Limit at TMIN, TMAX Unit Description
t1 20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 5 ns min SYNC falling edge to SCLK falling edge setup time
t
5
10
ns min
16
th
SCLK falling edge to
SYNC
rising edge (on 24
th
SCLK falling edge if using PEC)
t6 5 ns min Minimum SYNC high time (write mode)
t7 5 ns min Data setup time
t8 5 ns min Data hold time
t9, t10 1.5 µs max CLEAR pulse low/high activation time
t11 5 ns min Minimum SYNC high time (read mode)
t12 40 ns max SCLK rising edge to SDO valid (SDO CL = 15 pF)
t13 10 ns min RESET pulse low time
1 Guaranteed by characterization, but not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
AD5749 Data Sheet
Rev. D | Page 6 of 28
Timing Diagrams
Figure 2. Write Mode Timing Diagram
Figure 3. Readback Mode Timing Diagram
D15
1 2 16
D0
t
1
t
2
t
5
t
8
t
7
t
3
SCLK
SYNC
SDIN
CLEAR
IOUT
t
10
t
9
t
13
RESET
t
4
t
6
08923-002
t11
t
12
A2
SDIN
SYNC
SCLK
A0 R = 1 0 R3 R2 R1 R0
CLRSELOUTEN CLEAR RSET RESET
0 0A1
XSDO X XX X R3 R2 R1 R0
CLRSEL OUTEN RSET PEC
ERROR
OVER
TEMP
IOUT
FAULT
X
08923-003
Data Sheet AD5749
Rev. D | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 4.
Parameter Rating
AVDD to GND −0.3 V to +58 V
DVCC to GND −0.3 V to +7 V
Digital Inputs to GND −0.3 V to DVCC + 0.3 V, or 7 V
(whichever is less)
Digital Outputs to GND −0.3 V to DVCC + 0.3 V, or 7 V
(whichever is less)
VREF to GND −0.3 V to +7 V
VIN to GND −0.3 V to +7 V
IOUT to GND −0.3 V to AVDD
Operating Temperature Range
Industrial −40°C to +105°C
Storage Temperature Range
−65°C to +150°C
Junction Temperature (TJ max) 125°C
32-Lead LFCSP Package
θJA Thermal Impedance1 42°C/W
Lead Temperature JEDEC industry standard
Soldering J-STD-020
1 Simulated data based on a JEDEC 2S2P test board with thermal vias.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD5749 Data Sheet
Rev. D | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 SDO Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in
readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
This pin is a CMOS output.
2 CLRSEL
In hardware or software mode, this pin selects the clear value, either zero scale or midscale. In software
mode, this pin is implemented as a logic OR with the internal CLRSEL bit.
3 CLEAR
Active High Input. Asserting this pin sets the output current to zero-scale code or midscale of range
selected (user selectable). CLEAR is a logic OR with the internal CLEAR bit. See the Asynchronous Clear
(CLEAR) section for more details.
4 DVCC Digital Power Supply.
5 GND Ground Connection.
6 SYNC/RSET Positive Edge-Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift
register data into the AD5749 and also updates the output.
Resistor Select (RSET). In hardware mode, this pin selects whether the internal or the external current
sense resistor is used.
If RSET = 0, the external sense resistor is chosen.
If RSET = 1, the internal sense resistor is chosen.
7 SCLK/OUTEN
Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling
edge of SCLK. This pin operates at clock speeds up to 50 MHz.
Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin.
8 SDIN/R0 Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK.
Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output
current range setting on the part.
9 AD2/R1
Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD0 and AD1, allows up to
eight devices to be addressed on one bus.
Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output
current range setting on the part.
08923-004
NOTES
1. N C = NO CONNECT. CA N BE TI E D TO GND.
2. D NC = DO NOT CONNECT.
3. THE EXPOSED PADDLE IS TIED TO G ND.
DNC
DNC
GND
GND
DNC
DNC
IOUT
AVDD
SDO
CLRSEL
CLEAR
DVCC
GND
SYNC/RSET
SCLK/OUTEN
SDIN/R0
AD2/R1
AD1/R2
AD0/R3
REXT2
REXT1
VREF
VIN
GND
NC/IFAULT
FAULT/TEM
P
RESET
HW SELECT
NC
NC
NC
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
AD5749
TOP VIEW
(Not to Scale)
Data Sheet AD5749
Rev. D | Page 9 of 28
Pin No. Mnemonic Description
10 AD1/R2 Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD0 and AD2, allows up to
eight devices to be addressed on one bus.
Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output
current range setting on the part.
11
AD0/R3
Device Addressing Bit (AD0). In software mode, this pin, in conjunction with AD1 and AD2, allows up to
eight devices to be addressed on one bus.
Range Decode Bit (R3). In hardware mode, this pin, in conjunction with R0, R1, and R2, selects the output
current range setting on the part.
12, 13 REXT2, REXT1 A 15 kΩ external current setting resistor can be connected between the REXT1 and REXT2 pins to
improve the IOUT temperature drift performance.
14 VREF Buffered Reference Input.
15 VIN Buffered Analog Input (0 V to 4.096 V).
16 GND Ground Connection.
17 AVDD Positive Analog Supply.
18 IOUT Current Output.
19, 20, 23, 24 DNC Do not connect to these pins.
21, 22 GND Ground Connection.
25, 26, 27, 28 NC No Connect. Can be tied to GND.
29 HW SELECT This part is used to configure the part to hardware or software mode.
HW SELECT = 0 selects software control.
HW SELECT = 1 selects hardware control.
30 RESET In software mode, this pin resets the part to its power-on state. Active low.
In hardware mode, there is no reset. If using the part in hardware mode, the RESET pin should be tied high.
31 FAULT/TEMP Fault Alert (FAULT). In software mode, this pin acts as a general fault alert pin. It is asserted low when an
open-circuit, overtemperature error, or PEC interface error is detected. This pin is an open-drain output
and must be connected to a pull-up resistor.
Overtemperature Fault (TEMP). In hardware mode, this pin acts as an overtemperature fault pin. It is
asserted low when an overtemperature error is detected. This pin is an open-drain output and must be
connected to a pull-up resistor.
32 NC/IFAULT No Connect (NC). In software mode, this pin is a no connect. Instead, tie this pin to GND.
Open-Circuit Fault Alert (IFAULT). In hardware mode, this pin acts as an open-circuit fault alert pin. It is
asserted low when an open-circuit error is detected. This pin is an open-drain output and must be
connected to a pull-up resistor.
33 (EPAD) EPAD The exposed paddle is tied to GND.
AD5749 Data Sheet
Rev. D | Page 10 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. Integral Nonlinearity Error vs. VIN, External RSET Resistor
Figure 6. Integral Nonlinearity Error vs. VIN, Internal RSET Resistor
Figure 7. Integral Nonlinearity Current Mode, External RSET Sense Resistor
Figure 8. Integral Nonlinearity Current Mode, Internal RSET Sense Resistor
Figure 9. Total Unadjusted Error vs. VIN, External RSET Resistor
Figure 10. Total Unadjusted Error vs. VIN, Internal RSET Resistor
0.004
0.003
0.002
0.001
0
–0.001
–0.002
–0.003
–0.004
–0.005
0.005
0.020
0.293
0.585
0.878
1.170
1.463
1.755
2.048
2.341
2.633
2.926
3.218
3.511
3.803
4.096
INT E GRAL NONLI NE ARITY ( %F SR)
08923-005
V
IN
(V)
4mA TO 20mA EXTERNAL R
SET
RESISTOR
0mA TO 24mA EXTERNAL R
SET
RESISTOR
0.004
0.003
0.002
0.001
0
–0.001
–0.002
–0.003
–0.004
–0.005
0.005
0.020
0.293
0.585
0.878
1.170
1.463
1.755
2.048
2.341
2.633
2.926
3.218
3.511
3.803
4.096
INT EG RAL NO NL I NE ARI T Y ( %F SR)
08923-006
4mA TO 20mA INTERNAL R
SET
RESISTOR
0mA TO 24mA INTERNAL R
SET
RESISTOR
V
IN
(V)
0.010
0.008
0.006
0.004
0.002
0
–0.002
–0.004
–0.006
–0.008
–0.010 24V 48V 55V
SUPPLY VOLTAGE (AVDD)
INTEGRAL NONLINEARITY (%FSR)
08923-007
4mA TO 20mA EXTERNAL RSET LINEARITY
0mA TO 24mA EXTERNAL RSET LINEARITY
0.010
0.008
0.006
0.004
0.002
0
–0.002
–0.004
–0.006
–0.008
–0.010 24V 48V 55V
SUPPLY VOLTAGE (AVDD)
INT EGRAL NO NLINE ARITY (% F SR)
08923-008
4mA TO 20mA INTERNAL RSET LINEARITY
0mA TO 24mA INTERNAL RSET LINEARITY
0.04
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
0.05
0.020
0.293
0.585
0.878
1.170
1.463
1.755
2.048
2.341
2.633
2.926
3.218
3.511
3.803
4.096
TO TAL UNADJUS TED ER RO R ( %FSR)
08923-009
4mA TO 20mA EXTERNAL R
SET
TUE
0mA TO 24mA EXTERNAL R
SET
TUE
V
IN
(V)
0.04
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
0.05
0.020
0.293
0.585
0.878
1.170
1.463
1.755
2.048
2.341
2.633
2.926
3.218
3.511
3.803
4.096
TO TAL UNADJUS TED ER RO R ( %FSR)
08923-010
V
IN
(V)
4mA TO 20mA INT E RNAL R
SET
TUE
0mA TO 24mA INT E RNAL R
SET
TUE
Data Sheet AD5749
Rev. D | Page 11 of 28
Figure 11. Total Unadjusted Error Current Mode, External RSET Sense Resistor
Figure 12. Total Unadjusted Error Current Mode, Internal RSET Sense Resistor
Figure 13. Integral Nonlinearity Error vs. Temperature,
Internal RSET Sense Resistor
Figure 14. Integral Nonlinearity Error vs. Temperature,
External RSET Sense Resistor
Figure 15. Total Unadjusted Error vs. Temperature, Internal RSET Sense Resistor
Figure 16. Total Unadjusted Error vs. Temperature, External RSET Sense Resistor
0.020
0.015
0.010
0.005
0
–0.005
–0.010
–0.015
–0.02024V48V55V
SUPPLY VOLTAGE (AVDD)
TOTAL UNADJUSTED ERROR (%FSR)
08923-011
4mA TO 20mA EXTERNAL RSETPOSITIVE TUE
0mA TO 24mA EXTERNAL RSETPOSITIVE TUE
4mA TO 20mA EXTERNAL RSETNEGATIVE TUE
0mA TO 24mA EXTERNAL RSETNEGATIVE TUE
0.010
0.005
0
–0.005
–0.010
–0.015
–0.020
–0.025
24V48V55V
SUPPLY VOLTAGE (AVDD)
TOTAL UNADJUSTED ERROR (%FSR)
08923-012
4mA TO 20mA INTERNAL RSETNEGATIVE TUE
0mA TO 24mA INTERNAL RSETNEGATIVE TUE
0mA TO 24mA INTERNAL RSETPOSITIVE TUE
4mA TO 20mA INTERNAL RSETPOSITIVE TUE
0.003
0.004
0.005
0.002
0.001
0
–0.001
–0.002
–0.003
–0.004
–0.005
–40 25 105
TEMPERATURE (°C)
INTEGRAL NONLINEARITY (%FSR)
08923-013
4mA TO 20mA INTERNAL RSETLINEARITY
0mA TO 24mA INTERNAL RSETLINEARITY
0.003
0.004
0.005
0.002
0.001
0
–0.001
–0.002
–0.003
–0.004
–0.005
–40 25 105
TEMPERATURE (°C)
INTEGRAL NONLINEARITY (%FSR)
08923-014
4mA TO 20mA EXTERNAL RSETLINEARITY
0mA TO 24mA EXTERNALRSETLINEARITY
0.06
0.08
0.10
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–40 25 105
TEMPERATURE (°C)
POSITIVE/NEGATIVE TUE (%FSR)
08923-015
4mA TO 20mA INTERNAL R
SET
POSITIVE TUE
0mA TO 24mA INTERNAL R
SET
POSITIVE TUE
4mA TO 20mA INTERNAL R
SET
NEGATIVE TUE
0mA TO 24mA INTERNAL R
SET
NEGATIVE TUE
0.06
0.08
0.10
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–40 25 105
TEMPERATURE (°C)
POSITIVE/NEGATIVE TUE (%FSR)
08923-016
4mA TO 20mA EXTERNAL R
SET
POSITIVE TUE
0mA TO 24mA EXTERNAL R
SET
POSITIVE TUE
4mA TO 20mA EXTERNAL R
SET
NEGATIVE TUE
0mA TO 24mA EXTERNAL R
SET
NEGATIVE TUE
AD5749 Data Sheet
Rev. D | Page 12 of 28
Figure 17. Zero-Scale Error vs. Temperature, External RSET Sense Resistor
Figure 18. Zero-Scale Error vs. Temperature, Internal RSET Sense Resistor
Figure 19. Offset Error vs. Temperature, Internal RSET Sense Resistor
Figure 20. Offset Error vs. Temperature, External RSET Sense Resistor
Figure 21. Full-Scale Error vs. Temperature, External RSET Sense Resistor
Figure 22. Full-Scale Error vs. Temperature, Internal RSET Sense Resistor
40
45
50
35
30
25
20
15
10
5
0–40 25 105
TEMPERATURE (°C)
ZERO-SCALE ERRO R ( µA)
08923-017
4mA TO 20mA EXTE RNAL R
SET
0mA TO 24mA EXTE RNAL R
SET
40
35
30
25
20
15
10
5
0–40 25 105
TEMPERATURE (°C)
ZERO-SCALE ERRO R (µA)
08923-018
4mA TO 20mA INTE RNAL R
SET
0mA TO 24mA INTE RNAL R
SET
3
2
1
0
–1
–2
–3 –40 25 105
TEMPERATURE (°C)
OF FSET ERRO R ( µ A)
08923-019
4mA TO 20mA INTE RNAL R
SET
0mA TO 24mA INTE RNAL R
SET
3
4
2
1
0
–1
–2
–3 –40 25 105
TEMPERATURE (°C)
OF FSET ERRO R (µA)
08923-020
4mA TO 20mA EXTERNAL R
SET
0mA TO 24mA EXTERNAL R
SET
0.03
0.04
0.05
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05 –40 25 105
TEMPERATURE (°C)
FUL L-SCALE ERROR (%FSR)
08923-021
4mA TO 20mA EXTERNAL R
SET
0mA TO 24mA EXTERNAL R
SET
0.06
0.08
0.10
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10 –40 25 105
TEMPERATURE (°C)
FUL L-SCALE ERROR (%FSR)
08923-022
4mA TO 20mA INTE RNAL R
SET
0mA TO 24mA INTE RNAL R
SET
Data Sheet AD5749
Rev. D | Page 13 of 28
Figure 23. Gain Error vs. Temperature, External RSET Sense Resistor
Figure 24. Gain Error vs. Temperature, Internal RSET Sense Resistor
Figure 25. Output Compliance vs. Temperature
Tested When IOUT = 10.8 mA, 0 mA to 24 mA Range Selected
Figure 26. Output Current vs. Time on VDD Power-Up
Figure 27. Output Current vs. Time on Output Enable, 0 mA to 24 mA Range
Figure 28. 4 mA to 20 mA Output Current Step
0.06
0.08
0.10
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10 –40 25 105
TEMPERATURE (°C)
GAI N E RRO R (%FSR)
08923-023
4mA TO 20mA EXTERNAL R
SET
0mA TO 24mA EXTERNAL R
SET
0.06
0.08
0.10
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10 –40 25 105
TEMPERATURE (°C)
GAI N ERROR (%F S R)
08923-024
4mA TO 20mA INTE RNAL R
SET
0mA TO 24mA INTE RNAL R
SET
2.00
2.05
2.10
1.95
1.90
1.85
1.80
1.75
1.70
1.65 –40 25 105
TEMPERATURE (°C)
COMP L I ANCE (V )
08923-025
AV
DD
COMPLIANCE VOLTAGE
12
10
8
6
4
2
0
–2
0.000010
–0.000010
–0.000008
–0.000006
–0.000004
–0.000002
0
0.000002
0.000004
0.000006
0.000008
10–10–8–6–4–202468
TIME (ms)
08923-026
I
OUT
V
DD
V
DD
(V)
I
OUT
(A)
0
–18
–16
–14
–12
–10
–8
–6
–4
–2
8–2–101234567
TIME (µs)
08923-027
IOUT
(
µA)
0.025
0.020
0.015
0.010
0.005
068615448413428211481–12 –6
CURRENT (A)
TIME (µs)
08923-028
AD5749 Data Sheet
Rev. D | Page 14 of 28
Figure 29. DICC vs. Logic Input Voltage
Figure 30. AIDD vs. AVDD, IOUT = 0 mA
3000
2500
2000
1500
1000
500
00 0.51.01.52.02.53.03.54.04.55.0
LOGIC LEVEL (V)
08923-029
DI
CC
(µA)
DV
CC
=5V
DV
CC
=3V
4.10
4.05
4.00
3.95
3.90
3.85
3.80
3.75 24 48 55
08923-031
AI
DD
(mA)
AV
DD
(V)
Data Sheet AD5749
Rev. D | Page 15 of 28
TERMINOLOGY
Total Unadjusted Error (TUE)
TUE is a measure of the output error taking all the various
errors into account: INL error, offset error, gain error, and
output drift over supplies, temperature, and time. TUE is
expressed as a percentage of full-scale range (% FSR).
Relative Accuracy or Integral Nonlinearity (INL)
INL is a measure of the maximum deviation, in % FSR, from a
straight line passing through the endpoints of the output driver
transfer function. A typical INL vs. input voltage plot is shown
in Figure 5.
Full-Scale Error
Full-scale error is the deviation of the actual full-scale analog
output from the ideal full-scale output. Full-scale error is
expressed as a percentage of full-scale range (% FSR).
Full-Scale TC
Full-scale TC is a measure of the change in the full-scale error
with a change in temperature. It is expressed in ppm FSR/°C.
Gain Error
Gain error is a measure of the span error of the output. It is the
deviation in slope of the output transfer characteristic from the
ideal expressed in % FSR. A plot of gain error vs. temperature is
shown in Figure 23.
Gain Error TC
Gain error TC is a measure of the change in gain error with
changes in temperature. Gain error TC is expressed in ppm
FSR/°C.
Zero-Scale Error
Zero-scale error is the deviation of the actual zero-scale analog
output from the ideal zero-scale output. Zero-scale error is
expressed in millivolts (mV).
Zero-Scale TC
Zero-scale TC is a measure of the change in zero-scale error
with a change in temperature. Zero-scale error TC is expressed
in ppm FSR/°C.
Offset Error
Offset error is a measurement of the difference between the
actual VOUT and the ideal VOUT expressed in millivolts (mV)
in the linear region of the transfer function. It can be negative
or positive.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a half-scale input change.
Slew Rate
The slew rate of a device is a limitation in the rate of change
of the output voltage. The output slewing speed is usually
limited by the slew rate of the amplifier used at its output. Slew
rate is measured from 10% to 90% of the output signal and is
expressed in V/μs.
Current Loop Voltage Compliance
Current loop voltage compliance is the maximum voltage at
the IOUT pin for which the output current is equal to the
programmed value.
Power-On Glitch Energy
Power-on glitch energy is the impulse injected into the analog
output when the AD5749 is powered on. It is specified as the
area of the glitch in nV-sec.
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output is affected by changes in the
power supply voltage.
AD5749 Data Sheet
Rev. D | Page 16 of 28
THEORY OF OPERATION
The AD5749 is a single-channel, low cost, precision, current
output driver with hardware or software programmable output
ranges. The software ranges are configured via an SPI-/
MICROWIRE-compatible serial interface. The hardware ranges
are programmed using the range pins (R0 to R3). The analog
input to the AD5749 is provided from a low voltage, single-supply
DAC (0 V to 4.096 V), which is internally conditioned to provide
the desired output current range.
The output current range is programmable across two ranges:
0 mA to 24 mA, or 4 mA to 20 mA. An overrange of 2% is
available on the 0 mA to 24 mA and 4 mA to 20 mA current
ranges. The output range is selected by programming the R3
to R0 bits in the control register (see Table 7 and Table 8).
Figure 31 and Figure 32 show a typical configuration of AD5749
in software mode and in hardware mode, respectively, in an
output module system. The HW SELECT pin chooses whether
the part is configured in software or hardware mode. The analog
input to the AD5749 is provided from a low voltage, single-supply
DAC such as the AD5060 and AD5066 or AD5660 and AD5668,
which can provide an output range of 0 V to 4.096 V. T h e
supply and reference for the DAC, as well as the reference for
the AD5749, can be supplied from a reference such as the
ADR392. The AD5749 can operate with a single supply up to 55
V.
SOFTWARE MODE
The software-selectable output ranges are 0 mA to 24 mA, or
4 mA to 20 mA.
Figure 31. Typical System Configuration in Software Mode (Pull-Up Resistors Not Shown for Open-Drain Outputs)
08923-032
VIN
SCLK VDD REFIN
SDI/DIN
SDO
SYNC1
SYNC
SDO
SDIN
SCLK
MCU
STATUS REGISTER
VREF
HW SELECT
FAULT
ADP1720
ADR392
AVDD AGND
AVDD GND
AD5749
AD506x
AD566x
SERIAL
INTERFACE
IOUT OPEN FAULT
OVERTEMP FAULT
IOUT
RANGE
SCALE
IOUT
0mA TO 20mA,
0mA TO 24mA,
4mA TO 20mA
Data Sheet AD5749
Rev. D | Page 17 of 28
Figure 32. Typical System Configuration in Hardware Mode Using Internal DAC Reference (Pull-Up Resistors Not Shown for Open-Drain Outputs)
Table 6. Suggested Parts for Use with the AD5749
DAC Reference Power Resolution/Accuracy Description
AD5660 Internal ADP17201 16-bit/12-bit Mid-end system, single channel, internal reference
AD5664R Internal N/A 16-bit/12-bit Mid-end system, quad channel, internal reference
AD5668 Internal N/A 16-bit/12-bit Mid-end system, octal channel, internal reference
AD5060 ADR434 ADP1720 16-bit/16-bit High-end system, single channel, external reference
AD5064/AD5066 ADR434 N/A 16-bit/16-bit High-end system, quad channel, external reference
AD5662 ADR3922 ADR3922 16-bit/12-bit Mid-end system, single channel, external reference
AD5664 ADR3922 N/A 16-bit/12-bit Mid-end system, quad channel, external reference
1 ADP1720 input range up to 28 V.
2 ADR392 input range up to 15 V.
0
8923-033
R3
R2
R1
R0
VIN
SCLK VDD REFIN
SDI/DIN
SDO
SYNC1
MCU
VREF
TEMP IFAULT
ADP1720
ADR392
AD5749
A
V
DD
A
GND
OUTEN
HW SELECT
DVCC
AVDD GND
AD506x
AD566x
OUTPUT RANGE
SELECT PINS
IOUT
RANGE
SCALE IOUT
0mA TO 20mA,
0mA TO 24mA,
4mA TO 20mA
AD5749 Data Sheet
Rev. D | Page 18 of 28
CURRENT OUTPUT ARCHITECTURE
The voltage input from the analog input VIN core (0 V to 4.096 V)
is converted to a current (see Figure 33), which is then mirrored
to the supply rail so that the application simply sees a current
source output with respect to an internal reference voltage. The
reference is used to provide internal offsets for range and gain
scaling. The selectable output range is programmable through
the digital interface (software mode) or via the range pins (R0 to
R3) (hardware mode).
Figure 33. Current Output Configuration
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads, connect a 0.01 µF
capacitor between IOUT and GND. This ensures stability with
loads beyond 50 mH. There is no maximum capacitance limit.
The capacitive component of the load may cause slower settling.
POWER-ON STATE OF THE AD5749
On power-up, the AD5749 senses whether hardware or software
mode is loaded and sets the power-up conditions accordingly.
In software SPI mode, the output powers up in the tristate
condition (0 mA).
To put the part into normal operation, the user must set the
OUTEN bit in the control register to enable the output and, in
the same write, set the output range configuration using the R3
to R0 range bits. If the CLEAR pin is still high (active) during
this write, the part automatically clears to its normal clear state
as defined by the programmed range and by the CLRSEL pin or
the CLRSEL bit (see the Asynchronous Clear (CLEAR) section
for more details). The CLEAR pin must be taken low to operate
the part in normal mode.
The CLEAR pin is typically driven directly from a microcontroller.
In cases where the power supply for the AD5749 supply is
independent of the microcontroller power supply, the user can
connect a weak pull-up resistor to DVCC or a pull-down resistor
to ground to ensure that the correct power-up condition is
achieved independent of the microcontroller. A 10 kΩ pull-up/
pull-down resistor on the CLEAR pin should be sufficient for
most applications.
If hardware mode is selected, the part powers up to the conditions
defined by the R3 to R0 range bits and the status of the OUTEN
or CLEAR pin. It is recommended to keep the output disabled
when powering up the part in hardware mode.
DEFAULT REGISTERS AT POWER-ON
The AD5749 power-on-reset circuit ensures that all registers are
loaded with zero code.
In software SPI mode, the part powers up with the output
disabled (OUTEN bit = 0). The user must set the OUTEN bit in
the control register to enable the output and, in the same write,
set the output range configuration using the R3 to R0 bits.
If hardware mode is selected, the part powers up to the
conditions defined by the R3 to R0 bits and the status of the
OUTEN pin. It is recommended to keep the output disabled
when powering up the part in hardware mode.
RESET FUNCTION
In software mode, the part can be reset using the RESET pin
(active low) or the reset bit (reset = 1). A reset disables the
output to its power-on condition. The user must write to the
OUTEN bit to enable the output and, in the same write, set the
output range configuration. The RESET pin is a level sensitive
input; the part stays in reset mode as long as the RESET pin is
low. The reset bit clears to 0 following a reset command to the
control register.
In hardware mode, there is no reset. If using the part in
hardware mode, the RESET pin should be tied high.
OUTEN
In software mode, the output can be enabled or disabled using
the OUTEN bit in the control register. When the output is
disabled, it is placed into tristate. The user must set the OUTEN
bit to enable the output and simultaneously set the output range
configuration.
In hardware mode, the output can be enabled or disabled using
the OUTEN pin. When the output is disabled, it is placed into
tristate. The user must write to the OUTEN pin to enable the
output. It is recommended that the output be disabled when
changing the ranges.
SOFTWARE CONTROL
Software control is enabled by connecting the HW SELECT pin
to ground. In software mode, the AD5749 is controlled over a
versatile 3-wire serial interface that operates at clock rates up to
50 MHz. It is compatible with SPI, QSPI™, MICROWIRE, and
DSP standards.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device MSB first as a 16-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the falling edge of SCLK.
The input shift register consists of 16 control bits, as shown in
Table 7. The timing diagram for this write operation is shown in
Figure 2. The first three bits of the input shift register are used to set
the hardware address of the AD5749 device on the printed circuit
board (PCB). Up to eight devices can be addressed per board.
Bit D11, Bit D1, and Bit D0 must always be set to 0 during any
write sequence.
08923-034
AVDD
VIN
VREF
A1
A2
R1
R3R2
T1
T2
RANGE DECODE
FROM INTERFACE
RANGE
SCALING
IOUT
Data Sheet AD5749
Rev. D | Page 19 of 28
Table 7. Input Shift Register Contents for a Write Operation—Control Register
MSB
LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A2 A1 A0 R/W 0 R3 R2 R1 R0 CLRSEL OUTEN CLEAR RSET RESET 0 0
Table 8. Input Shift Register Descriptions for Control Register
Bit
Description
A2, A1, A0
Used in association with the AD2, AD1, and AD0 external pins to determine which part is being addressed by the system
controller.
A2 A1 A0 Function
0 0 0 Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 0.
0 0 1 Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 1.
0 1 0 Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 0.
0 1 1 Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 1.
1 0 0 Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 0.
1 0 1 Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 1.
1 1 0 Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 0.
1 1 1 Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 1.
R/W Indicates a read from or a write to the addressed register.
R3, R2, R1, R0 Selects the output configuration in conjunction with RSET.
RSET R3 R2 R1 R0 Output Configuration
0 0 0 0 0 4 mA to 20 mA (external 15 kΩ current sense resistor).
0 0 0 0 1 Unused command. Do not program.
0
0
0
1
0
0 mA to 24 mA (external 15 kΩ current sense resistor).
0 0 0 1 1 Unused command. Do not program.
0 0 1 0 0 Unused command. Do not program.
0 0 1 0 1 Unused command. Do not program.
0 0 1 1 0 Unused command. Do not program.
0 0 1 1 1 Unused command. Do not program.
0 1 0 0 0 Unused command. Do not program.
0 1 0 0 1 Unused command. Do not program.
0 1 0 1 0 Unused command. Do not program.
0 1 0 1 1 Unused command. Do not program.
0 1 1 0 0 Unused command. Do not program.
0 1 1 0 1 Unused command. Do not program.
0 1 1 1 0 Unused command. Do not program.
0 1 1 1 1 Unused command. Do not program.
1 0 0 0 0 4 mA to 20 mA (internal current sense resistor).
1 0 0 0 1 Unused command. Do not program.
1 0 0 1 0 0 mA to 24 mA (internal current sense resistor).
1
0
0
1
1
Unused command. Do not program.
1 0 1 0 0 Unused command. Do not program.
1 0 1 0 1 Unused command. Do not program.
1 0 1 1 0 Unused command. Do not program.
1 0 1 1 1 Unused command. Do not program.
1 1 0 0 0 Unused command. Do not program.
1 1 0 0 1 Unused command. Do not program.
1 1 0 1 0 Unused command. Do not program.
1 1 0 1 1 Unused command. Do not program.
1 1 1 0 0 Unused command. Do not program.
1 1 1 0 1 3.92 mA to 20.4 mA (internal current sense resistor).
1 1 1 1 0 Unused command. Do not program.
1 1 1 1 1 0 mA to 24.5 mA (internal current sense resistor).
AD5749 Data Sheet
Rev. D | Page 20 of 28
Bit Description
CLRSEL Sets clear mode to zero scale or midscale. See the Asynchronous Clear (CLEAR) section.
CLRSEL
Function
0 Clear to zero-scale.
1 Clear to midscale.
OUTEN Output enable bit. This bit must be set to 1 to enable the output.
CLEAR Software clear bit; active high.
RSET
Select internal/external current sense resistor.
RSET Function
1 Select internal current sense resistor; used with R3 to R0 bits to select range.
0 Select external current sense resistor; used with R3 to R0 bits to select range.
RESET Resets the part to its power-on state.
Data Sheet AD5749
Rev. D | Page 21 of 28
Status Bit Read Operation
A read of the status bits can be initiated as part of a normal write
operation. The read is activated by selecting the correct device
address (A2, A1, A0) and then setting the R/W bit to 1. By
default, the SDO pin is disabled. After having addressed the
AD5749 and setting R/W to 1 the SDO pin is enabled and data
is clocked out on the 5th rising edge of SCLK. After all the data
has been clocked out on SDO, a rising edge on SYNC disables
(tristates) the SDO pin again. Status register data (see Table 9)
and control register data are both available during the same
read cycle. Data contained in Bit D10 to Bit D0 of the write
operation are still valid and can be used to change the operating
mode of the AD5749 if required.
The status bits comprise three read-only bits. They are used to
notify the user of specific fault conditions that occur, such as
an open circuit on the output, over-temperature error or an
interface error. If any of these fault conditions occur, a hardware
FAULT is also asserted low, which can be used as a hardware
interrupt to the controller.
See the Detailed Description of Features section for a full
explanation of fault conditions.
HARDWARE CONTROL
Hardware control is enabled by connecting the HW SELECT
pin to DVCC. In this mode, the R3, R2, R1, and R0 pins, in
conjunction with the RSET pin, are used to configure the
output range, as per Table 8.
In hardware mode, there is no status register. The fault conditions
(open circuit, and overtemperature) are available on Pin IFAULT
and Pin TEMP. If any one of these fault conditions is set, a low is
asserted on the specific fault pin. IFAULT and TEMP are open-
drain outputs and, therefore, can be connected together to allow the
user to generate one interrupt to the system controller to commun-
icate a fault. If hardwired in this way, it is not possible to isolate
which fault occurred in the system.
TRANSFER FUNCTION
The AD5749 consists of an internal signal conditioning block
that maps the analog input voltage to a programmed output
range. The available analog input range is 0 V to 4.096 V.
For all ranges, the AD5749 implements a straight linear
mapping function, where 0 V maps to the lower end of the
selected range and 4.096 V maps to the upper end of the
selected range.
Table 9. Input Shift Register Contents for a Read Operation—Status Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A2 A1 A0 1 0 R3 R2 R1 R0 CLRSEL OUTEN RSET PEC Error OVER TEMP IOUT Fault Unused
Table 10. Status Bit Options
Bit Description
PEC Error
This bit is set if there is an interface error detected by CRC-8 error checking. See the Detailed Description of Features section.
OVER TEMP This bit is set if the AD5749 core temperature exceeds approximately 150°C.
IOUT Fault This bit is set if there is an open circuit on the IOUT pin.
AD5749 Data Sheet
Rev. D | Page 22 of 28
DETAILED DESCRIPTION OF FEATURES
OUTPUT FAULT ALERT—SOFTWARE MODE
In software mode, the AD5749 is equipped with one FAULT
pin; this is an open-drain output allowing several AD5749
devices to be connected together to one pull-up resistor for
global fault detection. In software mode, the FAULT pin is
forced active low by any one of the following fault scenarios:
• The voltage at IOUT attempts to rise above the compliance
range due to an open-loop circuit or insufficient power
supply voltage. The internal circuitry that develops the
fault output avoids using a comparator with window
limits because this requires an actual output error before
the fault output becomes active. Instead, the signal is
generated when the internal amplifier in the output stage
has less than approximately 1 V of remaining drive capa-
bility. Thus, the fault output activates slightly before the
compliance limit is reached. Because the comparison is
made within the feedback loop of the output amplifier, the
output accuracy is maintained by its open-loop gain, and
an output error does not occur before the fault output
becomes active.
• An interface error is detected due to the packet error
checking failure (PEC). See the Packet Error Checking
section.
• The core temperature of the AD5749 exceeds approxi-
mately 150°C.
OUTPUT FAULT ALERT—HARDWARE MODE
In hardware mode, the AD5749 is equipped with two fault pins:
IFAULT and TEMP. These are open-drain outputs allowing
several AD5749 devices to be connected together to one pull-up
resistor for global fault detection. In hardware control mode,
these fault pins are forced active by any one of the following
fault scenarios:
• An open-circuit is detected. The voltage at IOUT attempts
to rise above the compliance range, due to an open-loop
circuit or insufficient power supply voltage. The internal
circuitry that develops the fault output avoids using a
comparator with window limits because this requires an
actual output error before the fault output becomes active.
Instead, the signal is generated when the internal amplifier
in the output stage has less than approximately 1 V of
remaining drive capability. Thus, the fault output activates
slightly before the compliance limit is reached. Because the
comparison is made within the feedback loop of the output
amplifier, the output accuracy is maintained by its open-
loop gain, and an output error does not occur before the
fault output becomes active. If this fault is detected, the
IFAULT pin is forced low.
• The core temperature of the AD5749 exceeds approx-
imately 150°C. If this fault is detected, the TEMP pin is
forced low.
ASYNCHRONOUS CLEAR (CLEAR)
CLEAR is an active high clear that allows the output to be
cleared to either zero-scale or midscale, and is user-selectable
via the CLRSEL pin or the CLRSEL bit of the input shift register,
as described in Table 8. (The clear select feature is a logical
OR function of the CLRSEL pin and the CLRSEL bit). When
the CLEAR signal is returned low, the output returns to its
programmed value or to a new programmed value. A clear
operation can also be performed via the clear command in
the control register.
Table 11. CLRSEL Options
CLRSEL Output Clear Value
0 Zero scale; for example:
4 mA on the 4 mA to 20 mA range
0 mA on the 0 mA to 24 mA range
1 Midscale; for example:
12 mA on the 4 mA to 20 mA range
12 mA on the 0 mA to 24 mA range
EXTERNAL CURRENT SETTING RESISTOR
Referring to Figure 1, RSET is an internal sense resistor and is
part of the voltage-to-current conversion circuitry. The nominal
value of the internal current sense resistor is 15 kΩ. To allow for
overrange capability in current mode, the user can also select
the internal current sense resistor to be 14.7 kΩ, giving a nominal
2% overrange capability. This feature is available in the 0 mA to
24 mA, and 4 mA to 20 mA current ranges.
The stability of the output current value over temperature is
dependent on the stability of the value of RSET. As a method of
improving the stability of the output current over temperature,
an external low drift resistor can be connected to the REXT1
and REXT2 pins of the AD5749, which can be used instead of
the internal resistor. The external resistor is selected via the
input shift register. If the external resistor option is not used,
the REXT1 and REXT2 pins should be left floating.
PROGRAMMABLE OVERRANGE MODES
The AD5749 contains an overrange mode The overranges are
selected by configuring the R3, R2, R1, and R0 bits (or pins)
accordingly.
The overranges are typically 2%. For these ranges, the analog
input remains the same (0 V to 4.096 V).
Data Sheet AD5749
Rev. D | Page 23 of 28
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy
environments, the AD5749 offers the option of error checking
based on an 8-bit (CRC-8) cyclic redundancy check. The device
controlling the AD5749 should generate an 8-bit frame check
sequence using the following polynomial:
C(x) = x8 + x2 + x1 + 1
This is added to the end of the data-word, and 24 data bits are
sent to the AD5749 before taking SYNC high. If the AD5749
receives a 24-bit data frame, it performs the error check
when SYNC goes high. If the check is valid, then the data is
written to the selected register. If the error check fails, the
FAULT pin goes low and Bit D3 of the status register is set.
After reading this register, this error flag is cleared
automatically and the FAULT pin goes high again.
Figure 34. PEC Error Checking Timing
SCLK
SDIN
SYNC
UPDATE ON SYNC HIGH
D15
(MSB)
D0
(LSB)
16-BITDATA
16-BIT DATA TRANSFER—NO ERRORCHECKING
SCLK
SDIN
SYNC
FAULT
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
FAULT GOES LOW IF
ERROR CHECK FAILS
D23
(MSB)
D8
(LSB) D7 D0
16-BIT DATA 8-BIT FCS
16-BIT DATA TRANSFER WITH ERROR CHECKING
08923-035
AD5749 Data Sheet
Rev. D | Page 24 of 28
APPLICATIONS INFORMATION
TRANSIENT VOLTAGE PROTECTION
The AD5749 contains ESD protection diodes that prevent damage
from normal handling. The industrial control environment can,
however, subject I/O circuits to much higher transients. To protect
the AD5749 from excessively high voltage transients, external
power diodes and a surge current limiting resistor may be
required, as shown in Figure 35. The constraint on the resistor
value is that during normal operation the output level at IOUT
must remain within its voltage compliance limit of AVDD −
2.75 V and the two protection diodes and resistor must have
appropriate power ratings. Further protection can be added
with transient voltage suppressors if needed.
Figure 35. Output Transient Voltage Protection
THERMAL CONSIDERATIONS
It is important to understand the effects of power dissipation
on the package and how it affects junction temperature. The
internal junction temperature should not exceed 125°C. The
AD5749 is packaged in a 32-lead, 5 mm × 5 mm LFCSP pack-
age. The thermal impedance, θJA, is 42°C/W. It is important that
the devices not be operated under conditions that cause the
junction temperature to exceed its limit. Worst-case conditions
occur when the AD5749 is operated from the maximum AVDD
(55 V) and driving the maximum current (24 mA) directly to
ground. The quiescent current of the AD5749 should also be
taken into account, nominally ~4 mA.
The calculations in Table 12 estimate maximum power
dissipation under these worst-case conditions, and determine
maximum ambient temperature based on this. These figures
assume that proper layout and grounding techniques are
followed to minimize power dissipation, as outlined in the
Layout Guidelines section.
Table 12. Thermal and Supply Considerations
Considerations 32-Lead LFCSP Package
Maximum allowed power dissipation when operating at an ambient
temperature of 85°C
W95.0
42
85125 =
−
=
−
JA
AJMAX
θ
TT
Maximum allowed ambient temperature when operating from a supply of
55 V and driving 24 mA directly to ground (include 4 mA for internal AD5749
current)
TJMAX − (PD × θJA) = 125 − ((55 × 0.028) × 42) = 60.3°C
Maximum allowed supply voltage when operating at an ambient
temperature of 85°C and driving 24 mA directly to ground
( )
V34
42028.
0
85125 =
×
−
=
×
−
JA
DD
A
JMAX
θ
AI
TT
AD5749
08923-036
AVDD
AVDD
IOUT
RP
RLOAD
Data Sheet AD5749
Rev. D | Page 25 of 28
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The PCB on which the AD5749 is
mounted should be designed so that the AD5749 lies on the
analog plane.
The AD5749 should have ample supply bypassing of 10 μF in
parallel with 0.1 μF on each supply, located as close to the
package as possible, ideally right up against the device. The
10 μF capacitors are the tantalum bead type. The 0.1 μF capaci-
tor should have low effective series resistance (ESR) and low
effective series inductance (ESI) such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
In systems where there are many devices on one board, it is often
useful to provide some heat sinking capability to allow the power
to dissipate easily.
Figure 36. Paddle Connection to Board
The AD5749 has an exposed paddle beneath the device.
Connect this paddle to the GND of the AD5749. For optimum
performance, special considerations should be used to design
the motherboard and to mount the package. For enhanced
thermal, electrical, and board level performance, the exposed
paddle on the bottom of the package should be soldered to the
corresponding thermal land paddle on the PCB (GND).
Thermal vias should be designed into the PCB land paddle area
to further improve heat dissipation.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. The
iCoupler® family of products from Analog Devices, Inc., provides
voltage isolation in excess of 5.0 kV. The serial loading structure
of the AD5749 makes it ideal for isolated interfaces because the
number of interface lines is kept to a minimum. Figure 37 shows a
4-channel isolated interface to the AD5749 using an ADuM1400.
For further information, visit http://www.analog.com/icouplers.
Figure 37. Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5749 is via a serial bus that
uses a protocol compatible with microcontrollers and DSP proces-
sors. The communication channel is a 3-wire (minimum)
interface consisting of a clock signal, a data signal, and a SYNC
signal. The AD5749 requires a 16-bit data-word with data valid
on the falling edge of SCLK.
AD5749
GND
PLANE
BOARD
0
8923-037
VIA VOA
VIB VOB
VIC VOC
VID VOD
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
08923-038
SERIAL
CLOCK OUT
SERIAL
DATA OUT
SYNC OUT
CONTROL OUT
CONTROLLER
TO
SCLK
TO
SDIN
TO
SYNC
TO
CLEAR
ADuM1400
1
1ADDIT IO NA L PINS OMI TT E D F OR CL ARI TY.
AD5749 Data Sheet
Rev. D | Page 26 of 28
OUTLINE DIMENSIONS
Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.85 mm Package Height
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD5749ACPZ −40°C to +105°C 32-Lead LFCSP CP-32-2
AD5749ACPZ-RL7 −40°C to +105°C 32-Lead LFCSP CP-32-2
1 Z = RoHS Compliant Part.
3.25
3.10 SQ
2.95
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
1
32
8
9
25
24
17
16
COPLANARITY
0.08
3.50 REF
0.50
BSC
PIN 1
INDICATOR
PIN 1
INDICATOR
0.30
0.25
0.18
0.20 REF
12° MAX 0.80 MAX
0.65 TYP
1.00
0.85
0.80 0.05 MAX
0.02 NOM
0.50
0.40
0.30
4.75
BSC SQ
0.60 MAX
0.60 MAX
0.20 MIN
11-10-2017-B
TOP VIEW
EXPOSED
PAD
BOTTOM VIEW
5.10
5.00 SQ
4.90
SEATING
PLANE
PKG-001050
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Data Sheet AD5749
Rev. D | Page 27 of 28
NOTES
AD5749 Data Sheet
Rev. D | Page 28 of 28
NOTES
©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08923-0-1/18(D)