1. General description
The 74HC574; 74HCT574 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC574; 74HCT574 are octal D-type flip-flops featuring separate D-type inputs for
each flip-flop and 3-st ate output s for bus-oriented applications. A clock (CP) and an output
enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their
individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition. When OE is LOW the contents of the 8 flip-flops are available at the
outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Op eration of
the OE input does not affect the state of the flip-flop s.
The 74HC574; 74HCT574 is functionally identical to:
74HC564: but has non-inverting outputs
74HC374; 74HCT374: but has a different pin arrangement
2. Features and benefits
3-state non-inverting outputs for bus oriented applications
8-bit positive, edge-triggered register
Common 3-state output enable input
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 Cto+85C and from 40 Cto+125C
3. Ordering information
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 6 — 26 January 2015 Product data sheet
Table 1. Ordering information
Type number Package
Temp e r ature range Name Description Version
74HC574N 40 C to +125 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HCT574N
74HC574D 40 C to +125 C SO20 plastic small outline package; 20 leads;
body width 7.5 mm SOT163-1
74HCT574D
74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 2 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
4. Functional diagram
74HC574DB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm SOT339-1
74HCT574DB
74HC574PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
74HCT574PW
Table 1. Ordering information …continued
Type number Package
Temp e r ature range Name Description Version
Fig 1. Functional di agram
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74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 3 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
5. Pinning information
5.1 Pinning
Fig 3. Logic symbol Fig 4. IEC logic symbol
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74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 4 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the HIGH-to-LOW CP transition;
Z = high-impedance OFF-state;
= LOW-to-HIGH clock transition.
7. Limiting values
[1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO20: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
Table 2. Pin description
Symbol Pin Description
OE 1 3-state output enable input (active LOW)
D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input
GND 10 ground (0 V)
CP 11 clock input (LOW-to-HIGH, edge triggered)
Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output
VCC 20 supply voltage
Table 3. Function table[1]
Operating mode Input Internal
flip-flop Output
OE CP Dn Qn
Load and read register L lL L
LhH H
Load register and disable output H lL Z
HhH Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V - 20 mA
IOoutput current VO = 0.5 V to (VCC +0.5V) - 35 mA
ICC supply current - +70 mA
IGND ground current - 70 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation DIP20 p ackage [1] - 750 mW
SO20, SSOP20 and TSSOP20 packages [2] - 500 mW
74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 5 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC574 74HCT574 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC574
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO=20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO=20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO=6.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO=7.8 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO=20A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 6.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO= 7.8 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =6.0V --0.1 - 1.0 - 1.0 A
IOZ OFF-state
output current VI=V
IH or VIL;
VO=V
CC or GND;
VCC =6.0V
--0.5 - 5.0 - 10.0 A
74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 6 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80 - 160 A
CIinput
capacitance -3.5- pF
74HCT574
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=20 A 4.4 4.5 - 4.4 - 4.4 - V
IO=6 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=20A - 0 0.1 - 0.1 - 0.1 V
IO= 6.0 mA - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =5.5V --0.1 - 1.0 - 1.0 A
IOZ OFF-state
output current VI=V
IH or VIL; VCC =5.5V;
VO=V
CC or GND per input
pin; other inputs at VCC or
GND; IO=0A
--0.5 - 5.0 - 10 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V - - 8.0 - 80 - 160 A
ICC additional
supply current VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO=0A
per input pin; Dn inputs - 50 180 - 225 - 245 A
per input pin; OE input - 125 450 - 563 - 613 A
per input pin; CP input - 150 540 - 675 - 735 A
CIinput
capacitance -3.5- - - - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 7 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 10.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC574
tpd propagation
delay CP to Qn; see Figure 7 [1]
VCC = 2.0 V - 47 150 - 190 - 225 ns
VCC = 4.5 V - 17 30 - 35 - 45 ns
VCC =5V; C
L=15pF - 14 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 38 ns
ten enable time OE to Qn; see Figure 9 [2]
VCC = 2.0 V - 44 140 - 175 - 210 ns
VCC = 4.5 V - 16 28 - 35 - 42 ns
VCC = 6.0 V - 13 24 - 30 - 36 ns
tdis disable time OE to Qn; see Figure 9 [3]
VCC = 2.0 V - 39 125 - 155 - 190 ns
VCC = 4.5 V - 14 25 - 31 - 38 ns
VCC = 6.0 V - 11 21 - 26 - 32 ns
tttransition
time Qn; see Figure 7 [4]
VCC = 2.0 V - 14 60 - 75 - 90 ns
VCC = 4.5 V - 5 12 - 15 - 18 ns
VCC = 6.0 V - 4 10 - 13 - 15 ns
tWpulse width CP HIGH or LOW;
see Figure 8
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
tsu set-up time Dn to CP; see Figure 8
VCC = 2.0 V 60 6 - 75 - 90 - ns
VCC = 4.5 V 12 2 - 15 - 18 - ns
VCC = 6.0 V 10 2 - 13 - 15 - ns
thhold time Dn to CP; see Figure 8
VCC = 2.0 V 5 0 - 5 - 5 - ns
VCC = 4.5 V 5 0 - 5 - 5 - ns
VCC = 6.0 V 5 0 - 5 - 5 - ns
fmax maximum
frequency CP; see Figure 7
VCC = 2.0 V 6.0 37 - 4.8 - 4.0 - MHz
VCC = 4.5 V 30 112 - 24 - 20 - MHz
VCC =5V; C
L= 15 pF - 123 - - - - - MHz
VCC = 6.0 V 35 133 - 28 - 24 - MHz
74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 8 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
[1] tpd is the same as tPLH and tPHL.
[2] ten is the same as tPZH and tPZL.
[3] tdis is the same as tPLZ and tPHZ.
[4] tt is the same as tTHL and tTLH.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi = input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC
[5] -22- - - - -pF
74HCT574
tpd propagation
delay CP to Qn; see Figure 7 [1]
VCC = 4.5 V - 18 33 - 41 - 50 ns
VCC =5V; C
L=15pF - 15 - - - - - ns
ten enable time OE to Qn; see Figure 9 [2]
VCC = 4.5 V - 19 33 - 41 - 50 ns
tdis disable time OE to Qn; see Figure 9 [3]
VCC = 4.5 V - 16 28 - 35 - 42 ns
tttransition
time Qn; see Figure 7 [4]
VCC = 4.5 V - 5 12 - 15 - 18 ns
tWpulse width CP HIGH or LOW;
see Figure 8
VCC = 4.5 V 16 7 - 20 - 24 - ns
tsu set-up time Dn to CP; see Figure 8
VCC = 4.5 V 12 3 - 15 - 18 - ns
thhold time Dn to CP; see Figure 8
VCC = 4.5 V 5 1- 5 - 5 - ns
fmax maximum
frequency CP; see Figure 7
VCC = 4.5 V 30 69 - 24 - 20 - MHz
VCC =5V; C
L=15pF - 76 - - - - - MHz
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC 1.5 V [5] -25- - - - -pF
Table 7. Dy namic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 10.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 9 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width and the
maximum frequency (CP)
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VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times
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74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 10 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Enable and disable times
Table 8. Measurement points
Type Input Output
VMVMVXVY
74HC574 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT574 1.3 V 1.3 V 0.1VCC 0.9VCC
74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 11 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 10. Test circuit for measuring switching times
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Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC574 VCC 6ns 15pF, 50 pF 1kopen GND VCC
74HCT574 3 V 6 ns 15 p F, 50 pF 1 kopen GND VCC
74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 12 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
12. Package outline
Fig 11. Package outline SOT146-1 (DIP20)
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74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 13 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
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74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 14 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Fig 13. Package outline SOT339-1 (SSOP20)
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74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 15 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Fig 14. Package outline SOT360-1 (TSSOP20)
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74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 16 of 19
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviation s
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM