Advance ON Semiconductor Confidential and Proprietary AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Features 1/3-Inch 1.2 Mp CMOS Digital Image Sensor with Global Shutter AR0135AT Datasheet, Rev. 2 For the latest datasheet revision, please visit: www.onsemi.com Features Table 1: * ON Semiconductor's Next Generation Global Shutter Technology * Superior low-light performance * HD video (720p60) * Video/Single Frame mode * Flexible row-skip modes * On-chip AE and statistics engine * Parallel and serial output * Support for external LED or flash * Auto black level calibration * Context switching Key Parameters (continued) Parameter Output Frame rate Responsivity SNRMAX Dynamic range Supply voltage Typical Value Serial Parallel Full resolution 720p Monochrome * Automotive scene processing * Scanning and machine vision * 720p60 video applications I/O Digital Analog HiSPi Power consumption Operating temperature General Description Package options Applications The ON Semiconductor AR0135AT is a 1/3-inch 1.2Mp CMOS digital image sensor with an active-pixel array of 1280H x 960V. It is designed for low light performance and features a global shutter for accurate capture of moving scenes and synchronization with pulsed light sources. It includes sophisticated camera functions such as auto exposure control, windowing, scaling, row skip mode, and both video and single frame modes. It is programmable through a simple two-wire serial interface. The AR0135AT produces extraordinarily clear, sharp images, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, including automotive scene processing. Table 1: HiSPi 12-bit 54 fps 60 fps 3.22 V/lux*sec 42 ke-/lux*sec 40.7 dB 67.7 dB 1.8 or 2.8 V 1.8 V 2.8 V 0.4 V <400 mW -40C to + 105C (ambient) -40C to + 120C (junction) 9 x 9 mm 64-pin iBGA Bare die Key Parameters Parameter Typical Value Optical format Active pixels Pixel size Color filter array Shutter type Input clock range Output pixel clock (maximum) 1/3-inch (6 mm) 1280H x 960V = 1.2 Mp 3.75m Monochrome Global shutter 6 - 50 MHz 74.25 MHz AR0135AT/D Rev. 2, 1/16 EN 1 (c)Semiconductor Components Industries, LLC,2016 This document contains information on a new product. Specifications and information herein are subject to change without notice. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Ordering Information Ordering Information Table 2: Available Part Numbers Part Number Product Description Orderable Product Attribute Description AR0135AT2M00XUEA0-DPBR Mono, iBGA Dry Pack with Protective Film, Double Side BBAR Glass AR0135AT2M00XUEA0-DRBR Mono, iBGA Dry Pack without Protective Film, Double Side BBAR Glass AR0135AT2M00XUEA0-TPBR Mono, iBGA Tape & Reel with Protective Film, Double Side BBAR Glass AR0135AT2M00XUEA0-TRBR Mono, iBGA Tape & Reel without Protective Film, Double Side BBAR Glass AR0135AT2M00XUEAD3GEVK AR0135AT2M00XUEAH3GEVB AR0135AT2M00XPD20 Mono, iBGA, Demo3 Kit AR0135AT/D Rev. 2, 1/16 EN Mono, iBGA, Head Board Mono, Bare Die 2 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Table of contents Table of contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Features Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pixel Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Default Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Configuration and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Slave Address/Data Direction Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Message Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Typical Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Single READ from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Single WRITE to Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 HiSPi Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Power-On Reset and Standby Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Power-Down Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Standby Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 AR0135AT/D Rev. 2, 1/16 EN 3 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor General Description General Description The ON SemiconductorTM AR0135AT can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. The default mode output is a full-resolution image at 54 frames per second (fps). It outputs 12-bit raw data, using either the parallel or serial (HiSPi) output ports. The device may be operated in video (master) mode or in frame trigger mode. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a synchronized pixel clock. A dedicated FLASH pin can be programmed to control external LED or flash exposure illumination. The AR0135AT includes additional features to allow application-specific tuning: windowing, adjustable auto-exposure control, auto black level correction, on-board temperature sensor, and row skip and digital binning modes. The sensor is designed to operate in a wide temperature range (-40C to +105C). Functional Overview The AR0135AT is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 50 MHz. The maximum output pixel rate is 74.25 Mp/s, corresponding to a clock rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor. Figure 1: Block Diagram Active Pixel Sensor (APS) Array Power Temperature sensor Timing and Control (Sequencer) Memory PLL External Clock Auto Exposure and Stats Engine Pixel Data Path (Signal Processing) Analog Processing and A/D Conversion Serial Output Parallel Output Flash Trigger Two-Wire Serial Interface OTPM Control Registers User interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 1.2 Mp Active- Pixel Sensor array. The AR0135AT features global shutter technology for accurate capture of moving images. The exposure of the entire array is controlled by programming the integration time by register setting. All rows simultaneously integrate light prior to readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an analog-to- digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital AR0135AT/D Rev. 2, 1/16 EN 4 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Features Overview processing signal chain (which provides further data path corrections and applies digital gain). The pixel data are output at a rate of up to 74.25 Mp/s, in parallel to frame and line synchronization signals. Features Overview The AR0135AT Global Sensor shutter has a wide array of features to enhance functionality and to increase versatility. A summary of features follows. Please refer to the AR0135AT Developer Guide for detailed feature descriptions, register settings, and tuning guidelines and recommendations. * Operating Modes The AR0135AT works in master (video), trigger (single frame), or Auto Trigger modes. In master mode, the sensor generates the integration and readout timing. In trigger mode, it accepts an external trigger to start exposure, then generates the exposure and readout timing. The exposure time is programmed through the two-wire serial interface for both modes. Trigger mode is not compatible with the HiSPi interface. * Window Control Configurable window size and blanking times allow a wide range of resolutions and frame rates. Digital binning and skipping modes are supported, as are vertical and horizontal mirror operations. * Context Switching Context switching may be used to rapidly switch between two sets of register values. Refer to the AR0135AT Developer Guide for a complete set of context switchable registers. * Gain The AR0135AT Global Shutter sensor can be configured for analog gain of up to 8x, and digital gain of up to 8x. * Automatic Exposure Control The integrated automatic exposure control may be used to ensure optimal settings of exposure and gain are computed and updated every other frame. Refer to the AR0135AT Developer Guide for more details. * HiSPi The AR0135AT Global Shutter image sensor supports two or three lanes of StreamingSP or Packetized-SP protocols of ON Semiconductor's High-Speed Serial Pixel Interface. * PLL An on chip PLL provides reference clock flexibility and supports spread spectrum sources for improved EMI performance. * Reset The AR0135AT may be reset by a register write, or by a dedicated input pin. * Output Enable The AR0135AT output pins may be tri-stated using a dedicated output enable pin. * Temperature Sensor The temperature sensor is only guaranteed to be functional when the AR0135AT is initially powered-up or is reset at temperatures at or above 0C. * Black Level Correction * Row Noise Correction * Column Correction * Test Patterns Several test patterns may be enabled for debug purposes. These include a solid color, color bar, fade to grey, and a walking 1s test pattern. AR0135AT/D Rev. 2, 1/16 EN 5 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Pixel Data Format Pixel Data Format Pixel Array Structure The AR0135AT pixel array is configured as 1412 columns by 1028 rows, (see Figure 2). The dark pixels are optically black and are used internally to monitor black level. Of the right 108 columns, 64 are dark pixels used for row noise correction. Of the top 24 rows of pixels, 12 of the dark rows are used for black level correction. There are 1288 columns by 972 rows of optically active pixels that can be readable. While the sensor's format is 1280 x 960, the additional active columns and active rows are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. The pixel adjustment is always performed for monochrome version. The active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. Not all dummy pixels or barrier pixels can be read out. The optical center of the readable active pixels can be found between X_ADDR 643 and 644, and between Y_ADDR 485 and 486. Figure 2: Pixel Array Description 1412 1028 2 e xtra a ctive + 2 lig h t d u m m y + 4 b a rrie r + 1 0 0 d a rk + 4 b a rrie r 4 e xtra a ctive + 2 lig h t d u m m y + 4 b a rrie r + 2 4 d a rk + 1 0 b a rrie r 1 2 8 8 x9 7 2 (re a d a b le a ctive p ixe l) 4.8 3 x3 .6 4 5 m m ^2 2 lig h t d u m m y + 1 0 b a rrie r 6 e xtra a ctive + 2 lig h t d u m m y + 4 b a rrie r D a rk p ixe l AR0135AT/D Rev. 2, 1/16 EN B a rrie r p ixe l L ig h t dummy p ixe l 6 E xtra a ctive p ixe l R e a d a b le A ctive p ixe l (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Pixel Data Format Default Readout Order By convention, the sensor core pixel array is shown with the first addressable (logical) pixel (0,0) in the top right corner. This reflects the actual layout of the array on the die. Also, the physical location of the first pixel data read out of the sensor in default condition is that of pixel (112, 44). AR0135AT/D Rev. 2, 1/16 EN 7 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Configuration and Pinout Configuration and Pinout The figures and tables below show a typical configuration for the AR0135AT image sensor and show the package pinouts. Typical Configuration: Serial Four-Lane HiSPi Interface VDD_IO 1.5k2, 3 1.5k2 Digital Digital I/O Core power1 power1 Master clock (6-50 MHz) VDD HiSPi power1 VDD_SLVS Figure 3: EXTCLK VDD_PLL VAA VAA_PIX SLVS0_P SLVS0_N SLVS1_P SLVS1_N SLVS2_P SLVS2_N SDATA SCLK OE_BAR STANDBY RESET_BAR From controller Analog Analog PLL power1 power1 power1 SLVS3_P7 SLVS3_N7 SLVSC_P SLVSC_N To controller TEST FLASH VDD_IO VDD Notes: AR0135AT/D Rev. 2, 1/16 EN VDD_SLVS VDD_PLL VAA DGND AGND Digital ground Analog ground VAA_PIX 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but it may be greater for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. The parallel interface output pads can be left unconnected if the serial output interface is used. 5. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Refer to the AR0135AT demo headboard schematics for circuit recommendations. 6. ON Semiconductor recommends that analog power planes be placed in a manner such that coupling with the digital power planes is minimized. 7. Although 4 serial lanes are shown, the AR0135AT supports only 2 or 3 lane HiSPi. 8 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Configuration and Pinout Figure 4: Typical Configuration: Parallel Pixel Data Interface 1.5k2, 3 1.5k2 Digital Digital core I/O power1 power1 Master clock (6-50 MHz) VDD_IO PLL Analog Analog power1 power1 power1 VDD VDD_PLL VAA DOUT [11:0] EXTCLK PIXCLK LINE_VALID FRAME_VALID SDATA SCLK TRIGGER OE_BAR STANDBY RESET_BAR From Controller VAA_PIX To controller FLASH TEST DGND VDD_IO VDD VDD_PLL VAA VAA_PIX Digital ground Notes: AR0135AT/D Rev. 2, 1/16 EN AGND Analog ground 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but it may be greater for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. The serial interface output pads can be left unconnected if the parallel output interface is used. 5. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Refer to the AR0135AT demo headboard schematics for circuit recommendations. 6. ON Semiconductor recommends that analog power planes be placed in a manner such that coupling with the digital power planes is minimized. 9 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Configuration and Pinout Figure 5: 9x9mm 63-Ball iBGA Package 1 A 2 3 4 5 SLVS0N SLVS0P SLVS1N 6 7 SLVS1P VDD VDD STANDBY SLVS2P VDD VAA VAA B VDD_PLL SLVSCN SLVSCP SLVS2N C EXTCLK VDD_ SLVS (SLVS3N) (SLVS3P) D SADDR SCLK SDATA DGND DGND E LINE_ VALID FRAME_ VALID PIXCLK FLASH DGND F DOUT8 DOUT9 DOUT10 DOUT11 G DOUT4 DOUT5 DOUT6 H DOUT0 DOUT1 DOUT2 DGND VDD 8 AGND AGND VAA_PIX VAA_PIX VDD_IO RESERVED RESERVED DGND VDD_IO TEST RESERVED DOUT7 DGND VDD_IO TRIGGER OE_BAR DOUT3 DGND VDD_IO VDD_IO RESET _BAR VDD Top View (Ball Down) AR0135AT/D Rev. 2, 1/16 EN 10 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Configuration and Pinout Table 3: Pin Descriptions - 63-Ball iBGA Package Name iBGA Pin Type Description SLVS0_N SLVS0_P SLVS1_N SLVS1_P STANDBY VDD_PLL SLVSC_N SLVSC_P SLVS2_N SLVS2_P VAA EXTCLK VDD_SLVS SLVS3_N SLVS3_P DGND VDD AGND SADDR SCLK SDATA VAA_PIX LINE_VALID FRAME_VALID PIXCLK FLASH VDD_IO DOUT8 DOUT9 DOUT10 DOUT11 TEST DOUT4 DOUT5 DOUT6 DOUT7 TRIGGER A2 A3 A4 A5 A8 B1 B2 B3 B4 B5 B7, B8 C1 C2 C3 C4 C5, D4, D5, E5, F5, G5, H5 A6, A7, B6, C6, D6 C7, C8 D1 D2 D3 D7, D8 E1 E2 E3 E4 E6, F6, G6, H6, H7 F1 F2 F3 F4 F7 G1 G2 G3 G4 G7 Output Output Output Output Input Power Output Output Output Output Power Input Power Output Output Power Power Power Input Input I/O Power Output Output Output Output Power Output Output Output Output Input Output Output Output Output Input OE_BAR DOUT0 DOUT1 DOUT2 DOUT3 RESET_BAR G8 H1 H2 H3 H4 H8 Input Output Output Output Output Input Reserved E7, E8, F8 HiSPi serial data, lane 0, differential N. HiSPi serial data, lane 0, differential P. HiSPi serial data, lane 1, differential N. HiSPi serial data, lane 1, differential P. Standby-mode enable pin (active HIGH). PLL power. HiSPi serial DDR clock differential N. HiSPi serial DDR clock differential P. HiSPi serial data, lane 2, differential N. HiSPi serial data, lane 2, differential P. Analog power. External input clock. HiSPi power. (May leave unconnected if parallel interface is used) (Unsupported) HiSPi serial data, lane 3, differential N. (Unsupported) HiSPi serial data, lane 3, differential P. Digital GND. Digital power. Analog GND. Two-Wire Serial address select. Two-Wire Serial clock input. Two-Wire Serial data I/O. Pixel power. Asserted when DOUT line data is valid. Asserted when DOUT frame data is valid. Pixel clock out. DOUT is valid on rising edge of this clock. Control signal to drive external light sources. I/O supply power. Parallel pixel data output. Parallel pixel data output. Parallel pixel data output. Parallel pixel data output (MSB) Manufacturing test enable pin (connect to DGND). Parallel pixel data output. Parallel pixel data output. Parallel pixel data output. Parallel pixel data output. Exposure synchronization input. (Connect to DGND if HiSPi interface is used) Output enable (active LOW). Parallel pixel data output (LSB) Parallel pixel data output. Parallel pixel data output. Parallel pixel data output. Asynchronous reset (active LOW). All settings are restored to factory default. Reserved (do not connect). AR0135AT/D Rev. 2, 1/16 EN n/a 11 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Two-Wire Serial Register Interface Two-Wire Serial Register Interface The two-wire serial interface bus enables read/write access to control and status registers within the AR0135AT.The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5k resistor. Either the slave or master device can drive SDATA LOW--the interface protocol determines which device is allowed to drive SDATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLK LOW; the AR0135AT uses SCLK as an input only and therefore never drives it LOW. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of lowlevel protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH-to-LOW transition on SDATA while ScLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a "repeated start" or "restart" condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while ScLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when ScLK is LOW and must be stable while ScLK is HIGH. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A "0" in bit [0] indicates a WRITE, and a "1" indicates a READ. The default slave addresses used by the AR0135AT are 0x20 (write address) and 0x21 (read address) in accordance with the specification. Alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the SADDR input. AR0135AT/D Rev. 2, 1/16 EN 12 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Two-Wire Serial Register Interface An alternate slave address can also be programmed through R0x31FC. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the ScLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when ScLK is LOW and must be stable while ScLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA LOW during the ScLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a "0" indicates a write and a "1" indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave's internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit. AR0135AT/D Rev. 2, 1/16 EN 13 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Two-Wire Serial Register Interface Single READ from Random Location This sequence (Figure 6 on page 14) starts with a dummy WRITE to the 16-bit address that is to be used for the READ. The master terminates the WRITE by generating a restart condition. The master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. The master terminates the READ by generating a noacknowledge bit followed by a stop condition. Figure 6 shows how the internal register address maintained by the AR0135AT is loaded and incremented as the sequence proceeds. Figure 6: Single READ from Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] S = start condition P = stop condition Sr = restart condition A = acknowledge A = no-acknowledge A Reg Address, M Reg Address[7:0] A Sr Slave Address 1 A M+1 Read Data A P slave to master master to slave Single READ from Current Location This sequence (Figure 7) performs a read using the current value of the AR0135AT internal register address. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. The figure shows two independent READ sequences. Figure 7: Single READ from Current Location Previous Reg Address, N S Slave Address AR0135AT/D Rev. 2, 1/16 EN 1 A Reg Address, N+1 Read Data A P S 14 Slave Address 1 A N+2 Read Data A P (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Two-Wire Serial Register Interface Sequential READ, Start from Random Location This sequence (Figure 8) starts in the same way as the single READ from random location (Figure 6). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte READs until "L" bytes have been read. Figure 8: Sequential READ, Start from Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] M+1 M+2 A Reg Address, M Reg Address[7:0] A Sr Slave Address M+L-2 M+3 1 A M+L-1 M+1 Read Data A M+L Sequential READ, Start from Current Location This sequence (Figure 9) starts in the same way as the single READ from current location (Figure 7 on page 14). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte READs until "L" bytes have been read. Figure 9: Sequential READ, Start from Current Location Previous Reg Address, N S Slave Address 1 A Read Data N+1 A N+2 Read Data A Read Data N+L-1 A Read Data N+L A P Single WRITE to Random Location This sequence (Figure 10) begins with the master generating a start condition. The slave address/data direction byte signals a WRITE and is followed by the HIGH then LOW bytes of the register address that is to be written. The master follows this with the byte of write data. The WRITE is terminated by the master generating a stop condition. Figure 10: Single WRITE to Random Location Previous Reg Address, N S AR0135AT/D Rev. 2, 1/16 EN Slave Address 0 A Reg Address[15:8] 15 A Reg Address[7:0] Reg Address, M A Write Data M+1 A P A (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Two-Wire Serial Register Interface Sequential WRITE, Start at Random Location This sequence (Figure 11) starts in the same way as the single WRITE to random location (Figure 10). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte WRITEs until "L" bytes have been written. The WRITE is terminated by the master generating a stop condition. Figure 11: Sequential WRITE, Start at Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] M+1 Write Data AR0135AT/D Rev. 2, 1/16 EN M+2 A Write Data A Reg Address, M Reg Address[7:0] M+3 A Write Data M+L-2 Write Data A 16 M+1 A M+L-1 A Write Data M+L A P A (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Electrical Specifications Electrical Specifications Unless otherwise stated, the following specifications apply to the following conditions: VDD = 1.8V - 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8V 0.3V; VDD_SLVS = 0.4V - 0.1/+0.2; TA = -30C to +70C; output load = 10pF; PIXCLK frequency = 74.25 MHz; HiSPi off. Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 12 and Table 4. Figure 12: Two-Wire Serial Bus Timing Parameters SDATA tLOW tf tf tSU;DAT tr tHD;STA tr tBUF SCLK S tHD;STA Note: Table 4: tHD;DAT tHIGH tSU;STA tSU;STO Sr P S Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Two-Wire Serial Bus Characteristics f EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25C Standard-Mode Parameter SCLK Clock Frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCLK clock HIGH period of the SCLK clock Set-up time for a repeated START condition Data hold time: Data set-up time Rise time of both SDATA and SCLK signals Fall time of both SDATA and SCLK signals Set-up time for STOP condition AR0135AT/D Rev. 2, 1/16 EN Fast-Mode Symbol Min Max Min Max Unit fSCL 0 100 0 400 KHz tHD;STA 4.0 - 0.6 - S tLOW 4.7 4.0 4.7 - 1.3 0.6 0.6 - S S S 04 250 4.0 3.455 1000 300 - 06 1006 20 + 0.1Cb7 20 + 0.1Cb7 0.6 0.95 300 300 - S nS nS nS S tHIGH t SU;STA tHD;DAT tSU;DAT tr tf tSU;STO 17 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Electrical Specifications Table 4: Two-Wire Serial Bus Characteristics f EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25C Standard-Mode Parameter Symbol Bus free time between a STOP and START condition Capacitive load for each bus line Serial interface input pin capacitance SDATA max load capacitance SDATA pull-up resistor Notes: AR0135AT/D Rev. 2, 1/16 EN Fast-Mode Min Max Min Max Unit BUF 4.7 - 1.3 - s Cb CIN_SI CLOAD_SD RSD 1.5 400 3.3 30 4.7 1.5 400 3.3 30 4.7 pF pF pF K t This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor. Two-wire control is I2C-compatible. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1 VDD levels. Sensor EXCLK = 27 MHz. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. 5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF. 1. 2. 3. 4. 18 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Electrical Specifications I/O Timing By default, the AR0135AT launches pixel data, FV and LV with the falling edge of PIXCLK. The expectation is that the user captures DOUT[11:0], FV and LV using the rising edge of PIXCLK. The launch edge of PIXCLK can be configured in register R0x3028. See Figure 13 and Table 5 for I/O timing (AC) characteristics. Figure 13: I/O Timing Diagram tR t RP tF t FP 90% 90% 10% 10% t EXTCLK EXTCLK PIXCLK t PD Data[11:0] Pxl _0 Pxl _1 Pxl _2 Pxl _n t PLH LINE_VALID/ FRAME_VALID Table 5: t PFL t PFH t PLL I/O Timing Characteristics, Parallel Output (1.8V VDD_IO)1 Symbol Definition fEXTCLK tEXTCLK tR tF tjJITTER tcp Input clock frequency Input clock period Input clock rise time Input clock fall time Input clock jitter EXTCLK to PIXCLK propagation delay PIXCLK rise time PIXCLK fall time PIXCLK duty cycle PIXCLK frequency tRP tFP fPIXCLK tPD PIXCLK to data valid tPFH PIXCLK to FV HIGH tPLH PIXCLK to LV HIGH tPFL PIXCLK to FV LOW tPLL PIXCLK to LV LOW CIN Input pin capacitance AR0135AT/D Rev. 2, 1/16 EN FRAME_VALID trails LINE_VALID by 6 PIXCLKs. FRAME_VALID leads LINE_VALID by 6 PIXCLKs. Condition Min Typ 6 20 Max Unit 50 166 5.7 600 14.3 MHz ns ns ns ns ns 1.3 1.3 40 6 4.0 3.9 60 74.25 ns ns % MHz -2.5 2 ns -2.5 2 ns -3 1.5 ns -2.5 2 ns -3 1.5 ns 3 3 PLL enabled PLL enabled Nominal voltages, PLL disabled, PIXCLK slew rate = 4 PCLK slew rate = 6 PCLK slew rate = 6 PIXCLK slew rate = 6, Data slew rate = 7 PIXCLK slew rate = 6, Data slew rate = 7 PIXCLK slew rate = 6, Data slew rate = 7 PIXCLK slew rate = 6, Data slew rate = 7 PIXCLK slew rate = 6, Data slew rate = 7 PIXCLK slew rate = 6, Data slew rate = 7 50 2.5 19 pf (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Electrical Specifications Notes: Table 6: 1. Minimum and maximum values are taken at 70C, 1.7V and -30C, 1.95V. All values are taken at the 50% transition point. The loading used is 10 pF. 2. Jitter from PIXCLK is already taken into account in the data for all of the output parameters. I/O Timing Characteristics, Parallel Output (2.8V VDD_IO)1 Symbol Definition fEXTCLK tEXTCLK tR tF tjJITTER tcp Input clock frequency Input clock period Input clock rise time Input clock fall time Input clock jitter EXTCLK to PIXCLK propagation delay PIXCLK rise time PIXCLK fall time PIXCLK duty cycle PIXCLK frequency tRP tFP fPIXCLK Condition tPD PIXCLK to data valid tPFH PIXCLK to FV HIGH tPLH PIXCLK to LV HIGH tPFL PIXCLK to FV LOW tPLL PIXCLK to LV LOW CIN Input pin capacitance Notes: AR0135AT/D Rev. 2, 1/16 EN Min Typ 6 20 Max Unit 50 166 5.3 600 13.4 MHz ns ns ns ns ns 1.3 1.3 40 6 4.0 3.9 60 74.25 ns ns % MHz -2.5 2 ns -2.5 2 ns -2.5 2 ns -2.5 2 ns -2.5 2 ns 3 3 PLL enabled PLL enabled Nominal voltages, PLL disabled, PIXCLK slew rate = 4 PCLK slew rate = 6 PCLK slew rate = 6 PIXCLK slew rate = 6, Data slew rate = 7 PIXCLK slew rate = 6, Data slew rate = 7 PIXCLK slew rate = 6, Data slew rate = 7 PIXCLK slew rate = 6, Data slew rate = 7 PIXCLK slew rate = 6, Data slew rate = 7 PIXCLK slew rate = 6, Data slew rate = 7 50 2.5 pf 1. Minimum and maximum values are taken at 70C, 2.5V and -30C, 3.1V. All values are taken at the 50% transition point. The loading used is 10 pF. 2. Jitter from PIXCLK is already taken into account in the data for all of the output parameters. 20 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Electrical Specifications I/O Rise Slew Rate (2.8V VDD_IO)1 Table 7: Parallel Slew Rate (R0x306E[15:13]) Conditions Min Typ Max Units 7 6 5 4 3 2 1 0 Default Default Default Default Default Default Default Default 1.50 0.98 0.71 0.52 0.37 0.26 0.17 0.10 2.50 1.62 1.12 0.82 0.58 0.40 0.27 0.16 3.90 2.52 1.79 1.26 0.88 0.61 0.40 0.23 V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns Note: 1. Minimum and maximum values are taken at 70C, 2.5V and -30C, 3.1V. The loading used is 10 pF. I/O Fall Slew Rate (2.8V VDD_IO)1 Table 8: Parallel Slew Rate (R0x306E[15:13]) Conditions Min Typ Max Units 7 6 5 4 3 2 1 0 Default Default Default Default Default Default Default Default 1.40 0.97 0.73 0.54 0.39 0.27 0.18 0.11 2.30 1.61 1.21 0.88 0.63 0.43 0.29 0.17 3.50 2.48 1.86 1.36 0.88 0.66 0.44 0.25 V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns Note: AR0135AT/D Rev. 2, 1/16 EN 1. Minimum and maximum values are taken at 70C, 2.5V and -30C, 3.1V. The loading used is 10 pF. 21 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Electrical Specifications I/O Rise Slew Rate (1.8V VDD_IO)1 Table 9: Parallel Slew Rate (R0x306E[15:13]) Conditions Min Typ Max Units 7 6 5 4 3 2 1 0 Default Default Default Default Default Default Default Default 0.57 0.39 0.29 0.22 0.16 0.12 0.08 0.05 0.91 0.61 0.46 0.34 0.24 0.17 0.11 0.07 1.55 1.02 0.75 0.54 0.39 0.27 0.18 0.10 V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns Note: Table 10: I/O Fall Slew Rate (1.8V VDD_IO)1 Parallel Slew Rate (R0x306E[15:13]) Conditions Min Typ Max Units 7 6 5 4 3 2 1 0 Default Default Default Default Default Default Default Default 0.57 0.40 0.31 0.24 0.18 0.13 0.09 0.05 0.92 0.64 0.50 0.38 0.27 0.19 0.13 0.08 1.55 1.08 0.82 0.61 0.44 0.31 0.20 0.12 V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns Notes: AR0135AT/D Rev. 2, 1/16 EN 1. Minimum and maximum values are taken at 70C, 1,7V and -30C, 1.95V. The loading used is 10 pF. 1. Minimum and maximum values are taken at 70C, 1.7V and -30C, 1.95V. The loading used is 10 pF. 22 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Electrical Specifications DC Electrical Characteristics The DC electrical characteristics are shown in Table 11, Table 12, Table 13, and Table 14. Table 11: DC Electrical Characteristics Symbol Definition VDD VDD_IO VAA VAA_PIX VDD_PLL VDD_SLVS VIH VIL Core digital voltage I/O digital voltage Analog voltage Pixel supply voltage PLL supply voltage HiSPi supply voltage Input HIGH voltage Input LOW voltage IIN Input leakage current VOH VOL IOH IOL Output HIGH voltage Output LOW voltage Output HIGH current Output LOW current Caution Table 12: Condition Typ Max Unit 1.7 1.7/2.5 2.5 2.5 2.5 0.3 VDD_IO * 0.7 - 1.8 1.8/2.8 2.8 2.8 2.8 0.4 - - V V V V V V V V 20 - 1.95 1.9/3.1 3.1 3.1 3.1 0.6 - VDD_IO * 0.3 - A VDD_IO - 0.3 - -22 - - - - - - 0.4 - 22 V V mA mA No pull-up resistor; VIN = VDD_IO or DGND VDD_IO = 2.8V At specified VOH At specified VOL Stresses greater than those listed in Table 12 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Absolute Maximum Ratings Symbol Parameter VSUPPLY ISUPPLY IGND VIN VOUT TSTG1 Power supply voltage (all supplies) Total power supply current Total ground current DC input voltage DC output voltage Storage temperature Note: Table 13: Min Minimum Maximum Unit Symbol -0.3 - - -0.3 -0.3 -40 4.5 200 200 VDD_IO + 0.3 VDD_IO + 0.3 +125 V mA mA V V C VSUPPLY ISUPPLY IGND VIN VOUT TSTG1 1. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Current Consumption for Parallel Output VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8V; VDD= 1.8V; PLL Enabled and PIXCLK = 74.25 MHz; TA = 25C; CLOAD = 10pF Digital operating current I/O digital operating current Analog operating current Pixel supply current PLL supply current AR0135AT/D Rev. 2, 1/16 EN Condition Symbol Parallel, Streaming, Full resolution 54 fps Parallel, Streaming, Full resolution 54 fps Parallel, Streaming, Full resolution 54 fps Parallel, Streaming, Full resolution 54 fps Parallel, Streaming, Full resolution 54 fps IDD1 IDD_IO IAA IAA_PIX IDD_PLL 23 Min Typ Max Unit 46 52 46 7 8 60 - 55 9 10 mA mA mA mA mA (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Electrical Specifications Table 14: Standby Current Consumption Analog - VAA + VAA_PIX + VDD_PLL; Digital - VDD + VDD_IO; TA = 25C Definition Hard standby (clock off, driven low) Hard standby (clock on, EXTCLK = 20 MHz) Soft standby (clock off, driven low) Soft standby (clock on, EXTCLK = 20 MHz) Condition Min Typ Max Unit Analog, 2.8V Digital, 1.8V Analog, 2.8V Digital, 1.8V Analog, 2.8V Digital, 1.8V Analog, 2.8V Digital, 1.8V - - - - - - - - 3 25 12 1.1 3 25 12 1.1 15 125 25 1.7 15 125 25 1.7 A A A mA A A A mA HiSPi Electrical Specifications The ON Semiconductor AR0135AT sensor supports SLVS mode only, and does not have a DLL for timing adjustments. Refer to the High-Speed Serial Pixel (HiSPi) Interface Physical Layer Specification v2.00.00 for electrical definitions, specifications, and timing information. The VDD_SLVS supply in this data sheet corresponds to VDD_TX in the HiSPi Physical Layer Specification. Similarly, VDD is equivalent to VDD_HiSPi as referenced in the specification. The HiSPi transmitter electrical specifications are listed at 700 MHz. Table 15: Input Voltage and Current (HiSPi Power Supply 0.4 V) Measurement Conditions: Max Freq 700 MHz Parameter Supply current (PWRHiSPi) (driving 100 load) HiSPi common mode voltage (driving 100 load) HiSPi differential output voltage (driving 100 load) Change in VCM between logic 1 and 0 Change in |VOD| between logic 1 and 0 Vod noise margin Difference in VCM between any two channels Difference in VOD between any two channels Common-mode AC voltage (pk) without VCM cap termination Common-mode AC voltage (pk) with VCM cap termination Max overshoot peak |VOD| Max overshoot Vdiff pk-pk Eye Height Single-ended output impedance Output impedance mismatch AR0135AT/D Rev. 2, 1/16 EN Symbol Min Typ Max Unit IDD_SLVS - 10 15 mA VCMD VDD_SLVS x 0.45 VDD_SLVS/2 VDD_SLVS x 0.55 V |VOD| VDD_SLVS x 0.36 VDD_SLVS/2 VDD_SLVS x 0.64 V 25 25 30 50 mV mV % mV |VOD| 100 mV VCM_ac 50 mV VCM_ac 30 mV VOD_ac Vdiff_pkpk Veye Ro Ro 1.3 x |VOD| 2.6 x |VOD| V V 70 20 % VCM |VOD| NM |VCM| - 1.4 x VOD 35 24 50 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Electrical Specifications Figure 14: Differential Output Voltage for Clock or Data Pairs VDIFFmax VDIFFmin 0V Diff) Output Signal is 'Cp - Cn' or 'Dp - Dn' Table 16: Rise and Fall Times Measurement Conditions: HiSPi Power Supply 0.4V, Max Freq 700 MHz Parameter Data Rate Max setup time from transmitter Max hold time from transmitter Rise time (20% - 80%) Fall time (20% - 80%) Clock duty Bitrate Period Eye Width Data Total jitter (pk pk)@1e-9 Clock Period Jitter (RMS) Clock cycle to cycle jitter (RMS) Clock to Data Skew PHY-to-PHY Skew Mean differential skew Notes: AR0135AT/D Rev. 2, 1/16 EN Symbol Min Typ Max Unit 1/UI TxPRE TxPost RISE FALL PLL_DUTY tpw teye ttotaljit tckjit tcyjit tchskew t|PHYskew| tDIFFSKEW 280 0.3 0.3 - 150ps 45 1.43 0.3 - - - 0.25UI 0.25 UI 50 700 - - - - 55 3.57 Mb/s UI1 UI -0.1 -100 0.2 50 100 0.1 2.1 100 % ns1 UI1, 2 UI1, 2 ps2 ps2 UI1, 2 UI1, 5 ps6 1. One UI is defined as the normalized mean time between one edge and the following edge of the clock. 2. Taken from 0V crossing point. 3. Also defined with a maximum loading capacitance of 10pF on any pin. The loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3UI. 4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges. 5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges. 6. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two complementary edges at mean VCM point. 25 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Electrical Specifications Figure 15: Eye Diagram for Clock and Data Signals RISE 80% D A T A M A SK V d i ff 20% T x Pr e T x Po s t FALL UI/ 2 UI/ 2 V d i ff M a x V d i ff C L O C K M A SK T r i g ge r/ R efe re nce C L K JIT T ER Figure 16: Skew Within the PHY and Output Channels V C MD t C M PSK EW AR0135AT/D Rev. 2, 1/16 EN t C HSKEW1 PHY 26 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Power-On Reset and Standby Timing Power-On Reset and Standby Timing Power-Up Sequence The recommended power-up sequence for the AR0135AT is shown in Figure 17. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Turn on VDD_PLL power supply. 2. After 0-10 s, turn on VAA and VAA_PIX power supply. 3. After 0-10 s, turn on VDD_IO power supply. 4. After the last power supply is stable, enable EXTCLK. 5. If RESET_BAR is in a LOW state, hold RESET_BAR LOW for at least 1 ms. If RESET_BAR is in a HIGH state, assert RESET_BAR for at least 1 ms. 6. Wait 160000 EXTCLKs (for internal initialization into software standby). 7. Configure PLL, output, and image settings to desired values. 8. Wait 1 ms for the PLL to lock. 9. Set streaming mode (R0x301A[2] = 1). Figure 17: Power Up VDD_PLL (2.8) VAA_PIX VAA (2.8) t0 t1 VDD_IO (1.8/2.8) VDD (1.8) t2 t3 VDD_SLVS (0.4) EXTCLK t4 RESET_BAR tx t5 Hard Reset Table 17: t6 Software Standby PLL Lock Streaming Power-Up Sequence Definition VDD_PLL to VAA/VAA_PIX VAA/VAA_PIX to VDD_IO VDD_IO to VDD VDD to VDD_SLVS Xtal settle time Hard Reset Internal Initialization PLL Lock Time Notes: AR0135AT/D Rev. 2, 1/16 EN Internal Initialization Symbol Minimum Typical Maximum Unit t0 t1 t2 t3 tx t4 t5 t6 0 0 0 0 - 12 160000 1 10 10 10 10 301 - - - - - - - - - - - s s s s ms ms EXTCLKs ms 1. Xtal settling time is component-dependent, usually taking about 10 - 100 ms. 2. Hard reset time is the minimum time required after power rails are settled. In a circuit where hard reset is held down by RC circuit, then the RC time must include the all power rail settle time and Xtal settle time. 3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the others. If the case happens that VDD_PLL is powered after 27 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Power-On Reset and Standby Timing other supplies then the sensor may have functionality issues and will experience high current draw on this supply. Power-Down Sequence The recommended power-down sequence for the AR0135AT is shown in Figure 18. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Disable streaming if output is active by setting standby R0x301A[2] = 0 2. The soft standby state is reached after the current row or frame, depending on configuration, has ended. 3. Turn off VDD_SLVS. 4. Turn off VDD. 5. Turn off VDD_IO 6. Turn off VAA/VAA_PIX. 7. Turn off VDD_PLL. Figure 18: Power Down VDD_SLVS (0.4) t0 VDD (1.8) t1 V DD_IO (1.8/2.8) t2 VAA_PIX VAA (2.8) t3 VDD_PLL (2.8) EXTCLK t4 Power Down until next Power up cycle Table 18: Power-Down Sequence Definition VDD_SLVS to VDD VDD to VDD_IO VDD_IO to VAA/VAA_PIX VAA/VAA_PIX to VDD_PLL PwrDn until Next PwrUp Time Note: AR0135AT/D Rev. 2, 1/16 EN Symbol Minimum Typical Maximum Unit t0 t1 t2 t3 t4 0 0 0 0 100 - - - - - - - - - - s s s s ms t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged. 28 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Power-On Reset and Standby Timing Standby Sequence Figures 19 and 20 show timing diagrams for entering and exiting standby. Delays are shown indicating the last valid register write prior to entering standby as well as the first valid write upon exiting standby. Also shown is timing if the EXTCLK is to be disabled during standby. Figure 19: Enter Standby Timing FV E XTC L K 50 E XTC L Ks S DATA R egister Writes Valid R egister Writes Not Valid 750 E XTC L Ks S TANDBY Figure 20: Exit Standby Timing 28 rows + C IT FV E XTC L K S DATA R egister Writes Not Valid R egister Writes Valid 10 E XTC L Ks S TANDBY 1ms TR IGGE R AR0135AT/D Rev. 2, 1/16 EN 29 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Power-On Reset and Standby Timing Figure 21: Quantum Efficiency - Monochrome Sensor (Typical) 80 70 Quantum Efficiency (%) 60 50 40 30 20 10 0 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 Wavelength (nm) AR0135AT/D Rev. 2, 1/16 EN 30 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor Package Dimensions Package Dimensions Figure 22: 63-Ball iBGA Package Outline Drawing IBGA63 9x9 CASE 503AZ ISSUE O DATE 23 JUN 2015 Notes: AR0135AT/D Rev. 2, 1/16 EN 3. Lid material: Borosilicate glass 0.4 0.04 thickness. Refractive index at 20C = 1.5255 @ 546 nm and 1.5231 @ 588 nm. Double side AR Coating: 530-570nm R< 1%; 420-700nm R < 2%. 4. Solder ball material: SAC305 (95% Sn, 3% Ag, 0.5% Cu). Dimensions apply to solder balls post reflow. Pre-flow ball is 0.5 on a O0.4 SMD ball pad. 31 (c)Semiconductor Components Industries, LLC,2016. ON Semiconductor Confidential and Proprietary Advance AR0135AT 1/3-Inch 1.2Mp CMOS Digital Image Sensor ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC's product/patent coverage may be accessed at www.onsemi.com/site/pdf/ Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. AR0135AT/D Rev. 2, 1/16 EN 32 (c)Semiconductor Components Industries, LLC,2016 .